Storage device and storage system for generating one or more internal clock signals

Abstract

The present disclosure relates to memory devices and memory systems for generating one or more internal clock signals. A memory device includes a calibration code generation circuit configured to generate a calibration code based on a calibration test mode signal and a calibration clock signal. The memory device includes a code selection circuit configured to select one of the calibration code and a manual code as a selected calibration code based on a manual test mode signal. The memory device includes a clock activation signal calibration circuit configured to delay latch a clock activation signal to generate a delayed clock activation signal based on the selected calibration code. The memory device includes a clock calibration circuit configured to calibrate an internal clock signal to generate an internal calibrated clock signal based on the selected calibration code and the delayed clock activation signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2025-0052682, filed on April 22, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to storage devices and storage systems, and more specifically, to storage devices and storage systems configured to generate one or more internal clock signals. Background Technology

[0004] Stacked memory systems, such as high-bandwidth memory (HBM) devices, are used in a wide range of applications due to their high bandwidth and energy efficiency. Unlike traditional memory systems that use parallel data buses, stacked memory systems consist of stacked memory devices, which include base chips interconnected via through-silicon vias (TSVs) and multiple memory chips. The stacked memory device includes physical interfaces, such as a physical layer for communicating with a processor. This physical layer is designed for high-speed data transfer and efficient communication. Summary of the Invention

[0005] In one embodiment, this disclosure describes a storage device that may include: a calibration code generation circuit configured to generate a calibration code based on a calibration test mode signal and a calibration clock signal; a code selection circuit configured to select one of a calibration code and a manual code as a selected calibration code based on a manual test mode signal; a clock activation signal calibration circuit configured to delay latching a clock activation signal based on the selected calibration code to generate a delayed clock activation signal; and a clock calibration circuit configured to calibrate an internal clock signal based on the selected calibration code and the delayed clock activation signal to generate an internal calibration clock signal.

[0006] In one embodiment, this disclosure describes a memory system that may include a base die and a plurality of core dies disposed above an intermediary layer. The base die may include: a calibration code generation circuit configured to generate a calibration code based on a calibration test mode signal and a calibration clock signal; a code selection circuit configured to select one of a calibration code and a manual code as a selected calibration code based on a manual test mode signal; a clock activation signal calibration circuit configured to delay latching a clock activation signal based on the selected calibration code to generate a delayed clock activation signal; and a clock calibration circuit configured to calibrate an internal clock signal based on the selected calibration code and the delayed clock activation signal to generate an internal calibration clock signal.

[0007] In one embodiment, this disclosure describes a memory system that may include a base die configured to control a plurality of core dies. The base die may include: a physical layer configured to use multiple channels between the core dies and a processor to control the transmission of data, commands, and addresses; and a serial-to-parallel conversion circuit configured to convert serial signals transmitted serially through the physical layer into parallel signals, align the converted parallel signals through a plurality of alignment circuits, and transmit the parallel signals to via regions. At least one of the plurality of alignment circuits may include an internal clock generation circuit configured to generate a calibration code based on a calibration test mode signal and a calibration clock signal, delay a latched clock activation signal based on the calibration code to generate a delayed clock activation signal, and calibrate an internal clock signal based on the calibration code to generate an internal calibration clock signal. Attached Figure Description

[0008] Figure 1 An internal clock generation circuit according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A calibration code generation circuit according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A synthetic test gating pulse generation circuit according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A gating pulse synthesis circuit according to an embodiment of the present disclosure is shown.

[0012] Figure 5 This is a timing diagram of the operation period of the gating pulse synthesis circuit according to an embodiment of the present disclosure.

[0013] Figure 6 A gating pulse comparison circuit according to an embodiment of the present disclosure is shown.

[0014] Figure 7 This is a timing diagram of the operation period of the gating pulse comparison circuit according to an embodiment of the present disclosure.

[0015] Figure 8 A clock activation signal calibration circuit according to an example of this disclosure is shown.

[0016] Figure 9 This is a table illustrating the operation of a code decoder according to an example of this disclosure.

[0017] Figure 10 A code delay circuit according to an embodiment of the present disclosure is shown.

[0018] Figure 11 This is a timing diagram showing the operation of the clock activation signal calibration circuit and the clock calibration circuit according to embodiments of the present disclosure.

[0019] Figure 12 A basic die circuit according to an embodiment of the present disclosure is shown.

[0020] Figure 13 A storage system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0021] In the following description of embodiments, when a parameter is referred to as “preset” or “predetermined,” it may be intended to indicate that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during a period of execution of the process or algorithm.

[0022] Terms such as “first” and “second” are used to distinguish multiple components without implying the size, order, priority, number, or importance of the components. For example, in one example, the first component might be named the second component, while in another example, the second component might be named the first component.

[0023] When a component is marked as "connected" to another component, these components can be connected directly or through an intermediary component. When two components are marked as "directly connected," one component is directly connected to the other, and there is no intermediary component between them.

[0024] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. Signals with a logic high level are distinguished from signals with a logic low level. For example, when a signal at a first voltage level corresponds to a logic high level signal, a signal at a second voltage level corresponds to a logic low level signal. In one embodiment, a logic high level can be a voltage level higher than a logic low level. According to embodiments, the logic levels of signals can be different or opposite. For example, a signal at a logic high level in one embodiment can be at a logic low level in another embodiment, and vice versa.

[0025] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on these concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0026] Figure 1 An internal clock generation circuit 1 according to an embodiment of the present disclosure is shown.

[0027] like Figure 1As shown, the internal clock generation circuit 1 includes a calibration code generation circuit (CAL-CD GEN) 10, a code selection circuit (CD SEL) 11, a clock activation signal latch (CLK-EN LAT) 13, a clock activation signal calibration circuit (CLK-ENCAL) 15, and a clock calibration circuit (ICLK CAL) 17.

[0028] The calibration code generation circuit 10 generates the calibration code CAL-CD based on the calibration test mode signal TMCAL and the calibration clock signal CLK-CAL. The calibration code generation circuit 10 also generates a synthesized test strobe pulse (e.g., ...) based on the calibration test mode signal TMCAL and the calibration clock signal CLK-CAL. Figure 2 The synthesized test gating pulse (TSTB-S) and clock gating pulse (e.g., Figure 2 The calibration test mode signal TMCAL is a test mode signal activated for calibration test operations. The calibration test operation is performed to calibrate the internal clock (ICLK, QCLK, ICLKB, QCLKB). The calibration test mode signal TMCAL can be activated or deactivated via command and address during initialization operations of the mode register group, etc. The calibration code generation circuit 10 can generate a calibration code CAL-CD with a bit group corresponding to the delay interval difference, in order to calibrate the delay interval difference between the paths traversed by the transmission strobe pulse signal and the clock signal.

[0029] The code selection circuit 11 is electrically connected to the calibration code generation circuit 10 and receives the calibration code CAL-CD from the calibration code generation circuit 10. The code selection circuit 11 generates a selected calibration code SCAL-CD based on the calibration code CAL-CD, the manual test mode signal TMM-CD, and the manual code M-CD. When the manual test mode signal TMM-CD is activated, the code selection circuit 11 selects and outputs the manual code M-CD as the selected calibration code SCAL-CD; when the manual test mode signal TMM-CD is deactivated, the code selection circuit 11 selects and outputs the calibration code CAL-CD as the selected calibration code SCAL-CD.

[0030] Clock activation signal latch 13 generates a latched clock activation signal LCLK-EN based on the test mode activation signal TMCLK-EN and the internal clock signal QBCLK. Clock activation signal latch 13 latches the test mode activation signal TMCLK-EN based on the internal clock signal QBCLK to generate the latched clock activation signal LCLK-EN. The test mode activation signal TMCLK-EN can be activated to execute a test mode. Clock activation signal latch 13 latches the activated test mode activation signal TMCLK-EN synchronously with the rising edge of the internal clock signal QBCLK to generate the activated latched clock activation signal LCLK-EN. The rising edge of the internal clock signal QBCLK indicates the point at which the logic level of the internal clock signal QBCLK changes from logic low to logic high. The internal clock signal QBCLK used to latch the test mode activation signal TMCLK-EN is only an example and can be implemented using other internal clocks ICLK, QCLK, ICLKB according to embodiments.

[0031] The clock activation signal calibration circuit 15 is electrically connected to the code selection circuit 11 and the clock activation signal latch 13. It receives a selected calibration code SCAL-CD from the code selection circuit 11 and a latched clock activation signal LCLK-EN from the clock activation signal latch 13. The clock activation signal calibration circuit 15 generates a delayed clock activation signal CLK-ENd based on the selected calibration code SCAL-CD and the latched clock activation signal LCLK-EN. The clock activation signal calibration circuit 15 delays the latched clock activation signal LCLK-EN by the calibration period set by the selected calibration code SCAL-CD to generate the delayed clock activation signal CLK-ENd.

[0032] Clock calibration circuit 17 is electrically connected to code selection circuit 11 and clock activation signal calibration circuit 15. It receives a selected calibration code SCAL-CD from code selection circuit 11 and a delayed clock activation signal CLK-ENd from clock activation signal calibration circuit 15. Clock calibration circuit 17 calibrates internal clock signals ICLK, QCLK, ICLKB, and QCLKB based on the selected calibration code SCAL-CD and the delayed clock activation signal CLK-ENd, generating internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C, respectively. After the delayed clock activation signal CLK-ENd is activated, clock calibration circuit 17 generates internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C by delaying the internal clock signals ICLK, QCLK, ICLKB, and QCLKB by the calibration period set by the selected calibration code SCAL-CD. The delayed clock activation signal CLK-ENd is generated by delaying the latched clock activation signal LCLK-EN by a calibration period. Therefore, the delayed clock activation signal CLK-ENd is activated after the calibration code CAL-CD is updated. Thus, in one embodiment, after the calibration code CAL-CD is updated by the delayed clock activation signal CLK-End, the clock calibration circuit 17 generates internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C by calibrating the internal clock signals ICLK, QCLK, ICLKB, and QCLKB respectively. This prevents or mitigates glitch occurrences in the internal clock signals ICLK, QCLK, ICLKB, and QCLKB due to the update of the calibration code CAL-CD, which are then included in the internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C.

[0033] Figure 2 For example, as shown Figure 1 The calibration code generation circuit 10 shown is an embodiment of the present disclosure.

[0034] like Figure 2 As shown, the calibration code generation circuit 10 includes a synthesized test strobe pulse generation circuit (TSTB-S GEN) 101, a clock strobe pulse generation circuit (CLK-STB GEN) 103, and a strobe pulse comparison circuit (STB COM) 105.

[0035] The synthetic test gating pulse generation circuit 101 generates a synthetic test gating pulse TSTB-S based on the calibration test mode signal TMCAL and the calibration clock signal CLK-CAL. The synthetic test gating pulse generation circuit 101 latches the calibration test mode signal TMCAL based on the calibration clock signal CLK-CAL to generate multiple test patterns (e.g., Figure 3 The test patterns (TPT1, TPT2, TPT3, and TPT4) are used to synthesize multiple test patterns to generate the synthesized test strobe pulse TSTB-S. The multiple test patterns can be configured to transition from logic low to logic high or from logic high to logic low, and can be driven by multiple drivers with different driving forces (e.g., ...). Figure 3 The test strobe generation circuit 101 transmits each of the multiple test patterns to the strobe line to generate multiple test strobe pulses, and synthesizes the multiple test strobe pulses to generate a synthesized test strobe pulse TSTB-S. The synthesized test strobe pulse generation circuit 101 generates a synthesized test strobe pulse TSTB-S, which has a logic level that changes synchronously with the latest time point among the logic level transitions of the multiple test strobe pulses.

[0036] The clock gating pulse generation circuit 103 generates a clock gating pulse CLK-STB based on the calibration test mode signal TMCAL and the calibration clock signal CLS-CAL. When the calibration test mode signal TMCAL is activated, the clock gating pulse generation circuit 103 delays the calibration clock signal CLK-CAL by a preset clock delay period to generate a delayed calibration clock (not shown), and generates the clock gating pulse CLK-STB synchronously with the delayed calibration clock. The clock delay period can be determined by the clock driver (not shown) driving the calibration clock signal CLK-CAL and the clock transmission line (not shown) transmitting the calibration clock signal CLK-CAL. When the calibration test mode signal TMCAL is activated, the clock gating pulse generation circuit 103 generates the clock gating pulse CLK-STB as a pulse generation synchronously with the first rising edge of the delayed calibration clock signal. The clock gating pulse CLK-STB can be generated as a pulse with a preset pulse width, starting from the time point when the first rising edge of the delayed calibration clock signal is generated.

[0037] The gating pulse comparator circuit 105 is electrically connected to the synthesized test gating pulse generation circuit 101 and the clock gating pulse generation circuit 103 to receive the synthesized test gating pulse TSTB-S from the synthesized test gating pulse generation circuit 101 and the clock gating pulse CLK-STB from the clock gating pulse generation circuit 103. The gating pulse comparator circuit 105 generates a calibration code CAL-CD based on the synthesized test gating pulse TSTB-S and the clock gating pulse CLK-STB. The gating pulse comparator circuit 105 sequentially delays the clock gating pulse CLK-STB by unit delay periods to generate multiple delayed gating pulses (e.g., ...). Figure 6 The test strobe pulse TSTB-S is synchronously latched with each of the multiple delayed strobe pulses (STB1D, STB2D, and STB3D) to generate a calibration code CAL-CD. The strobe pulse comparator circuit 105 generates the calibration code CAL-CD, which includes bits having logic levels determined according to the logic levels of the synthesized test strobe pulse TSTB-S synchronously latched with each of the multiple delayed strobe pulses.

[0038] Figure 3 For example, as shown Figure 2 The synthetic test gating pulse generation circuit 101 shown is according to an embodiment of the present disclosure.

[0039] like Figure 3 As shown, the synthesized test strobe pulse generation circuit 101 includes a first test input latch 111-1, a second test input latch 111-2, a first test driver 113-1, a second test driver 113-2, a third test driver 113-3, a fourth test driver 113-4, a first strobe pulse line (STB LINE) 115-1, a second strobe pulse line 115-2, a third strobe pulse line 115-3, a fourth strobe pulse line 115-4, and a strobe pulse synthesis circuit (STB SUM) 117.

[0040] The first test input latch 111-1 latches and outputs the calibration test mode signal TMCAL based on the calibration clock signal CLK-CAL. The first test input latch 111-1 latches and outputs the calibration test mode signal TMCAL synchronously with the rising edge of the calibration clock signal CLK-CAL. The first test input latch 111-1 generates a signal that transitions from a logic low level to a logic high level when the rising edge of the calibration clock signal CLK-CAL occurs.

[0041] The second test input latch 111-2 latches and outputs the inverted signal of the calibration test mode signal TMCAL based on the calibration clock signal CLK-CAL. The second test input latch 111-2 latches and outputs the inverted signal of the calibration test mode signal TMCAL synchronously with the rising edge of the calibration clock signal CLK-CAL. The second test input latch 111-2 generates a signal that transitions from a logic high level to a logic low level when the rising edge of the calibration clock signal CLK-CAL occurs.

[0042] The first test driver 113-1 is electrically connected to the first test input latch 111-1 to receive a signal that the logic level changes from logic low to logic high when the rising edge of the calibration clock signal CLK-CAL occurs. The first test driver 113-1 drives the first test pattern TPT1 based on the output signal of the first test input latch 111-1. The first test driver 113-1 can be implemented as a PN driver with a PMOS transistor and an NMOS transistor coupled in a CMOS structure. The PN driver pulls the first test pattern TPT1 up to the power supply voltage VDD through the PMOS transistor and drives the first test pattern TPT1 to the ground voltage VSS through the NMOS transistor. The PN driver drives the first test pattern TPT1 to the ground voltage VSS and then drives the first test pattern TPT1 to the power supply voltage VDD. In one embodiment, P in the PN driver represents PMOS (P-type MOSFET), and N represents NMOS (N-type MOSFET). In one embodiment, the PN driver can be referred to as a push-pull driver or a CMOS driver.

[0043] The second test driver 113-2 is electrically connected to the first test input latch 111-1 to receive a signal that the logic level transitions from logic low to logic high when the rising edge of the calibration clock signal CLK-CAL is generated. The second test driver 113-2 drives the second test pattern TPT2 based on the output signal of the first test input latch 111-1. The second test driver 113-2 can be implemented as an NN driver using only NMOS transistors. The NN driver pulls the second test pattern TPT2 up to the supply voltage VDD—threshold voltage Vth via the NMOS transistor, and drives the second test pattern TPT2 to ground voltage VSS via the NMOS transistor. The NN driver drives the second test pattern TPT2 to ground voltage VSS, and then drives the second test pattern TPT2 to the supply voltage VDD—threshold voltage Vth. The NN driver consumes more power than the PN driver but has greater driving force and can perform higher-speed operation than the PN driver. In one embodiment, the NN driver may be referred to as a pull-down driver or a low-side driver including NMOS transistors.

[0044] The third test driver 113-3 is electrically connected to the second test input latch 111-2 to receive a signal that the logic level transitions from logic high to logic low when the rising edge of the calibration clock signal CLK-CAL is generated. The third test driver 113-3 drives the third test pattern TPT3 based on the output signal of the second test input latch 111-2. The third test driver 113-3 can be implemented as a PN driver with PMOS and NMOS transistors coupled in a CMOS structure. The PN driver pulls the third test pattern TPT3 up to the power supply voltage VDD through the PMOS transistor and drives the third test pattern TPT3 to the ground voltage VSS through the NMOS transistor. The PN driver drives the third test pattern TPT3 to the ground voltage VSS, and then drives the third test pattern TPT3 back to the power supply voltage VDD.

[0045] The fourth test driver 113-4 is electrically connected to the second test input latch 111-2 to receive a signal from the second test input latch 111-2 indicating that the logic level transitions from logic high to logic low when the rising edge of the calibration clock signal CLK-CAL occurs. The fourth test driver 113-4 drives the fourth test pattern TPT4 based on the output signal of the second test input latch 111-2. The fourth test driver 113-4 can be implemented as an NN driver using only NMOS transistors. The NN driver pulls the fourth test pattern TPT4 up to the supply voltage VDD—threshold voltage Vth through the NMOS transistor, and drives the fourth test pattern TPT4 to ground voltage VSS through the NMOS transistor. The NN driver drives the fourth test pattern TPT4 to ground voltage VSS, and then drives the fourth test pattern TPT4 using the supply voltage VDD—threshold voltage Vth.

[0046] The first strobe pulse line 115-1 is electrically connected between the first test driver 113-1 and the strobe pulse synthesis circuit 117. The first test pattern TPT1 output from the first test driver 113-1 is transmitted through the first strobe pulse line 115-1 and received by the strobe pulse synthesis circuit 117 as the first test strobe pulse TSTB1. The first test strobe pulse TSTB1 is generated by transmitting the first test pattern TPT1, driven by the first test driver 113-1 (implemented as a PN driver), through the first strobe pulse line 115-1. Therefore, the timing of the transition from logic low to logic high in the first test strobe pulse TSTB1 can be determined by the driving force of the first test driver 113-1 and the transmission characteristics of the first strobe pulse line 115-1.

[0047] The second gating pulse line 115-2 is electrically connected between the second test driver 113-2 and the gating pulse synthesis circuit 117. The second test pattern TPT2 output from the second test driver 113-2 is transmitted through the second gating pulse line 115-2 and received by the gating pulse synthesis circuit 117 as the second test gating pulse TSTB2. The second test gating pulse TSTB2 is generated by transmitting the second test pattern TPT2 driven by the second test driver 113-2, which is implemented as an NN driver, through the second gating pulse line 115-2. Therefore, the timing of the logic level transition from logic low to logic high in the second test gating pulse TSTB2 can be determined by the driving force of the second test driver 113-2 and the transmission characteristics of the second gating pulse line 115-2.

[0048] The third strobe pulse line 115-3 is electrically connected between the third test driver 113-3 and the strobe pulse synthesis circuit 117. The third test pattern TPT3 output from the third test driver 113-3 is transmitted through the third strobe pulse line 115-3 and received by the strobe pulse synthesis circuit 117 as the third test strobe pulse TSTB3. The third test strobe pulse TSTB3 is generated by transmitting the third test pattern TPT3 driven by the third test driver 113-3, which is implemented as a PN driver, through the third strobe pulse line 115-3. Therefore, the timing of the logic level transition from logic low to logic high of the third test strobe pulse TSTB3 can be determined by the driving force of the third test driver 113-3 and the transmission characteristics of the third strobe pulse line 115-3.

[0049] The fourth strobe pulse line 115-4 is electrically connected between the fourth test driver 113-4 and the strobe pulse synthesis circuit 117. The fourth test pattern TPT4 output from the fourth test driver 113-4 is transmitted through the fourth strobe pulse line 115-4 and received by the strobe pulse synthesis circuit 117 as the fourth test strobe pulse TSTB4. The fourth test strobe pulse TSTB4 is generated by transmitting the fourth test pattern TPT4 driven by the fourth test driver 113-4, which is implemented as an NN driver, through the fourth strobe pulse line 115-4. Therefore, the timing of the logic level transition from logic low to logic high in the fourth test strobe pulse TSTB4 can be determined by the driving force of the fourth test driver 113-4 and the transmission characteristics of the fourth strobe pulse line 115-4.

[0050] A gating pulse synthesis circuit 117 is electrically connected to a first gating pulse line 115-1, a second gating pulse line 115-2, a third gating pulse line 115-3, and a fourth gating pulse line 115-4 to receive a first test gating pulse TSTB1 from the first gating pulse line 115-1, a second test gating pulse TSTB2 from the second gating pulse line 115-2, a third test gating pulse TSTB3 from the third gating pulse line 115-3, and a fourth test gating pulse TSTB4 from the fourth gating pulse line 115-4. The gating pulse synthesis circuit 117 generates a synthesized test gating pulse TSTB-S based on the first test gating pulse TSTB1, the second test gating pulse TSTB2, the third test gating pulse TSTB3, and the fourth test gating pulse TSTB4. The gating pulse synthesis circuit 117 generates a synthesized test gating pulse TSTB-S, which has a logic level that changes synchronously with the latest logic level transition time among the logic level transition times of the first test gating pulse TSTB1, the second test gating pulse TSTB2, the third test gating pulse TSTB3, and the fourth test gating pulse TSTB4. For example, when the logic level of the first test gating pulse TSTB1 changes from logic low to logic high at a first time point, the logic level of the second test gating pulse TSTB2 changes from logic low to logic high at a second time point, the logic level of the third test gating pulse TSTB3 changes from logic high to logic low at a third time point, and the logic level of the fourth test gating pulse TSTB4 changes from logic high to logic low at a fourth time point, and the third time point is the latest among the first to fourth time points, the gating pulse synthesis circuit 117 generates a synthesized test gating pulse TSTB-S whose logic level changes from logic low to logic high synchronously with the third time point.

[0051] Figure 4 For example, as shown Figure 3 The shown is a gating pulse synthesis circuit 117 according to an embodiment of the present disclosure.

[0052] like Figure 4As shown, the gating pulse synthesis circuit 117 includes inverters 121-1 and 121-2 and an AND gate 123. Inverter 121-1 inverts and buffers the third test gating pulse TSTB3 and outputs the inverted and buffered third test gating pulse TSTB3, while inverter 121-2 inverts and buffers the fourth test gating pulse TSTB4 and outputs the inverted and buffered fourth test gating pulse TSTB4. AND gate 123 receives the first test gating pulse TSTB1, the second test gating pulse TSTB2, the output signal of inverter 121-1, and the output signal of inverter 121-2, and performs a logical AND operation. The strobe pulse synthesis circuit 117 generates a synthesized test strobe pulse TSTB-S. The logic level of the synthesized test strobe pulse TSTB-S changes from logic low to logic high synchronously with the latest logic level transition time among the logic level transition times of the first test strobe pulse TSTB1, the second test strobe pulse TSTB2, the third test strobe pulse TSTB3, and the fourth test strobe pulse TSTB4.

[0053] Figure 5 For example, Figure 4 The timing diagram shown illustrates the operation of the gating pulse synthesis circuit 117 according to an embodiment of the present disclosure.

[0054] like Figure 5 As shown, by Figure 3 The first test pattern TPT1, implemented as a PN driver, is driven by the first test driver 113-1. Figure 3 The second test pattern TPT2, implemented as an NN driver, is driven by the second test driver 113-2. Figure 3 The third test pattern TPT3, implemented as a PN driver, is driven by the third test driver 113-3 and is driven by... Figure 3 The logic level of the fourth test pattern TPT4, driven by the fourth test driver 113-4 implemented as an NN driver, changes at different points in time. This occurs when the first test pattern TPT1 is transmitted... Figure 3 The first test gating pulse TSTB1 generated at the first gating pulse line 115-1 is transmitted through the second test pattern TPT2. Figure 3 The second test gating pulse TSTB2 generated at the second gating pulse line 115-2 is transmitted through the third test pattern TPT3. Figure 3 The third test gating pulse TSTB3 generated at the third gating pulse line 115-3 and transmitted through the fourth test pattern TPT4 are also mentioned. Figure 3The logic level of the fourth test strobe pulse TSTB4, generated at the fourth strobe pulse line 115-4, changes at different time points. The synthesized test strobe pulse TSTB-S is generated synchronously with the latest logic level transition time T11 among the logic level transition times of the first test strobe pulse TSTB1, the second test strobe pulse TSTB2, the third test strobe pulse TSTB3, and the fourth test strobe pulse TSTB4, that is, the time point at which the logic level of the fourth test strobe pulse TSTB4 changes from logic high to logic low. In other words, all logic level transition times of the first test strobe pulse TSTB1, the second test strobe pulse TSTB2, and the third test strobe pulse TSTB3 occur before the time point at which the logic level of the fourth test strobe pulse TSTB4 changes from logic high to logic low. Therefore, in this example, the synthesized test strobe pulse TSTB-S is generated synchronously with the latest logic level transition time T11, which is the logic level transition time for the fourth test strobe pulse TSTB4. In another example, with Figure 5 Unlike the previous example, when the third test strobe pulse TSTB3 transitions to the latest time among the logic level transition times of the first test strobe pulse TSTB1, the second test strobe pulse TSTB2, and the fourth test strobe pulse TSTB4, the synthesized test strobe pulse TSTB-S is generated synchronously with the logic level transition time for the third test strobe pulse TSTB3.

[0055] Figure 6 For example, as shown Figure 2 The shown is a gating pulse comparison circuit 105 according to an embodiment of the present disclosure.

[0056] like Figure 6 As shown, the strobe pulse comparison circuit 105 includes a first strobe pulse delay circuit 131-1, a first calibration code latch circuit 133-1, a second strobe pulse delay circuit 131-2, a second calibration code latch circuit 133-2, a third strobe pulse delay circuit 131-3, and a third calibration code latch circuit 133-3.

[0057] The first gating pulse delay circuit 131-1 delays the clock gating pulse CLK-STB by a first unit delay period based on the power supply voltage VDD to generate a first-delayed gating pulse STB1D. The first gating pulse delay circuit 131-1 can be implemented as a resistor-capacitor (RC) delay circuit, but this is merely an example and not a limitation. The capacitor included in the first gating pulse delay circuit 131-1 can be implemented as a MOS transistor that receives the ground voltage VSS through its gate.

[0058] The first calibration code latch circuit 133-1 is electrically connected to the first gating pulse delay circuit 131-1 and receives the first delayed gating pulse STB1D from the first gating pulse delay circuit 131-1. The first calibration code latch circuit 133-1 generates the first bit CAL-CD of the calibration code based on the first delayed gating pulse STB1D and the synthesized test gating pulse TSTB-S. <0> The first calibration code latch circuit 133-1 latches the synthesized test gating pulse TSTB-S synchronously with the rising edge of the first delayed gating pulse STB1D, and outputs the latched synthesized test gating pulse TSTB-S as the first bit CAL-CD of the calibration code. <0> .

[0059] The second gating pulse delay circuit 131-2 delays the first delayed gating pulse STB1D by a second unit delay period based on the power supply voltage VDD to generate a second delayed gating pulse STB2D. The second gating pulse delay circuit 131-2 can be implemented as an RC delay circuit, but this is merely an example and not a limitation. The second unit delay period can be set to be the same as the first unit delay period, but this is also merely an example and not a limitation.

[0060] The second calibration code latch circuit 133-2 is electrically connected to the second gating pulse delay circuit 131-2 and receives the second-delayed gating pulse STB2D from the second gating pulse delay circuit 131-2. The second calibration code latch circuit 133-2 generates the second bit CAL-CD of the calibration code based on the second-delayed gating pulse STB2D and the synthesized test gating pulse TSTB-S. <1> The second calibration code latch circuit 133-2 latches the synthesized test gating pulse TSTB-S synchronously with the rising edge of the second delayed gating pulse STB2D, and outputs the latched synthesized test gating pulse TSTB-S as the second bit CAL-CD of the calibration code. <1> .

[0061] The third gating pulse delay circuit 131-3 delays the second-delayed gating pulse STB2D by a third unit delay period based on the power supply voltage VDD to generate a third-delayed gating pulse STB3D. The third gating pulse delay circuit 131-3 can be implemented as an RC delay circuit, but this is merely an example and not a limitation. The third unit delay period can be set to be the same as the first unit delay period, but this is also merely an example and not a limitation.

[0062] The third calibration code latch circuit 133-3 is electrically connected to the third gating pulse delay circuit 131-3 and receives the third-delayed gating pulse STB3D from the third gating pulse delay circuit 131-3. The third calibration code latch circuit 133-3 generates the third bit CAL-CD of the calibration code based on the third-delayed gating pulse STB3D and the synthesized test gating pulse TSTB-S. <2> The third calibration code latch circuit 133-3 latches the synthesized test gating pulse TSTB-S synchronously with the rising edge of the third delayed gating pulse STB3D, and outputs the latched synthesized test gating pulse TSTB-S as the third bit CAL-CD of the calibration code. <2> .

[0063] The gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the first delayed gating pulse STB1D generated by delaying the clock gating pulse CLK-STB by a first unit delay period, and inverts the latched synthesized test gating pulse TSTB-S to output the first bit of the calibration code CAL-CD. <0> The gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the second-delayed gating pulse STB2D, which is generated by delaying the first-delayed gating pulse STB1D by a second unit delay period. The latched synthesized test gating pulse TSTB-S is then inverted to output the second bit of the calibration code, CAL-CD. <1> The gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the third-delayed gating pulse STB3D, which is generated by delaying the second-delayed gating pulse STB2D by a third unit delay period, and inverts the latched synthesized test gating pulse TSTB-S to output the third bit of the calibration code CAL-CD. <2> . Figure 6 Only the first to third gating pulse delay circuits 131-1, 131-2, and 131-3 and the first to third calibration code latch circuits 133-1, 133-2, and 133-3, which generate the first to third bits of the calibration code CAL-CD<0:2>, are shown. However, the number of gating pulse delay circuits and the number of calibration code latch circuits can be increased proportionally to the number of calibration codes.

[0064] Figure 7 For example, Figure 6 The timing diagram shown illustrates the operation of the gating pulse comparator circuit 105 according to an embodiment of the present disclosure.

[0065] like Figure 7As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the first delayed gating pulse STB1D generated by delaying the clock gating pulse CLK-STB by a first unit delay period, and inverts the latched synthesized test gating pulse TSTB-S to generate the first bit CAL-CD of the logic high level (H) of the calibration code. <0> .

[0066] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the second-delayed gating pulse STB2D generated by delaying the first-delayed gating pulse STB1D by a second unit delay period, and inverts the latched synthesized test gating pulse TSTB-S to generate the second bit CAL-CD of the logic high level (H) of the calibration code. <1> .

[0067] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the third-delayed gating pulse STB3D, which is generated by delaying the second-delayed gating pulse STB2D by a third unit delay period, and inverts the latched synthesized test gating pulse TSTB-S to generate the third bit CAL-CD of the logic high level (H) of the calibration code. <2> .

[0068] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the fourth-delayed gating pulse STB4D generated by delaying the third-delayed gating pulse STB3D by a fourth unit delay period, and inverts the latched synthesized test gating pulse TSTB-S to generate the fourth bit CAL-CD of the logic high level (H) of the calibration code. <3> .

[0069] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the fifth-delayed gating pulse STB5D, which is generated by delaying the fourth-delayed gating pulse STB4D by a fifth unit delay period. The latched synthesized test gating pulse TSTB-S is then inverted to generate the fifth bit CAL-CD of the logic high level (H) of the calibration code. <4> .

[0070] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the sixth-delayed gating pulse STB6D generated by delaying the fifth-delayed gating pulse STB5D by a sixth unit delay period, and outputs the latched synthesized test gating pulse TSTB-S as the sixth bit CAL-CD of the logic high level (H) of the calibration code. <5> .

[0071] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the seventh-delayed gating pulse STB7D, which is generated by delaying the sixth-delayed gating pulse STB6D by a seventh unit delay period, and outputs the latched synthesized test gating pulse TSTB-S as the seventh bit CAL-CD of the logic high level (H) of the calibration code. <6> .

[0072] Unlike the first five bits of the calibration code, CAL-CD<0:4>, the sixth and seventh bits of the calibration code, CAL-CD<5:6>, are not generated by inverting the latched synthetic test strobe pulse TSTB-S. This is to ensure that the sixth and seventh bits of the calibration code, CAL-CD<5:6>, are generated within the logic high-level interval by increasing the sixth and seventh unit delay periods from the point when the logic level of the synthetic test strobe pulse TSTB-S transitions from logic low to logic high, thereby allowing signals such as data, commands, and addresses to be stably selected by the synthetic test strobe pulse TSTB-S.

[0073] like Figure 7 As shown, the gating pulse comparator circuit 105 synchronously latches the synthesized test gating pulse TSTB-S with the eighth-delayed gating pulse STB8D, which is generated by delaying the seventh-delayed gating pulse STB7D by an eighth unit delay period. The latched synthesized test gating pulse TSTB-S is then inverted to generate the eighth bit CAL-CD of the logic low level (L) of the calibration code. <7> .

[0074] Figure 8 For example, as shown Figure 1 The clock activation signal calibration circuit 15 shown is an example of this disclosure.

[0075] like Figure 8 As shown, the clock activation signal calibration circuit 15 includes a code decoder (CD DEC) 141 and a code delay circuit (CD DLY) 143.

[0076] Code decoder 141 decodes the selected calibration code SCAL-CD to generate a decoded code DEC-CD. The selected calibration code SCAL-CD includes multiple bits, and at least one of the bits included in the selected calibration code SCAL-CD can be activated to set a calibration delay period. For example, in the first to eighth bits of the selected calibration code SCAL-CD<0:7>, the first bit of the selected calibration code SCAL-CD <0> The calibration delay period can be activated to set the first delay period. As another example, in the first to eighth bits of the selected calibration code SCAL-CD<0:7>, the first and second bits of the selected calibration code SCAL-CD<0:1> can be activated to set the calibration delay period to the second delay period. The decoded code DEC-CD comprises multiple bits, and each bit included in the decoded code DEC-CD can be activated corresponding to multiple delay periods. For example, in the first to eighth bits of the decoded code DEC-CD<0:7>, the first bit of the decoded code DEC-CD... <0> This can be activated to set the calibration delay period to the first delay period. As another example, in the first to eighth bits of the decoded code DEC-CD<0:7>, the second bit of the decoded code DEC-CD... <1> It can be activated to set the calibration delay period as the second delay period.

[0077] Code delay circuit 143 is electrically connected to code decoder 141 to receive decoded code DEC-CD from code decoder 141. Code delay circuit 143 delays latch clock activation signal LCLK-EN based on decoded code DEC-CD to generate delayed clock activation signal CLK-End. Code delay circuit 143 delays latch clock activation signal LCLK-EN by a delay period set by decoded code DEC-CD to generate delayed clock activation signal CLK-ENd. For example, when only the second bit of the decoded code DEC-CD<0:7> is decoded in the first to eighth bits of the decoded code DEC-CD. <1> When activated, the code delay circuit 143 can generate a delayed clock activation signal CLK-ENd by setting the delay of the latched clock activation signal LCLK-EN to the calibration delay period of the second delay period.

[0078] Figure 9 It is shown, for example, as Figure 8 The table shown illustrates the operation of the code decoder 141 according to an embodiment of this disclosure.

[0079] like Figure 9As shown in the first line, the code decoder 141 converts the first to eighth bits of the selected calibration code corresponding to the first delay period, SCAL-CD<0:7>, to generate the first to eighth bits of the decoded code corresponding to the first delay period, DEC-CD<0:7>. More specifically, when only the first bit of SCAL-CD is received... <0> When the first to eighth bits of the selected calibration code SCAL-CD<0:7> are activated by the logic high level "H", the code decoder 141 generates only the first bit of DEC-CD. <0> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0080] like Figure 9 As shown in the second line, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the second delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the second delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which both the first and second bits SCAL-CD<0:1> are activated at logic high level "H", are received, the code decoder 141 generates only the second bit DEC-CD. <1> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0081] like Figure 9 As shown in the third line, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the third delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the third delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which the first to third bits SCAL-CD<0:2> are activated at the logic high level "H", are received, the code decoder 141 generates only the third bit DEC-CD. <2> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0082] like Figure 9As shown in the fourth line, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the fourth delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the fourth delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which the first to fourth bits SCAL-CD<0:3> are activated at the logic high level "H", are received, the code decoder 141 generates only the fourth bit DEC-CD. <3> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0083] like Figure 9 As shown in the fifth line, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the fifth delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the fifth delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which the first to fifth bits SCAL-CD<0:4> are activated at the logic high level "H", are received, the code decoder 141 generates only the fifth bit DEC-CD. <4> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0084] like Figure 9 As shown in the sixth line, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the sixth delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the sixth delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which the first to sixth bits of SCAL-CD<0:5> are activated at the logic high level "H", are received, the code decoder 141 generates only the sixth bit of the DEC-CD. <5> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0085] like Figure 9As shown in the seventh line, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the seventh delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the seventh delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which the first to seventh bits SCAL-CD<0:6> are activated at the logic high level "H", are received, the code decoder 141 generates only the seventh bit of the DEC-CD. <6> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0086] like Figure 9 As shown in line 8, the code decoder 141 converts the first to eighth bits of the selected calibration code SCAL-CD<0:7> corresponding to the eighth delay period to generate the first to eighth bits of the decoded code DEC-CD<0:7> corresponding to the eighth delay period. More specifically, when the first to eighth bits of the selected calibration code SCAL-CD<0:7>, in which all of the first to eighth bits of SCAL-CD<0:7> are activated at logic high level "H", are received, the code decoder 141 generates only the eighth bit of the DEC-CD. <7> The first to eighth bits of the decoded code, DEC-CD<0:7>, are activated when the logic high level "H" is activated.

[0087] Figure 10 For example, as shown Figure 8 The code delay circuit 143 shown is an embodiment of the present disclosure.

[0088] like Figure 10As shown, the code delay circuit 143 includes NAND gates 151-1, 151-2, 151-3, 151-4, 151-5, 151-6, 151-7, and 151-8. When only the first bit of the decoded code is in the DEC-CD... <0> When the logic high level is activated, the code delay circuit 143 sets the latch clock activation signal LCLK-EN to the calibration delay period of the first delay period through NAND gates 151-7 and 151-8 to generate the delayed clock activation signal CLK-ENd. When only the second bit of the decoded code DEC-CD... <1> When the logic high level is activated, the code delay circuit 143 sets the latch clock activation signal LCLK-EN to the calibration delay period of the second delay period through NAND gates 151-4, 151-5, 151-6, and 151-8 to generate the delayed clock activation signal CLK-ENd. When only the third bit of the decoded code, DEC-CD... <2> When the logic high level is activated, the code delay circuit 143 sets the latch clock activation signal LCLK-EN to the calibration delay period of the third delay period through NAND gates 151-1, 151-2, 151-3, 151-5, 151-6 and 151-8 to generate the delayed clock activation signal CLK-ENd.

[0089] exist Figure 10 In this paper, only NAND gates 151-1, 151-2, 151-3, 151-4, 151-5, 151-6, 151-7, and 151-8 are disclosed to delay one of the first to third delay periods of the latch clock activation signal LCLK-EN by using the first to third bits of the decoded code DEC-CD<0:2>. However, as the number of bits in the decoded code increases, NAND gates can be added to increase the delay period used to delay the latch clock activation signal LCLK-EN.

[0090] Figure 11 For example, Figure 1 The timing diagram shown illustrates the operation of the clock activation signal calibration circuit 15 and the clock calibration circuit 17 according to an embodiment of the present disclosure.

[0091] like Figure 11As shown, the clock activation signal calibration circuit 15 delays the latched clock activation signal LCLK-EN, which is activated at time T21, based on the selected calibration code SCAL-CD, to generate a delayed clock activation signal CLK-ENd, which is activated at time T22. In one embodiment, the clock activation signal calibration circuit 15 decodes the selected calibration code SCAL-CD to generate a decoded code DEC-CD, and delays the latched clock activation signal LCLK-EN by a calibration period (from time T21 to time T22) based on the decoded code DEC-CD to generate the delayed clock activation signal CLK-ENd. This prevents or mitigates glitches in the delayed clock activation signal CLK-ENd when the selected calibration code SCAL-CD is updated.

[0092] like Figure 11 As shown, after the delayed clock activation signal CLK-ENd is activated at time T22, the clock calibration circuit 17 delays the internal clock signals ICLK, QCLK, ICLKB, and QCLKB by a calibration period set by the selected calibration code SCAL-CD to generate internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C. Because the delayed clock activation signal CLK-ENd is generated by delaying the latched clock activation signal LCLK-EN by a calibration period, the delayed clock activation signal CLK-ENd is activated after the calibration code CAL-CD is updated. Therefore, in one embodiment, after the calibration code CAL-CD is updated by the delayed clock activation signal CLK-End, the clock calibration circuit 17 generates internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C by calibrating the internal clock signals ICLK, QCLK, ICLKB, and QCLKB. This prevents or mitigates glitches appearing in the internal clock signals ICLK, QCLK, ICLKB, and QCLKB due to the update of the calibration code CAL-CD, which are then included in the internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C. The internal calibration clock signals ICLK-C, QCLK-C, ICLKB-C, and QCLKB-C are generated sequentially after the delayed clock activation signal CLK-End is activated, and according to embodiments, they can be generated sequentially from multiple points in time.

[0093] Figure 12 The base die 2 is shown according to an embodiment of the present disclosure.

[0094] like Figure 12As shown, the basic die 2 includes a physical layer (PHY), a serial-to-parallel conversion circuit (PHYSER), alignment circuits 21-1, 21-2, 21-3, 21-4, 21-5 and 21-6, a via region (TSV), a direct access region (DA) and a logic circuit region (DARTL).

[0095] The physical layer (PHY) controls the interaction between the core die and the processor (e.g., Figure 13 Data, commands, and addresses between processors 49 in the system are transmitted through multiple channels. The Physical Layer (PHY) includes data control circuitry that controls data transmission through the multiple channels and command and address control circuitry that controls command and address transmission through the multiple channels. The Physical Layer (PHY) is used for high-speed data transmission, maintaining signal integrity, and low-power design in High Bandwidth Memory (HBM) systems.

[0096] The serial-to-parallel conversion circuit (PHYSER) converts the serial signal transmitted serially through the physical layer (PHY) into a parallel signal. The converted parallel signal is aligned by the alignment circuits 21-1, 21-2, 21-3, 21-4, 21-5 and 21-6, and then the converted and aligned parallel signal is transmitted to the via region (TSV). Figure 1 The internal clock generation circuit 1 shown can be disposed in alignment circuits 21-1, 21-2, 21-3, 21-4, 21-5, and 21-6. According to an embodiment, the internal clock generation circuit 1 can be disposed in some of the alignment circuits 21-1, 21-2, 21-3, 21-4, 21-5, and 21-6, and the selected calibration code SCAL-CD generated in the internal clock generation circuit 1 can be transmitted to the remaining alignment circuits 21-1, 21-2, 21-3, 21-4, 21-5, and 21-6. Alignment circuits 21-1, 21-2, 21-3, and 21-4 can be implemented as circuits for aligning data, while alignment circuits 21-5 and 21-6 can be implemented as circuits for aligning commands, addresses, and data; however, this is merely an example, and the present disclosure is not limited thereto. The position and number of alignment circuits 21-1, 21-2, 21-3, 21-4, 21-5, and 21-6 can be modified in various ways according to embodiments.

[0097] The via region (TSV) includes multiple vias connecting the base die 2 and multiple core dies, and transmits parallel signals from the serial-to-parallel converter (PHYSER) to the core dies, or outputs parallel signals from the core dies to the serial-to-parallel converter (PHYSER).

[0098] Direct access areas (DAs) include those used in the processor (e.g., Figure 13The processor 39 in the processor directly accesses the pads of the core die without going through the memory controller or the like. Signals for performing various tests (such as tests based on the IEEE 1500 standard) can be transmitted through the direct access area (DA). In one embodiment, the direct access area (DA) can provide low latency and high bandwidth, and can reduce power consumption.

[0099] The logic circuit region (DA RTL) is implemented as a register-transfer level (RTL) circuit and can control or test the core die stacked on top of the base die 2 (e.g., Figure 13 The operation of core die 321-1 to core die 321-L.

[0100] Figure 13 A storage system 3 according to an embodiment of the present disclosure is shown.

[0101] like Figure 13 As shown, the storage system 3 includes a printed circuit board (PCB) 31, a substrate 33, an interposer 35, a storage device 37, and a processor 39.

[0102] Printed circuit board 31 connects various electronic components to form an electronic circuit. The electronic circuit includes a storage system 3. A copper (Cu) layer, a solder mask, silkscreen printing, etc., are formed on the printed circuit board 31. Circuit paths for transmitting or carrying signals or electricity are formed in the copper (Cu) layer. In one embodiment, the solder mask prevents or mitigates damage to the circuit and protects specific areas of the soldered components. Silkscreen printing uses characters or symbols printed on the surface of the printed circuit board 31 to indicate the location or information of the electronic components.

[0103] A substrate 33 is disposed on a printed circuit board 31 (with bump pads therebetween, such as bump pad 311) and mechanically supports an interposer 35, a storage device 37, and a processor 39. The substrate 33 serves as the physical foundation of the printed circuit board 31 and is an insulator. The substrate 33 may include materials such as flame-retardant FR4 (an insulator made of glass fiber and epoxy resin), ceramics (which can withstand high temperatures, have suitable thermal conductivity, and are used in high-frequency circuits), and polyimide (which is used as a base material for flexible PCBs due to its flexibility).

[0104] Intermediate layer 35 is disposed on substrate 33 (with bump pads therein) and includes wiring connecting electronic components (e.g., storage device 37 and processor 39) that have mismatched size specifications or pin arrangements or different spacing. Intermediate layer 35 converts signals from different interfaces, such as Double Data Rate (DDR), High Bandwidth Memory (HBM), and Peripheral Component Interconnect High Speed ​​(PCIe).

[0105] Storage device 37 is disposed on interposer layer 35, with pads (e.g., microbump pads 313) therebetween. Storage device 37 stores data received from processor 39 or outputs stored data to processor 39 under the control of processor 39. Storage device 37 includes base die 320 and multiple core dies 321-1 to 321-L, where L is an integer greater than 1. Core dies 321-1 to 321-L are stacked on base die 320, with microbump pads therebetween. Base die 320 and core dies 321-1 to 321-L are perpendicularly connected to each other using vias and microbump pads. Base die 320 controls data transfer between processor 39 and core dies 321-1 to 321-L. Base die 320 receives input / output power supply voltage (drain voltage for I / O, also known as output stage drain power supply voltage) VDDQ as an operating voltage used during the operation of internal circuitry included in base die 320. The base die 320 receives the input / output power supply voltage VDDQ from the printed circuit board 31 via the substrate 33 and the interposer 35. The input / output power supply voltage VDDQ is the voltage supplied to the buffer transmitting data and is distinct from or different from the power supply voltage VDD. Core dies 321-1 to 321-L use the peripheral voltage VPERI as the operating voltage during the operation of the internal circuitry included in the core dies 321-1 to 321-L. Core dies 321-1 to 321-L generate the peripheral voltage VPERI from the input / output power supply voltage VDDQ received via the base die 320. Core dies 321-1 to 321-L generate the peripheral voltage VPERI at a voltage level lower than the input / output power supply voltage VDDQ and use the peripheral voltage VPERI as the operating voltage. Each of the core dies 321-1 to 321-L includes multiple channel regions, for example, eight or sixteen independently operating channel regions. Each of the multiple channel regions is assigned an independently operating channel for receiving or transmitting data. The number L of core dies 321-1 to 321-L can be four, eight, twelve, sixteen, etc. For example, when each of core dies 321-1 to 321-12 has eight channels, core dies 321-1 to 321-4, core dies 321-5 to 321-8, and core dies 321-9 to 321-12 each include thirty-two channel regions, and data is transmitted and received from processor 39 in units of rank (memory column) containing thirty-two channels.

[0106] In one embodiment, the base die 320 can be implemented as Figure 12 The base die 2 shown, and the base die 320 may include Figure 1The internal clock generation circuit 1 shown in the figure delays the clock activation signal based on the calibration code used to calibrate the internal clock signal to generate a delayed clock activation signal, and calibrates the internal clock signal according to the calibration code after the delayed clock activation signal is activated, thereby preventing or mitigating glitches in the calibrated internal clock signal.

[0107] The concepts have been disclosed in conjunction with various examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concepts of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. The scope of this disclosure is not limited to these descriptions. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A storage device, comprising: The calibration code generation circuit generates calibration codes based on the calibration test mode signal and the calibration clock signal; The code selection circuit selects one of the calibration code and the manual code as the selected calibration code based on the manual test mode signal; A clock activation signal calibration circuit that delays latching the clock activation signal based on the selected calibration code to generate a delayed clock activation signal; as well as A clock calibration circuit that calibrates an internal clock signal based on the selected calibration code and the delayed clock activation signal to generate an internal calibration clock signal.

2. The storage device according to claim 1, wherein, The calibration code generation circuit receives the calibration test mode signal, which is a test mode signal activated for calibration test operations.

3. The storage device according to claim 1, wherein, The calibration code generation circuit: Based on the calibration test mode signal and the calibration clock signal, a synthetic test gating pulse and a clock gating pulse are generated, and The synthetic test strobe pulse and the clock strobe pulse are compared to generate the calibration code.

4. The storage device according to claim 1, wherein, The calibration code generation circuit includes: A synthetic test gating pulse generation circuit generates a synthetic test gating pulse based on the calibration test mode signal and the calibration clock signal; A clock gating pulse generation circuit that generates a clock gating pulse based on the calibration test mode signal and the calibration clock signal; and A strobe pulse comparison circuit compares the synthesized test strobe pulse and the clock strobe pulse to generate the calibration code.

5. The storage device according to claim 4, wherein, The synthetic test gating pulse generation circuit: Based on the calibration clock signal, the calibration test mode signal is latched to generate multiple test patterns, and The multiple test patterns are synthesized to generate the synthesized test gating pulse.

6. The storage device according to claim 5, in, The synthetic test gating pulse generation circuit generates the first to fourth test patterns. In this test pattern, the logic level changes from logic low to logic high, and the first test pattern is driven by a PN driver, where PN can be PMOS or NMOS. In this test pattern, the logic level changes from logic low to logic high, and the second test pattern is driven by an NN driver, where NN is an NMOS transistor. In this process, the logic level of the third test pattern changes from logic high to logic low, and the third test pattern is driven by a PN driver. The logic level of the fourth test pattern changes from logic high to logic low, and the fourth test pattern is driven by an NN driver.

7. The storage device according to claim 6, wherein, The synthetic test gating pulse generation circuit includes: The first test input latch latches and outputs the calibration test mode signal based on the calibration clock signal; The second test input latch latches and outputs the inverted signal of the calibration test mode signal based on the calibration clock signal; The first test driver is implemented as a PN driver and drives the first test pattern based on the output signal of the first test input latch; The second test driver is implemented as an NN driver and drives the second test pattern based on the output signal of the first test input latch; A third test driver, implemented as a PN driver, drives the third test pattern based on the output signal of the second test input latch; and The fourth test driver, implemented as an NN driver, drives the fourth test pattern based on the output signal of the second test input latch.

8. The storage device according to claim 7, wherein, The synthetic test gating pulse generation circuit also includes: The first gating pulse line transmits the first test pattern as the first test gating pulse; The second gating pulse line transmits the second test pattern as the second test gating pulse; The third gating pulse line transmits the third test pattern as the third test gating pulse; The fourth gating pulse line transmits the fourth test pattern as the fourth test gating pulse; and A gating pulse synthesis circuit generates the synthesized test gating pulse based on the first test gating pulse, the second test gating pulse, the third test gating pulse, and the fourth test gating pulse.

9. The storage device according to claim 8, wherein, The gating pulse synthesis circuit generates the synthesized test gating pulse, which includes a logic level that changes synchronously with the latest logic level transition time among the logic level transition times of the first test gating pulse, the second test gating pulse, the third test gating pulse, and the fourth test gating pulse.

10. The storage device according to claim 4, wherein, The clock gating pulse generation circuit: When the calibration test mode signal is activated, the calibration clock signal is delayed by a preset clock delay period to generate a delayed calibration clock signal; as well as The clock strobe pulse is generated in sync with the delayed calibration clock signal.

11. The storage device according to claim 4, wherein, The gating pulse comparison circuit: The clock gating pulses are sequentially delayed by unit delay periods to generate multiple delayed gating pulses; as well as The synthesized test gating pulse is latched synchronously with each of the plurality of delayed gating pulses to generate the calibration code.

12. The storage device according to claim 4, wherein, The gating pulse comparison circuit includes: A first gating pulse delay circuit delays the clock gating pulse by a first unit delay period to generate a gating pulse with a first delay. A first calibration code latching circuit latches the synthetic test strobe pulse based on the first delayed strobe pulse, and outputs the synthetic test strobe pulse as the first bit of the calibration code. A second gating pulse delay circuit delays the first delayed gating pulse by a second unit delay period to generate a second delayed gating pulse; and The second calibration code latching circuit latches the synthetic test strobe pulse based on the strobe pulse of the second delay, and outputs the synthetic test strobe pulse as the second bit of the calibration code.

13. The storage device according to claim 12, wherein, The gating pulse comparison circuit sets the first unit delay period and the second unit delay period to be substantially the same.

14. The storage device according to claim 1, wherein, The clock activation signal calibration circuit includes: A code decoder that decodes the selected calibration code to generate a decoded code; and A code delay circuit that delays the latch clock activation signal based on the decoded code to generate the delayed clock activation signal.

15. The storage device according to claim 14, wherein, The code decoder generates the decoded code, which includes bits from a binary bit group that is configured differently from the bit group included in the selected calibration code.

16. The storage device according to claim 14, wherein, The code delay circuit: When the first bit of the decoded code is activated, the latch clock activation signal is delayed by a first delay period to generate the delayed clock activation signal. When the second bit of the decoded code is activated, the latch clock activation signal is delayed by a second delay period to generate the delayed clock activation signal.

17. The storage device according to claim 1, wherein, After the delayed clock activation signal is activated, the clock calibration circuit delays the internal clock signal by a calibration delay period set by the selected calibration code to generate the internal calibration clock signal.

18. A storage system, comprising: The base die and multiple core dies are set above the intermediary layer. The base die includes: The calibration code generation circuit generates calibration codes based on the calibration test mode signal and the calibration clock signal; The code selection circuit selects one of the calibration code and the manual code as the selected calibration code based on the manual test mode signal; A clock activation signal calibration circuit that delays and latches the clock activation signal based on the selected calibration code to generate a delayed clock activation signal; and A clock calibration circuit that calibrates an internal clock signal based on the selected calibration code and the delayed clock activation signal to generate an internal calibration clock signal.

19. The storage system according to claim 18, wherein, The calibration code generation circuit: Based on the calibration test mode signal and the calibration clock, a synthetic test gating pulse and a clock gating pulse are generated, and The test strobe pulse and the clock strobe pulse are compared to generate the calibration code.

20. The storage system according to claim 18, wherein, The calibration code generation circuit includes: A synthetic test gating pulse generation circuit generates a synthetic test gating pulse based on the calibration test mode signal and the calibration clock signal; A clock gating pulse generation circuit that generates a clock gating pulse based on the calibration test mode signal and the calibration clock signal; and A strobe pulse comparison circuit compares the synthesized test strobe pulse and the clock strobe pulse to generate the calibration code.

21. The storage system according to claim 18, wherein, The clock activation signal calibration circuit includes: A code decoder that decodes the selected calibration code to generate a decoded code; and A code delay circuit that delays the latch clock activation signal based on the decoded code to generate the delayed clock activation signal.

22. The storage system according to claim 21, wherein, The code decoder generates the decoded code, which includes bits from a binary bit group that is configured differently from the bit group included in the selected calibration code.

23. The storage system according to claim 21, wherein, The code delay circuit: When the first bit of the decoded code is activated, the latch clock activation signal is delayed by a first delay period to generate the delayed clock activation signal. When the second bit of the decoded code is activated, the latch clock activation signal is delayed by a second delay period to generate the delayed clock activation signal.

24. The storage system according to claim 18, wherein, After the delayed clock activation signal is activated, the clock calibration circuit delays the internal clock signal by a calibration delay period set by the selected calibration code to generate the internal calibration clock signal.

25. A storage system, comprising: The base die controls multiple core dies. The base die includes: The physical layer uses multiple channels between the core die and the processor to control the transmission of data, commands, and addresses; and A serial-to-parallel conversion circuit converts a serial signal transmitted serially through the physical layer into a parallel signal, aligns the converted parallel signal using multiple alignment circuits, and then transmits the parallel signal to the via region. At least one of the plurality of alignment circuits includes an internal clock generation circuit, which: generates a calibration code based on a calibration test mode signal and a calibration clock signal; delays a latched clock activation signal based on the calibration code to generate a delayed clock activation signal; and calibrates an internal clock signal based on the calibration code to generate an internal calibration clock signal.

26. The storage system according to claim 25, wherein, The calibration code generated from at least one of the plurality of alignment circuits is transmitted to the remaining alignment circuits of the plurality of alignment circuits.

27. The storage system according to claim 25, wherein, The internal clock generation circuit includes: A calibration code generation circuit generates the calibration code based on a calibration test mode signal and a calibration clock signal; A clock activation signal calibration circuit that delays and latches the clock activation signal based on the calibration code to generate a delayed clock activation signal; and A clock calibration circuit that calibrates the internal clock signal based on the calibration code and the delayed clock activation signal to generate the internal calibration clock signal.

28. The storage system according to claim 27, wherein, The calibration code generation circuit: Based on the calibration test mode signal and the calibration clock signal, a synthetic test gating pulse and a clock gating pulse are generated, and The synthetic test strobe pulse and the clock strobe pulse are compared to generate the calibration code.

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