Methods, apparatuses, and media for implementing logically time-multiplexed memory
Patent Information
- Application Number
- CN202511206927.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-04-01
- Filing Date
- 2025-08-27
- Publication Date
- 2026-10-23
Smart Images
Figure CN122967700A_ABST
Abstract
Description
Technical Field
[0001] This invention generally relates to systems and methods for designing logic circuits. Background Technology
[0002] Digital logic is typically described using specialized programming languages, often referred to as hardware description languages (HDLs), such as Verilog and the Very High Speed Integrated Circuit Hardware Description Language (VHDL). Other types of programming, on the other hand, describe the components of a design as instances of sub-designs, such as individual HDL code files. This helps designers abstract design elements, enabling the implementation of complex architectures. Summary of the Invention
[0003] This invention provides a method for implementing a logical time-division multiplexed memory, the method comprising: receiving an original design by a computer system, the original design including an original memory having a first capacity and including a first address input and a first read output, the first address input having a first address width; generating a time-division multiplexed design by the computer system based on the original design, the time-division multiplexed design including N instances of time-division multiplexed memory based on the original memory, where N is an integer, the time-division multiplexed memory including: a second capacity, the second capacity being 2^C times the first capacity, where C equals ceil(log2(N)); a second address input, the second address input having a second address width, the second address width being the first address width plus C; a second read output, the second read output being configured to output data read from the time-division multiplexed memory; and a chain of N registers, each register having an input and an output, the input of the first register in the chain of N registers being coupled to the second read output, and the inputs of the remaining N-1 registers in the chain of N registers being coupled to the output of the preceding register in the chain of N registers, respectively.
[0004] In one embodiment of the present invention, the time-division multiplexing design further includes a C bit mod N free running counter, which is coupled to the most significant bit of the second address input.
[0005] In one embodiment of the present invention, the original memory has a first write address input, a first write enable input, and a write data input, the first write address input having a first address width; and the time-division multiplexed memory has a second write address input, the second write address input having a second address width, and the C-bit modulo N free-running counter is coupled to the most significant bit of the second write address input.
[0006] In one embodiment of the present invention, the original design further includes combinational logic, and the time-division multiplexing design also includes the combinational logic.
[0007] In one embodiment of the invention, the time-division multiplexing design includes the combinational logic coupled to the output of the penultimate register in the chain of the N registers; the original memory includes a first read enable input, the combinational logic being coupled to the first read enable input in the original design; the time-division multiplexed memory includes a second read enable input coupled to the combinational logic; and the time-division multiplexing design includes a multiplexer having a selection input coupled to the second read enable input, a first input coupled to the second read output, and a second input coupled to the output of the last register in the chain of the N registers, the output of the multiplexer being coupled to the input of the first register in the chain of the N registers.
[0008] In one embodiment of the invention, the selection input of the multiplexer is coupled to the second read enable input via a flip-flop, the input of the flip-flop is coupled to the second read enable input, and the output of the flip-flop is coupled to the selection input of the multiplexer. The flip-flop and the time-division multiplexed memory each have a clock input coupled to a common clock signal.
[0009] In one embodiment of the invention, the original memory includes a first read enable input, the combinational logic being coupled to the first read enable input in the original design; the time-division multiplexed memory includes a second read enable input coupled to the combinational logic; and the time-division multiplexed design includes a multiplexer having a selection input coupled to the second read enable input, a first input coupled to the second read output, and a second input coupled to the output of the last register in the chain of the N registers, the output of the multiplexer being coupled to the input of the first register in the chain of the N registers and coupled to the combinational logic.
[0010] In one embodiment of the present invention, the combinational logic includes a plurality of logic gates, the logic gates including at least one of AND, NAND, OR, NOR, XOR, and XNOR.
[0011] In one embodiment of the present invention, the original design and the time-division multiplexing design each include one or more hardware description language files, and the method further includes: generating a netlist based on the time-division multiplexing design; generating a physical layout based on the netlist; and manufacturing an application-specific integrated circuit (ASIC) that implements the time-division multiplexing design.
[0012] In one embodiment of the present invention, the original design and the time-division multiplexing design each include one or more hardware description language files, and the method further includes: generating a netlist based on the time-division multiplexing design; and programming the gates of the field-programmable gate array to implement the netlist.
[0013] The present invention also provides an apparatus for implementing a logical time-division multiplexed memory, the apparatus comprising: an N-instance time-division multiplexing device, the N-instance time-division multiplexing device including a memory having an address input and a read output, the address input being configured to receive an address, the read output being configured to output data read from the memory; and a chain of N registers, each register having an input and an output, the input of the first register in the chain of N registers being coupled to the read output, and the inputs of the remaining N-1 registers in the chain of N registers being coupled to the output of the preceding register in the chain of N registers, respectively.
[0014] The present invention also provides a non-transitory computer-readable medium for storing executable code, which, when executed by one or more processing devices, causes the one or more processing devices to: receive an original design, the original design including an original memory having a first capacity and including a first address input and a first read output, the first address input having a first address width; generate a time-division multiplexing design based on the original design, the time-division multiplexing design including N instances of time-division multiplexing memory based on the original memory, where N is an integer, the time-division multiplexing memory including: a second capacity, the second capacity being 2^C times the first capacity, where C equals ceil(log2(N)); a second address input, the second... The address input has a second address width, which is the first address width plus C; a second read output configured to output data read from the time-division multiplexed memory; a chain of N registers, each register having an input and an output, the input of the first register in the chain of N registers coupled to the second read output, and the inputs of the remaining N-1 registers in the chain of N registers respectively coupled to the output of the preceding register in the chain of N registers; a C-bit modulo N free-running counter coupled to the most significant bit of the second address input; and combinational logic coupled to the second address input and the second read output. Attached Figure Description
[0015] To facilitate understanding of the advantages of the present invention, a more detailed description of the invention, briefly described above, will be provided in conjunction with the specific embodiments shown in the accompanying drawings. It should be understood that these drawings depict only typical embodiments of the invention and should not be considered as limiting its scope. The present invention will be described and explained in more specific and detailed manner in conjunction with the accompanying drawings, in which:
[0016] Figure 1 This is a simplified representation of a digital logic design that can be converted using logical time-division multiplexing (TDM) according to an embodiment of the present invention;
[0017] Figure 2 This is a schematic block diagram illustrating the conversion of the state of a digital logic design into multiple logic TDM states according to an embodiment of the present invention.
[0018] Figure 3 A schematic block diagram of a logic TDM design according to an embodiment of the present invention;
[0019] Figure 4A A schematic diagram illustrating a first method for implementing a logic TDM design of a memory according to an embodiment of the present invention;
[0020] Figure 4B A schematic diagram illustrating a second method for implementing a logic TDM design according to an embodiment of the present invention;
[0021] Figure 5 A schematic block diagram illustrating the bridging logic for logic TDM design according to an embodiment of the present invention;
[0022] Figure 6 To illustrate the functional timing diagram of the bridging logic for logic TDM design according to an embodiment of the present invention;
[0023] Figure 7 This is a schematic block diagram of a computing device that can be used to implement the systems and methods described herein. Detailed Implementation
[0024] It is readily understood that, as generally described and illustrated in the accompanying drawings, the components of the present invention can be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of the embodiments of the invention shown in the drawings is not intended to limit the scope of the invention as claimed, but is merely representative of certain examples of embodiments presently contemplated according to the invention. The embodiments currently described will be better understood with reference to the accompanying drawings, wherein the same components are consistently indicated by the same numbers.
[0025] This invention was developed based on the existing level of technology, and in particular, it was developed to address problems and needs that have not yet been fully solved by existing equipment and methods.
[0026] Embodiments of the present invention can be embodied as devices, methods, or computer program products. Therefore, the invention can be implemented entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or in a combination of software and hardware aspects, collectively referred to herein as "modules" or "systems." Furthermore, the invention can also take the form of a computer program product embodied in any tangible medium containing computer-usable program code.
[0027] Any combination of one or more computer-usable or computer-readable media can be used. For example, a computer-readable medium may include one or more of a portable computer floppy disk, a hard disk, a random access memory (RAM) device, a read-only memory (ROM) device, an erasable programmable read-only memory (EPROM or flash memory) device, a portable optical disc read-only memory (CDROM), an optical storage device, and a magnetic storage device. In selected embodiments, a computer-readable medium may include any non-transitory medium that can contain, store, communicate, propagate, or transmit programs for use by or in conjunction with an instruction execution system, device, or apparatus.
[0028] The implementation can also be carried out in a cloud computing environment. In this specification and the claims below, "cloud computing" can be defined as a model for enabling ubiquitous, convenient, and on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services), which can be rapidly configured through virtualization, published with minimal management effort or service provider interaction, and then scaled accordingly. The cloud model can include various features (e.g., on-demand self-service, extensive network access, resource pooling, rapid elasticity, and measurable services), service models (e.g., Software as a Service (“SaaS”), Platform as a Service (“PaaS”), and Infrastructure as a Service (“IaaS”)), and deployment models (e.g., private cloud, community cloud, public cloud, and hybrid cloud).
[0029] The computer program code used to perform the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++, etc., and traditional procedural programming languages such as the "C" programming language or similar programming languages. The program code can be executed entirely on the computer system as a standalone software package, or on a standalone hardware unit, or partially on a remote computer located at a distance from the computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the computer via any type of network, including local area networks (LANs) or wide area networks (WANs), or it can be connected to an external computer (e.g., via the Internet provided by an Internet service provider).
[0030] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions or code. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in the flowchart illustrations and / or one or more block diagram blocks.
[0031] refer to Figure 1Digital logic designs can be described using programming languages used to describe electronic circuits, such as hardware description languages (HDLs). For example, Verilog, VHDL, or other HDLs can be used to define digital logic designs. Digital logic designs can describe logic that can be implemented using features formed in an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) configuration, or other types of configurable hardware device configuration.
[0032] The method described in this paper is particularly applicable to single-clock-driven digital designs (SCDDs) 100. Most SCDDs 100 are characterized by having combinational logic 102 that receives inputs and generates outputs based on a logical function of the inputs. The combinational logic 102 does not have persistent states, but only generates outputs based on the inputs after a signal has propagated through the combinational logic 102 for a period of time.
[0033] The SCDD 100 may also feature a data memory capable of storing multiple states set by combinational logic 102 and persisting from one clock cycle to the next. In the example shown, each state in the data memory is represented as a flip-flop (FF), for example, s flip-flops FF[0] to FF[s-1] shown, each flip-flop having a data input D, a clock input CK, and an output Q. At each clock cycle (e.g., at each rising edge), each flip-flop FF changes its state, causing the output Q to become the level of the input D (1 or 0), and holds that state until the level of the data input D changes at the next rising edge. In the example described herein, it is assumed that the state changes in response to a rising edge, but it should be understood that a design with a falling edge transition will operate in a similar manner.
[0034] In SCDD 100, for each FF[i], the state input D, i = 0 to s-1, is coupled to the state interface output dbit[i], i = 0 to s-1, from combinational logic 102. Therefore, in response to the rising edge of the clock line clk connected to the clock input CK of FF[i], the value of the assert bit on dbit[i] is stored as its state. Furthermore, the state output Q of each FF[i] is connected to the corresponding state interface input qbit[i], i = 0 to s–1, from combinational logic 102.
[0035] The combinational logic 102 also receives one or more input bits (interface_in) from a source outside the SCDD and generates one or more output bits (interface_out) for the receiving device outside the SCDD. The number of input bits (num_of_input_bits) and output bits (num_of_output_bits) can be arbitrary.
[0036] Combinational logic 102 can perform logical operations (AND, OR, NAND, NOR, MUX, etc.) on the input bits interface_in and qbit[i]. The combinational logic generates output signals on interface_out and dbit[i]. The value currently set on dbit[i] is stored by FF[i] in response to the rising edge of the clock line clk.
[0037] The illustrated SCDD 100 is a simplified abstraction of any SCDD. Components implementing combinational logic 102 and flip-flops FF[i] can be distributed throughout the digital logic design, including different sub-design instances incorporated into the digital logic design. However, any SCDD can be characterized by an architecture with the illustrated SCDD 100.
[0038] In some digital logic designs, there may be multiple instances (N) of the same SCDD 100. Therefore, fully instantiating each SCDD 100 would result in instantiating the same combinational logic 102 and flip-flops FF[i] N times. This consumes silicon area, FPGA gates, or space in any device used to implement the digital logic design. In some applications, such as embedded devices, space is limited. Using the method described in this paper, N instances of SCDD 100 can be converted into logic time-division multiplexed (TDM) SCDDs, which significantly reduce space consumption, use fewer gates, or otherwise improve performance.
[0039] Figure 2 A method is shown to convert a design of SCDD 100 into a design containing N logical time-division multiplexing (TDM) SCDD instances (“TDM Design 200”). TDM Design 200 contains a single instance of combinational logic 102. For each flip-flop FF[i] in SCDD 100, the design will contain a set of N flip-flops FF[i][j], j = 0 to N–1. This set of N flip-flops FF[i][j] can be arranged in a flip-flop chain. For example, the input D of the first flip-flop FF[i][0] is connected to the output dbit[i] of the combinational logic 102, and the input D of the remaining flip-flops is connected to the output of the previous flip-flop: the input D of flip-flop FF[i][j] is connected to the output Q of flip-flop FF[i][j-1]. The output Q of the last flip-flop FF[i][N-1] is connected to the input qbit[i] of the combinational logic.
[0040] The clock input CK of the flip-flop FF[i][j] is connected to the divided clock signal clkNx, a modified version of the TDM Design 200 external clock, where each external clock cycle corresponds to N clock cycles. In one aspect, the clock signal clkNx is generated by a clock multiplier that accepts an external clock as input. This clock multiplier may include, for example, a phase-locked loop (PLL) to ensure that the external clock signal and the clkNx signal are substantially phase aligned.
[0041] refer to Figure 3 In TDM Design 200, the output of combinational logic 102 at any given time will be a function of the output Q of the last flip-flop FF[i][N-1] and the signal on the external input interface_in. The output of combinational logic 102 at any given time will be set on the external output interface_out. The output of dbit[i] will be stored in the first flip-flop FF[i][0] on each rising edge of the divided clock clkNx. A bridging circuit can be used (see...). Figure 6 and Figure 7 The outputs of combinational logic 102 are combined into a set of outputs, which correspond to N instances of SCDD 100 implemented by TDM design 200.
[0042] from Figure 2 and Figure 3 As can be seen, the N flip-flops FF[i][j], j = 0 to N-1, pass the state from the first flip-flop FF[i][0] to the last flip-flop FF[i][N-1] over N clock cycles, such that the input latched into the first flip-flop FF[i][0] in clock cycle C[0] will be output from the output Q of the last flip-flop FF[i][N-1] in clock cycle C[N]. Therefore, every Nth clock cycle, the input (interface_in and qbit[i]) and output (interface_out and dbit[i]) of combinational logic 102 will correspond to the same instance j of SCDD 100, and the value latched into the first flip-flop FF[i][0] in every Nth clock cycle will also correspond to instance j.
[0043] refer to Figure 4ASome SCDD 100s may include memory for storing values at addresses from which those values can be read. In its simplest form, the memory can be implemented as an array of flip-flops as described above. In other applications, the memory may be random access memory (RAM) 400a, which stores data at addresses within RAM 400a and reads data from addresses within RAM 400a. In the implementation shown, RAM 400a stores data in a word width of Dwidth (e.g., 8 bits, 16 bits, 32 bits, 64 bits, or other bit widths). RAM 400a includes a data input wData for receiving data written to RAM 400a and a data output rData for outputting data read from RAM 400a. RAM 400a may include a write enable input Wr_en, a read enable input Rd_en, a write address input wAddr[K-1:0] (where K is the number of bits per address), a read address input rAddr[K-1:0], and a clock input CK.
[0044] When the write enable input Wr_en is set, in response to the rising edge of the clock input CK, the data stored on wData is stored at address wAddr[K-1:0] in RAM 400a. When a rising clock edge is received on the clock input CK and the read enable input Rd_en is set, the data stored at address rAddr[K-1:0] in RAM 400a is retrieved, and when the next rising clock edge is received on the clock input CK, it is output to the data output rData.
[0045] RAM 400a can be modified to obtain RAM 400b used in TDM design 200, and other components shown in TDM design 200 can be used to enable RAM 400b to be used with a single instance of combinational logic 102.
[0046] RAM 400b can be modified relative to RAM 400a in some or all of the following ways:
[0047] The capacity of RAM can be increased from 2^K to 2^(K+C), where C is ceil(log2(N)).
[0048] (That is, the original capacity multiplied by 2^C).
[0049] • The widths of the read address input rAddr and the write address input wAddr can be increased from K to K+C (rAddr[K-1:0] increases to rAddr[C+K-1:0], wAddr[K-1:0] increases to wAddr[C+K-1:0]).
[0050] Apart from these modifications, RAM 400b functions identically to RAM 400a. Therefore, TDM design 200 can use pre-defined wrappers defined in a pre-defined design library available to designers.
[0051] The write data input wData and the read data output rData can remain unchanged, for example, having the same width Dwidth. The input to the read address input rAddr can be a concatenation of the output of counter 402 and the read address output of combinational logic 102, with the most significant bit (MSB) of the concatenation serving as the output of counter 402. Similarly, the input to the write address input wAddr can be a concatenation of the output of counter 402 and the write address output of combinational logic 102, with the most significant bit (MSB) of the concatenation serving as the output of counter 402.
[0052] Counter 402 can be a free-running counter with modulo-N operations. The output O of counter 402 increments on each rising edge of the divided clock clkNx received by the clock input CK of counter 402 until it reaches N-1, at which point output O returns to 0 on the next rising edge. Output O can be C bits wide.
[0053] RAM 400a is expected to function such that: (a) after receiving a rising clock edge with the read enable input Rd_en set, the read data becomes available on the output rData on the next rising clock edge; and (b) the data remains available until the read enable input Rd_en is set again during the rising clock edge. Therefore, TDM design 200 may include components to ensure that RAM 400b correctly performs these functions for each instance of TDM design 200.
[0054] For example, there can be N registers R[j], j = 0 to N-1. Register R[j] can be viewed as an array of flip-flops with input D, output Q, and clock input CK, where the number of flip-flops in each array is equal to Dwidth. Therefore, upon receiving the rising edge of clock input CK, the value on the D input of the array is latched and output to output Q until a different value appears on input D during the rising edge of clock input CK. The input D of each register R[j], j = 1 to N-1, is coupled to the output Q of the previous register R[j-1].
[0055] The input D of register R[0] can be coupled to the output of multiplexer 404. The select line of multiplexer 404 can be coupled to the output Q of flip-flop 406. The input D of flip-flop 406 can be coupled to the read enable input Rd_en of RAM 400b. Flip-flop 406 also includes a clock input CK, which is coupled to the divided clock clkNx.
[0056] The inputs of multiplexer 404 can be coupled to the read data output rData (e.g., coupled to input 1 of multiplexer 404) and the output Q of the last register R[N-1] (e.g., coupled to input 0 of multiplexer 404).
[0057] The following will refer to the rising edges 0 to N and rising edge ax N of the divider clock clkNx, where a is an integer, to describe the operation of TDM design 200 relative to RAM 400b.
[0058] When the combinational logic sets the read enable input Rd_en on the rising edge (rising edge 0) of the divider clock clkNx, flip-flop 406 latches the set bit to its output Q, and RAM 400b performs data reading at the cascaded address of the output O of counter 402 and the address set on the read address input rAddr. The read data will be set to the read data output rData on the next rising edge (rising edge 1) of the divider clock clkNx.
[0059] Since the output of flip-flop 406 is set (e.g., 1) in response to the previously set read enable input Rd_en, the select line input of multiplexer 404 passes the select 1 input to the first register R[0], i.e., the output value of the read data output rData. The first register R[0] then latches this value to its output Q in response to a rising edge 1. Upon receiving the second clock edge, if combinational logic 102 has not set the read enable input, flip-flop 406 latches 0 to its output Q, thereby switching multiplexer 404 to select the 0 input (the output of the last register R[N-1]).
[0060] With each subsequent rising edge (rising edge 2 to N-1) of the divided clock clkNx, the data latched into the first register R[0] will be passed along registers R[1] to R[N-2]. Therefore, when rising edge N-1 occurs, the read data will be located at the output Q of register R[N-2] (the penultimate register) and input to combinational logic 102, replacing the read data output rData of RAM 400b. When rising edge N occurs, the read data will be located at Q of the last register R[N-1]. If the output of flip-flop 406 is 0 when rising edge N is received (the read enable input Rd_en was not set at the previous rising edge N-1), then the 0 input of multiplexer 404 is selected, and the output Q of the last register R[N-1] will be latched into the first register R[0] when rising edge N+1 occurs.
[0061] Therefore, if the read enable input Rd_en is not set on rising edge N or another rising edge ax N, the read data will continue to be passed along register R[0] to R[N] and from R[N] to R[0]. Thus, the read data will be at the output of register R[N-2] on each rising edge ax N of the divided clock clkNx, until the rising edge (a+1)x N after the read enable input Rd_en is set during rising edge ax N. This process repeats when the read enable input Rd_en is set on a rising edge ax N following rising edge 0, for example, in subsequent iterations of the above process, the rising edge will be rising edge 0.
[0062] refer to Figure 4B Some RAM 400a modules may output data on the read output rData within the same clock cycle, with the read enable line Rd_en set at the rising edge of that clock cycle. For such applications, the TDM design 200 can be modified for RAM 400b. Modifications to RAM 400b relative to RAM 400a can be made with... Figure 4A The implementation method is the same. Similarly, Figure 4B Components with the same number can be arranged according to Figure 4A The description in the document is as follows.
[0063] exist Figure 4B In this implementation, the flip-flop 406 can be omitted, and the output of the multiplexer 404 can be input to the combinational logic 102 as the read data output from the read data output rData. The selection line of the multiplexer 404 can be coupled to the read enable input Rd_en. Therefore, when the read enable input Rd_en is set, input 1 of the multiplexer 404 is coupled to the output, i.e., the read data from the read data output rData.
[0064] The output of multiplexer 404 is also coupled to the input D of the first register R[0]. Therefore, when the read enable input Rd_en is set and a rising edge of the clock is received, the read data will be latched into the first register R[0]. When the read enable input Rd_en is not set, the 0 input of multiplexer 404 will be coupled to the output, that is, the output of the last register R[N-1] will be coupled to the input of the first register R[0]. When the read enable input Rd_en is not set, the output of the last register will be latched into the first register R[0] when a rising edge of the clock is received. Therefore, the read data will cycle between registers R[0] and R[N-1] and be output from multiplexer 404 every Nth clock cycle until the read enable input Rd_en is set during the rising edge of the clock.
[0065] refer to Figure 5Multiple instances of SCDD 100 can be used in conjunction with design interface 500a, which provides clock signals and inputs in0 to in(n-1) to each instance of SCDD 100 (e.g., the interface_in line of each SCDD 100) and receives outputs out0 to out(n-1) from each instance of SCDD 100 (e.g., the interface_out line of each SCDD 100).
[0066] Design interface 500a can be modified to implement design interface 500b for use with TDM design 200, thereby replacing multiple instances of SCDD. Design interface 500b may include input bridge circuit 502, which receives inputs in0 to in(n-1) of the multiple instances of SCDD 100 replaced by TDM design 200, and outputs outputs out0 to out(n-1) of the multiple instances of SCDD 100 replaced by TDM design 200. Design interface 500b can receive or generate an external clock clk, and receive or generate a divided clock clkNx. The operation of input bridge circuit 502 and output bridge circuit 504 will be described below. Figure 6 The timing diagram is described in detail.
[0067] refer to Figure 6 The input lines in0 to in(n-1) can be respectively fed on the rising edge of the external clock clk (e.g., clock period t in the example shown) to input data D0(t) to D... n-1 (t) is set. D0(t) to D n-1 Each of the values in (t) can be a set of S values, where S is the number of lines in the interface_in of SCDD 100.
[0068] The input bridging circuit 502 can bridge the input data D0(t) to D throughout the entire clock cycle. n-1 (t) can be stored, or the interface 500b can be designed to allow input data D0(t) to be stored to D n-1 (t) is held in place by an external component throughout the entire clock cycle.
[0069] The input bridging circuit 502 sequentially transmits the input data D0(t) to D at the rising edge of the frequency divider clock clkNx. n-1 (t) is set to the input of TDM Design 200 (e.g., interface_in), thereby passing the input data D0(t) to D n-1(t) Serialization. For example, on each of the next N rising edges of clkNx, where the first rising edge occurs simultaneously with the rising edge of the external clock clk (e.g., within 2ms), the input bridge circuit 502 can output from the input data D0(t) to D n-1 Another set of input data for (t): rising edge 0 -> output D0(t); rising edge 1, output D1(t), ... rising edge N-1, output D n-1 (t).
[0070] The output bridge circuit 504 deserializes the output data Q0(t) from the TDM design 200 into Q on each rising edge of the divided clock clkNx. n-1 (t)(e.g., interface_out). Therefore, the output bridge circuit 504 can include a register (B i (i = 0 to N-1) to be used for each SCDD instance implemented by TDM Design 200. For example, for each of the N rising edges of the divided clock, the output bridge circuit 504 can sequentially store the output of TDM Design 200 in different output registers: rising edge 0, stored in B0; rising edge 1, stored in B1, ... rising edge N-1, stored in B... N-1 middle.
[0071] The output register can output on the last rising edge of N rising edges, for example, rising edge n-1, i.e., the last output Q. n-1 The rising edge of (t) is active and sets the outputs (out0 to out(n-1)) of the bridge circuit. Therefore, the outputs Q0(t) to Q n-1 (t) can be latched into the memory element downstream of the design interface on the next rising edge of the external clock (e.g., clock cycle t+1).
[0072] As described above, SCDD 100 can be automatically converted into TDM design 200, which contains only one instance of combinational logic 102. Therefore, TDM design 200 will occupy less silicon area, use fewer FPGA gates, or use fewer resources of any type of device to implement TDM design 200.
[0073] According to any of the embodiments disclosed herein, the TDM design 200 can be in the form of an HDL file or other programming language used to describe circuit designs. The TDM design 200 can then be converted into a netlist, which in turn is converted into a physical layout of transistors. This physical layout can then be fabricated on silicon to obtain an ASIC. Similarly, an FPGA can be programmed using the netlist generated from the TDM design 200 to implement the TDM design 200.
[0074] Figure 7 An example computing device 700 is shown, which can be used to convert a digital logic design into a TDM design 200, or may be combined with hardware that implements the TDM design 200.
[0075] The computing device 700 includes one or more processors 702, one or more memory devices 704, one or more interfaces 706, one or more mass storage devices 708, one or more input / output (I / O) devices 710, and a display device 730, all of which are coupled to a bus 712. The processor 702 includes one or more processors or controllers for executing instructions stored in the memory devices 704 and / or the mass storage devices 708. The processor 702 may also include various types of computer-readable media, such as cache memory.
[0076] The memory device 704 includes various computer-readable media, such as volatile memory (e.g., random access memory (RAM) 714) and / or non-volatile memory (e.g., read-only memory (ROM) 716). The memory device 704 may also include rewritable ROM, such as flash memory.
[0077] Mass storage devices 708 include various computer-readable media, such as magnetic tape, magnetic disks, optical disks, solid-state storage (e.g., flash memory), etc. Figure 7 As shown, a specific mass storage device is a hard disk drive 724. Mass storage device 708 may also include various drives to enable reading and / or writing from various computer-readable media. Mass storage device 708 includes removable media 726 and / or non-removable media.
[0078] I / O device 710 includes various devices that allow data and / or other information to be input to or retrieved from computing device 700. Example I / O device 710 includes cursor control device, keyboard, keypad, microphone, monitor or other display device, speaker, printer, network interface card, modem, lens, CCD or other image capture device, etc.
[0079] Display device 730 includes any type of device capable of displaying information to one or more users of computing device 700. Examples of display device 730 include monitors, display terminals, video projection devices, etc.
[0080] Interface 706 includes various interfaces that allow computing device 700 to interact with other systems, devices, or computing environments. Example interface 706 includes any number of different network interfaces 720, such as interfaces for connecting to a local area network (LAN), wide area network (WAN), wireless network, and the Internet. Other interfaces include user interfaces 718 and peripheral device interfaces 722. Interface 706 may also include one or more user interface elements 718. Interface 706 may also include one or more peripheral interfaces, such as interfaces for printers, pointing devices (mouse, touchpad, etc.), keyboards, etc.
[0081] Bus 712 allows processor 702, memory device 704, interface 706, mass storage device 708, and I / O device 710 to communicate with each other and with other devices or components connected to bus 712. Bus 712 represents one or more types of bus architectures, such as system bus, PCI bus, IEEE 1394 bus, USB bus, etc.
[0082] For ease of illustration, programs and other executable program components are shown as discrete boxes herein, but it will be understood that these programs and components may reside in different memory components of computing device 700 at different times and be executed by processor 702. Alternatively, the systems and programs described herein may be implemented in hardware, or a combination of hardware, software, and / or firmware. For example, one or more application-specific integrated circuits (ASICs) may be programmed to execute one or more systems and programs described herein.
[0083] In the foregoing disclosure, reference has been made to the accompanying drawings, which form part of this disclosure and illustrate specific implementations of the disclosure by way of example. It should be understood that other implementations and structural modifications can be made without departing from the scope of this disclosure. References to "one embodiment," "implementation," "exemplary embodiment," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, these expressions do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, it should be understood that those skilled in the art can influence that feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.
[0084] Implementations of the systems, apparatuses, and methods disclosed herein may include or utilize a special-purpose or general-purpose computer, which includes computer hardware, such as one or more processors and system memory as described herein. Implementations within the scope of this disclosure may also include physical media and other computer-readable media for carrying or storing computer-executable instructions and / or data structures. Such computer-readable media may be any available medium, provided that it is accessible to a general-purpose or special-purpose computer system. A computer-readable medium storing computer-executable instructions is referred to as a computer storage medium (apparatus). A computer-readable medium carrying computer-executable instructions is referred to as a transport medium. Therefore, by way of example and not limitation, implementations of this disclosure may include at least two distinct types of computer-readable media: a computer storage medium (apparatus) and a transport medium.
[0085] Computer storage media (devices) include RAM, ROM, EEPROM, CD-ROM, solid-state drive (“SSD”) (e.g., RAM-based), flash memory, phase-change memory (“PCM”), other types of memory, other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store required program code units in the form of computer-executable instructions or data structures and that can be accessed by a general-purpose or special-purpose computer.
[0086] The apparatuses, systems, and methods disclosed herein can be implemented via computer networks. "Network" is defined as one or more data links enabling the transmission of electronic data between computer systems and / or modules and / or other electronic devices. When information is transmitted or provided to a computer via a network or other communication connection (wired, wireless, or a combination of wired and wireless), the computer considers that connection as a transmission medium. Transmission media may include networks and / or data links, which can be used to carry the required program code in the form of computer-executable instructions or data structures, and are accessible by general-purpose or special-purpose computers. The above combinations should also be included within the scope of computer-readable media.
[0087] Computer-executable instructions include, for example, instructions and data that, when executed on a processor, cause a general-purpose computer, a special-purpose computer, or a special-purpose processing device to perform a specific function or set of functions. Computer-executable instructions can be, for example, binary files, intermediate format instructions such as assembly language, or even source code. Although this subject matter has been described using language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the features or actions described above. Rather, the described features and actions are disclosed as exemplary forms for implementing the claims.
[0088] Those skilled in the art will understand that this disclosure can be practiced in network computing environments with various computer system configurations, including in-vehicle computers, personal computers, desktop computers, laptops, message processors, handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframes, mobile phones, PDAs, tablets, pagers, routers, switches, and various storage devices. This disclosure can also be practiced in distributed system environments, where local and remote computer systems are linked via a network (through a hardwired data link, a wireless data link, or a combination of hardwired and wireless data links) and jointly perform tasks. In a distributed system environment, program modules can reside in local and remote memory storage devices.
[0089] Furthermore, where appropriate, the functions described herein can be performed using one or more of the following: hardware, software, firmware, digital components, or analog components. For example, one or more application-specific integrated circuits (ASICs) can be programmed to execute one or more systems and programs described herein. Throughout the specification and claims, certain terms are used to refer to specific system components. Those skilled in the art will understand that components may use different names. This document is not intended to distinguish between components with different names but different functions.
[0090] It should be noted that the sensor implementations described above may include computer hardware, software, firmware, or any combination thereof to perform at least a portion of their functions. For example, a sensor may include computer code configured to execute in one or more processors, and may include hardware logic / circuit controlled by the computer code. The example devices provided herein are for illustrative purposes only and are not intended to be limiting. Embodiments of this disclosure may be implemented in other types of devices, as is known to those skilled in the art.
[0091] At least some embodiments of this disclosure relate to computer program products that include such logic (e.g., in software form) stored on any computer-usable medium. When such software is executed in one or more data processing devices, it causes the devices to operate as described herein.
[0092] While various embodiments of this disclosure have been described above, it should be understood that these embodiments are presented by way of example only and not limitation. Those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.
[0093] The foregoing description is for illustrative and descriptive purposes only. It is not intended to be exhaustive or to limit this disclosure to its precise form. In view of the foregoing teachings, many modifications and variations are possible. Furthermore, it should be noted that any or all of the foregoing alternative implementations may be used in any desired combination to form additional hybrid implementations of this disclosure.
Claims
1. A method for implementing a logical time-division multiplexed memory, the method comprising: The computer system receives an original design, the original design including an original memory having a first capacity and including a first address input and a first read output, the first address input having a first address width; The computer system generates a time-division multiplexing design based on the original design. The time-division multiplexing design includes N instances of time-division multiplexing memory based on the original memory, where N is an integer. The time-division multiplexing memory includes: The second capacity is 2^C times the first capacity, where C equals ceil(log2(N)); A second address input, the second address input having a second address width, the second address width being the first address width plus C; A second read output, configured to output data read from the time-division multiplexed memory; and A chain of N registers, each register having an input and an output, wherein the input of the first register in the chain of N registers is coupled to the second read output, and the inputs of the remaining N-1 registers in the chain of N registers are respectively coupled to the output of the preceding register in the chain of N registers.
2. The method according to claim 1, wherein, The time-division multiplexing design also includes a C-bit modulo N free-running counter, which is coupled to the most significant bit of the second address input.
3. The method according to claim 2, wherein: The original memory has a first write address input, a first write enable input, and a write data input, wherein the first write address input has a first address width; and The time-division multiplexed memory has a second write address input with a second address width, and the C-bit modulo N free-running counter is coupled to the most significant bit of the second write address input.
4. The method according to claim 1, wherein, The original design also includes combinational logic, and the time-division multiplexing design includes the combinational logic.
5. The method according to claim 4, wherein: The time-division multiplexing design includes the combinational logic coupled to the output of the penultimate register in the chain of the N registers; The original memory includes a first read enable input, and the combinational logic is coupled to the first read enable input in the original design; The time-division multiplexed memory includes a second read enable input coupled to the combinational logic; as well as The time-division multiplexing design includes a multiplexer having a selection input coupled to the second read enable input, a first input coupled to the second read output, and a second input coupled to the output of the last register in the chain of the N registers. The output of the multiplexer is coupled to the input of the first register in the chain of the N registers.
6. The method according to claim 5, wherein: The selection input of the multiplexer is coupled to the second read enable input via a flip-flop, the input of the flip-flop is coupled to the second read enable input, and the output of the flip-flop is coupled to the selection input of the multiplexer. The flip-flop and the time-division multiplexed memory each have a clock input coupled to a common clock signal.
7. The method according to claim 4: The original memory includes a first read enable input, and the combinational logic is coupled to the first read enable input in the original design; The time-division multiplexed memory includes a second read enable input coupled to the combinational logic; and The time-division multiplexing design includes a multiplexer having a selection input coupled to the second read enable input, a first input coupled to the second read output, and a second input coupled to the output of the last register in the chain of the N registers. The output of the multiplexer is coupled to the input of the first register in the chain of the N registers and to the combinational logic.
8. The method according to claim 4, wherein, The combinational logic includes multiple logic gates, and the logic gates include at least one of AND, NAND, OR, NOR, XOR, and XNOR.
9. The method according to claim 1, wherein, The original design and the time-division multiplexing design each contain one or more hardware description language files, and the method further includes: Generate a netlist based on the time-division multiplexing design; Generate a physical layout based on the netlist; and Fabricate an application-specific integrated circuit (ASIC) to implement the time-division multiplexing design.
10. The method according to claim 1, wherein, The original design and the time-division multiplexing design each contain one or more hardware description language files, and the method further includes: Generate a netlist based on the time-division multiplexing design; and The gates of the field-programmable gate array are programmed to implement the netlist.
11. An apparatus for implementing a logical time-division multiplexed memory, the apparatus comprising: An N-instance time-division multiplexing device, the N-instance time-division multiplexing device including a memory, the memory having an address input and a read output, the address input being configured to receive an address, and the read output being configured to output data read from the memory; and A chain of N registers, each register having an input and an output, wherein the input of the first register in the chain of N registers is coupled to the read output, and the inputs of the remaining N-1 registers in the chain of N registers are respectively coupled to the output of the preceding register in the chain of N registers.
12. The device according to claim 11, wherein: The N-instance time-division multiplexing device further includes a C-bit modulo N free-running counter, which is coupled to the most significant bit of the address input, where C equals ceil(log2(N)): The memory has a write address input, a write enable input, and a write data input, and the C-bit modulo N free-running counter is coupled to the most significant bit of the write address input.
13. The device of claim 12, further comprising combinational logic coupled to the least significant bit of the address input.
14. The device according to claim 13, wherein: The combinational logic is coupled to the output of the second-to-last register in the chain of the N registers; The memory includes a read enable input coupled to the combinational logic; and The N-instance time-division multiplexing device further includes a multiplexer having a selection input coupled to the read enable input, a first input coupled to the read output, and a second input coupled to the output of the last register in the chain of the N registers. The output of the multiplexer is coupled to the input of the first register in the chain of the N registers, and the first register in the chain of the N registers is coupled to the read output through the multiplexer.
15. The device according to claim 14, wherein: The select input of the multiplexer is coupled to the read enable input via a flip-flop, the input of the flip-flop is coupled to the read enable input, and the output of the flip-flop is coupled to the select input of the multiplexer. The flip-flop and the memory each have a clock input coupled to a common clock signal.
16. The device according to claim 13, wherein: The memory includes a read enable input coupled to the combinational logic; and The N-instance time-division multiplexing device includes a multiplexer having a selection input coupled to the read enable input, a first input coupled to the read output, and a second input coupled to the output of the last register in the chain of N registers. The output of the multiplexer is coupled to the input of the first register in the chain of N registers and to the combinational logic. The first register in the chain of N registers is coupled to the read output through the multiplexer.
17. The device according to claim 13, wherein, The combinational logic includes multiple logic gates, and the logic gates include at least one of AND, NAND, OR, NOR, XOR, and XNOR.
18. A non-transitory computer-readable medium storing executable code, which, when executed by one or more processing means, causes the one or more processing means to: Receive an original design, the original design including an original memory having a first capacity and including a first address input and a first read output, the first address input having a first address width; A time-division multiplexing design is generated based on the original design. The time-division multiplexing design includes N instances of time-division multiplexing memory based on the original memory, where N is an integer. The time-division multiplexing memory includes: The second capacity is 2^C times the first capacity, where C equals ceil(log2(N)); A second address input, the second address input having a second address width, the second address width being the first address width plus C; A second read output, configured to output data read from the time-division multiplexed memory; A chain of N registers, each register having an input and an output, wherein the input of the first register in the chain of N registers is coupled to the second read output, and the inputs of the remaining N-1 registers in the chain of N registers are respectively coupled to the output of the preceding register in the chain of N registers; A C-bit modulo-N free-running counter, the C-bit modulo-N free-running counter being coupled to the most significant bit of the second address input; and Combinational logic, which is coupled to the second address input and the second read output.
19. The non-transitory computer-readable medium according to claim 18, wherein: The time-division multiplexing design includes the combinational logic coupled to the output of the penultimate register in the chain of the N registers; The original memory includes a first read enable input, and the combinational logic is coupled to the first read enable input in the original design; The time-division multiplexed memory includes a second read enable input coupled to the combinational logic; as well as The time-division multiplexing design includes a multiplexer having a selection input coupled to the second read enable input, a first input coupled to the second read output, and a second input coupled to the output of the last register in the chain of N registers. The output of the multiplexer is coupled to the input of the first register in the chain of N registers. The selection input of the multiplexer is coupled to the second read enable input via a flip-flop. The input of the flip-flop is coupled to the second read enable input, and the output of the flip-flop is coupled to the selection input of the multiplexer. The flip-flop and the time-division multiplexed memory each have a clock input coupled to a common clock signal.
20. The non-transitory computer-readable medium of claim 18, wherein: The original design also includes combinational logic; The time-division multiplexing design includes the combinational logic; The original memory includes a first read enable input, and the combinational logic is coupled to the first read enable input in the original design; The time-division multiplexed memory includes a second read enable input coupled to combinational logic; as well as The time-division multiplexing design includes a multiplexer having a selection input coupled to the second read enable input, a first input coupled to the second read output, and a second input coupled to the output of the last register in the chain of the N registers. The output of the multiplexer is coupled to the input of the first register in the chain of the N registers and to the combinational logic.