Memory device and operating method thereof

Abstract

The disclosure provides a memory device and an operating method thereof. The memory device can include: a memory cell array including a first type of memory block and a second type of memory block, a main memory block address being assigned to the first type of memory block, user data being stored in the first type of memory block, no user data being stored in the second type of memory block; an address management circuit configured to request a read operation on the second type of memory block, and based on data read from each second type of memory block, set flag information indicating a usage state of each second type of memory block; and an address adjustment circuit configured to selectively assign the main memory block address to the second type of memory block based on the flag information of each second type of memory block.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0052311, filed on April 22, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to an electronic device, and more specifically, to a memory device and a method of operating the same. Background Technology

[0003] Non-volatile memory devices have the characteristic of performing data programming and erasure electrically.

[0004] The memory device includes multiple memory blocks, including a main memory block for storing user data and dedicated memory blocks with restricted user access. For example, extension blocks, extra blocks, and spare blocks are dedicated memory blocks. Dedicated memory blocks are designated as spaces for storing data other than user data. Users cannot access dedicated memory blocks except in special circumstances.

[0005] On the other hand, some dedicated memory blocks can remain in an erased state. These dedicated memory blocks can remain unused in this state until the memory device is discarded. In other words, when a large number of unused dedicated memory blocks exist in a memory device, it reduces the user's data storage capacity and degrades the performance of the memory device. Summary of the Invention

[0006] Various embodiments relate to a memory device that can increase the storage capacity for user data.

[0007] According to an embodiment, a memory device may include: a memory cell array including a first type of memory block and a second type of memory block, wherein a main memory block address is assigned to the first type of memory block, user data is stored in the first type of memory block, and no user data is stored in the second type of memory block; an address management circuit configured to request a read operation on the second type of memory block and set flag information indicating the usage status of each second type of memory block based on data read from each second type of memory block; and an address adjustment circuit configured to selectively assign a main memory block address to the second type of memory block based on the flag information of each second type of memory block.

[0008] According to an embodiment, a memory device may include: a memory cell array including a first type of memory block and a second type of memory block, wherein a main memory block address is assigned to the first type of memory block, user data is stored in the first type of memory block, and no user data is stored in the second type of memory block; an address management circuit configured to store preset flag information indicating the usage status of each second type of memory block; and an address adjustment circuit configured to assign a main memory block address to the second type of memory block based on the preset flag information. Attached Figure Description

[0009] Figure 1 A memory device according to an embodiment of the present disclosure is shown; Figure 2 Show Figure 1 The memory cell array shown includes memory blocks; Figure 3 Show operation Figure 1 The method of the address management circuit, data verification circuit, address decoder, and address adjustment circuit shown; Figure 4 Show Figure 3 The verification circuit shown; Figure 5 Show Figure 3 The address adjustment circuit shown illustrates the main memory block address allocation method. Figure 6 This illustrates an address allocation method for a second type of storage block according to an embodiment of the present disclosure; Figure 7 A memory device according to another embodiment of the present disclosure is shown; Figure 8 A memory card system according to an embodiment of the present disclosure is shown; and Figure 9 A solid-state drive (SSD) system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0010] The specific structural or functional descriptions of the concepts disclosed in this specification are merely illustrative and are intended to describe examples of embodiments based on these concepts. These examples of embodiments based on these concepts may be implemented in various forms, but these descriptions are not limited to the examples of embodiments described in this specification.

[0011] Figure 1 A memory device 100 according to an embodiment of the present disclosure is shown. Figure 2 Show Figure 1 The memory cell array 110 shown includes memory blocks.

[0012] Reference Figure 1The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0013] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz, where z is a positive integer greater than 1. The multiple memory blocks BLK1 to BLKz are connected to row decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to page buffer group 123 via bit lines BL1 to BLn, where n is a positive integer greater than 1. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In this embodiment, the multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line can be defined as a page. Therefore, a memory block can include multiple pages.

[0014] The memory cells included in the memory cell array 110 may include a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, or a four-level cell (QLC) that stores four data bits.

[0015] Reference Figure 2 The memory cell array 110 includes a first type of memory block BLK1s (hereinafter referred to as "first type memory block BLK1s") and a second type of memory block BLK2s (hereinafter referred to as "second type memory block BLK2s").

[0016] The first type of storage block BLK1s is the main storage block for storing user data. In response to user commands, the peripheral circuit 120 can perform programming, reading, and erasing operations on the first type of storage block BLK1s.

[0017] The second type of storage block BLK2s is a storage block that cannot store user data. Regardless of whether a user command is present, the peripheral circuit 120 cannot perform programming, reading, or erasing operations on the second type of storage block BLK2s.

[0018] The second type of storage block, BLK2s, includes spare blocks, extended blocks, and extra blocks. Spare blocks are used to replace bad blocks. Extra blocks can be used as content-addressable storage (CAM) blocks or one-time programmable (OTP) blocks. Extended blocks can be used to expand the capacity of the main storage block.

[0019] Each of the first-class storage blocks BLK1s is a storage block that stores user data and allows user access, while each of the second-class storage blocks BLK2s is a storage block that does not store user data. Each of the first-class storage blocks BLK1s and the second-class storage blocks BLK2s can be in a used state where data is stored or in an unused state where no data is stored.

[0020] Reference Figure 1 The peripheral circuitry 120 can be configured, under the control of the control logic 130, to perform programming, reading, or erasing operations on selected regions of the memory cell array 110. The peripheral circuitry 120 can drive the memory cell array 110. For example, under the control of the control logic 130, the peripheral circuitry 120 can apply various operating voltages to the row lines RL and bit lines BL1 to BLn, or it can release the applied voltages.

[0021] The peripheral circuitry 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sensing circuit 126.

[0022] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row line RL may include at least one source select line, multiple word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row line RL may further include a pipe select line.

[0023] Row decoder 121 is configured to decode row address RADD received from control logic 130. Row decoder 121 selects at least one memory block from memory blocks BLK1 to BLKz based on row address RADD. In addition, row decoder 121 may select at least one word line of the selected memory block based on row address RADD to apply the voltage generated by voltage generator 122 to the at least one word line WL.

[0024] For example, during a programming operation, the line decoder 121 applies a programming voltage to the selected word line and a programming pass voltage lower than the programming voltage to the unselected word line. During a programming verification operation, the line decoder 121 applies a verification voltage to the selected word line and a verification pass voltage higher than the verification voltage to the unselected word line. During a read operation, the line decoder 121 applies a read voltage to the selected word line and a read pass voltage higher than the read voltage to the unselected word line.

[0025] In this embodiment, the erase operation of the memory device 100 is performed on a block-by-block basis. During the erase operation, the row decoder 121 may select a memory block based on the row address RADD. During the erase operation, the row decoder 121 may apply a ground voltage to the word line connected to the selected memory block.

[0026] Voltage generator 122 operates under the control of control logic 130. Voltage generator 122 is configured to generate multiple voltages using the external power supply voltage supplied to memory device 100. More specifically, voltage generator 122 can generate various operating voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, voltage generator 122 can generate programming voltage, verification voltage, pass voltage, read voltage, and erase voltage under the control of control logic 130.

[0027] In this embodiment, voltage generator 122 can adjust an external power supply voltage to generate an internal power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0028] In the example, voltage generator 122 can generate multiple voltages using either an external power supply voltage or an internal power supply voltage.

[0029] For example, voltage generator 122 includes multiple pump capacitors that receive internal power supply voltages and selectively activates the multiple pump capacitors under the control of control logic 130 to generate multiple voltages. Line decoder 121 can supply multiple voltages to memory cell array 110.

[0030] Page buffer group 123 includes page buffers PB1 to PBn. Buffers PB1 to PBn are connected to memory cell array 110 via bit lines BL1 to BLn. Page buffers PB1 to PBn operate under the control of control logic 130. More specifically, page buffers PB1 to PBn can operate in response to a page buffer control signal PBSIGNALS from control logic 130. For example, page buffers PB1 to PBn can temporarily store data received via bit lines BL1 to BLn, or can sense the voltage or current of bit lines BL1 to BLn during read or verification operations.

[0031] More specifically, during programming operations, when a programming voltage is applied to the selected word line, page buffers PB1 to PBn can transmit data DATA received through input / output circuit 125 to the selected memory cell via bit lines BL1 to BLn. The memory cell of the selected page is programmed based on the transmitted data DATA. During programming verification operations, page buffers PB1 to PBn sense the voltage or current received from the selected memory cell via bit lines BL1 to BLn to verify the data stored in the selected page.

[0032] During a read operation, page buffers PB1 to PBn can read data DATA from the memory cell of the selected page via bit lines BL1 to BLn, and can output the read data DATA to the input / output circuit 125 under the control of column decoder 124.

[0033] During an erase operation, page buffers PB1 to PBn can either float bit lines BL1 to BLn or apply an erase voltage to bit lines BL1 to BLn.

[0034] The column decoder 124 can transfer data between the input / output circuit 125 and the page buffer group 123 based on the column address CADD. For example, the column decoder 124 can exchange data with the page buffers PB1 to PBn via the data lines DL, or with the input / output circuit 125 via the column lines CL.

[0035] The input / output circuit 125 can transmit commands CMD and addresses ADDR received from the memory controller (not shown) to the control logic 130, or it can exchange data DATA with the column decoder 124.

[0036] The sensing circuit 126 generates a reference current in response to the enabled bit signal VRYBIT, compares the reference voltage generated by the reference current with the sensed voltage VPB received from the page buffer group 123, and outputs a pass signal PASS or a failure signal FAIL during a read operation or a verification operation.

[0037] Address management circuit 127 can request control logic 130 to perform a read operation on the second type of memory block BLK2s, and can store the flag information Flag Info of each of the second type of memory blocks BLK2s based on whether the read data exists in the corresponding second type of memory block.

[0038] The Flag Info indicates whether data is stored in each of the second-class storage blocks (BLK2s). In other words, the Flag Info can indicate whether the corresponding second-class storage block is in an erase state. Alternatively, the Flag Info can indicate whether the corresponding second-class storage block is in use or unused.

[0039] After performing a read operation on the second-class memory blocks BLK2s, the data verification circuit 128 can acquire data from each of the second-class memory blocks BLK2s via the input / output circuit 125. The data verification circuit 128 outputs a flag value Flag Result based on the data from each of the second-class memory blocks BLK2s. The flag value Flag Result can be output as multiple values. Among these multiple values, the final flag value Flag Result is set and stored in the address management circuit 127 as the flag information FlagInfo for the corresponding second-class memory block. The address management circuit 127 provides the flag information FlagInfo and address information Addr Info for the corresponding second-class memory block to the address adjustment circuit 1292.

[0040] Address adjustment circuit 1292 receives flag information Flag Info and address information AddrInfo from address management circuit 127. Based on the stored flag information Flag Info, address information Addr Info, and last major block address information LMB Addr Info, address adjustment circuit 1292 allocates first-class storage block addresses to unused second-class storage blocks. The last major block address information LMB Addr Info may include information about the most recently allocated major block address for storing user data, i.e., the last major block address.

[0041] Figure 3 Show Figure 1 The operation of the address management circuit 127, data verification circuit 128, address decoder 129, and address adjustment circuit 1292 shown.

[0042] Reference Figure 3 When the conditions for increasing storage capacity are met or the configuration block usage is completed before device installation, control logic 130 releases the access restriction on the second type of storage block BLK2s, and then transmits the address allocation command ASCMD to the address management circuit 127. Once the access restriction on the second type of storage block BLK2s is released, Figure 1 The peripheral circuit 120 can perform read operations on the second type of memory blocks BLK2s within the memory cell array 110. Access restrictions on all or at least one of the spare blocks, extended blocks, or additional blocks in the second type of memory blocks BLK2s can be preferentially lifted.

[0043] Address management circuit 127 receives an address allocation command ASCMD from control logic 130 and, in response to the address allocation command ASCMD, transmits a read start command RSCMD to control logic 130. Address management circuit 127 stores address information Addr Info for all second-class memory blocks BLK2s. Based on the address information Addr Info of the second-class memory blocks BLK2s, spare blocks, extended blocks, and additional blocks can be identified. When access restrictions on at least one of the spare blocks, extended blocks, or additional blocks are lifted, address management circuit 127 can transmit a read start command RSCMD for at least one second-class memory block whose restrictions have been lifted.

[0044] Address management circuit 127 transmits read start commands (RSCMD) for all target memory blocks to control logic 130 based on the address information (Addr Info) of the second-class memory blocks (BLK2s). The read start command (RSCMD) request from address management circuit 127 may include transmitting read commands to control logic 130 for all second-class memory blocks (BLK2s) corresponding to the range from the first address to the last address of the second-class memory blocks (BLK2s). Optionally, address management circuit 127 may transmit read start commands (RSCMD) for at least one of spare blocks, extended blocks, or additional blocks, or may transmit read start commands (RSCMD) to control logic 130 in a specified order among spare blocks, extended blocks, and additional blocks.

[0045] Control logic 130 can respond to a read start command RSCMD to control peripheral circuitry 120 to perform a read operation on the second type of memory block BLK2s. Peripheral circuitry 120 performs the read operation based on the address of the second type of memory block BLK2s included in the read start command RSCMD. Data DATA read from the second type of memory block BLK2s in memory cell array 110 is stored in page buffer PB and provided to data verification circuitry 128 via input / output circuitry 125.

[0046] Address management circuit 127 includes a flag information storage device 1271 for storing flag information Flag Info and an address information storage device 1272 for storing address information Addr Info.

[0047] The address management circuit 127 stores the final calculated value, i.e., the final flag value Flag Result, received from the data verification circuit 128 as flag information Flag Info in the flag information storage device 1271. The flag value Flag Result is the value calculated and output by the data verification circuit 128 for each second-type storage block BLK2s. The flag information Flag Info indicates whether data is stored in each second-type storage block BLK2s or whether each second-type storage block BLK2s is used or unused. In other words, the data verification circuit 128 sequentially receives the read data DATA from each second-type storage block BLK2s and outputs multiple flag values ​​Flag Result using the arithmetic circuit. The final flag value Flag Result of each second-type storage block BLK2s can be stored as flag information Flag Info in the address management circuit 127.

[0048] Additionally, the address management circuit 127 can store the address information Addr Info in the address information storage device 1272. The address information Addr Info refers to the address of the second type of storage block corresponding to the flag information Flag Info. The address information Addr Info can be used to identify the second type of storage block with the flag information Flag Info, or it can be used when a main storage block address has not yet been allocated to the second type of storage block.

[0049] When the read operation of the second type of memory block BLK2s is completed, the address management circuit 127 can receive the read completion message REMSG from the control logic 130. The read completion message REMSG indicates that the read operation of the second type of memory block BLK2s has been completed.

[0050] When the address management circuit 127 receives the read completion message REMSG, the address management circuit 127 provides the stored flag information Flag Info and the corresponding address information Addr Info to the address adjustment circuit 1292.

[0051] The data verification circuit 128 receives read data DATA from the second-class memory blocks BLK2s provided by the page buffers PB1 to PBn of the page buffer group 123 via the input / output circuit 125. The data verification circuit 128 inputs the read data DATA into the verification circuit CC to check whether data exists in each second-class memory block BLK2s, and outputs a flag value Flag Result as the result value.

[0052] The data verification circuit 128 includes a verification circuit CC for checking whether data is stored in each Class 2 memory block BLK2s. The verification circuit CC receives data DATA from each Class 2 memory block BLK2s and outputs a flag value FlagResult. The data DATA in a single memory block can correspond to DQ[n-1:0], which contains n bits of input data. The flag value FlagResult is output every clock cycle (CLK). Among the flag values ​​FlagResult associated with each Class 2 memory block BLK2s, the final flag value FlagResult is used as the flag information FlagInfo.

[0053] The data verification circuit 128 can output different flag values ​​(Flag Result) depending on whether data is stored in the corresponding memory block BLK2s. The flag value (Flag Result) is used to distinguish whether the second type of memory block BLK2s is in an erased or unerased state and to determine whether the second type of memory block BLK2s is used or unused. When the flag value (Flag Result) of an unused second type of memory block is "1", the flag value (Flag Result) of a used second type of memory block can be set to "0".

[0054] For example, when the data read from the predetermined second type of memory block is in an erased state, i.e., ALL FFH (0xFFFFFFFF), the verification circuit CC can output the flag value Flag Result as "1". When at least one memory cell in the predetermined second type of memory block contains data, the verification circuit CC can output the flag value Flag Result as "0", and the flag information Flag Info can also be "0". Optionally, the output flag value can be the opposite of the above.

[0055] Figure 4 Show Figure 3 The verification circuit CC is shown.

[0056] Reference Figure 4 The verification circuit CC may include a first XOR gate XOR1, a D flip-flop D-FF, and a second XOR gate XOR2.

[0057] The first XOR gate XOR1 performs an XOR operation on the data DATA read from the second type of memory block at its input and provides the output to the D input of the D flip-flop D-FF. The data DATA read and input to the first XOR gate XOR1 can be DQ[7:0].

[0058] The D flip-flop (D-FF) includes a D input terminal that receives the output of the first XOR gate (XOR1), a clock input terminal that receives the clock signal CLK, and an output terminal. The D flip-flop performs D flip-flop operations and outputs the result through its output terminal. The second XOR gate (XOR2) may include a first input terminal that receives the output of the D flip-flop (D-FF), a second input terminal that receives the output of the first XOR gate (XOR1), and an output terminal. The output terminal outputs the result of the XOR operation performed between the output of the D flip-flop (D-FF) and the output of the first XOR gate (XOR1).

[0059] Since the first and second inputs of the second logic gate XOR2 simultaneously receive the output and input of the D flip-flop D-FF, the final flag value Flag Result output by XOR2 can indicate whether data is stored in the second type of memory block. That is, when the final flag value Flag Result is "1", it is determined that the second type of memory block is in an erased state and is unused; when the final flag value Flag Result is "0", it is determined that the second type of memory block is in a data storage state and is being used.

[0060] The final flag value Flag Result output by the second logic OR gate XOR2 is provided to the address management circuit 127. This final flag value Flag Result can be set to flag information Flag Info and can be stored in... Figure 3 The address management circuit 127 provides the stored flag information Flag Info and the corresponding stored address information Addr Info to the address decoder 129 in the flag information storage device 1271.

[0061] Refer to Figure 3 The address decoder 129 includes a row decoder 121, a column decoder 124, a block decoder 1291, and an address adjustment circuit 1292.

[0062] The line decoder 121 receives the line address RADD from the address. The line decoder 121 decodes the line address RADD to generate a line selection signal, which is used to select one of the word lines WL.

[0063] Column decoder 124 receives column address CADD from the address. Column decoder 124 decodes column address CADD to generate column select signal, which is used to select one of the bit lines BL.

[0064] The address adjustment circuit 1292 allocates a primary storage block address (or a primary storage block address) for each unused Class II storage block (BLK2s) to be used for storing user data, and stores the allocated primary storage block address in the adjustment table TT for management. The allocation of the primary storage block address for each unused Class II storage block (BLK2s) can be performed based on flag information (Flag Info), address information (Addr Info), and the last primary storage block address information (LMB Addr Info).

[0065] The primary block address assigned to an unused Class 2 storage block (BLK2s) is the next primary block address after the last primary block address in the LMB Addr Info primary block address information.

[0066] The adjustment table TT stores the address of the unused second type of storage block as the first mapped storage block address, and stores the main storage block address mapped to the first mapped storage block address as the second mapped storage block address corresponding to the first mapped storage block address.

[0067] Subsequently, when the address adjustment circuit 1292 receives a block address for accessing a memory block, it determines whether the received block address corresponds to the first mapped memory block address recorded in the adjustment table TT. If the received block address corresponds to the first mapped memory block address, the address adjustment circuit 1292 converts the first mapped memory block address to a second mapped memory block address and provides the converted second mapped memory block address to the block decoder 1291 as the memory block address for memory block selection. If the received block address does not correspond to the first mapped memory block address, the address adjustment circuit 1292 provides the received block address to the block decoder 1291 as the memory block address.

[0068] The block decoder 1291 can receive the memory block address from the address adjustment circuit 1292, decode the received memory block address, and selectively generate a signal for memory block selection based on the decoded memory block address.

[0069] Figure 5 Show Figure 3 The address adjustment circuit 1292 shown illustrates the main memory block address allocation method.

[0070] Reference Figure 5 The first type of storage block, BLK1s, refers to the main storage block that stores user data. Since each first type of storage block, BLK1s, is used as a storage area for user data, it is irrelevant whether each first type of storage block is actually used. Finally, the address information of the main storage block, LMB Addr Info, is represented by "X".

[0071] For simplicity, assume that the second type of storage blocks BLK2s includes first spare blocks SBLK1 to fourth spare blocks SBLK4, first extended blocks EdBLK1 to fourth extended blocks EdBLK4, and first additional blocks ErBLK1 to fourth additional blocks ErBLK4.

[0072] The first and second backup blocks SBLK1 and SBLK2 are in use, and their corresponding flag information (Flag Info) is "0". The third and fourth backup blocks SBLK3 and SBLK4 are not in use, and their corresponding flag information (Flag Info) is "1".

[0073] Address adjustment circuit 1292 assigns main memory block addresses to the third spare block SBLK3 and the fourth spare block SBLK4, whose flag information Flag Info is "1". More specifically, since the last main memory block address information LMB Addr Info is "X", the main memory block address "X+1" is assigned to the third spare block SBLK3, and the main memory block address "X+2" is assigned to the fourth spare block SBLK4, and these addresses are stored in the adjustment table TT. In this case, the last main memory block address information LMBAddr Info is updated to "X+2".

[0074] The first extension block EdBLK1 and the second extension block EdBLK2 are in use, and their corresponding flag information Flag Info is "0". The third extension block EdBLK3 and the fourth extension block EdBLK4 are not in use, and their corresponding flag information Flag Info is "1".

[0075] Address adjustment circuit 1292 assigns main memory block addresses to the third extension block EdBLK3 and the fourth extension block EdBLK4, whose flag information Flag Info is "1". More specifically, since the last main memory block address information LMB Addr Info is "X+2", the main memory block address "X+3" is assigned to the third extension block EdBLK3, and the main memory block address "X+4" is assigned to the fourth extension block EdBLK4, and these main memory block addresses are stored in the adjustment table TT. In this case, the last main memory block address information LMB Addr Info is updated to "X+4".

[0076] The first extra block ErBLK1 and the second extra block ErBLK2 are in use, and their corresponding flag information Flag Info is "0". The third extra block ErBLK3 and the fourth extra block ErBLK4 are not in use, and their corresponding flag information Flag Info is "1".

[0077] Address adjustment circuit 1292 assigns main memory block addresses to the third extra block ErBLK3 and the fourth extra block ErBLK4, whose flag information Flag Info is "1". More specifically, since the last main memory block address information LMB Addr Info is "X+4", the main memory block address "X+5" is assigned to the third extra block ErBLK3, and the main memory block address "X+6" is assigned to the fourth extra block ErBLK4, and these main memory block addresses are stored in the adjustment table TT. In this case, the last main memory block address information LMB Addr Info is updated to "X+6".

[0078] Figure 6 An address allocation method for a second type of storage block according to an embodiment of the present disclosure is shown.

[0079] Reference Figure 6 The address allocation method includes a flag setting process S1100 based on whether there is stored data in the second type of storage block, and a process S1200 based on the flag information to allocate the main storage block address to the second type of storage block.

[0080] In the flag setting process S1100, in step S1111, from Figure 3 The control logic 130 receives a request to allocate the address of the main storage block to the second type of storage block. In step S1112, when the address allocation request is received, a read request for the second type of storage block BLK2s is transmitted to the control logic 130.

[0081] Upon receiving the read request, control logic 130 controls... Figure 1 The peripheral circuit 120 performs a read operation on each second-class memory block BLK2s and stores the data corresponding to the read operation of each second-class memory block BLK2s in [the relevant storage location]. Figure 1 The page buffers PB1 to PBn are used in the page buffers.

[0082] In step S1113, in the data verification circuit 128, based on the data stored in page buffers PB1 to PBn, it verifies whether there is stored data in each second-class storage block BLK2s. In step S1114, the corresponding flag information Flag Info is stored in the address management circuit 127. Flag Info "1" indicates an erase state, meaning the second-class storage block is not used; Flag Info "0" indicates a programming state, meaning the second-class storage block is in use. In this case, in step S1115, based on the address information Addr Info associated with the current second-class storage block, it is determined whether the address of the current second-class storage block to be verified corresponds to the last address in the second-class storage block BLK2s. If the address of the current second-class storage block does not correspond to the last address, the address of the current second-class storage block to be verified is incremented. Then, in step S1113, it is verified whether there is stored data in the second-class storage block corresponding to the incremented address, and step S1114 is executed to store the corresponding flag information. Repeat steps S1113 and S1114 until the current address of the second type of storage block corresponds to the last address.

[0083] After the flag setting process S1100 is completed, the main storage block address allocation process S1200 begins.

[0084] In step S1211, the address information Addr Info and flag information Flag Info stored in the address management circuit 127 can be searched. In step S1212, it is determined whether the searched flag information Flag Info is "1". If the searched flag information Flag Info is "1", then in step S1213, the main memory block address is assigned to the corresponding second-type memory block with flag information "1". More specifically, in step S1213, based on the last main memory block address information LMB Addr Info, the main memory block address obtained by adding "1" to the last assigned main memory block address is assigned to the corresponding second-type memory block, and the last main memory block address information LMB Addr Info is updated. On the other hand, if the searched flag information Flag Info is not "1", then the address of the second-type memory block corresponding to the searched flag information Flag Info is incremented, and the process returns to step S1211.

[0085] After allocating the main storage block address to the corresponding second-type storage block in step S1213, in step S1214, the address information Addr Info is used to determine whether the address of the second-type storage block corresponding to the second-type storage block with the flag information "1" corresponds to the last address of the second-type storage block BLK2s. If it is determined in step S1214 that the second-type storage block address corresponds to the last address, the main storage block address allocation process S1200 terminates. On the other hand, if it is determined in step S1214 that the second-type storage block address does not correspond to the last address, the address of the second-type storage block is incremented, and the process returns to step S1211, thereby repeating the main storage block address allocation process S1200.

[0086] Figure 7 A memory device 100-1 according to another embodiment of the present disclosure is shown.

[0087] Figure 7 Description of the memory device 100-1 and Figure 3 The descriptions of the memory device 100 overlap, so the overlapping parts are omitted and only the differences are described.

[0088] Reference Figure 3 and Figure 7 , Figure 3 The memory device 100 shown performs a read operation on the second type of memory blocks BLK2s and determines whether each second type of memory block BLK2s is in an erased state, an unerased state, or a stored state. Based on the determination result, flag information Flag Info is set.

[0089] on the contrary, Figure 7 The memory device 100-1 shown contains preset flag information Flag Info. Therefore, Figure 7 The memory device 100-1 shown does not perform a read operation on the second type of memory block BLK 2s, nor does it contain... Figure 3 The data verification circuit 128 verifies the data read in the middle.

[0090] The address adjustment circuit 1292 allocates the address of the first type of memory block (or the address of the main memory block) to an unused second type of memory block in the second type of memory blocks BLK2s based on the last main memory block address information LMB Addr Info stored therein and the preset flag information Flag Info and the corresponding address information Addr Info received from the address management circuit 127. The unused second type of memory blocks can be predetermined by the preset flag information.

[0091] Figure 8 A memory card system 3000 according to an embodiment of the present disclosure is shown.

[0092] Reference Figure 8The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0093] Controller 3100 can be coupled to memory device 3200. Controller 3100 can access memory device 3200. For example, controller 3100 can control programming, reading, erasing, or background operation of memory device 3200. Controller 3100 can provide an interface between memory device 3200 and the host. Controller 3100 can drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0094] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on specific communication protocols. For example, controller 3100 can communicate with external devices via at least one of the following protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory High-Speed ​​Interface (NVMe). For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0095] Memory device 3200 may include a plurality of memory cells, and is referenced above. Figure 1 The memory device 100 described is configured in the same manner.

[0096] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form memory cards such as: PCMCIA cards, small form factor (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro or eMMC), SD cards (SD, miniSD, microSD or SDHC), universal flash memory (UFS), etc.

[0097] Figure 9 A solid-state drive (SSD) system 4000 according to an embodiment of the present disclosure is shown.

[0098] Reference Figure 9 The SSD system 4000 may include a host 4100 and a solid-state drive 4200. The solid-state drive 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power PWR through a power connector 4002. The solid-state drive 4200 may include a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0099] The controller 4210 can control a plurality of memory devices 4221 to 422n in response to signals received from the host 4100. In embodiments, these signals may be based on the interface between the host 4100 and the SSD 4200. For example, these signals may be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory High-Speed ​​Interface (NVMe).

[0100] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. The configuration of each of the plurality of memory devices 4221 to 422n may be consistent with... Figure 1 The memory device 100 shown is the same.

[0101] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be powered and charged by host 4100. When the power supply to host 4100 is unstable, auxiliary power supply 4230 can power SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be mounted on the motherboard and supply auxiliary power to SSD 4200.

[0102] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0103] This technology increases the user data storage capacity of a memory device by allocating main block addresses to unused storage blocks within a dedicated storage block.

[0104] While the exemplary embodiments described herein are for illustrative purposes only, those skilled in the art will understand that various modifications, additions, and substitutions can be made. Therefore, the invention is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device, comprising: The memory cell array includes a first type of memory block and a second type of memory block. The main memory block address is assigned to the first type of memory block and user data is stored in the first type of memory block. No user data is stored in the second type of memory block. The address management circuit requests a read operation on the second type of memory block and sets flag information indicating the usage status of each second type of memory block based on the data read from each second type of memory block; as well as The address adjustment circuit selectively assigns the main memory block address to the second type of memory block based on the flag information of each second type of memory block.

2. The memory device of claim 1, further comprising a data verification circuit that outputs a flag value based on data read from each of the second type of memory blocks. in, The address management circuit sets the final flag value from the flag values ​​associated with each of the second type of storage blocks from the data verification circuit as the flag information.

3. The memory device according to claim 1, wherein, The address management circuit includes a flag information storage device and an address information storage device. The flag information storage device stores the flag information of each second type of storage block, and the address information storage device stores the address information of the second type of storage block corresponding to the flag information. The address management circuit provides the flag information and the address information to the address adjustment circuit.

4. The memory device according to claim 1, wherein, The address adjustment circuit allocates the main memory block address to each of the second type of memory block based on the flag information, the corresponding address information, and the last main memory block address information. The last primary storage block address information includes information about the address of the last primary storage block most recently allocated to the storage block used to store user data.

5. The memory device according to claim 4, wherein, The address adjustment circuit assigns the address of the next main memory block after the last main memory block address to the second type of memory block that has flag information indicating the erase status.

6. The memory device according to claim 1, wherein, The address adjustment circuit includes an adjustment table. For each unused second-class storage block, the adjustment table stores the address of the second-class storage block as a first mapped storage block address and stores the address of the main storage block mapped to the first mapped storage block address as a second mapped storage block address.

7. The memory device according to claim 6, wherein, When the received storage block address for accessing the storage block corresponds to the first mapped storage block address stored in the adjustment table, the address adjustment circuit provides the second mapped storage block address instead of the first mapped storage block address to the address decoder.

8. The memory device according to claim 1, further comprising: The peripheral circuitry performs read operations on the second type of memory block; as well as Control logic controls the peripheral circuits. The address management circuit receives an address allocation command for the second type of memory block from the control logic, and in response to the address allocation command, transmits a read start command for the second type of memory block to the control logic.

9. A method of operating a memory device, the method comprising: A read request is sent to the second type of storage block in the first type of storage block and the second type of storage block. The main storage block address is assigned to the first type of storage block and the user data is stored in the first type of storage block. No user data is stored in the second type of storage block. Based on the data read from each of the second type of storage blocks, set flag information indicating the usage status of each of the second type of storage blocks; as well as Based on the flag information, the main storage block address is selectively assigned to each of the second type of storage blocks.

10. The method of claim 9, further comprising outputting a flag value based on the read data. in, Setting the flag information includes setting the final flag value among the flag values ​​associated with each of the second type of storage blocks to the flag information.

11. The method according to claim 9, wherein, Setting the flag information includes storing the flag information and the address information of the second type of storage block corresponding to the flag information.

12. The method according to claim 9, wherein, The allocation of the main storage block address includes selectively allocating the main storage block address to each of the second type of storage block based on the flag information, the address information corresponding to the flag information, and the last main storage block address information. The last primary storage block address information includes information about the address of the last primary storage block most recently allocated to the storage block used to store user data.

13. The method according to claim 12, wherein, The allocated primary memory block address corresponds to the next primary memory block address after the last primary memory block address.

14. The method according to claim 9, wherein, When the adjustment table is configured for each unused second-class storage block, it stores the address of the second-class storage block as the first mapped storage block address, and stores the address of the primary storage block mapped to the first mapped storage block address as the second mapped storage block address. The method further includes providing the second mapped storage block address corresponding to the first mapped storage block address to the address decoder when the received storage block address for accessing the storage block corresponds to the first mapped storage block address stored in the adjustment table.

15. The method according to claim 9, wherein, When an address allocation command for the second type of storage block is received, the transmission of the read request is executed.

16. A memory device, comprising: The memory cell array includes a first type of memory block and a second type of memory block. The main memory block address is assigned to the first type of memory block and user data is stored in the first type of memory block. No user data is stored in the second type of memory block. The address management circuit stores preset flag information indicating the usage status of each of the second type of memory blocks; as well as The address adjustment circuit selectively allocates the main memory block address to each of the second type of memory blocks based on the preset flag information.

17. The memory device according to claim 16, wherein, The address adjustment circuit selectively allocates the main storage block address to each of the second type of storage blocks based on the preset flag information, the address information of the second type of storage block corresponding to the preset flag information, and the last main storage block address information. The last main storage block address information includes information about the last main storage block address most recently allocated to the storage block used to store user data.

18. The memory device according to claim 17, wherein, The address adjustment circuit assigns the address of the next main memory block after the last main memory block address to the second type of memory block that has flag information indicating the erase status.

19. The memory device according to claim 16, wherein, The address adjustment circuit includes an adjustment table. For each unused second-class storage block, the adjustment table stores the address of the second-class storage block as a first mapped storage block address and stores the address of the main storage block mapped to the first mapped storage block address as a second mapped storage block address.

20. The memory device according to claim 19, wherein, When the received storage block address for accessing the storage block corresponds to the first mapped storage block address stored in the adjustment table, the address adjustment circuit provides the second mapped storage block address instead of the first mapped storage block address to the address decoder.

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