Semiconductor device

Abstract

A semiconductor device includes a first semiconductor structure including a first memory string, a first even bit line, and a first odd bit line, a second semiconductor structure bonded to the first semiconductor structure and including a second memory string, a second even bit line, and a second odd bit line, and a third semiconductor structure bonded to the first semiconductor structure and including an even page buffer shared by the first even bit line and the second even bit line, an odd page buffer shared by the first odd bit line and the second odd bit line, and a peripheral circuit located between the even page buffer and the odd page buffer.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to electronic devices, and more specifically, to a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as advancements in the integration density of semiconductor devices with memory cells formed as a single layer on a substrate have approached their physical limits, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to enhance the operational reliability of these semiconductor devices. However, further improvements are still needed to meet the ever-growing demand for more compact and higher-performance semiconductor devices. Summary of the Invention

[0003] According to embodiments of this disclosure, an improved three-dimensional semiconductor device (hereinafter referred to as a semiconductor device) is provided.

[0004] Some advantages of the implementation methods provide a semiconductor device with a stable structure and improved characteristics. Therefore, in embodiments of this disclosure, a semiconductor device may include: a first semiconductor structure including a first memory string, a first even bit line, and a first odd bit line; a second semiconductor structure coupled to the first semiconductor structure and including a second memory string, a second even bit line, and a second odd bit line; and a third semiconductor structure coupled to the first semiconductor structure and including an even page buffer shared by the first and second even bit lines, an odd page buffer shared by the first and second odd bit lines, and peripheral circuitry located between the even page buffer and the odd page buffer.

[0005] In another embodiment of this disclosure, a semiconductor device may include: a first semiconductor structure including a first memory string, a first even bit line, a first odd bit line, a first dummy bit line, and a second dummy bit line; a second semiconductor structure coupled to the first semiconductor structure and including a second memory string, a second even bit line, and a second odd bit line; and a third semiconductor structure coupled to the first semiconductor structure and including an even page buffer shared by the first even bit line and the second even bit line, and an odd page buffer shared by the first odd bit line and the second odd bit line, wherein the second odd bit line can be connected to the odd page buffer via the first dummy bit line.

[0006] Those skilled in the art will better understand these and other features and advantages of embodiments of this disclosure from the following accompanying drawings and detailed description. Attached Figure Description

[0007] Figure 1A and Figure 1BThis is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4A and Figure 4B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 5A and Figure 5B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 8 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 9 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0016] Various embodiments of this disclosure relate to a semiconductor device having a stable structure and improved properties, and a method of manufacturing the semiconductor device.

[0017] By using three-dimensional stacked memory cells, the integration density of semiconductor devices can be improved. It also provides a semiconductor device with a stable structure and improved reliability.

[0018] Hereinafter, embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0019] Figure 1A and Figure 1B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A It is a block diagram showing the configuration of a semiconductor device, and Figure 1B This is a circuit diagram showing the configuration of a memory cell array.

[0020] Reference Figure 1A and Figure 1BThe semiconductor device 100 according to the embodiment may include a memory cell array 110, peripheral circuitry 120, a line decoder 130, and a read / write circuitry 140.

[0021] The memory cell array 110 may include memory cells MC. Memory cells MC may be volatile or non-volatile memory cells. For example, the memory cell array 110 may include a first memory cell array and a second memory cell array interconnected by a bonding structure. The memory cell array 110 may include memory blocks, each memory block may include a memory string MS. Each memory string MS may include at least one drain selection transistor DST, a plurality of memory cells MC, and at least one source selection transistor SST connected in series with each other.

[0022] The memory cell array 110 can be connected to the row decoder 130 via row lines RL. The row lines RL may include at least one drain select line DSL, multiple word lines WL, and at least one source select line SSL. The memory cell array 110 can be connected to the read / write circuitry 140 via bit lines BL.

[0023] The row decoder 130 can select one of the memory blocks included in the memory cell array 110 in response to the row address R_ADD provided from the peripheral circuitry 120. The row decoder 130 can transmit the operating voltage R_V provided from the peripheral circuitry 120 to the memory cell array 110 via the row line RL.

[0024] The read / write circuit 140 may include multiple page buffers PB, each connected to a bit line BL. For example, the bit line BL may include odd-numbered bit lines BLo and even-numbered bit lines BLe, and the read / write circuit 140 may include odd-numbered page buffers and even-numbered page buffers. The read / write circuit 140 may receive a page buffer control signal PB_C from peripheral circuit 120, and may send and receive a data signal DATA from peripheral circuit 120. The read / write circuit 140 may control the bit line BL in response to the page buffer control signal PB_C. The read / write circuit 140 may write data to or read data from a memory cell MC connected to an enabled word line.

[0025] During programming operations, the read / write circuit 140 can operate as a write driver. For example, the read / write circuit 140 can apply a signal to the bit line BL based on the data signal DATA received from the peripheral circuit 120 in response to the page buffer control signal PB_C, and can accordingly write data to the memory cell MC of the memory cell array 110.

[0026] During read or verification operations, the read / write circuit 140 can operate as a sense amplifier. For example, the read / write circuit 140 can detect data stored in the memory cells of the memory cell array 110 by sensing the signal of the bit line BL in response to the page buffer control signal PB_C, and can send a data signal DATA to the peripheral circuit 120 based on the detected data.

[0027] The peripheral circuit 120 can receive command signals CMD, address signals ADD, and control signals CTRL from the controller, and can also send data signals DATA to and receive data signals DATA from the controller. Based on the received CMD, ADD, and CTRL signals, the peripheral circuit 120 can output signals for writing data to or reading data from the memory cell array 110.

[0028] To support the internal functions of the semiconductor device 100, the peripheral circuitry 120 can be configured to generate various internal voltages. The peripheral circuitry 120 can generate internal voltages of various levels required for the semiconductor device 100 to perform internal operations, and can provide the generated internal voltages to the line decoder 130. The internal voltages can be operating voltages R_V used for performing programming operations, read operations, erase operations, etc.

[0029] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, content repeated from the previous description may be omitted.

[0030] Reference Figure 2 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a third semiconductor structure S3. The first semiconductor structure S1 may include a first memory cell array 1, the second semiconductor structure S2 may include a second memory cell array 2, and the third semiconductor structure S3 may include an odd-numbered page buffer 3, an even-numbered page buffer 4, and peripheral circuitry 5.

[0031] A first semiconductor structure S1 may be located between a second semiconductor structure S2 and a third semiconductor structure S3. The first semiconductor structure S1 and the second semiconductor structure S2 may be in contact with each other, and a first bonding interface BI1 is inserted between them. The first semiconductor structure S1 and the second semiconductor structure S2 may be electrically connected to each other through a first bonding pad BP12 of the first semiconductor structure S1 and a second bonding pad BP2 of the second semiconductor structure S2.

[0032] The first semiconductor structure S1 and the third semiconductor structure S3 can be in contact with each other, and a second bonding interface BI2 is inserted between them. The first semiconductor structure S1 and the third semiconductor structure S3 can be electrically connected to each other through the first bonding pad BP11 of the first semiconductor structure S1 and the third bonding pad BP3 of the third semiconductor structure S3. In addition, the second semiconductor structure S2 and the third semiconductor structure S3 can be electrically connected to each other through the second bonding pad BP2, the first bonding pad BP12, the first bonding pad BP11, and the third bonding pad BP3.

[0033] According to the above structure, the odd-numbered page buffer 3 can be shared by the first memory cell array 1 and the second memory cell array 2. The even-numbered page buffer 4 can be shared by the first memory cell array 1 and the second memory cell array 2. The peripheral circuit 5 can be located between the odd-numbered page buffer 3 and the even-numbered page buffer 4.

[0034] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, content repeated from the previous description may be omitted.

[0035] Reference Figure 3A The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a third semiconductor structure S3. The first semiconductor structure S1 may include a first memory cell array, and the second semiconductor structure S2 may include a second memory cell array.

[0036] The first semiconductor structure S1 may include a first gate line GL1, a first channel structure CH1, a first slit structure SLS1, a first source line SL1, a first contact plug CT1, a second contact plug CT2, a first odd bit line BL1O, a first even bit line BL1E, a first dummy bit line D_BL1, a second dummy bit line D_BL2, and first bonding pads BP11A, BP11B, BP11C, BP11D, BP12C, and BP12D.

[0037] The first channel structure CH1 and the first slit structure SLS1 may extend through the stacked first gate line GL1. The first gate line GL1 may be a source select line, a word line, or a drain select line. Each first channel structure CH1 may include a channel layer, a memory layer surrounding the channel layer, and an insulating core located in the channel layer. Each first slit structure SLS1 may each include an insulating material, a semiconductor material, or a conductive material.

[0038] The first source line SL1 may be located above the first gate line GL1, while the first odd-numbered bit line BL1O and the first even-numbered bit line BL1E may be located below the first gate line GL1. Alternatively, the first source line SL1 may be located below the first gate line GL1, while the first odd-numbered bit line BL1O and the first even-numbered bit line BL1E may be located above the first gate line GL1.

[0039] Reference Figure 3A and Figure 3B The first odd-numbered bit line BL1O and the first even-numbered bit line BL1E may extend along a first direction I. The first odd-numbered bit line BL1O and the first even-numbered bit line BL1E may be arranged alternately along a second direction II that intersects the first direction I. The first dummy bit line D_BL1 may be located at the same or substantially the same height as the first odd-numbered bit line BL1O, and the second dummy bit line D_BL2 may be located at the same or substantially the same height as the first even-numbered bit line BL1E.

[0040] The second semiconductor structure S2 may include a second gate line GL2, a second channel structure CH2, a second slit structure SLS2, a second source line SL2, a second odd-numbered bit line BL2O, a second even-numbered bit line BL2E, and second bonding pads BP21 and BP22. The second channel structure CH2 and the second slit structure SLS2 may extend through the stacked second gate line GL2. The second gate line GL2 may be a source select line, a word line, or a drain select line. Each second channel structure CH2 may include a channel layer, a memory layer surrounding the channel layer, and an insulating core located within the channel layer. Each second slit structure SLS2 may each include an insulating material, a semiconductor material, or a conductive material.

[0041] like Figure 3A As shown, the second source line SL2 can be located above the second gate line GL2, and the second odd-numbered bit line BL2O and the second even-numbered bit line BL2E can be located below the second gate line GL2. Alternatively, the second source line SL2 can be located below the second gate line GL2, and the second odd-numbered bit line BL2O and the second even-numbered bit line BL2E can be located above the second gate line GL2. The second odd-numbered bit line BL2O and the second even-numbered bit line BL2E can be arranged alternately.

[0042] The third semiconductor structure S3 may include a substrate 30, an odd-page buffer O_PB, an even-page buffer E_PB, peripheral circuitry 35, a first interconnect structure IC1, a second interconnect structure IC2, a third interconnect structure IC3, and third bonding pads BP31, BP32, BP33, and BP34. Peripheral circuitry 35 may be located between the odd-page buffer O_PB and the even-page buffer E_PB. The first interconnect structure IC1 may be connected to the odd-page buffer O_PB, the second interconnect structure IC2 may be connected to the even-page buffer E_PB, and the third interconnect structure IC3 may be connected to peripheral circuitry 35.

[0043] The odd-numbered page buffer O_PB may include a first odd-numbered switch SW1O, a second odd-numbered switch SW2O, and an odd-numbered sensing unit SSO. The even-numbered page buffer E_PB may include a first even-numbered switch SW1E, a second even-numbered switch SW2E, and an even-numbered sensing unit SSE.

[0044] The first odd-numbered bit line BL1O can be connected to the first odd-numbered switch SW1O via the first bonding pad BP11A, the third bonding pad BP31, and the first interconnect structure IC1. The first odd-numbered switch SW1O can be connected to the odd-numbered sensing unit SSO via the first interconnect structure IC1.

[0045] The second odd bit line BL2O can be connected to the second odd switch SW2O via the second bonding pad BP21, the first bonding pad BP12C, the first contact plug CT1, the first dummy bit line D_BL1, the first bonding pad BP11C, the third bonding pad BP33, and the first interconnect structure IC1. The second odd switch SW2O can be connected to the odd sensing unit SSO via the first interconnect structure IC1.

[0046] The first even-numbered bit line BL1E can be connected to the first even-numbered switch SW1E via the first bonding pad BP11B, the third bonding pad BP32, and the second interconnect structure IC2. The first even-numbered switch SW1E can be connected to the even-numbered sensing unit SSE via the second interconnect structure IC2.

[0047] The second even-numbered bit line BL2E can be connected to the second even-numbered switch SW2E via the second bonding pad BP22, the first bonding pad BP12D, the second contact plug CT2, the second dummy bit line D_BL2, the first bonding pad BP11D, the third bonding pad BP34, and the second interconnect structure IC2. The second even-numbered switch SW2E can be connected to the even-numbered sensing unit SSE via the second interconnect structure IC2.

[0048] According to the above structure, the odd-numbered page buffer O_PB can be shared by the first odd-numbered bit line BL1O and the second odd-numbered bit line BL2O. The even-numbered page buffer E_PB can be shared by the first even-numbered bit line BL1E and the second even-numbered bit line BL2E. The odd-numbered page buffer O_PB and the even-numbered page buffer E_PB can be distributed and disposed at opposite edges of the memory plane, and the peripheral circuitry is disposed at the center of the memory plane. As a result, even when the first semiconductor structure S1 and the second semiconductor structure S2 are joined together, the area occupied by the page buffers does not increase, although the spacing may increase. Therefore, this configuration allows for efficient resource sharing and space optimization within the memory plane.

[0049] Furthermore, the second odd-numbered bit line BL2O can be connected to the odd-numbered page buffer O_PB using the first dummy bit line D_BL1 of the first semiconductor structure S1. The second even-numbered bit line BL2E can be connected to the even-numbered page buffer E_PB using the second dummy bit line D_BL2 of the first semiconductor structure S1. When the first odd-numbered bit line BL1O and the first even-numbered bit line BL1E are formed, the first dummy bit line D_BL1 and the second dummy bit line D_BL2 can be formed together with the first odd-numbered bit line BL1O and the first even-numbered bit line BL1E. Therefore, even if the first semiconductor structure S1 and the second semiconductor structure S2 are bonded to each other, the second semiconductor structure S2 can be connected to the third semiconductor structure S3 without adding a wiring process.

[0050] Figure 4A and Figure 4B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Figure 4A The layout of the third semiconductor structure S3 is shown. Figure 4B This shows the connection between the page buffer and the bit lines. Content repeated in the following description may be omitted.

[0051] Reference Figure 4A and Figure 4B The third semiconductor structure S3 may include an odd-page buffer region OPB_R, an even-page buffer region EPB_R, and a peripheral circuit region PC_R disposed between the odd-page buffer region OPB_R and the even-page buffer region EPB_R. Multiple odd-page buffers O_PB may be located within the odd-page buffer region OPB_R. Multiple even-page buffers E_PB may be located within the even-page buffer region EPB_R. The peripheral circuit region PC_R located between the odd-page buffer region OPB_R and the even-page buffer region EPB_R may include peripheral circuitry 25.

[0052] When the layout of the memory plane PL included in the first semiconductor structure S1 and the layout of the third semiconductor structure S3 are compared with each other, the odd-numbered page buffer region OPB_R and the even-numbered page buffer region EPB_R can be distributed and disposed at the opposite edges of the memory plane PL. The peripheral circuit region PC_R can be located at the center of the memory plane PL.

[0053] The odd-numbered page buffer region OPB_R may include multiple high-voltage regions Ho and multiple low-voltage regions Lo. The high-voltage regions Ho and low-voltage regions Lo may be arranged in an alternating sequence of two high-voltage regions followed by two low-voltage regions. That is, two high-voltage regions Ho and two low-voltage regions Lo may be arranged alternately, and this arrangement may be repeated as needed. The even-numbered page buffer region EPB_R may include multiple high-voltage regions He and multiple low-voltage regions Le. The high-voltage regions He and low-voltage regions Le may also be arranged in an alternating pattern of two high-voltage regions and two low-voltage regions. That is, two high-voltage regions He and two low-voltage regions Le may be arranged alternately. This arrangement may be repeated as needed.

[0054] The odd-numbered page buffer O_PB may include a first odd-numbered switch SW1O, a second odd-numbered switch SW2O, and an odd-numbered sensing unit SSO. The first odd-numbered switch SW1O controls the connection between the odd-numbered page buffer O_PB and the first odd-numbered bit line BL1O. The second odd-numbered switch SW2O controls the connection between the odd-numbered page buffer O_PB and the second odd-numbered bit line BL2O.

[0055] The odd-number sensing unit SSO is used to sense data from the first odd-number bit line BL1O and the second odd-number bit line BL2O, and may include a latch. The odd-number sensing unit SSO can be connected to a first node N1, and the first node N1 can be connected to the first odd-number bit line BL1O via a first odd-number switch SW1O or to the second odd-number bit line BL2O via a second odd-number switch SW2O.

[0056] The first odd-numbered switch SW10 and the second odd-numbered switch SW20 may be located in the high-voltage region Ho and may include a high-voltage transistor. The odd-numbered sensing unit SSO may be located in the low-voltage region Lo and may include a low-voltage transistor. The high-voltage transistor may have a larger size and channel length than the low-voltage transistor. Even if a high voltage is applied to the first odd-numbered bit line BL10 and / or the second odd-numbered bit line BL20 during an erase operation, the first odd-numbered switch SW10 and the second odd-numbered switch SW20, including the high-voltage transistor, will not be damaged. Furthermore, by turning off the first odd-numbered switch SW10 and the second odd-numbered switch SW20, high voltage transmission to the odd-numbered sensing unit SSO can be prevented.

[0057] The even-numbered page buffer E_PB may include a first even-numbered switch SW1E, a second even-numbered switch SW2E, and an even-numbered sensing unit SSE. The first even-numbered switch SW1E controls the connection between the even-numbered page buffer E_PB and the first even-numbered bit line BL1E. The second even-numbered switch SW2E controls the connection between the even-numbered page buffer E_PB and the second even-numbered bit line BL2E.

[0058] The even-number sensing unit SSE can be configured to sense data from the first even-number bit line BL1E and the second even-number bit line BL2E. The even-number sensing unit SSE can sense data from the first even-number bit line BL1E and the second even-number bit line BL2E, and may include a latch. The even-number sensing unit SSE can be connected to a second node N2, which can be connected to the first even-number bit line BL1E via a first even-number switch SW1E or to the second even-number bit line BL2E via a second even-number switch SW2E.

[0059] The first even-numbered switch SW1E and the second even-numbered switch SW2E may be located in the high-voltage region He and may include high-voltage transistors. The even-numbered sensing unit SSE may be located in the low-voltage region Le and may include low-voltage transistors. For example, during an erase operation, a high voltage may be applied to the first even-numbered bit line BL1E and / or the second even-numbered bit line BL2E, and by turning off the first even-numbered switch SW1E and the second even-numbered switch SW2E, the high voltage transmission to the even-numbered sensing unit SSE can be prevented.

[0060] According to the above configuration, the odd-numbered page buffer O_PB located in the third semiconductor structure S3 can be shared by the first odd-numbered bit line BL1O of the first semiconductor structure S1 and the second odd-numbered bit line BL2O of the second semiconductor structure S2. During a read operation, when the first odd-numbered switch SW1O is turned on and the second odd-numbered switch SW2O is turned off, the first odd-numbered bit line BL1O is selected. The current of the first odd-numbered bit line BL1O is transmitted to the odd-numbered sensing unit SSO through the first node N1, and the current level of the first odd-numbered bit line BL1O is read by the sensing circuit of the odd-numbered sensing unit SSO.

[0061] The even-numbered page buffer E_PB located in the third semiconductor structure S3 can be shared by the first even-numbered bit line BL1E of the first semiconductor structure S1 and the second even-numbered bit line BL2E of the second semiconductor structure S2. During a read operation, the first even-numbered bit line BL1E is selected when the first even-numbered switch SW1E is turned on and the second even-numbered switch SW2E is turned off. The current of the first even-numbered bit line BL1E is transmitted to the even-numbered sensing unit SSE through the second node N2, and the current level of the first even-numbered bit line BL1E is read by the sensing circuit of the even-numbered sensing unit SSE.

[0062] Figure 5A and Figure 5B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. In the following text, content repeated from the previous description may be omitted.

[0063] Reference Figure 5A and Figure 5BThe semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a third semiconductor structure S3. The first semiconductor structure S1 may include a first odd-numbered bit line BL1O and a first even-numbered bit line BL1E, and the second semiconductor structure S2 may include a second odd-numbered bit line BL2O and a second even-numbered bit line BL2E.

[0064] The third semiconductor structure S3 may include an active region ACT located in a high-voltage region and a gate line G. The active region ACT may be arranged along a first direction I, and the gate line G may extend along a second direction II. For example, two gate lines G may be located on one active region ACT, and the high-voltage transistor may be arranged along the first direction I and the second direction II. The high-voltage transistor may be a first odd-numbered switch SW1O, a second odd-numbered switch SW2O, a first even-numbered switch SW1E, or a second even-numbered switch SW2E.

[0065] Because the first semiconductor structure S1 and the third semiconductor structure S3 are arranged facing each other, the first even-numbered bit line BL1E and the first odd-numbered bit line BL1O can be directly connected to their respective target nodes. As used herein, "direct connection" refers to a vertical connection path to a node that does not involve horizontal detours. Specifically, the first odd-numbered bit line BL1O can be directly connected to the third node N32 and the fourth node N42, while the first even-numbered bit line BL1E can be directly connected to the fifth node N52 and the sixth node N62. This configuration allows for efficient vertical interconnection between semiconductor structures, thereby minimizing layout complexity and improving integration density.

[0066] Since the first semiconductor structure S1 is located between the second semiconductor structure S2 and the third semiconductor structure S3, the second even-numbered bit line BL2E and the second odd-numbered bit line BL2O may not be directly connected to their respective target nodes. Instead, these bit lines can be routed to the desired nodes via the first interconnect structure IC1 and the second interconnect structure IC2 disposed in the third semiconductor structure S3. Despite the physical separation, this indirect routing allows for efficient signal connectivity, thereby supporting more flexible and densely stacked semiconductor architectures.

[0067] The second odd-numbered bit line BL2O can be connected to the first dummy bit line D_BL1 via the first contact plug CT11, and can also be connected to the third node N31 via the first dummy bit line D_BL1. The second odd-numbered bit line BL2O can be connected to the first dummy bit line D_BL1 via the first contact plug CT12, and can also be connected to the fourth node N41 via the first bypass path P1. The first bypass path P1 can be provided via the first interconnect structure IC1 of the third semiconductor structure S3.

[0068] The second even-numbered bit line BL2E can be connected to the second dummy bit line D_BL2 via the second contact plug CT21, and can also be connected to the fifth node N51 via the second dummy bit line D_BL2. The second even-numbered bit line BL2E can be connected to the second dummy bit line D_BL2 via the second contact plug CT22, and can also be connected to the sixth node N61 via the fourth bypass path P4. The fourth bypass path P4 can be provided via the second interconnect structure IC2 of the third semiconductor structure S3.

[0069] First node N11 can be connected to the odd-numbered sensing unit SSO via the second path P2 provided by the first interconnect structure IC1. First node N12 can be connected to the odd-numbered sensing unit SSO via the third path P3 provided by the first interconnect structure IC1. Second node N21 can be connected to the even-numbered sensing unit SSE via the fifth path P5 provided by the second interconnect structure IC2. Second node N22 can be connected to the even-numbered sensing unit SSE via the sixth path P6 provided by the second interconnect structure IC2.

[0070] According to the above structure, a bypass path can be provided through the first interconnect structure IC1 and the second interconnect structure IC2 of the third semiconductor structure S3. Therefore, the second odd-numbered bit line BL2O and the second even-numbered bit line BL2E of the second semiconductor structure S2 can be connected to the desired node.

[0071] Figure 6 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0072] Reference Figure 6 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a third semiconductor structure S3. The first semiconductor structure S1 may be located between the third semiconductor structure S3 and the second semiconductor structure S2. The first semiconductor structure S1 may be coupled to both the third semiconductor structure S3 and the second semiconductor structure S2.

[0073] The first semiconductor structure S1 may include a first memory cell array. The first semiconductor structure S1 may include a first gate structure GST1, a first source line SL1, a first channel structure CH1, a first drain select line DSL1, a first contact structure CS1, a first insulating spacer SP1, a first bit line BL1, a contact plug CT, a dummy bit line D_BL, first bonding pads BP11 and BP12, and first bonding layers BD11 and BD12.

[0074] The first gate structure GST1 may include alternating layers of conductive layers 11 and insulating layers 12. For example, the conductive layer 11 may include at least one first source select line and multiple first word lines. The first source line SL1 may be located above the first gate structure GST1. The first drain select line DSL1 may be located below the first gate structure GST1.

[0075] The first channel structure CH1 may include a first sub-channel structure CH11 and a second sub-channel structure CH12. The first sub-channel structure CH11 may extend through the first gate structure GST1 and may be connected to the first source line SL1. The second sub-channel structure CH12 may extend through the first drain select line DSL1 and may be connected to the first sub-channel structure CH11 and the first bit line BL1.

[0076] The first contact structure CS1 may extend through the first gate structure GST1 and may be connected to the conductive layer 11. First insulating spacers SP1 may surround the sidewalls of the first contact structure CS1. These first insulating spacers SP1 are used to electrically isolate the first contact structure CS1 from adjacent components, such that each first contact structure CS1 may contact only one conductive layer 11.

[0077] The second semiconductor structure S2 may include a second memory cell array. The second semiconductor structure S2 may include a second gate structure GST2, a second source line SL2, a second channel structure CH2, a second drain select line DSL2, a second contact structure CS2, a second insulating spacer SP2, a second bit line BL2, a second bonding pad BP2, and a second bonding layer BD2.

[0078] The second gate structure GST2 may include alternating layers of conductive layer 21 and insulating layer 22. For example, conductive layer 21 may include at least one second source select line and multiple second word lines. The second source line SL2 may be located above the second gate structure GST2. The second drain select line DSL2 may be located below the second gate structure GST2.

[0079] The second channel structure CH2 may include a first sub-channel structure CH21 and a second sub-channel structure CH22. The first sub-channel structure CH21 may extend through the second gate structure GST2 and may be connected to the second source line SL2. The second sub-channel structure CH22 may extend through the second drain select line DSL2 and may be connected to the first sub-channel structure CH21 and the second bit line BL2.

[0080] The second contact structure CS2 may extend through the second gate structure GST2 and may be connected to the conductive layer 21. The second insulating spacers SP2 may surround the sidewalls of the second contact structures CS2 to ensure that each second contact structure CS2 can be connected to only one of the conductive layers 21.

[0081] The third semiconductor structure S3 may include circuitry for driving the first memory cell array and the second memory cell array. For example, the circuitry may include peripheral circuitry, odd-page buffers, even-page buffers, etc. The third semiconductor structure S3 may include a semiconductor substrate 30, a transistor TR, a third bonding pad BP3, and a third bonding layer BD3.

[0082] The first bonding layer BD11 and the third bonding layer BD3 can be bonded to each other, and the first bonding layer BD12 and the second bonding layer BD2 can be bonded to each other. The first bonding pad BP11 and the third bonding pad BP3 can be electrically connected to each other, and the first bonding pad BP12 and the second bonding pad BP2 can be electrically connected to each other.

[0083] According to the above structure, the first bit line BL1 can be connected to the transistor TR of the third semiconductor structure S3 through the first bonding pad BP11 and the third bonding pad BP3. The second bit line BL2 can be connected to the transistor TR of the third semiconductor structure S3 through the second bonding pad BP2, the first bonding pad BP12, the contact plug CT, the dummy bit line D_BL, the first bonding pad BP11, and the third bonding pad BP3.

[0084] Figure 7 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0085] Reference Figure 7 The semiconductor device may include a gate structure GST, a drain select line DSL, a channel structure CH, a slit structure SLS, a contact structure CS, and an insulating spacer SP surrounding the contact structure CS.

[0086] The slit structure SLS can extend through the gate structure GST in a first direction I. For example, the slit structure SLS may include irregular structures on its sidewalls. First, a plurality of holes arranged in the first direction I can be formed at the location where the slit is to be formed. These plurality of holes can be formed simultaneously with the channel holes. Subsequently, a slit with irregular structures on its sidewalls can be formed by enlarging the holes to connect them to each other. The slit structure SLS can then be formed in the slit. For reference, the slit structure SLS may also have a linear shape without irregular structures.

[0087] The drain select lines DSL may be adjacent to each other in a second direction II that intersects with the first direction I, and may extend along the first direction I. In this embodiment, the gate structure GST and the drain select lines DSL are shown separately, but the drain select lines DSL may be included in the gate structure GST.

[0088] The contact structures CS may have different heights and may be individually connected to the conductive layers belonging to the gate structure GST. The contact structures CS may extend through the gate structure GST. Alternatively, the gate structure GST may include a stepped structure, with individual pads of the conductive layers defined by the stepped structure. In this case, the contact structures CS may be individually connected to the pads.

[0089] The structure and manufacturing method according to the above embodiments can be applied to semiconductor devices with various structures. Figure 8 and Figure 9 A schematic configuration of a semiconductor device applicable to the above embodiments is shown.

[0090] Figure 8 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0091] Reference Figure 8 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on the same substrate.

[0092] The substrate SUB may be made of or comprise a semiconductor material. In embodiments, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors may include ZnS, ZnO, or CdS.

[0093] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0094] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB may include Group II, III, IV, V, or VI impurities. In an embodiment, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0095] The peripheral circuitry PC can be disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In some embodiments, the peripheral circuitry PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wires, etc.

[0096] A memory cell array (CA) may include memory cells. In one embodiment, the memory cell array (CA) may include memory strings connected between source lines and bit lines, each memory string comprising stacked memory cells. In another embodiment, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0097] Figure 9 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0098] Reference Figure 9 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may also include a support base SP_B.

[0099] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. In an embodiment, after fabricating a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer can be electrically connected via a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer can be removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0100] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown using selective epitaxial growth (SEG), or a layer formed using metal-induced lateral crystallization (MILC). The support substrate SP_B can be monocrystalline, polycrystalline, or amorphous. The support substrate SP_B can include Group II, Group III, Group IV, Group V, or Group VI impurities.

[0101] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In embodiments, the memory cell array CA and the peripheral circuit PC can be bonded using wafer-to-wafer bonding, chip-to-wafer bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. The bonding pads may include metals and / or alloys such as copper and aluminum. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected through the bonding structure BS.

[0102] For reference, interconnect structures included in the memory cell array (CA) and / or peripheral circuitry (PC) can be directly connected without bonding pads. In an embodiment, bonding layers included in the memory cell array (CA) and bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, and interconnect structures included in the memory cell array (CA) and interconnect structures included in the peripheral circuitry (PC) can be directly connected. Thus, contacts, wires, etc., formed on different wafers can be electrically connected without separate bonding pads.

[0103] Other configurations can be referenced above. Figure 8 The configurations described are the same or similar.

[0104] Additionally, semiconductor devices may have the above reference. Figure 8 and Figure 9 The described implementation scheme may have a structure, or a structure that may have some modifications. (Refer to...) Figure 8 and Figure 9 In the described implementation, the positions of the memory cell array CA and the peripheral circuit PC can be changed. At least one memory cell array CA and / or at least one peripheral circuit PC can be additionally coupled to a reference. Figure 8 and Figure 9 The described implementation method. In this implementation method, a portion of the peripheral circuitry PC may be located in the memory cell array CA.

[0105] While the foregoing description provides exemplary embodiments based on the technical concepts of this disclosure, these embodiments are presented merely for the purpose of description in conjunction with the accompanying drawings. Embodiments of this disclosure are not limited to the specific embodiments described herein. Various modifications, substitutions, alterations, and combinations of embodiments will occur to those skilled in the art without departing from the scope and technical concepts of this disclosure as defined by the following claims. It will be understood that such modifications and substitutions are covered within the scope of this disclosure.

[0106] Cross-reference to related applications

[0107] This application claims priority to Korean Patent Application No. 10-2025-0052993, filed on April 23, 2025, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A first semiconductor structure, the first semiconductor structure including a first memory string, a first even bit line and a first odd bit line; A second semiconductor structure is bonded to the first semiconductor structure and includes a second memory string, a second even bit line, and a second odd bit line. as well as A third semiconductor structure is coupled to the first semiconductor structure and includes an even-page buffer shared by the first even-number bit line and the second even-number bit line, an odd-page buffer shared by the first odd-number bit line and the second odd-number bit line, and peripheral circuitry located between the even-page buffer and the odd-page buffer.

2. The semiconductor device according to claim 1, wherein, The odd-page buffer includes: A first odd-numbered switch controls the connection between the first odd-numbered bit line and the odd-numbered page buffer; A second odd-number switch controls the connection between the second odd-number bit line and the odd-number page buffer; and An odd-number sensing unit is connected to the first odd-number bit line via the first odd-number switch or to the second odd-number bit line via the second odd-number switch.

3. The semiconductor device according to claim 2, wherein, During the read operation, the first odd switch is turned on, the second odd switch is turned off, and the current of the first odd bit line is transmitted to the odd sensing unit.

4. The semiconductor device according to claim 2, wherein, The first odd-numbered switch and the second odd-numbered switch include high-voltage transistors.

5. The semiconductor device according to claim 2, wherein, The odd-number sensing unit includes a low-voltage transistor.

6. The semiconductor device according to claim 1, wherein, The even-numbered page buffer includes: A first even-numbered switch controls the connection between the first even-numbered bit line and the even-numbered page buffer; A second even-numbered switch controls the connection between the second even-numbered bit line and the even-numbered page buffer; and An even-numbered sensing unit is connected to the first even-numbered bit line via the first even-numbered switch or to the second even-numbered bit line via the second even-numbered switch.

7. The semiconductor device according to claim 6, wherein, During the read operation, the first even-numbered switch is turned on, the second even-numbered switch is turned off, and the current of the first even-numbered bit line is transmitted to the even-numbered sensing unit.

8. The semiconductor device according to claim 6, wherein, The first even-numbered switch and the second even-numbered switch include high-voltage transistors.

9. The semiconductor device according to claim 6, wherein, The even-numbered sensing unit includes a low-voltage transistor.

10. The semiconductor device according to claim 1, wherein, The first semiconductor structure further includes a first dummy bit line located at substantially the same height as the first odd bit line, and The second odd bit line is connected to the odd page buffer via the first dummy bit line.

11. The semiconductor device according to claim 1, wherein, The first semiconductor structure further includes a second dummy bit line located at substantially the same height as the first even-numbered bit line, and The second even-numbered bit line is connected to the even-numbered page buffer via the second dummy bit line.

12. A semiconductor device comprising: A first semiconductor structure includes a first memory string, a first even bit line, a first odd bit line, a first dummy bit line, and a second dummy bit line. A second semiconductor structure is bonded to the first semiconductor structure and includes a second memory string, a second even bit line, and a second odd bit line. as well as A third semiconductor structure, which is bonded to the first semiconductor structure, includes an even-numbered page buffer shared by the first even-numbered bit lines and the second even-numbered bit lines, and an odd-numbered page buffer shared by the first odd-numbered bit lines and the second odd-numbered bit lines. The second odd bit line is connected to the odd page buffer via the first dummy bit line.

13. The semiconductor device according to claim 12, wherein, The second even bit line is connected to the even page buffer via the second dummy bit line.

14. The semiconductor device according to claim 12, wherein, The first odd bit line and the first dummy bit line are at substantially the same height.

15. The semiconductor device according to claim 12, wherein, The first even bit line and the second dummy bit line are located at substantially the same height.

16. The semiconductor device according to claim 12, wherein, The third semiconductor structure also includes peripheral circuitry located between the even-page buffer and the odd-page buffer.

17. A semiconductor device comprising: A first semiconductor structure, the first semiconductor structure including a first memory cell stack, a first even bit line and a first odd bit line; A second semiconductor structure is bonded to the first semiconductor structure and includes a second memory cell stack, a second even bit line, and a second odd bit line. as well as A third semiconductor structure is coupled to the first semiconductor structure and includes an even-page buffer shared by the first even-number bit line and the second even-number bit line, an odd-page buffer shared by the first odd-number bit line and the second odd-number bit line, and peripheral circuitry located between the even-number page buffer and the odd-number page buffer. The even-numbered page buffer includes: A first even-numbered switch controls the connection between the first even-numbered bit line and the even-numbered page buffer; A second even-numbered switch controls the connection between the second even-numbered bit line and the even-numbered page buffer; and An even-numbered sensing unit is connected to the first even-numbered bit line via the first even-numbered switch or to the second even-numbered bit line via the second even-numbered switch.

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