Semiconductor device and method of operating a semiconductor device

Abstract

A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a refresh control circuit that generates a refresh address during a refresh operation, and a row decoder that decodes a row address during normal operation and decodes the refresh address during the refresh operation, the refresh address having a different number of bits than the row address.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0053173, filed on April 23, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to an integrated circuit technology, and more specifically, to a semiconductor device and a method of operating the semiconductor device. Background Technology

[0004] As the integration density of semiconductor devices increases, ensuring stable operation of transistors within those devices becomes increasingly difficult. Specifically, because gate linewidths are decreasing dramatically and transistor dimensions are shrinking due to finer manufacturing processes, the transistor characteristics that need to be ensured (such as threshold voltage, current drive capability, and operating speed) are approaching their limits.

[0005] Therefore, semiconductor devices that require a refresh operation to be performed at each set time to retain the data stored in the semiconductor device are being developed to increase the number of memory cells refreshed after a refresh operation is started, so as to reduce the frequency of refresh operations.

[0006] However, in these semiconductor devices, the power noise increases because a large number of memory cells are refreshed at once. This power noise can cause semiconductor device failure. Summary of the Invention

[0007] According to embodiments of this disclosure, a semiconductor device may include: a refresh control circuit that generates a refresh address during a refresh operation; and a row decoder that: decodes the row address during normal operation; and decodes the refresh address during a refresh operation, the refresh address having a different number of bits than the row address.

[0008] According to embodiments of this disclosure, a semiconductor device may include: a row decoder that decodes a row address during normal operation and a refresh address during a refresh operation; and a refresh control circuit that generates a refresh address during a refresh operation. The refresh address includes a number of bits fewer than the number of bits in the row address.

[0009] According to embodiments of this disclosure, a method of operating a semiconductor device may include: generating a refresh address during a refresh operation; decoding a row address during normal operation; and decoding the refresh address during the refresh operation. The refresh address includes a number of bits fewer than the number of bits in the row address. Attached Figure Description

[0010] Figure 1 This is a view illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A view showing the detailed configuration of the refresh control circuit.

[0012] Figure 3 and Figure 4 This is a timing diagram illustrating the operation of a semiconductor device according to embodiments of the present disclosure.

[0013] Other features, aspects, and advantages of the invention will become clear from the following description and drawings. Detailed Implementation

[0014] In the following description, embodiments based on the technical spirit of this disclosure are illustrated with reference to the accompanying drawings.

[0015] Various embodiments will now be described in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete, and fully conveys the scope of this disclosure to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily limited to only one embodiment, and different references to any such phrases are not necessarily the same embodiment(s). Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of this disclosure.

[0016] Embodiments of this disclosure relate to techniques for reducing power noise that occurs after a refresh operation has begun.

[0017] According to embodiments of this disclosure, semiconductor devices can ensure high operational stability by reducing power noise.

[0018] Figure 1 This is a view illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0019] refer to Figure 1 The semiconductor device may include a refresh control circuit 10, a line decoder 20, and a memory bank (i.e., a memory storage bank) 30.

[0020] The refresh control circuit 10 can receive a refresh command signal REF_C. When the refresh command signal REF_C is received, the refresh control circuit 10 can generate an internal refresh signal I_REF and a row address (i.e., refresh address) REF_RA<0:n-1> for refreshing. For example, when the refresh command signal REF_C is received, the refresh control circuit 10 can generate an internal refresh signal I_REF that is activated for a predetermined time. Furthermore, whenever the internal refresh signal I_REF is activated, the refresh control circuit 10 can generate a row address REF_RA<0:n-1> for refreshing with an incremented address value. In this case, the refresh command signal REF_C can be a signal that is periodically generated by a refresh command received from outside the semiconductor device, or it can be a signal that is periodically generated internally.

[0021] The line decoder 20 can enable multiple word lines WL based on the activation signal ACT, the precharge signal PCG, the line address (i.e., the line address used for normal operation) RA<0:n>, the internal refresh signal I_REF, and the line address REF_RA<0:n-1> used for refresh. <0> _Q0 to WL <m>_Q0, Multiple word lines <0> _Q1 to WL <m>_Q1, Multiple character lines <0> _Q2 to WL <m>_Q2 and multiple word lines <0> _Q3 to WL <m>One of _Q3. In this case, the activation signal ACT, the precharge signal PCG, and the row address RA<0:n> can each be a signal generated from a signal received from outside the semiconductor device.

[0022] For example, line decoder 20 can select a word line to be activated by decoding the line address RARA_<0:n>. Line decoder 20 can enable a selected word line in response to the activation signal ACT, and can deactivate (or precharge) the activated word line in response to the precharge signal PCG.

[0023] The line decoder 20 can select at least one word line to be activated by decoding the line address REF_RA<0:n-1> used for refreshing. When the internal refresh signal I_REF is received, the line decoder 20 can enable the selected at least one word line for a predetermined time. In this case, the number of word lines selected by decoding the line address REF_RA<0:n-1> used for refreshing can be different from the number of word lines selected by decoding the line address RA<0:n>. The number of word lines selected by decoding the line address REF_RA<0:n-1> used for refreshing can be greater than the number of word lines selected by decoding the line address RA<0:n>. Because the address value included in the line address REF_RA<0:n-1> used for refreshing is one bit smaller than the address value of the line address RA<0:n>, the number of word lines selected by decoding the line address REF_RA<0:n-1> used for refreshing can be twice the number of word lines selected by decoding the line address RA<0:n>. More specifically, for example, assuming there exists a row decoder that selects eight word lines and n is 2, then the row address RA<0:2> can have eight decoded values: 000, 001, 010, 011, 100, 101, 110, and 111. Since eight word lines need to be selected based on these eight decoded values, one decoded value can correspond to one word line. Because the row address REF_RA<0:1> used for refreshing can have four decoded values: 00, 01, 10, and 11, and eight word lines need to be selected based on these four decoded values, one decoded value can correspond to two word lines. The number of address bits included in the row address REF_RA<0:n-1> used for refreshing can be less than the number of address bits included in the row address RA<0:n>. For example, the row address REF_RA<0:n-1> used for refreshing can include fewer address bits than the row address RA<0:n>. <n>The address bits REF_RA included in the row address REF_RA<0:n-1> used for refreshing. <n-1>It can be the lowest row address bits used for refreshing.

[0024] The memory bank 30 may include first to fourth sub-memory banks Q0 31, Q1 32, Q2 33 and Q3 34. In this case, a memory bank may include multiple sub-memory banks. Figure 1 An embodiment is shown where a memory bank 30 includes four sub-memories Q0, Q1, Q2, and Q3. Additionally, multiple word lines WL are also shown. <0> _Q0 to WL <m>_Q0, multiple word lines WL <0> _Q1 to WL <m>_Q1, Multiple Word Lines WL <0> _Q2 to WL <m>_Q2 and multiple word lines WL <0> _Q3 to WL <m>_Q3 can include the first group of word lines WL. <0> _Q0 to WL <m>_Q0、Second group of word lines WL <0> _Q1 to WL <m>_Q1, Third group of letter lines WL <0> _Q2 to WL <m>_Q2 and the fourth group of word lines WL <0> _Q3 to WL <m>_Q3. First to fourth group of word lines WL <0> _Q0 to WL <m>_Q0、WL <0> _Q1 to WL <m>_Q1、WL <0> _Q2 to WL <m>_Q2 and WL <0> _Q3 to WL <m>Each group of word lines in _Q3 can include multiple word lines.

[0025] The first sub-memory Q0 may include connections to the first set of word lines WL <0> _Q0 to WL <m>Multiple storage units of _Q0.

[0026] The second sub-memory Q1 may include connections to the second word line WL. <0> _Q1 to WL <m>Multiple storage units of _Q1.

[0027] The third sub-memory Q2 may include a connection to the third word line WL. <0> _Q2 to WL <m>Multiple storage units of _Q2.

[0028] The fourth sub-memory Q3 may include connections to the fourth word line WL. <0> _Q3 to WL <m>Multiple storage units of _Q3.

[0029] In this configuration, the multiple memory cells included in each of the first to fourth sub-memory cells Q0, Q1, Q2, and Q3 can store data by receiving data via multiple bit lines (not shown), and the stored data can be transmitted. For example, a memory cell can be electrically connected between a word line and a bit line. When a word line is activated, the memory cell can be electrically connected to the bit line. When a word line is deactivated, the memory cell can be electrically disconnected from the bit line. The semiconductor device according to embodiments of this disclosure relates to word line operations; therefore, a description of the bit lines is omitted.

[0030] The first to fourth sets of word lines WL connected to the memory cells of memory bank 30 <0> _Q0 to WL <m>_Q0、WL <0> _Q1 to WL <m>_Q1、WL <0> _Q2 to WL <m>_Q2 and WL <0> _Q3 to WL <m>Each group of word lines in _Q3 can be selectively activated by the line decoder 20.

[0031] For example, after normal operation begins, the word line selected by the line decoder 20 as the line address RA<0:n> is decoded by the line decoder 20 can be the first group of word lines WL. <0> _Q0 to WL <m>_Q0、Second group of word lines WL <0> _Q1 to WL <m>_Q1, Third group of letter lines WL <0> _Q2 to WL <m>_Q2 and the fourth group of word lines WL <0> _Q3 to WL <m>One word line selected from a set of word lines in _Q3. That is, one of the sub-memory banks Q0, Q1, Q2, and Q3 may include a word line that is activated when the row address RA<0:n> is decoded by the row decoder 20. Furthermore, after the refresh operation begins, each of some of the sub-memory banks Q0, Q1, Q2, and Q3 may include a word line that is activated when the row address REF_RA<0:n-1> used for refresh is decoded by the row decoder 20.

[0032] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A view showing the detailed configuration of the refresh control circuit.

[0033] refer to Figure 2 The refresh control circuit 10 may include an internal refresh signal generation circuit 11 and a refresh address counting circuit 12.

[0034] Whenever a refresh command signal REF_C is received, the internal refresh signal generation circuit 11 can generate an internal refresh signal I_REF. In this case, the internal refresh signal I_REF can be in pulse form and can be activated for a predetermined time. The internal refresh signal generation circuit 11 may include a pulse generation circuit.

[0035] Whenever the internal refresh signal I_REF is activated, the refresh address counting circuit 12 can increment the address value of the row address REF_RA<0:n-1> used for refreshing. For example, whenever the internal refresh signal I_REF is activated, the refresh address counting circuit 12 can increment the address value of the row address RREF_RA<0:n-1> used for refreshing by +1. The refresh address counting circuit 12 may include a counting circuit, such as a counter.

[0036] Figure 3 and Figure 4 This is a timing diagram illustrating the operation of a semiconductor device according to embodiments of the present disclosure. In this case, Figure 3 and Figure 4 These are merely embodiments used to describe the operation of semiconductor devices and are not intended to limit the operation of semiconductor devices according to embodiments of this disclosure.

[0037] Figure 3 A timing diagram is shown of the operation of a semiconductor device according to an embodiment of the present disclosure via the row address RA<0:n> enable word line after it has begun normal operation.

[0038] After normal operation begins, the semiconductor device can enable one of a plurality of word lines by receiving an activation signal ACT and a row address RA<0:n> from an external source. In response to a precharge signal PCG received from an external source, the semiconductor device can deactivate the word line that was activated after normal operation began.

[0039] refer to Figure 3 The line decoder 20 can decode the line address RA<0:n> to obtain the first group of word lines WL. <0> _Q0 to WL <m>_Q0、Second group of word lines WL <0> _Q1 to WL <m>_Q1, Third group of letter lines WL <0> _Q2 to WL <m>_Q2 and the fourth group of word lines WL <0> _Q3 to WL <m>In _Q3, select a group of letter lines, and you can also select one letter line to include in that selected group. In this case, Figure 3 This demonstrates how the first group of word lines WL is selected by decoding the row address RA<0:n> after normal operation has begun. <0> _Q0 to WL <m>_Q0, and included in the selected group of word lines WL <0> _Q0 to WL <m>One word line in _Q0 is activated. In this case, because the first set of word lines WL <0> _Q0 to WL <m>_Q0 includes word lines connected to the memory cells of the first sub-memory Q0, so a selected word line is shown as (Q0:WL). The second set of word lines is WL. <0> _Q1 to WL <m>_Q1 includes word lines connecting to the memory cells of the second sub-memory bank Q1. Therefore, when the second set of word lines WL <0> _Q1 to WL <m>When _Q1 is selected, in the second group of word lines WL <0> _Q1 to WL <m>The word line to be selected in _Q1 will be represented as (Q1:WL). The third group of word lines is WL. <0> _Q2 to WL <m>_Q2 includes word lines connecting to the memory cells of the third sub-memory bank Q2. Therefore, when the third set of word lines WL <0> _Q2 to WL <m>When _Q2 is selected, the third word line WL <0> _Q2 to WL <m>The word line to be selected in _Q2 will be represented as (Q2:WL). The fourth word line is WL. <0> _Q3 to WL <m>_Q3 includes word lines connecting to the memory cells of the fourth sub-memory bank Q3. Therefore, when the fourth set of word lines WL <0> _Q3 to WL <m>When _Q3 is selected, the fourth word line WL <0> _Q3 to WL <m>The word line to be selected in _Q3 will be shown as (Q3:WL).

[0040] When the activation signal ACT is received, the line decoder 20 can enable the first word line WL. <0> _Q0 to WL <m>The word line selected in _Q0 (Q0:WL).

[0041] When the precharge signal PCG is received, the line decoder 20 can deactivate the first word line WL. <0> _Q0 to WL <m>A word line (Q0:WL) that is active in _Q0.

[0042] After starting normal operation, when the first to fourth word lines WL <0> _Q0 to WL <m>_Q0、WL <0> _Q1 to WL <m>_Q1、WL <0> _Q2 to WL <m>_Q2 and WL <0> _Q3 to WL <m>When one of the selected word lines in the selected group of word lines in _Q3 is activated, data can be stored in a memory cell (not shown) via a bit line (not shown), or data stored in a memory cell can be output from the memory cell via a bit line.

[0043] Figure 4 A timing diagram is shown of the operation of a semiconductor device according to an embodiment of the present disclosure via the row address REF_RA<0:n-1> enable word line for refreshing.

[0044] Figure 4 The timing diagram shows the operation of enabling word lines after the refresh operation begins by using an internal refresh signal I_REF generated within the semiconductor device and the row address REF_RA<0:n-1> used for refresh.

[0045] refer to Figure 4 As a result of decoding the row address REF_RA<0:n-1> used for refreshing, when the lowest row address REF_RA used for refreshing... <n-1>When at a low level, the line decoder 20 can select the first group of word lines WL. <0> _Q0 to WL <m>One word line in _Q0 and the third group of word lines WL <0> _Q2 to WL <m>A word line in _Q2. Furthermore, as a result of decoding the row address REF_RA<0:n-1> used for refreshing, when the lowest row address REF_RA used for refreshing... <n-1>When at a high level, the line decoder 20 can select the second group of word lines WL. <0> _Q1 to WL <m>One word line in _Q1 and the fourth group of word lines WL <0> _Q3 to WL <m>A word line in _Q3. In this case, Figure 4 In the middle, because the first group of character lines WL <0> _Q0 to WL <m>_Q0 includes word lines connected to the memory cells of the first sub-memory Q0, so in the first set of word lines WL <0> _Q0 to WL <m>The selected word line in _Q0 is shown as (Q0:WL). This is because the second group of word lines is WL. <0> _Q1 to WL <m>_Q1 includes word lines connecting to the memory cells of the second sub-memory Q1, so in the second set of word lines WL <0> _Q1 to WL <m>The selected word line in _Q1 is shown as (Q1:WL). This is because the third group of word lines is WL. <0> _Q2 to WL <m>_Q2 includes word lines connecting to memory cells in the third sub-memory Q2, so in the third set of word lines WL <0> _Q2 to WL <m>The selected word line in _Q2 is shown as (Q2:WL). This is because the fourth word line is WL. <0> _Q3 to WL <m>_Q3 includes word lines connecting to the memory cells of the fourth sub-memory Q3, so in the fourth set of word lines WL <0> _Q3 to WL <m>The selected word line in _Q3 is shown as (Q3:WL).

[0046] During the period (or moment) when the internal refresh signal I_REF is first activated, that is, during the first rise time, the line decoder 20 can enable the first group of word lines WL <0> _Q0 to WL <m>The selected word line in _Q0 (Q0:WL) and the word line in the third group WL <0> _Q2 to WL <m>The selected word line in Q2 (Q2:WL). The lowest row address used for flushing, REF_RA, during the period when the internal refresh signal I_REF is first activated. <n-1>It can be at a low level.

[0047] During the period when the internal refresh signal I_REF is first deactivated, i.e., during the first fall timing, the line decoder 20 can deactivate the first word line WL. <0> _Q0 to WL <m>One word line activated in _Q0 (Q0:WL) and in the third group of word lines WL <0> _Q2 to WL <m>A word line (Q2:WL) that is activated in _Q2.

[0048] Subsequently, during the period when the internal refresh signal I_REF is activated for the second time, i.e., during the second rising time, the line decoder 20 can enable the second group of word lines WL. <0> _Q1 to WL <m>The selected word line in _Q1 (Q1:WL) and the word line in the fourth group WL <0> _Q3 to WL <m>The selected word line in Q3 (Q3:WL). The lowest row address used for flushing, REF_RA, during the period when the internal refresh signal I_REF is activated for the second time.<n+1> It can be at a high level.

[0049] During the period when the internal refresh signal I_REF is deactivated for the second time, that is, during the second fall timing, the line decoder 20 can deactivate the second word line WL. <0> _Q1 to WL <m>One word line activated in _Q1 (Q1:WL) and in the fourth group of word lines WL <0> _Q3 to WL <m>A word line (Q3:WL) that is active in _Q3.

[0050] The semiconductor device according to embodiments of this disclosure can reduce power noise after a refresh operation has begun because the semiconductor device is configured to minimize the number of word lines that are simultaneously activated by decoding the row address used for refresh (including fewer bits than the row address) after a refresh operation within a memory cell has begun.

[0051] Although embodiments according to the technical spirit of this disclosure have been described above with reference to the accompanying drawings, these embodiments are provided merely to illustrate embodiments based on the concept of this disclosure, and this disclosure is not limited to these embodiments. Those skilled in the art to which this disclosure pertains may substitute, modify, and alter the embodiments in various ways without departing from the technical spirit of this disclosure as set forth in the claims. Such substitutions, modifications, and alterations are said to fall within the scope of this disclosure.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / m> < / m> < / m>

Claims

1. A semiconductor device, comprising: A refresh control circuit that generates a refresh address during a refresh operation; as well as Line decoder, which: Decoding the row address during normal operation, and During the refresh operation, the refresh address is decoded, and the refresh address has a different number of bits than the row address.

2. The semiconductor device as claimed in claim 1, wherein, The row decoder receives the refresh address, which includes fewer bits than the row address.

3. The semiconductor device as claimed in claim 1, wherein, The refresh address has one fewer bit length than the row address.

4. The semiconductor device as claimed in claim 3, wherein, The refresh address does not include the bit corresponding to the least significant bit of the row address.

5. The semiconductor device as claimed in claim 4, wherein, The number of word lines selected by the line decoder during the refresh operation by decoding the refresh address is twice the number of word lines selected by the line decoder by decoding the line address during the normal operation.

6. The semiconductor device of claim 1, wherein, When a refresh command signal is received, the refresh control circuit: Generate an internal refresh signal; and Whenever the internal refresh signal is generated, the address value of the refresh address is increased.

7. The semiconductor device of claim 1, further comprising: The first sub-memory includes a plurality of memory cells electrically connected to a first set of word lines; The second sub-memory includes a plurality of memory cells electrically connected to a second set of word lines; The third sub-memory includes a plurality of memory cells electrically connected to a third set of word lines; as well as The fourth sub-memory bank includes multiple memory cells electrically connected to the fourth set of word lines. The first sub-storage to the fourth sub-storage form a storage unit.

8. The semiconductor device of claim 7, wherein, The line decoder: During the normal operation, select one group of character lines from the first group to the fourth group of character lines, and activate one character line included in the selected group of character lines. as well as During the refresh operation, one character line in each group of character lines from the first group to the fourth group is activated.

9. The semiconductor device of claim 8, wherein: The refresh address includes one less address bit than the row address. The least one of the address bits included in the refresh address is the least significant bit of the row address, and The line decoder: When the least significant bit of the refresh address is at the first level, one word line in each of the first group of word lines and the third group of word lines is activated. as well as During the refresh operation, when the least significant bit of the refresh address is at the second level, one word line included in each of the second and fourth word lines is activated.

10. A semiconductor device, comprising: Line decoder, which: Decoding the row address during normal operation, and Decode the refresh address during the refresh operation; and A refresh control circuit that generates the refresh address during the refresh operation. The refresh address includes fewer bits than the row address.

11. The semiconductor device of claim 10, wherein: The refresh address includes one less bit than the row address; and The refresh address does not include the bit corresponding to the least significant bit of the row address.

12. The semiconductor device of claim 11, wherein, The line decoder: During the normal operation, by decoding the row address, one word line from a plurality of word lines is selected, and During the refresh operation, two word lines are selected from the plurality of word lines by decoding the refresh address.

13. The semiconductor device of claim 12, further comprising: The first sub-memory includes a plurality of memory cells electrically connected to a first set of word lines of the plurality of word lines; The second sub-memory includes a plurality of memory cells that are electrically connected to a second set of word lines of the plurality of word lines; The third sub-memory includes a plurality of memory cells that are electrically connected to a third set of word lines of the plurality of word lines; as well as The fourth sub-memory includes a plurality of memory cells that are electrically connected to a fourth group of word lines of the plurality of word lines; The first sub-storage to the fourth sub-storage form a storage unit.

14. The semiconductor device of claim 13, wherein, The line decoder: During the normal operation, a word line included in one of the first to fourth sets of word lines is activated by decoding the line address; as well as During the refresh operation, one word line in each of the two sets of word lines from the first set to the fourth set of word lines is activated by decoding the refresh address.

15. The semiconductor device of claim 14, wherein, During the refresh operation, the row decoder: When the least significant bit of the refresh address is at the first level, one word line included in each of the first and third word lines is activated. as well as When the least significant bit of the refresh address is at the second level, one word line included in each of the second and fourth word lines is activated.

16. A method of operating a semiconductor device, the method comprising: Generate a refresh address during the refresh operation; Decode the row address during normal operation; as well as The refresh address is decoded during the refresh operation. The refresh address includes fewer bits than the row address.

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