Memory device, control method, storage system, and computer device

Abstract

The application discloses a memory device, a control method, a storage system and a computer device, and belongs to the technical field of storage. The memory device comprises a stacked storage array and a peripheral circuit. The storage array comprises a plurality of memory banks, and each memory bank comprises a plurality of memory blocks. The peripheral circuit comprises a plurality of bit line sense amplifiers and a first driving circuit connected with the bit line sense amplifiers. The first driving circuit comprises a first sub-circuit and at least one second sub-circuit. The first sub-circuit comprises a first level converter, and the second sub-circuit comprises a first inverter. The second sub-circuit overlaps the memory blocks in a stacking direction. The second sub-circuit is separated from the driving circuit and arranged in a region stacked with the memory banks. In this way, the spacing region between the memory banks can be reduced, and the storage density of the memory device is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory device, control method, storage system and computer equipment. Background Technology

[0002] With the development of storage technology, the storage performance and storage density of memory have been greatly improved.

[0003] A memory typically includes peripheral circuitry and a memory array. The peripheral circuitry includes bit-line sensing amplifiers and corresponding driver circuits. The memory array includes multiple memory banks, each containing multiple memory blocks. The driver circuits drive the bit-line sensing amplifiers to perform reading, refreshing, and other processing on the data in the memory blocks. Summary of the Invention

[0004] This application provides a memory device, a control method, a storage system, and a computer device, which can solve the problem of increasing the storage density of the memory device. The technical solution is as follows:

[0005] In a first aspect, a memory device is provided, comprising a stacked memory array and peripheral circuitry. The memory array includes a plurality of memory banks, each memory bank including a plurality of memory blocks. The peripheral circuitry includes a plurality of bit line sense amplifiers and a first driving circuit connected to the plurality of bit line sense amplifiers. The first driving circuitry includes a first sub-circuit and at least one second sub-circuit, the first sub-circuit including a first level shifter, and the second sub-circuit including a first inverter, the second sub-circuit overlapping the memory blocks in the stacking direction.

[0006] In some embodiments, the first sub-circuit overlaps with a first region in the memory array in the stacking direction, the first region being the region between memory cells.

[0007] In some embodiments, the first driving circuit includes a plurality of second sub-circuits. The input terminals of the plurality of second sub-circuits are respectively connected to the output terminals of the first sub-circuit, and the output terminal of each second sub-circuit is connected to the driving terminal of a bit line sensing amplifier.

[0008] In some embodiments, for multiple bit line sense amplifiers connected to the same first driving circuit, the memory blocks to which the multiple bit line sense amplifiers are respectively connected are memory blocks located in the same row in the memory bank.

[0009] In some embodiments, the peripheral circuitry further includes a second driving circuit connected to a plurality of bit line sensing amplifiers. The bit line sensing amplifiers include a first sensing unit and a second sensing unit. The first driving circuit is used to drive the first sensing unit, and the second driving circuit is used to drive the second sensing unit.

[0010] The second driving circuit includes a third sub-circuit and at least one fourth sub-circuit. The third sub-circuit includes a second level converter, and the fourth sub-circuit includes a second inverter. The control terminal of the first level converter included in the first driving circuit is connected to the control terminal of the second inverter included in the second driving circuit.

[0011] In some embodiments, for the first driving circuit: before a first time point, the first level converter receives a first high level and the first inverter receives a low level, so that the first inverter outputs the first high level, and the first time point is the time point at which the sensing phase switches to the pre-charging phase. After the first time point, both the first level converter and the first inverter receive a low level, so that the first inverter outputs a second high level, wherein the first high level is higher than the second high level.

[0012] In some embodiments, the first sub-circuit further includes a first signal processing unit, the input terminal of which is connected to the output terminal of a first level shifter, and the first signal processing unit includes a pair of transistors connected in parallel. The second sub-circuit further includes a second signal processing unit and a third signal processing unit, the input terminal of the second signal processing unit and the first input terminal of the third signal processing unit are connected to the output terminal of the first signal processing unit, the output terminal of the second signal processing unit is connected to the second input terminal of the third signal processing unit, and the output terminal of the third signal processing unit is connected to the input terminal of a first inverter. The second signal processing unit includes a pair of transistors connected in parallel, and the third signal processing unit includes two pairs of transistors connected in parallel.

[0013] In some embodiments, the second sub-circuit further includes a first signal processing unit, a second signal processing unit, and a third signal processing unit. The input terminal of the first signal processing unit is connected to the output terminal of the first level converter in the first sub-circuit. The input terminal of the second signal processing unit and the first input terminal of the third signal processing unit are connected to the output terminal of the first signal processing unit. The output terminal of the second signal processing unit is connected to the second input terminal of the third signal processing unit. The output terminal of the third signal processing unit is connected to the input terminal of the first inverter. The first signal processing unit includes a pair of transistors connected in parallel, the second signal processing unit includes a pair of transistors connected in parallel, and the third signal processing unit includes two pairs of transistors connected in parallel.

[0014] In some embodiments, the memory device is dynamic random access memory (DRAM).

[0015] Secondly, a control method for a memory device is provided. The memory device includes a memory array and peripheral circuitry. The memory array includes multiple memory banks, each of which includes multiple memory blocks. The peripheral circuitry includes bit line sensing amplifiers connected to the multiple memory blocks and a first driving circuit connected to the bit line sensing amplifiers. The first driving circuit includes a first sub-circuit and at least one second sub-circuit. The first sub-circuit includes a first level shifter, and the second sub-circuit includes a first inverter. The control method includes:

[0016] Before the first time point, the first level converter receives a first high level and the first inverter receives a low level, so that the first inverter outputs a first high level. The first time point is the time point at which the sensing phase switches to the pre-charging phase. After the first time point, both the first level converter and the first inverter receive a low level, so that the first inverter outputs a second high level, wherein the first high level is higher than the second high level.

[0017] In some embodiments, the first sub-circuit further includes a first signal processing unit, the input terminal of which is connected to the output terminal of a first level shifter, and the first signal processing unit includes a pair of transistors connected in parallel. The second sub-circuit further includes a second signal processing unit and a third signal processing unit, the input terminal of the second signal processing unit and the first input terminal of the third signal processing unit are connected to the output terminal of the first signal processing unit, the output terminal of the second signal processing unit is connected to the second input terminal of the third signal processing unit, and the output terminal of the third signal processing unit is connected to the input terminal of a first inverter. The second signal processing unit includes a pair of transistors connected in parallel, and the third signal processing unit includes two pairs of transistors connected in parallel.

[0018] In some embodiments, the control method further includes: before the second time point, a first level converter receives a low level to cause a second signal processing unit to output a first high level and a third signal processing unit to output a second high level, wherein the second time point is located within the row gating phase. After the second time point, the first level converter receives the first high level to cause the second signal processing unit to output a low level and the third signal processing unit to output the first high level.

[0019] In some embodiments, the first inverter includes a first input terminal and a second input terminal, wherein the first input terminal is connected to the output terminal of the third signal processing unit.

[0020] In some embodiments, before a first time point, a first level converter receives a first high level and a first inverter receives a low level, so that the first inverter outputs a first high level, including:

[0021] Before the first time point: the first level converter receives a first high level, causing the third signal processing unit to output a first high level to the first input terminal. The first inverter receives a low level through the second input terminal, and outputs a first high level under the influence of the first high level received at the first input terminal.

[0022] In some embodiments, the first level converter receives a first high level to cause the third signal processing unit to output a first high level to the first input terminal, including: the first level converter receiving the first high level and outputting the first high level to the first signal processing unit. Under the influence of the input first high level, the first signal processing unit outputs a low level to the input terminal of the second signal processing unit. Under the influence of the input low level, the second signal processing unit outputs the first high level to the input terminal of the third signal processing unit. Under the influence of the input first high level, the third signal processing unit outputs the first high level to the first input terminal.

[0023] In some embodiments, after the first time point, both the first level shifter and the first inverter receive a low level to cause the first inverter to output a second high level, including:

[0024] After the first time point: the first level converter receives a low level, causing the third signal processing unit to output a second high level to the first input terminal. The first inverter receives a low level through the second input terminal, and under the influence of the second high level received at the first input terminal, outputs a second high level.

[0025] In some embodiments, the first level converter receiving a low level to cause the third signal processing unit to output a second high level to the first input terminal includes: the first level converter receiving a low level and outputting a low level to the first signal processing unit; the first signal processing unit outputting a first high level to the input terminal of the second signal processing unit under the influence of the input low level; the second signal processing unit outputting a low level to the input terminal of the third signal processing unit under the influence of the input first high level; and the third signal processing unit outputting a second high level to the first input terminal under the influence of the input low level.

[0026] In some embodiments, the method further includes: before a third time point, a first level converter receives a first high level, and a first inverter receives a first high level, so that the first inverter outputs a low level; the third time point is the time point at which the row gating stage switches to the sensing stage. After the third time point, the first level converter receives a first high level, and the first inverter receives a low level, so that the first inverter outputs a first high level.

[0027] Thirdly, a storage system is provided, comprising a memory device as described in the first aspect above, and a controller coupled to the memory device and configured to control the memory device.

[0028] Fourthly, a computer device is provided, the computer device including a processor and a storage system as described in the third aspect above.

[0029] The beneficial effects of the technical solution provided in this application are:

[0030] In this application, the drive circuit of the bit line sense amplifier is split into a first sub-circuit including a level shifter and a second sub-circuit including an inverter, wherein the second sub-circuit is located in the region overlapping with the memory blocks. Thus, after the second sub-circuit is separated, the remaining first sub-circuit occupies a smaller area, thereby reducing the area between memory blocks and increasing the density of memory blocks in the memory device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0034] Figure 3 This is a planar schematic diagram of a storage array provided in an embodiment of this application;

[0035] Figure 4 This application provides a schematic diagram of a planar view showing the overlap between a storage block and a peripheral circuit.

[0036] Figure 5 This is a schematic diagram of a bit line sensing amplifier provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of a driving circuit for a bit line sensing amplifier provided in an embodiment of this application;

[0038] Figure 7 This is a signal schematic diagram of a bit line sensing amplifier driving circuit provided in an embodiment of this application;

[0039] Figure 8 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application;

[0040] Figure 9This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0041] Figure 10 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0042] Figure 11 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0043] Figure 12 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0044] Figure 13 This is a flowchart of a control method provided in an embodiment of this application;

[0045] Figure 14 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0046] Figure 15 This is a signal schematic diagram of a bit line sensing amplifier driving circuit provided in an embodiment of this application;

[0047] Figure 16 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0048] Figure 17 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0049] Figure 18 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application.

[0050] Illustration

[0051] 1. Storage array; 11. Storage volume; 111. Storage block;

[0052] 2. Peripheral circuits; 21. Bit line sensing amplifier; 22. First driving circuit; 221. First sub-circuit; 222. Second sub-circuit; 2211. First level converter; 2221. First inverter; 23. Second driving circuit; 231. Third sub-circuit; 232. Fourth sub-circuit; 2311. Second level converter; 2321. Second inverter; 2212. First signal processing unit; 2222. Second signal processing unit; 2223. Third signal processing unit; 2224. Fourth signal processing unit; 2221a. First input terminal; 2221b. Second input terminal. Detailed Implementation

[0053] Figure 1 This is a schematic diagram of the structure of a memory device 100 provided in an embodiment of this application. Figure 1As shown, the memory device 100 may include peripheral circuitry 102 and a memory array 104. In one example, the peripheral circuitry 102 and the memory array 104 may be formed on different substrates and then bonded together to form the memory device 100.

[0054] Peripheral circuitry 102 may include various digital, analog, and / or mixed-signal circuits for operating the memory array 104. For example, peripheral circuitry 102 may include one or more page buffers, decoders (such as row decoders and column decoders), sense amplifiers, drivers (such as word line drivers, precharge voltage drivers, and discharge voltage drivers), I / O (input / output) circuitry, etc.

[0055] The memory array 104 includes word lines, bit lines, and multiple memory cells. In one example, the memory cell can be a DRAM memory cell, which includes a transistor and a capacitor. In the DRAM memory cell, the capacitor represents the storage of binary data "1" or "0" by storing the amount of charge, and the transistor is used to control the connection between the capacitor and the bit line, and is triggered to turn on or off by a signal from the word line.

[0056] Figure 2 This is a schematic diagram of the structure of a storage array 104 provided in an embodiment of this application. Figure 2 As shown, each memory cell 200 in the memory array 104 can be a dynamic random access memory (DRAM) memory cell, including a transistor 202 and a capacitor 204. The gate of the transistor 202 can be coupled to the word line 206, one of the source and drain of the transistor 202 can be coupled to the bit line 208, and the other can be coupled to one electrode of the capacitor 204, while the other electrode of the capacitor 204 can be grounded.

[0057] In some embodiments, since the transistor 202 always leaks a small amount of charge, the capacitor 204 will discharge slowly, resulting in poor stability of the memory cell 200. Therefore, the memory cells in the memory array 104 can be periodically refreshed by the peripheral circuit 102 to ensure the stability of the memory cells.

[0058] Figure 3 A planar schematic diagram of a storage array 104 is shown. (As shown) Figure 3 As shown, the memory device 100 may include one or more memory arrays 104. Each memory array 104 may include multiple memory banks 1041, and each memory bank 1041 may also include multiple memory blocks 1042. In one example, a memory array 104 may include eight memory banks 1041, and each memory bank 1041 may include multiple memory blocks 1042. Figure 6 As shown, storage Bank 1041 may include m (in the word line / x direction) × n (in the bit line / y direction) storage Blocks 1042.

[0059] To improve the overall operating speed of the memory device, different memory arrays 104 can independently perform operations such as reading, programming, or erasing. In some embodiments, to achieve independent operation, the memory device 100 may include multiple peripheral circuits 102, each corresponding to a memory array 104. The peripheral circuits 102 may include word line drivers, X decoders, bit line sense amplifiers, precharge voltage drivers, discharge voltage drivers, etc. In one example, the memory arrays 104 may be stacked above or below the peripheral circuits 102. The memory banks 1041 or memory blocks 1042 included in the memory arrays 104 may partially overlap with the peripheral circuits 102.

[0060] Figure 4 A planar schematic diagram showing the overlap between storage block 1042 and peripheral circuitry 102 is shown. Figure 4 As shown, the peripheral circuitry corresponding to and operating the storage Block 1042 may include a word line driver (WLD) 402 coupled to the word lines of the storage Block 1042, and a bit line sense amplifier (BLSA) 404 coupled to the bit lines of the storage Block 1042. The word line driver 402 can drive the word lines by applying operating voltages corresponding to various operations to the word lines. The word line driver 402 may include one or more string drivers, each string driver may include one or more transistors. The bit line sense amplifier 404 may be configured to detect and amplify current signals in the bit lines. Figure 4 As shown, the memory array 104 includes a memory block 1042, a word line driver 402, and a bit line sense amplifier 404, which may overlap or partially overlap in the vertical direction. Figure 4 The dashed lines in the text represent stacked storage (Block 1042). Figure 4 The diagram only shows the stacking arrangement of one storage block 1042 with its corresponding word line driver 402 and bit line sense amplifier 404. A storage bank 1041 can include multiple such... Figure 4 The memory block 1042 shown, along with its corresponding word line driver 402 and bit line sense amplifier 404, can be arranged in the x and y directions.

[0061] In one example, the peripheral circuitry also includes an X decoder (XDEC) 408, which can be arranged in a non-overlapping region of storage Block 1042. The X decoder 408 can perform operations such as row address decoding, row activation, and pre-charging. Each X decoder 408 can be used to operate on one row of storage Block 1042 in storage Bank 1041. Specifically, the X decoder 408 is located in a region that does not overlap with storage Bank 1041 and storage Block 1042; for example, it can be located in a region that overlaps with the region between two adjacent storage Banks 1041. Figure 3 The area where the Bank Row Control Circuit (BRCT) of the memory bank is located.

[0062] Figure 5 This is a schematic diagram of a bit line sensing amplifier provided in an embodiment of this application. Figure 5 As shown, the bit-line sensing amplifier includes two sensing units, which can be referred to as a first sensing unit 211 and a second sensing unit 212 in this embodiment. In one example, the first sensing unit 211 may include transistor a and transistor b, and the second sensing unit 212 may include transistor c and transistor d, wherein the source or drain of transistor a and transistor c are connected, and the source or drain of transistor b and transistor d are connected. (Continue to see...) Figure 5 The remaining unconnected source or drain of transistors a to d can be connected to the bit line (BL) and the anti-phase line (BLb) through other transistors, and then the data can be sensed by the voltage difference between the bit line and the anti-phase line.

[0063] The gates of the transistors included in the first sensing unit 211 or the second sensing unit 212 can be driven by the driving circuit of the bit line sensing amplifier. In one example, the driving circuit of the bit line sensing amplifier includes a first driving circuit 22 and a second driving circuit 23, wherein the first driving circuit 22 can be used to drive the transistors in the first sensing unit 211, and the second driving circuit 23 can be used to drive the transistors in the second sensing unit 212. Figure 6 This is a schematic diagram of a driving circuit for a bit line sensing amplifier provided in an embodiment of this application, as shown below. Figure 6 As shown, the driving circuit includes a level shifter (LVSH) and multiple signal processing units, such as a first signal processing unit 2212 directly connected to the output of the level shifter, a second signal processing unit 2222 and a third signal processing unit 2223 respectively connected to the output of the first signal processing unit 2212, and a fourth signal processing unit 2224 connected to the output of the third signal processing unit 2223.

[0064] like Figure 6As shown, the first signal processing unit 2212 includes a pair of transistors, namely a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are the input terminals of the first signal processing unit 2212 and are connected to the output terminal of the level converter. The first terminal of the PMOS transistor is connected to a high level Vsph, and the first terminal of the NMOS transistor is connected to a low level Vss. The second terminals of the PMOS transistor and the NMOS transistor are connected together, serving as the output terminal of the first signal processing unit 2212. In this embodiment, the signal output by the first signal processing unit 2212 can be referred to as Blsb_vp_ctl, and the first and second terminals can represent the source or drain of the transistor.

[0065] The structure of the second signal processing unit 2222 is similar to that of the first signal processing unit 2212, consisting of a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor serve as the input terminals of the second signal processing unit 2222 and are connected to the output terminals of the first signal processing unit 2212. The first terminal of the PMOS transistor is connected to a high level Vsph, and the first terminal of the NMOS transistor is connected to a low level Vss. The second terminals of the PMOS transistor and the NMOS transistor are connected together, serving as the output terminal of the second signal processing unit 2222.

[0066] The third signal processing unit 2223 includes two pairs of transistors, wherein: the first pair of transistors includes a PMOS transistor and an NMOS transistor, the gates of the PMOS transistor and the NMOS transistor are respectively the input terminals of the third signal processing unit 2223, the gate of the PMOS transistor is connected to the output terminal of the second signal processing unit 2222, and the gate of the NMOS transistor is connected to the output terminal of the first signal processing unit 2212 (this connection...). Figure 6 (Directly shown in the diagram). The first terminals of the PMOS and NMOS transistors are connected to VDD1i, and the second terminals of the PMOS and NMOS transistors are the output terminals of the third signal processing unit 2223. The second pair of transistors includes a PMOS and an NMOS transistor. The gates of the PMOS and NMOS transistors are also the input terminals of the third signal processing unit 2223. The gate of the PMOS transistor is connected to the output terminal of the first signal processing unit 2212, and the gate of the NMOS transistor is connected to the output terminal of the second signal processing unit 2222. The first terminals of the PMOS and NMOS transistors are connected to vsph, and the second terminals of the PMOS and NMOS transistors are the output terminals of the third signal processing unit 2223.

[0067] The fourth signal processing unit 2224 includes a pair of transistors, namely a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are the input terminals of the fourth signal processing unit 2224, which can be connected to external control signals. The first terminal of the PMOS transistor is the input terminal of the fourth signal processing unit 2224 and is connected to the output terminal of the third signal processing unit 2223. The first terminal of the NMOS transistor is connected to Vss. The second terminals of the PMOS transistor and the NMOS transistor are the output terminals of the fourth signal processing unit 2224, which can be connected to the control terminal of the first sensing unit or the second sensing unit of the bit line sense amplifier.

[0068] In some embodiments, the driving circuitry of the bit-line sense amplifier is integrated into the XDEC. Since the area occupied by the XDEC (hereinafter referred to as the XDEC area) is located between memory banks (here, "between" refers to the area overlapping with the memory banks), the larger the area of ​​the XDEC, the sparser the arrangement of the multiple banks, and the lower the storage density of the memory device. Therefore, how to reduce the area of ​​the XDEC and increase the storage density of the memory device is a problem that urgently needs to be solved.

[0069] Additionally, in the drive circuit of the bit line sense amplifier, the transistors included in the sensing unit will have gate leakage current (IDD2). Gate leakage current is a small current that leaks from the gate through the gate oxide layer to the substrate (or source / drain) when the transistor is in the off state. The gate leakage current is related to the voltage applied to the transistor gate. In one example, the higher the voltage applied to the transistor gate, the higher the gate leakage current, and thus the higher the power consumption of the memory device.

[0070] In some embodiments, in order to reduce the power consumption impact caused by gate leakage current, a relatively small high level voltage can be applied to the gate of the transistor in the sensing unit during the pre-charging phase of operations such as reading and writing the memory cell. This high level can be referred to as the second high level. The second high level is lower than the high level applied to the gate of the sensing unit during the sensing phase or lower than the high level applied to the level converter. The high level applied to the gate of the sensing unit or the high level applied to the level converter during the sensing phase can be collectively referred to as the first high level.

[0071] Figure 7 This is a signal schematic diagram of a bit-line sense amplifier's drive circuit. The drive circuit can be used to drive... Figure 5 The first driving circuit 22 of the first sensing unit 211 can also be used for driving. Figure 5 The second driving circuit 23 of the second sensing unit 212. In one example, Figure 7The Blsa_n signal shown is the control signal input to the fourth signal processing unit 2224 in the second driving circuit 23. The Blsb_n signal is the control signal input to the fourth signal processing unit 2224 in the first driving circuit 22. The Blsb_vp_trim signal is the control signal input to the level converter in the first driving circuit 22. The Blsb_vp_ctl signal is the output signal of the first signal processing unit 2212 in the first driving circuit 22, the Blsb_vp signal is the output signal of the third signal processing unit 2223, the Blsb signal is the driving signal output by the first driving circuit 22, and the Blsa signal is the driving signal output by the second driving circuit 23. Figure 7 In this context, VPP and Vsph can both represent the first high level, and vdd1i can represent the second high level.

[0072] Taking the second driving circuit as an example, during the pre-charging phase, the Blsb_vp_trim signal is low. Therefore, the level converter outputs a low level, making the Blsb_vp_ctl signal output by the first signal processing unit 2212 a first high level, and the signal output by the second signal processing unit 2222 a low level. (See also...) Figure 6The third signal processing unit 2223 includes two pairs of transistors. The first pair of transistors has a second high level input, which is lower than the first high level. The second pair of transistors has a first high level input. The low level output by the second signal processing unit 2222 acts on the gate of the PMOS transistor in the first pair of transistors and the gate of the NMOS transistor in the second pair of transistors. The high level output by the first signal processing unit 2212 acts on the gate of the NMOS transistor in the first pair of transistors and the gate of the PMOS transistor in the second pair of transistors. Thus, all transistors in the first pair of transistors are turned on, causing the first pair of transistors to output a second high level through their second terminals. All transistors in the second pair of transistors are turned off, and no signal is output. Therefore, under the influence of the output signals from the first signal processing unit 2212 and the second signal processing unit 2222, the third signal processing unit 2223 outputs a Blsb_vp signal with a second high level. In the fourth signal processing unit 2224, the first terminal of the PMOS transistor receives the Blsb_vp signal (second high level), and the gate of the PMOS transistor receives the Blsb_n signal (low level). Thus, the second terminal of the PMOS transistor in the fourth signal processing unit 2224 outputs a second high level, while the NMOS transistor in the fourth signal processing unit 2224 is turned off under the influence of the low level and does not output any signal. This allows the fourth signal processing unit 2224 to output a second high level under the influence of the Blsb_vp and Blsb_n signals. In other words, during the pre-charging phase, the second driving circuit applies a relatively lower second high level voltage to the transistor in the second sensing unit, thereby reducing the transistor gate leakage current and thus reducing the power consumption of the memory device.

[0073] The input and output signals of the first driving circuit 22 are similar to those of the second driving circuit 23, and will not be described again in this embodiment. It can be seen that the level converters of the first driving circuit 22 and the second driving circuit 23, as well as the fourth signal processing unit 2224, all require external control signals. Thus, each driving circuit needs to receive two external control signals, which increases the wiring overhead of the memory device and consequently increases its cost.

[0074] The memory device and corresponding control method provided in this application embodiment can reduce the area of ​​XDEC and increase the storage density of the memory device. On the other hand, it can reduce the gate leakage current stored in the drive circuit of the bit line sense amplifier and reduce the corresponding line overhead, thus saving the cost of the memory device.

[0075] Figure 8 This is a schematic diagram of the structure of a memory device provided in an embodiment of this application, such as... Figure 8As shown, the memory device includes a stacked memory array 1 and peripheral circuitry 2. The memory array 1 includes multiple memory banks 11, and each memory bank 11 includes multiple memory blocks 111. The memory banks 11 are the memory banks described in the above embodiments, and the memory blocks 111 are the memory blocks described in the above embodiments.

[0076] The peripheral circuit 2 includes multiple bit line sensing amplifiers 21 and a first driving circuit 22 connected to each of the multiple bit line sensing amplifiers 21. The first driving circuit 22 includes a first sub-circuit 221 and at least one second sub-circuit 222. The first sub-circuit 221 includes a first level converter 2211, and the second sub-circuit 222 includes a first inverter 2221. The second sub-circuit 222 overlaps with the memory block 111 in the stacking direction, and the first sub-circuit 221 overlaps with a first region in the memory array 1 in the stacking direction, wherein the first region is the region between the memory blocks 11.

[0077] In this embodiment, the first inverter 2221 may refer to the first signal processing unit 2212, the second signal processing unit 2222, the third signal processing unit 2223, or the fourth signal processing unit 2224 in the above embodiments. Wherein:

[0078] When the first inverter 2221 is the first signal processing unit 2212, the second sub-circuit 222 includes the first signal processing unit 2212, the second signal processing unit 2222, the third signal processing unit 2223, and the fourth signal processing unit 2224.

[0079] When the first inverter 2221 is the second signal processing unit 2222, the second sub-circuit 222 includes at least the second signal processing unit 2222, the third signal processing unit 2223 and the fourth signal processing unit 2224. In this case, the first signal processing unit 2212 can be located in the first sub-circuit 221 or in the second sub-circuit 222.

[0080] When the first inverter 2221 is the third signal processing unit 2223, the second sub-circuit 222 includes at least the third signal processing unit 2223 and the fourth signal processing unit 2224. In this case, the first signal processing unit 2212 and the second signal processing unit 2222 can be located in the first sub-circuit 221 or in the second sub-circuit 222, or the first signal processing unit 2212 can be located in the first sub-circuit 221 and the second signal processing unit 2222 can be located in the second sub-circuit 222.

[0081] When the first inverter 2221 is the fourth signal processing unit 2224, the second sub-circuit 222 includes at least the fourth signal processing unit 2224. In this case, the first signal processing unit 2212, the second signal processing unit 2222, and the third signal processing unit 2223 can be located in the first sub-circuit 221 or in the second sub-circuit 222, or the first signal processing unit 2212, the second signal processing unit 2222, and the third signal processing unit 2223 can be distributed in the first sub-circuit 221 and the second sub-circuit 222.

[0082] In one example, the first inverter 2221 is a signal processing unit that receives external data signals (such as the BLSb-n signal), namely the fourth signal processing unit 2224. The first sub-circuit 221 may include a first level converter 2211 and a first signal processing unit 2212. The second sub-circuit 222 includes a second signal processing unit 2222, a third signal processing unit 2223, and the first inverter 2221.

[0083] In other words, in this embodiment, the driving circuit of the bit line sensing amplifier 21 can be divided into two parts: a first sub-circuit 221 including a first level converter 2211, and a second sub-circuit 222 including a first inverter 2221. The first sub-circuit 221 is located in the XDEC region, while the second sub-circuit 222 is located in the region overlapping with the memory block 111. This reduces the area occupied by the XDEC region, thereby reducing the area between the memory blocks 11 and increasing the storage density of the memory device.

[0084] In one possible implementation, the first driving circuit 22 includes a plurality of second sub-circuits 222. The input terminals of the plurality of second sub-circuits 222 are respectively connected to the output terminals of the first sub-circuit 221, and the output terminal of each second sub-circuit 222 can be respectively connected to the driving terminal of a bit line sensing amplifier 21, that is, the second sub-circuit 222 and the driving terminal of the bit line sensing amplifier 21 can have a one-to-one correspondence.

[0085] Depend on Figure 4 It is known that the area of ​​the peripheral circuit 2 overlapping with the storage block 111 includes not only circuits such as the bit line sensing amplifier 21, but also a portion of free space, namely the area between BLSA 404 and WLD 402 in the x-direction. Therefore, in this embodiment, the second sub-circuit 222 is located within this free space. Figure 9This is a planar distribution diagram of a first sub-circuit 221 and a second sub-circuit 222 provided in an embodiment of this application. Since each memory block 111 overlaps with a free area in the peripheral circuit 2, in this embodiment, one second sub-circuit 222 can be matched for each memory block 111. That is, the first driving circuit can include one first sub-circuit 221 and multiple second sub-circuits 222, the number of which is the same as the number of memory blocks 111 in a row of the memory bank 11. In one example, one memory block 111 can correspond to multiple bit line sensing amplifiers 21, the number of which can be the same as the number of bit lines connected to the memory block 111. One second sub-circuit 222 can be used to drive the multiple bit line sensing amplifiers 21 corresponding to one memory block 111, specifically driving the sensing units included in the multiple bit line sensing amplifiers 21, such as the first sensing unit 211. This reduces the area occupied by the XDEC region and increases the storage density of the memory device. On the other hand, by making reasonable use of the free space in the memory device and allocating a second sub-circuit 222 to each bit line sensing amplifier 21, the driving capability of each bit line sensing amplifier 21 can be improved, thereby improving the stability of the memory device.

[0086] See also Figure 9 For the multiple bit line sense amplifiers 21 connected to the same first driving circuit 22, the memory blocks 111 connected to each of the multiple bit line sense amplifiers 21 are memory blocks 111 located in the same row in the memory bank 11. In this way, XDEC can still control the memory blocks 111 row by row without the need for software adaptation.

[0087] In one example, such as Figure 10 As shown, the first inverter 2221 refers to the fourth signal processing unit 2224. The first sub-circuit 221 includes a first level converter 2211 and a first signal processing unit 2212. The input terminal of the first signal processing unit 2212 is connected to the output terminal of the first level converter 2211. The second sub-circuit 222 includes a second signal processing unit 2222, a third signal processing unit 2223, and the first inverter 2221. The input terminal of the second signal processing unit 2222 and the first input terminal of the third signal processing unit 2222 are connected to the output terminal of the first signal processing unit 2212. The output terminal of the second signal processing unit 2222 is connected to the second input terminal of the third signal processing unit 2223. The output terminal of the third signal processing unit 2223 is connected to the input terminal of the first inverter 2221.

[0088] In this case, the first level converter 2211 only needs to drive one first signal processing unit 2212. Therefore, the driving capability requirement of the first level converter 2211 is low, so the size of the first level converter 2211 can be relatively small, thereby further reducing the area of ​​the XDEC region.

[0089] In another example, such as Figure 11 As shown, the first inverter 2221 refers to the fourth signal processing unit 2224, and the first sub-circuit 221 only includes the first level converter 2211. The second sub-circuit 222 includes the first signal processing unit 2212, the second signal processing unit 2222, the third signal processing unit 2223, and the first inverter 2221. The input terminal of the first signal processing unit 2212 is connected to the output terminal of the first level converter 2211 in the first sub-circuit 221. The input terminal of the second signal processing unit 2222 and the first input terminal of the third signal processing unit 2222 are connected to the output terminal of the first signal processing unit 2212. The output terminal of the second signal processing unit 2222 is connected to the second input terminal of the third signal processing unit 2223. The output terminal of the third signal processing unit 2223 is connected to the input terminal of the first inverter 2221.

[0090] In this configuration, since each signal processing unit is located in the area overlapping with the memory block 111, the area of ​​the XDEC region is further reduced, increasing the storage density of the memory device. Furthermore, since the first level converter 2211 only needs to drive multiple first signal processing units 2212, a first level converter 2211 with higher driving capability can be selected in this case.

[0091] The above embodiments have described the first driving circuit 22. By splitting the first driving circuit 22 into a first sub-circuit 221 and a second sub-circuit 222, with the second sub-circuit 222 located in the region overlapping with the storage block 111, the storage density of the memory device is improved. The memory device also includes a second driving circuit 23 for driving the second sensing unit 212 in the bit line sensing amplifier 21. Similarly, as... Figure 12 As shown, the second driving circuit 23 includes a third sub-circuit 231 and at least one fourth sub-circuit 232. The third sub-circuit 231 includes a second level converter 2311, and the fourth sub-circuit 232 includes a second inverter 2321. Accordingly, the second inverter 2321 can be a processing unit that receives an external control signal as input to the second driving circuit 23.

[0092] The second driving circuit 23 includes a third sub-circuit 231 and a fourth sub-circuit 232. The third sub-circuit 231 includes a second level converter 2311, and the fourth sub-circuit 232 includes a second inverter 2321. In one example, the third sub-circuit 231 is located in the XDEC region, and the fourth sub-circuit 232 is located in the region overlapping with the memory block 111. This reduces the area occupied by the XDEC region, thereby reducing the area between the memory blocks 11 and further improving the storage density of the memory device. In another example, the third sub-circuit 231 and the fourth sub-circuit 232 may not overlap with the memory block 111, i.e., both may be located in the XDEC region. That is, in this embodiment, as long as one of the second sub-circuit 222 in the first driving circuit 22 and the fourth sub-circuit 232 in the second driving circuit 23 is located in the region overlapping with the memory block 111, the area occupied by the XDEC region can be reduced, thereby increasing the storage density of the memory device.

[0093] The detailed descriptions of the third sub-circuit 231 and the fourth sub-circuit 232 are similar to those of the first sub-circuit 221 and the second sub-circuit 222. Please refer to the descriptions of the first sub-circuit 221 and the second sub-circuit 222 in the above embodiments. They will not be repeated in the embodiments of this application.

[0094] exist Figure 12 Based on this, embodiments of this application also provide a control method for a memory device, which can reduce the gate leakage current present in the bit line sense amplifier. Figure 13 This is a flowchart of a control method provided in an embodiment of this application, such as... Figure 13 As shown, the control method includes:

[0095] Step 1301: Before the first time point, the first level converter 2211 receives the first high level and the first inverter 2221 receives the low level, so that the first inverter 2221 outputs the first high level. The first time point is the time point when the sensing stage switches to the pre-charging stage.

[0096] Step 1302: After the first time point, both the first level converter 2211 and the first inverter 2221 receive a low level, so that the first inverter 2221 outputs a second high level, wherein the first high level is higher than the second high level.

[0097] The control methods shown in steps 1301 and 1302 can be used in... Figure 6 Based on the driving circuit shown, or in Figure 14 This is an application based on the driving circuit shown. For the corresponding signal processing procedure, please refer to... Figure 7 The signal diagram shown, or see [link / reference] Figure 15The signal diagram is shown. The control methods shown in steps 1301 and 1302 are applied in... Figure 6 or Figure 14 When the driving circuit shown is in operation, in steps 1301 and 1302, the first level converter 2211 refers to... Figure 6 or Figure 14 The LVSH shown, the first inverter 2221 refers to Figure 6 or Figure 14 The fourth signal processing unit 2224 shown.

[0098] like Figure 7 As shown, the process of reading and writing data in the memory cells of a memory device can be divided into three stages: a row selection stage, a sensing stage, and a pre-charging stage. These three stages can alternate sequentially. In this embodiment, the first time point refers to the time point at which the sensing stage switches to the pre-charging stage. That is, during the sensing stage, the input terminal of the first level converter 2211 receives a first high level, such as... Figure 7 The Blsb_vp_trim signal. The first inverter 2221 receives a low level, such as... Figure 7 The first driving circuit 22 applies a first high level to the first sensing unit 211 included in the bit line sensing amplifier 21 by transmitting the Blsb_n signal. During the pre-charge phase, the input of the first level converter 2211 receives a low level, and the first inverter 2221 also receives a low level, so that the first driving circuit 22 applies a second high level to the first sensing unit 211 included in the bit line sensing amplifier 21. In this way, the high level applied to the first sensing unit 211 during the pre-charge phase is relatively low, which can reduce the leakage current of the transistor in the first sensing unit 211 and reduce the power consumption of the memory device.

[0099] In one feasible implementation, embodiments of this application provide a novel control method for the first driving circuit 22. For example... Figure 12 As shown, the control terminal of the first level converter 2211 included in the first driving circuit 22 is connected to the control terminal of the second inverter 2321 included in the second driving circuit 23.

[0100] The control terminals of the first level converter 2211 and the second inverter 2321 are respectively ports for receiving external control signals. For example, in Figure 7 In this circuit, the control terminal of the first level converter 2211 is connected to the port of Blsb_vp_trim. The control terminal of the second inverter 2321 is connected to the Blsa_n signal. Relative to... Figure 7The difference lies in this embodiment: the control terminal of the first level converter 2211 is connected to the control terminal of the second inverter 2321. That is, the input signal to the control terminal of the first level converter 2211 is the same as the input signal to the control terminal of the second inverter 2321, both being Blsa_n signals. Thus, compared to... Figure 7 Similarly, during the sensing phase before the first time point, the input of the level converter 2211 receives a first high level and the first inverter 2221 receives a low level. During the sensing phase after the first time point, the input of the level converter 2211 receives a first high level and the first inverter 2221 receives a low level, thereby reducing the power consumption of the memory device during the pre-charge phase.

[0101] As can be seen, in this embodiment, the first level converter 2211 in the first driving circuit 22 and the second inverter 2321 in the second driving circuit 23 can be controlled by a single control signal, such as the Blsa_n signal. Thus, the first driving circuit 22 and the second driving circuit 23 only require three control signals to reduce the power consumption of the memory device while ensuring normal driving of the sensing unit. This reduces the line overhead of the control signals, saving costs for the memory device.

[0102] Figure 14 This is a schematic diagram of a first driving circuit provided in an embodiment of this application, and... Figure 6 The difference is, Figure 14 In the driving circuit, the first level converter 2211 and the first signal processing unit 2212 are located in the XDEC region, and the second signal processing unit 2222 to the fourth signal processing unit 2224 are located in the region overlapping with the storage block. The input of the first level converter 2211 is the control signal of the second inverter 2321 in the second driving circuit 23, namely Blsa_n.

[0103] Figure 15 This is a schematic diagram of a control signal provided in an embodiment of this application. The following is in conjunction with... Figures 12 to 15 The control method provided in the embodiments of this application will be further described as follows:

[0104] This application embodiment involves a first time point, a second time point, and a third time point. The first time point is the time point at which the sensing phase switches to the pre-charging phase; the second time point is the time point within the row gating phase; and the third time point is the time point at which the row gating phase switches back to the sensing phase. The specific location of the second time point within the row gating phase can be preset by a technician; this application embodiment will not provide an example. The following explanation uses the second time point, third time point, and first time point in sequence as an example to illustrate the solution:

[0105] Before the second time point, the first level converter 2211 receives a low level, causing the second signal processing unit 2222 to output a first high level and the third signal processing unit 2223 to output a second high level. After the second time point, the first level converter receives the first high level, causing the second signal processing unit 2222 to output a low level and the third signal processing unit 2223 to output a first high level. Figure 16 As shown, the output of the third signal processing unit 2223 can be connected to the first input terminal 2221a of the first inverter 2221, and the second input terminal 2221b of the first inverter 2221 can be connected to an external control signal, such as the Blsb_n signal.

[0106] like Figure 14 and Figure 15 As shown, during the row selection phase, and before the second time point, the input (Blsa_n signal) of the first level converter 2211 is low, and its output is also low. At this time, the input of the first signal processing unit 2212 is low, and the output (Blsa_vp_ctl signal) of the first signal processing unit 2212 is a first high level, while the output of the second signal processing unit 2222 is low. Thus, under the influence of the outputs of the first and second signal processing units 2222 respectively, the transistors connected to the second high level (Vdd1i) in the third signal processing unit 2223 will conduct, thereby making the output signal (Blsa_vp signal) of the third signal processing unit 2223 Vdd1i. However, since the input (Blsb_n signal) of the first inverter 2221 is high, it blocks the conduction of Vdd1i inside the first inverter 2221, so the final output signal (Blsb signal) of the first inverter 2221 is low (Vss).

[0107] During the row selection phase, and after the second time point, the input (Blsa_n signal) of the first level converter 2211 changes from low to high, and the output is also high. At this time, the input of the first signal processing unit 2212 is high, the output (Blsa_vp_ctl signal) of the first signal processing unit 2222 is low, and the output of the second signal processing unit 2222 is high. Thus, under the influence of the outputs of the first and second signal processing units 2222, the transistors connected to the low level (Vsph) in the four transistors of the third signal processing unit 2223 will conduct, thereby making the output signal (Blsa_vp signal) of the third signal processing unit 2223 Vsph. Since the input (Blsb_n signal) of the first inverter 2221 is still high, it still blocks the conduction of Vsph inside the first inverter 2221, so the final output signal (Blsb signal) of the first inverter 2221 is still low.

[0108] Before the third time point, the first level converter 2211 receives a first high level, and the first inverter 2221 receives a first high level, so that the first inverter 2221 outputs a low level. The third time point is the time point when the row selection stage switches to the sensing stage. After the third time point, the first level converter 2211 receives a first high level, and the first inverter 2221 receives a low level, so that the first inverter 2221 outputs a first high level.

[0109] like Figure 14 and Figure 15 As shown, before the third time point, which is after the second time point, the situation before the third time point will not be described again. After the third time point, that is, during the sensing phase, the input (Blsa_n signal) of the first level converter 2211 remains unchanged and is still at a high level. Therefore, the output signal (Blsa_vp signal) of the third signal processing unit 2223 is still Vsph. However, since the input (Blsb_n signal) of the first inverter 2221 is at a low level, the Vsph output by the third signal processing unit 2223 will be turned on inside the first inverter 2221. Therefore, during the sensing phase, the signal (Blsb signal) output by the first inverter 2221 is Vsph.

[0110] Before the first time point, the first level converter 2211 receives a first high level, causing the third signal processing unit 2223 to output a first high level to the first input terminal 2221a. The first inverter 2221 receives a low level through the second input terminal 2221b and outputs a first high level under the influence of the first high level received at the first input terminal 2221a. After the first time point, the first level converter 2211 receives a low level, causing the third signal processing unit 2223 to output a second high level to the first input terminal 2221a. The first inverter 2221 receives a low level through the second input terminal 2221b and outputs a second high level under the influence of the second high level received at the first input terminal 2221a.

[0111] Before the first time point, which is after the third time point, the situation before the third time point will not be described further. After the first time point, that is, during the pre-charge phase, the input (Blsa_n signal) of the first level converter 2211 is low. Therefore, the output signal (Blsa_vp signal) of the third signal processing unit 2223 is vdd1i. However, since the input (Blsb_n signal) of the first inverter 2221 remains unchanged, the vdd1i output by the third signal processing unit 2223 is turned on inside the first inverter 2221. Therefore, during the pre-charge phase, the signal (Blsb signal) output by the first inverter 2221 is vdd1i.

[0112] From the above Figures 12 to 16 According to the relevant embodiments in this application, after the control signal of the second directional device of the second driving circuit is connected to the first level converter of the first driving circuit, the new path overhead of the memory device is reduced on the one hand, and the gate leakage current in the bit line sensing amplifier is reduced during the pre-charging stage, thereby reducing the power consumption of the bit line sensing amplifier.

[0113] Figure 17 This is a schematic diagram of a storage system structure provided in an embodiment of this application. The storage system 1700 includes the memory device 1701 as described in the above embodiment, for example... Figure 8 The memory device shown also includes a controller 1702 configured to control the memory device, for example, the controller is configured to write or read data from the memory device.

[0114] Figure 18 This is a schematic diagram of a computer device structure provided in an embodiment of this application. The computer device 1800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 18 As shown, computer device 1800 may include processor 1801. In one example, processor 1801 may be a central processing unit (CPU) or a system-on-a-chip (SoC), and processor 1801 is configured to send data to or receive data from storage system 1802.

[0115] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0116] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory device, characterized in that, The memory device includes a stacked memory array and peripheral circuitry; The storage array includes multiple storage units, and each storage unit includes multiple storage blocks; The peripheral circuit includes a plurality of bit line sense amplifiers and a first driving circuit connected to the plurality of bit line sense amplifiers. The first driving circuit includes a first sub-circuit and at least one second sub-circuit. The first sub-circuit includes a first level converter, and the second sub-circuit includes a first inverter. The second sub-circuit overlaps with the memory block in the stacking direction.

2. The memory device according to claim 1, characterized in that, The first sub-circuit overlaps with a first region in the memory array in the stacking direction, the first region being the area between the memory cells.

3. The memory device according to claim 1, characterized in that, The first driving circuit includes multiple second sub-circuits; The input terminals of the plurality of second sub-circuits are respectively connected to the output terminals of the first sub-circuit, and the output terminal of each second sub-circuit is connected to the driving terminal of a bit line sensing amplifier.

4. The memory device according to claim 3, characterized in that, For multiple bit line sense amplifiers connected to the same first driving circuit, the memory blocks connected to the multiple bit line sense amplifiers are memory blocks located in the same row in the memory bank.

5. The memory device according to claim 1, characterized in that, The peripheral circuit also includes a second driving circuit connected to the plurality of bit line sensing amplifiers. The bit line sensing amplifier includes a first sensing unit and a second sensing unit. The first driving circuit is used to drive the first sensing unit, and the second driving circuit is used to drive the second sensing unit. The second driving circuit includes a third sub-circuit and at least one fourth sub-circuit. The third sub-circuit includes the second level converter, and the fourth sub-circuit includes the second inverter. The control terminal of the first level converter included in the first driving circuit is connected to the control terminal of the second inverter included in the second driving circuit.

6. The memory device according to claim 5, characterized in that, For the first driving circuit: Before the first time point, the first level converter receives a first high level and the first inverter receives a low level, so that the first inverter outputs the first high level. The first time point is the time point at which the sensing phase switches to the pre-charging phase. After the first time point, both the first level converter and the first inverter receive a low level, so that the first inverter outputs a second high level, wherein the first high level is higher than the second high level.

7. The memory device according to any one of claims 1 to 6, characterized in that, The first sub-circuit further includes a first signal processing unit, the input terminal of which is connected to the output terminal of a first level converter, and the first signal processing unit includes a pair of transistors connected in parallel. The second sub-circuit further includes a second signal processing unit and a third signal processing unit. The input terminal of the second signal processing unit and the first input terminal of the third signal processing unit are connected to the output terminal of the first signal processing unit. The output terminal of the second signal processing unit is connected to the second input terminal of the third signal processing unit. The output terminal of the third signal processing unit is connected to the input terminal of the first inverter. The second signal processing unit includes a pair of transistors connected in parallel, and the third signal processing unit includes two pairs of transistors connected in parallel.

8. The memory device according to any one of claims 1 to 6, characterized in that, The second sub-circuit further includes a first signal processing unit, a second signal processing unit, and a third signal processing unit; The input terminal of the first signal processing unit is connected to the output terminal of the first level converter in the first sub-circuit. The input terminal of the second signal processing unit and the first input terminal of the third signal processing unit are connected to the output terminal of the first signal processing unit. The output terminal of the second signal processing unit is connected to the second input terminal of the third signal processing unit. The output terminal of the third signal processing unit is connected to the input terminal of the first inverter. The first signal processing unit includes a pair of transistors connected in parallel. The second signal processing unit includes a pair of transistors connected in parallel. The third signal processing unit includes two pairs of transistors connected in parallel.

9. The memory device according to any one of claims 1 to 6, characterized in that, The memory device is a dynamic random access memory (DRAM).

10. A method for controlling a memory device, characterized in that, The memory device includes a memory array and peripheral circuitry. The memory array includes multiple memory cells, and each memory cell includes multiple memory blocks. The peripheral circuitry includes multiple bit line sense amplifiers and a first driving circuit connected to the multiple bit line sense amplifiers. The first driving circuitry includes a first sub-circuit and at least one second sub-circuit. The first sub-circuit includes a first level shifter, and the second sub-circuit includes a first inverter. The method includes: Before the first time point, the first level converter receives a first high level and the first inverter receives a low level, so that the first inverter outputs the first high level. The first time point is the time point at which the sensing phase switches to the pre-charging phase. After the first time point, both the first level converter and the first inverter receive a low level, so that the first inverter outputs a second high level, wherein the first high level is higher than the second high level.

11. The method according to claim 10, characterized in that, The first sub-circuit further includes a first signal processing unit, the input terminal of which is connected to the output terminal of a first level converter, and the first signal processing unit includes a pair of transistors connected in parallel. The second sub-circuit further includes a second signal processing unit and a third signal processing unit. The input terminal of the second signal processing unit and the first input terminal of the third signal processing unit are connected to the output terminal of the first signal processing unit. The output terminal of the second signal processing unit is connected to the second input terminal of the third signal processing unit. The output terminal of the third signal processing unit is connected to the input terminal of the first inverter. The second signal processing unit includes a pair of transistors connected in parallel, and the third signal processing unit includes two pairs of transistors connected in parallel.

12. The method according to claim 11, characterized in that, The method further includes: Before the second time point, the first level converter receives a low level to cause the second signal processing unit to output the first high level, and the third signal processing unit outputs the second high level, wherein the second time point is within the row gating stage; After the second time point, the first level converter receives the first high level, causing the second signal processing unit to output a low level, and the third signal processing unit to output the first high level.

13. The method according to claim 11, characterized in that, The first inverter includes a first input terminal and a second input terminal, wherein the first input terminal is connected to the output terminal of the third signal processing unit.

14. The method according to claim 13, characterized in that, Before the first time point, the first level converter receives a first high level, and the first inverter receives a low level, so that the first inverter outputs the first high level, including: Before the first time point: The first level converter receives the first high level so that the third signal processing unit outputs the first high level to the first input terminal; The first inverter receives a low level through the second input terminal and outputs the first high level when it receives the first high level at the first input terminal.

15. The method according to claim 14, characterized in that, The first level converter receives the first high level to cause the third signal processing unit to output the first high level to the first input terminal, including: The first level converter receives the first high level and outputs the first high level to the first signal processing unit; Under the influence of the first high-level input, the first signal processing unit outputs a low-level input to the input terminal of the second signal processing unit; When the input is low, the second signal processing unit outputs the first high level to the input terminal of the third signal processing unit; The third signal processing unit outputs the first high level to the first input terminal under the action of the first high level input.

16. The method according to claim 13, characterized in that, After the first time point, both the first level converter and the first inverter receive a low level, so that the first inverter outputs a second high level, including: After the first time point: The first level converter receives a low level, so that the third signal processing unit outputs the second high level to the first input terminal; The first inverter receives a low level through the second input terminal and outputs the second high level when it receives the second high level through the first input terminal.

17. The method according to claim 15, characterized in that, The first level converter receives a low level to cause the third signal processing unit to output the second high level to the first input terminal, including: The first level converter receives a low level and outputs a low level to the first signal processing unit; When the input low level is applied, the first signal processing unit outputs the first high level to the input terminal of the second signal processing unit; Under the influence of the first high-level input, the second signal processing unit outputs a low-level input to the input terminal of the third signal processing unit; The third signal processing unit outputs the second high level to the first input terminal under the action of the input low level.

18. The method according to any one of claims 10 to 17, characterized in that, The method further includes: Before the third time point, the first level converter receives the first high level, and the first inverter receives the first high level, so that the first inverter outputs a low level. The third time point is the time point at which the row gating stage switches to the sensing stage. After the third time point, the first level converter receives the first high level, and the first inverter receives the low level, so that the first inverter outputs the first high level.

19. A storage system, characterized in that, The storage system includes a memory device as described in any one of claims 1 to 9, and a controller coupled to the memory device and configured to control the memory device.

20. A computer device, characterized in that, The computer device includes a processor and a storage system as described in claim 19.

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