Bitline precharge-free high-speed low-power pseudo dual-port sram circuit and operating method

Abstract

The application discloses a kind of free bit line pre-charging high-speed low-power pseudo dual-port SRAM circuit and operating method, wherein the circuit includes: read-write column selection signal generation module, for receiving read address signal, write address signal and read clock and write clock, and generate read column selection signal and write column selection signal;Bit line pre-charging signal generation module is connected with the read-write column selection signal generation module, for generating bit line pre-charging control signal according to the read column selection signal and the write column selection signal;And bit line generation module is connected with the read-write column selection signal generation module and the bit line pre-charging signal generation module, for according to the read column selection signal and the write column selection signal, the bit line pair of corresponding column is gated, and according to the bit line pre-charging control signal, whether to pre-charge the bit line pair is controlled.The application can effectively shorten read-write period, and frequency is faster, and can reduce once full swing enable and pre-charging, greatly reduce dynamic power consumption.

Description

Technical Field

[0001] This invention relates to the field of SRAM circuit technology, and in particular to a bit-line-free precharged high-speed, low-power pseudo-dual-port SRAM circuit and its operation method. Background Technology

[0002] With the rapid development of SRAM technology and semiconductor manufacturing, pseudo-dual-port SRAM is gradually gaining popularity among existing SRAM technologies. Pseudo-dual-port SRAM is favored by users due to its ability to simultaneously read and write and its higher density compared to dual-port SRAM. Pseudo-dual-port SRAM performs read and write operations on traditional 6TB memory cells, resulting in a smaller area compared to the 8TB memory cells of dual-port SRAM. Furthermore, pseudo-dual-port SRAM has the same two address compilation systems as dual-port SRAM, but only one clock. For users, the reduced clock frequency provides significant convenience for chip design, but for pseudo-dual-port SRAM designers, it increases the difficulty of timing processing.

[0003] Current technology requires pre-charging the bit lines of a memory cell to a high potential before performing a read operation, then re-charging the bit lines to a high potential before performing a write operation. This process has the following drawbacks: (1) After reading, the bit line is precharged before writing, and the bit line waveform between reading and writing is required to be clearly distinguishable, that is, the bit line is precharged to the top. This will lead to a decrease in the operating frequency and will not have a competitive advantage in high-speed scenarios.

[0004] (2) When the sensitive amplifier is connected to multiple column memory cells at the same time, reading one column bit line will cause the potential of other bit lines to gradually decrease due to the opening of word lines, resulting in more dynamic power consumption. If the bit line negative voltage write assist is enabled in the circuit, the lower bit line negative voltage will cause the transistors of other column select signals to turn on, thereby causing erroneous write operations.

[0005] (3) The timing between the column select address and the precharge signal is difficult to control. Due to the inconsistency between the drive and parasitic resistance and capacitance of the column select address and the precharge signal, there is a risk of competition between the column select address and the precharge signal.

[0006] Therefore, existing pseudo-dual-port SRAMs need to be improved to meet the practical needs of increasing operating frequency and reducing dynamic power consumption. Summary of the Invention

[0007] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a bit-line-free precharged high-speed low-power pseudo dual-port SRAM circuit and operation method, which has the advantages of increasing the operating frequency and reducing dynamic power consumption.

[0008] The objective of this invention is achieved through the following technical solution: According to a first aspect of the present disclosure, a bit-line-free precharged high-speed, low-power pseudo-dual-port SRAM circuit is provided, comprising: The read / write column select signal generation module includes multiple inverters and NAND gates, used to receive read address signals, write address signals, read clock and write clock, and generate read column select signals and write column select signals; A bit line precharge signal generation module, including multiple inverters and NAND gates, is connected to the read / write column select signal generation module and is used to generate a bit line precharge control signal based on the read column select signal and the write column select signal; and The bit line generation module includes multiple inverters, transmission gates and PMOS transistors, and is connected to the read / write column select signal generation module and the bit line precharge signal generation module. It is used to select the bit line pairs of the corresponding columns according to the read column select signal and the write column select signal, and to control whether to precharge the bit line pairs according to the bit line precharge control signal. In a read / write cycle, when read and write operations target the same column of memory cells, the bit line precharge control signal becomes invalid after the read operation begins to stop precharging, and becomes valid again after the write operation ends. No valid pulse for precharging is generated between the read and write operations, so that the bit line pair can directly enter the write operation based on the voltage difference established by the read operation.

[0009] In some exemplary embodiments, when read and write operations target different column memory cell bit lines, the bit line precharge signal generation module maintains the bit line pairs of the column memory cells that did not participate in the read operation in a precharge state after the read operation is completed, and stops precharging the bit line pairs of the column memory cells that participated in the write operation when the write operation begins.

[0010] In some exemplary embodiments, the bit line precharge control signal is a single pulse signal that becomes invalid at the start of a read operation to stop precharge and becomes valid after a write operation to resume precharge; when read and write operations are performed on the same column, the pulse signal remains invalid between the read and write operations and does not undergo level switching.

[0011] In some exemplary embodiments, the bit line generation module includes: Multiple bit line pairs, each bit line pair corresponds to a column of memory cells, and each bit line pair includes the first bit line and the second bit line; Multiple transmission gates, each controlled by the read column select signal and the write column select signal, are used to connect the bit line pairs to a sensitive amplifier during a read operation and to connect the bit line pairs to a write drive circuit during a write operation; and, Multiple PMOS precharge transistors, controlled by the bit line precharge control signal, are used to charge the bit line pair to a high level when precharge is active.

[0012] In some exemplary embodiments, when read and write operations target the same column of memory cells, the first bit line is pulled down to a first voltage by the memory cell during a read operation, and is directly pulled up to a high level or pulled down to a low level by the write driver circuit according to the data being written during a write operation.

[0013] In some exemplary embodiments, the read / write column select signal generation module includes 12 inverters and 8 NAND gates for decoding the read address and write address, and generating the read column select signal and the write column select signal under the control of the read clock and write clock.

[0014] In some exemplary embodiments, the bit line precharge signal generation module includes four inverters and four NAND gates for generating the bit line precharge control signal based on the combination of the read column select signal and the write column select signal.

[0015] In some exemplary embodiments, the circuit further includes a sensitive amplifier for amplifying the voltage difference generated between bit line pairs during a read operation.

[0016] In some exemplary embodiments, during a write operation, the write drive circuit provides a negative voltage to the target bit line; the bit line precharge control signal of the bit line pair of the non-target column memory cell remains active during the write operation to keep the non-target bit line pair in a high-level precharge state.

[0017] According to a second aspect of the present disclosure, a method for operating a bit-line-free precharged high-speed, low-power pseudo-dual-port SRAM is provided, the method being implemented based on the circuit described in the first aspect, comprising: Within a read / write cycle, a read operation is performed first, selecting the bit line pair of the target column memory cell, stopping its pre-charge, and establishing a read voltage difference on the bit line pair; After the read operation is completed, the write operation begins immediately. If the target column of the write operation is the same as the target column of the read operation, the bit pair of that column is not pre-padded between the read and write operations, and the write operation is performed directly on that bit pair. After the write operation is completed, all bit pairs are pre-charged in preparation for the next read / write cycle.

[0018] In summary, compared with the prior art, the present invention has the following beneficial effects: This invention provides a high-speed, low-power pseudo-dual-port SRAM circuit and operation method without bit-line precharge. The circuit includes: a read / write column select signal generation module, comprising multiple inverters and NAND gates, for receiving read address signals, write address signals, read clocks, and write clocks, and generating read and write column select signals; a bit-line precharge signal generation module, comprising multiple inverters and NAND gates, connected to the read / write column select signal generation module, for generating a bit-line precharge control signal based on the read and write column select signals; and a bit-line generation module, comprising multiple inverters, transmission gates, and PMOS transistors, connected to the read / write column select signal generation module and the bit-line precharge signal generation module, for selecting bit-line pairs in corresponding columns based on the read and write column select signals, and controlling whether to precharge the bit-line pairs based on the bit-line precharge control signal. This invention stops pre-charging the selected address during read / write operations while maintaining pre-charging for unselected addresses. Furthermore, when the read and write column selection addresses are the same, pre-charging of the bit lines is unnecessary; the write driver circuit directly drives the bit lines for write operations, resulting in shorter read / write cycles and higher frequencies. When reading and writing the same column selection address within a cycle, the bit line pre-charging signal remains disabled, reducing one full-swing enable and pre-charging operation and significantly lowering dynamic power consumption. When a read bit line is pulled down to a low potential by a memory cell, it does not need to be re-pre-charged to a high potential before being pulled down again by the write driver, further reducing dynamic power consumption caused by read bit line swing pre-charging and pull-down. When writing to a column bit line, if other bit lines stop pre-charging, they will be in a floating state. If the write negative voltage is low, the column selection NMOS will be turned on, potentially writing to adjacent memory cells incorrectly. However, since the unselected bit lines are in a pre-charging state, the NMOS conduction will not cause incorrect writing. Attached Figure Description

[0019] Figure 1 This is a circuit schematic diagram of a bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit in an embodiment of the present invention.

[0020] Figure 2 The circuit simulation waveforms are shown in the embodiment of the present invention when the read and write bit line addresses are different in the high-speed, low-power pseudo-dual-port SRAM circuit without bit line pre-charge.

[0021] Figure 3 This is a circuit simulation waveform diagram of the high-speed, low-power pseudo-dual-port SRAM circuit without bit-line pre-charge in an embodiment of the present invention, when the read and write bit-line addresses are the same.

[0022] The numbers and letters in the diagram represent the names of the corresponding components: 10. Read / Write Column Select Signal Generation Module; 20. Bit Line Precharge Signal Generation Module; 30. Bit Line Generation Module. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] like Figures 1 to 3 As shown, the first aspect of this invention provides a high-speed, low-power pseudo-dual-port SRAM circuit without bit-line precharge, comprising: a read / write column select signal generation module 10, including multiple inverters and NAND gates, for receiving read address signals, write address signals, read clocks, and write clocks, and generating read column select signals and write column select signals; a bit-line precharge signal generation module 20, including multiple inverters and NAND gates, connected to the read / write column select signal generation module 10, for generating bit-line precharge control signals based on the read column select signals and write column select signals; and a bit-line generation module 30, including multiple inverters, transmission gates, and PMOS transistors, connected to the read / write column select signal generation module 10 and the bit-line precharge signal generation module 20, for selecting bit-line pairs of corresponding columns based on the read column select signals and write column select signals, and controlling whether to precharge the bit-line pairs based on the bit-line precharge control signals.

[0025] Reference Figure 1 The specific signals are: read address signal RYP[3:0], write address signal WYP[3:0], read clock READ_CLK, write clock WRITE_CLK, read column select signal YSR[3:0], write column select signal YSW[3:0], bit line precharge control signal BLPR[3:0], and bit line pair BL / BLB.

[0026] In a single read / write cycle, when read and write operations target the same column of memory cells' bit lines, the bit line precharge control signal becomes invalid after the read operation begins to stop precharging, and becomes valid again after the write operation ends. No valid pulse for precharging is generated between read and write operations, so that the bit line pair can directly enter the write operation based on the voltage difference established by the read operation. This eliminates the bit line precharge time between read and write, increases the operating frequency, and reduces the dynamic power consumption caused by full-swing precharging and subsequent pull-down of the bit lines.

[0027] When read and write operations target different column memory cell bit lines, the bit line precharge signal generation module 20 maintains the bit line pairs of the column memory cells that did not participate in the read operation in a precharge state after the read operation is completed, and stops precharging the bit line pairs of the column memory cells that participate in the write operation when the write operation begins.

[0028] In this embodiment, the bit line precharge control signal is a single pulse signal. This pulse signal becomes invalid at the start of a read operation to stop precharge and becomes valid after a write operation to restore precharge. When read and write operations target the same column, the pulse signal remains invalid between the read and write operations and does not undergo level flipping, thereby reducing the dynamic power consumption caused by the charging and discharging of the large load capacitor of the bit line precharge signal.

[0029] Specifically, the bit line generation module 30 includes: multiple bit line pairs, each bit line pair corresponding to a column of memory cells, each bit line pair including a first bit line BL and a second bit line BLB; multiple transmission gates, controlled by read column select signals and write column select signals respectively, used to connect the bit line pairs to a sensitive amplifier during read operations and to connect the bit line pairs to a write drive circuit during write operations; and multiple PMOS precharge transistors, controlled by bit line precharge control signals, used to charge the bit line pairs to a high level when precharge is active.

[0030] In the case of read and write operations targeting the same column of memory cells, the first bit line is pulled down to the first voltage by the memory cell during the read operation, and is directly pulled up to the high level or pulled down to the low level by the write driver circuit according to the data to be written during the write operation. There is no need to precharge to the high level before the write operation, thereby reducing the bit line voltage swing and the corresponding dynamic power consumption.

[0031] In a specific example, the read / write column select signal generation module 10 includes 12 inverters and 8 NAND gates, used to decode the read address and write address, and generate read column select signals and write column select signals under the control of the read clock and write clock; the bit line precharge signal generation module 20 includes 4 inverters and 4 NAND gates, used to generate bit line precharge control signals based on the combination of read column select signals and write column select signals.

[0032] Furthermore, the circuit also includes a sensitive amplifier to amplify the voltage difference generated between bit line pairs during the read operation, thereby shortening the read time, accelerating the read cycle, and making the speed-up effect more obvious.

[0033] In this embodiment, the circuit employs negative voltage write-assisted technology. During the write operation, the write drive circuit provides a negative voltage to the target bit line. The bit line precharge control signal of the bit line pair of the non-target column memory cell remains valid during the write operation, so that the non-target bit line pair is kept in a high-level precharge state. Even if the negative voltage causes the column select transmission gate to conduct, the non-target memory cell cannot be mistakenly written, thereby ensuring the reliability of the write operation.

[0034] The following is combined with Figure 2 and Figure 3 Provide a detailed explanation. Figure 2 The circuit simulation waveforms are shown when the bit line addresses are different for reading and writing. Figure 3The circuit simulation waveform diagram is shown when the read and write bit line addresses are the same.

[0035] like Figure 2 As shown, the pseudo-dual-port SRAM first performs a read operation. At this time, READ_CLK generates a valid pulse. Assuming the read address RYP[0] is valid, LC_YSRB[0] and LC_BLPR[0] generate valid pulses simultaneously. BL[0] and BLB[0] are stopped from pre-charging. At this time, it can be observed that 6TCell pulls down BL, and a read voltage difference of about 360mV is generated between it and BLB. This voltage difference will be sent to the sensitive amplifier for small signal amplification. Meanwhile, the other three columns of memory cell bit lines LC_BLPR[3:1] are in the pre-charge valid state, and BL[3:1] and BLB[3:1] are in the high-level pre-charge state.

[0036] After the read operation is completed, WRITE_CLK generates a valid pulse, WL starts up again, and if the write address WYP[3] is valid, then LC_YSW[3] and LC_BLPR[3] generate valid pulses at the same time. BL[3] and BLB[3] are stopped from precharging and are provided with write voltage by WBL and WBLB respectively. At this time, it can be observed that the BLB of 6TCell is pulled down to 0 due to the influence of WBLB, and the internal value nv0 / nv1 of the memory cell undergoes write flipping. Before this, the 6TCell read receives the precharge signals of BL and BLB and performs precharging. If WBL or WBLB is negative during the write cycle, although LC_YSW[2:0] is ground potential, the low negative voltage will also cause NMOS to conduct, which is very easy to cause write interference to the memory cell corresponding to LC_YSW[2:0]. However, since the bit line precharging of these addresses is turned on during the write period, the negative voltage interference of BL / BLB is resolved.

[0037] like Figure 3 As shown, LC_YSRB[3] and LC_BLPR[3] are effective during the read cycle. The BL / BLB of the 6TCELL is pulled down to create a voltage difference. When BL drops to around 500mV, the read cycle ends and no precharge is performed. Instead, it is pulled up to a high level or pulled down to a low level by WBL during the write cycle. From the waveform diagram, it can be seen that LC_YSRB[3] and LC_YSW[3] are effective one after another. However, LC_BLPR[3] does not generate two-phase non-overlapping waveforms. Instead, it is replaced by a single pulse. Because BL and BLB must be in a fully precharged state before the next read cycle, the pulse width of LC_BLPR will affect the operating frequency. This technique of removing the precharge of two-phase non-overlapping bit lines saves the precharge time between read and write, thereby increasing the operating frequency.

[0038] In addition, as the number of storage bits increases, LC_BLPR will carry a large capacitor. This technology also greatly reduces the dynamic power consumption caused by precharging between reading and writing LC_BLPR. If the storage cell is pulled down to a low level by WBL after BL is pulled down by the read current, the dynamic power consumption caused by bit line precharging is also reduced by one time. The more bits there are, the more obvious the reduction in dynamic power consumption will be.

[0039] refer to Figure 1 The circuit schematic is shown below. In this embodiment, the read / write column select signal generation module 10 consists of 12 inverters and 8 NAND gates, the bit line precharge signal generation module 20 consists of 4 inverters and 4 NAND gates, the bit line generation module 30 consists of 12 inverters, 8 transmission gates and 20 PMOS, and also includes 4 standard 6T memory cell modules.

[0040] Based on this circuit, the following operations are performed: 1) The input signals READ_CLK and WRITE_CLK of the read / write column select signal generation module 10 are alternately given positive pulse signals to simulate the internal clock signal generation of the pseudo dual-port SRAM.

[0041] 2) RYP[3:0] and WYP[3:0] each have one high level signal and the rest are low level, providing column select address for pseudo dual-port SRAM. At this time, it can be observed that YSR[3:0] / YSW[3:0] and BLPR[3:0] of bit line precharge signal generation module 20 both have pulses generated for the corresponding column select address bits.

[0042] 3) Provide a high level with an initial value of VDD to RBL / RBLB to simulate the operation of pre-charging RBL / RBLB to high before the pseudo-dual-port SRAM read operation.

[0043] 4) Provide a WL with the same phase as READ_CLK. At this time, it can be observed that the BL / BLB selected by the read column select signal begins to be pulled down by the memory cell pull-down transistor.

[0044] 5) Provide a WL with the same phase as WRITE_CLK, and provide a write 0 / write 1 signal to WBL / WBLB respectively. At this time, it can be observed that the BL / BLB selected by the write column select signal generates a low level and a high level respectively, and finally writes the stored value into the memory cell.

[0045] 6) When the provided column select read address and write address are the same, the corresponding LC_BLPR receives the read precharge enable and write precharge enable closely and is affected by RC delay, ultimately forming a signal waveform with only one pulse width.

[0046] The read / write mechanism of pseudo-dual-port SRAM does not require a clear read / write recovery potential, so this bit-line-free precharge technology can skip one read / write precharge, achieving both high speed and low power consumption.

[0047] A second aspect of this invention provides a bit-line-free precharged high-speed, low-power pseudo-dual-port SRAM operation method, the method being implemented based on the circuit described in the first aspect, including: S100. In one read / write cycle, first perform a read operation, select the bit line pair of the target column storage cell, stop pre-charging it, and establish a read voltage difference on the bit line pair. S200. After the read operation is completed, the write operation begins immediately. If the target column of the write operation is the same as the target column of the read operation, the bit line pair of that column is not pre-filled between the read and write operations, and the write operation is performed directly on that bit line pair. S300 After the write operation is completed, all bit line pairs are pre-charged to prepare for the next read / write cycle.

[0048] This invention stops pre-charging the selected address during read / write operations while maintaining pre-charging for unselected addresses. Furthermore, when the read and write column selection addresses are the same, pre-charging of the bit lines is unnecessary; the write driver circuit directly drives the bit lines for write operations, resulting in shorter read / write cycles and higher frequencies. When reading and writing the same column selection address within a cycle, the bit line pre-charging signal remains disabled, reducing one full-swing enable and pre-charging operation and significantly lowering dynamic power consumption. When a read bit line is pulled down to a low potential by a memory cell, it does not need to be re-pre-charged to a high potential before being pulled down again by the write driver, further reducing dynamic power consumption caused by read bit line swing pre-charging and pull-down. When writing to a column bit line, if other bit lines stop pre-charging, they will be in a floating state. If the write negative voltage is low, the column selection NMOS will be turned on, potentially writing to adjacent memory cells incorrectly. However, since the unselected bit lines are in a pre-charging state, the NMOS conduction will not cause incorrect writing.

[0049] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention. These are all equivalent modifications and improvements made to the above embodiments based on the essential technology of the present invention, and all of these fall within the protection scope of the present invention.

Claims

1. A bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit, characterized in that, include: The read / write column select signal generation module includes multiple inverters and NAND gates, used to receive read address signals, write address signals, read clock and write clock, and generate read column select signals and write column select signals; The bit line precharge signal generation module includes multiple inverters and NAND gates, and is connected to the read / write column select signal generation module. It is used to generate a bit line precharge control signal based on the read column select signal and the write column select signal. as well as, The bit line generation module includes multiple inverters, transmission gates and PMOS transistors, and is connected to the read / write column select signal generation module and the bit line precharge signal generation module. It is used to select the bit line pairs of the corresponding columns according to the read column select signal and the write column select signal, and to control whether to precharge the bit line pairs according to the bit line precharge control signal. In a read / write cycle, when read and write operations target the same column of memory cells, the bit line precharge control signal becomes invalid after the read operation begins to stop precharging, and becomes valid again after the write operation ends. No valid pulse for precharging is generated between the read and write operations, so that the bit line pair can directly enter the write operation based on the voltage difference established by the read operation.

2. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1, characterized in that, When read and write operations target different column storage cell bit lines, the bit line precharge signal generation module maintains the bit line pairs of the column storage cells that did not participate in the read operation in a precharge state after the read operation is completed, and stops precharging the bit line pairs of the column storage cells that participate in the write operation when the write operation begins.

3. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1 or 2, characterized in that, The bit line precharge control signal is a single pulse signal that becomes invalid at the start of a read operation to stop precharge and becomes valid after a write operation to restore precharge. When read and write operations are performed on the same column, the pulse signal remains invalid between the read and write operations and does not undergo level switching.

4. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1, characterized in that, The bit line generation module includes: Multiple bit line pairs, each bit line pair corresponds to a column of memory cells, and each bit line pair includes the first bit line and the second bit line; Multiple transmission gates, each controlled by the read column select signal and the write column select signal, are used to connect the bit line pairs to a sensitive amplifier during a read operation and to connect the bit line pairs to a write drive circuit during a write operation; and, Multiple PMOS precharge transistors, controlled by the bit line precharge control signal, are used to charge the bit line pair to a high level when precharge is active.

5. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 4, characterized in that, When read and write operations target the same column of memory cells, the first bit line is pulled down to the first voltage by the memory cell during the read operation, and is directly pulled up to the high level or pulled down to the low level by the write driver circuit according to the data to be written during the write operation.

6. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1, characterized in that, The read / write column select signal generation module includes 12 inverters and 8 NAND gates, used to decode the read address and write address, and generate the read column select signal and the write column select signal under the control of the read clock and write clock.

7. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1, characterized in that, The bit line precharge signal generation module includes four inverters and four NAND gates, used to generate the bit line precharge control signal based on the combination of the read column select signal and the write column select signal.

8. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1, characterized in that, The circuit also includes a sensitive amplifier for amplifying the voltage difference generated between bit line pairs during a read operation.

9. The bit-line-free pre-charged high-speed, low-power pseudo-dual-port SRAM circuit according to claim 1, characterized in that, During a write operation, the write drive circuit provides a negative voltage to the target bit line; the bit line precharge control signal for the bit line pair of the non-target column memory cell remains active during the write operation to keep the non-target bit line pair in a high-level precharge state.

10. A bit-line-free pre-charge high-speed, low-power pseudo-dual-port SRAM operation method, characterized in that, The operation method is implemented based on the circuit described in any one of claims 1-9, and includes: Within a read / write cycle, a read operation is performed first, selecting the bit line pair of the target column memory cell, stopping its pre-charge, and establishing a read voltage difference on the bit line pair; After the read operation is completed, the write operation begins immediately. If the target column of the write operation is the same as the target column of the read operation, the bit pair of that column is not pre-padded between the read and write operations, and the write operation is performed directly on that bit pair. After the write operation is completed, all bit pairs are pre-charged in preparation for the next read / write cycle.

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