Memory circuit and method of operation thereof

Abstract

Embodiments of the present application disclose a memory circuit and an operating method thereof. The memory circuit comprises a first decoder configured to receive a first clock pulse signal, a second pulse signal, a first part of a first address signal and a first part of a second address signal, and generate a first decoding signal; a second decoder configured to receive a second part of the first address signal or a second part of the second address signal to generate a second decoding signal; and a third decoder configured to receive a third part of the first address signal or a third part of the second address signal to generate a third decoding signal.

Description

Technical Field

[0001] Embodiments of this application relate to memory circuits and methods of operation thereof. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the repeated reduction in the size of the smallest components, allowing more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a memory circuit is provided, comprising: a memory cell and a word line (WL), wherein access to the memory cell is controlled by the WL; a WL driver coupled to the WL and configured to assert the WL; and a controller operably coupled to the WL driver and configured to provide a plurality of decoding signals, the decoding signals being collectively configured to assert the WL; wherein the controller includes: a first decoder configured to receive a first clock pulse signal, a second pulse signal, a first portion of a first address signal, and a first portion of a second address signal, and to generate a first decoding signal from a plurality of decoding signals based on the first clock pulse signal, the second pulse signal, the first portion of the first address signal, and the first portion of the second address signal; and a second decoder configured to receive... A third decoder is configured to receive a second part of the first address signal or a second part of the second address signal to generate a second decoded signal among a plurality of decoded signals; a third decoder is configured to receive a third part of the first address signal or a third part of the second address signal to generate a third decoded signal among a plurality of decoded signals; and a multiplexer is configured to (i) receive a selection signal; (ii) when the selection signal is provided in a first logic state, provide a second part of the first address signal to the second decoder and provide a third part of the first address signal to the third decoder respectively; and (iii) when the selection signal is provided in a second logic state, provide a second part of the second address signal to the second decoder and provide a third part of the second address signal to the third decoder respectively.

[0004] According to another aspect of the embodiments of this application, a memory circuit is provided, comprising: a controller operatively coupled to a plurality of word line (WL) drivers and a memory array, wherein the controller is configured to provide a plurality of decoding signals, the decoding signals being collectively configured to assert one of the plurality of WLs of the memory array via a corresponding one of the WL drivers; wherein the controller includes: a first decoder configured to generate a first decoding signal in the decoding signals based on a first clock pulse signal, a second pulse signal, a first portion of a first address signal, and a first portion of a second address signal, wherein the first address signal and the second address signal correspond to a first operating mode of the memory array and a second operating mode of the memory array, respectively; and a second decoder configured to generate a first decoding signal based on a second portion of the first address signal or a second... The second part of the address signal is used to generate the second decoded signal in the decoded signal; the third decoder is configured to generate the third decoded signal in the decoded signal based on the third part of the first address signal or the third part of the second address signal; and the multiplexer is configured to (i) receive a selection signal having a first logic state corresponding to a first operating mode or a second logic state corresponding to a second operating mode; (ii) in response to the selection signal being equal to the first logic state, provide the second part of the first address signal to the second decoder and provide the third part of the first address signal to the third decoder; and (iii) in response to the selection signal being equal to the second logic state, provide the second part of the second address signal to the second decoder and provide the third part of the second address signal to the third decoder.

[0005] According to another aspect of the embodiments of this application, a method for operating a memory circuit is provided, comprising: providing a selection signal for switching between a first logic state and a second logic state, the first logic state of the selection signal corresponding to a first operating mode and the second logic state of the selection signal corresponding to a second operating mode; in response to identifying a transition edge of a first pulse signal, providing a first combination of a first decoding signal, a second decoding signal, and a third decoding signal based on a first address signal corresponding to the first operating mode; asserting a first word line connected to a first memory cell based on the first combination of the first to third decoding signals, the first memory cell being configured in the first operating mode; in response to identifying a transition edge of a second pulse signal appearing after the first pulse signal, providing a second combination of the first decoding signal, the second decoding signal, and the third decoding signal based on a second address signal corresponding to the second operating mode; and asserting a second word line connected to a second memory cell based on the second combination of the first to third decoding signals, the second memory cell being configured in the second operating mode. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An example block diagram of a memory circuit according to some embodiments is shown.

[0008] Figure 2 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of a portion of the memory circuit.

[0009] Figure 2A The following are examples of implementations based on... Figure 2 Schematic diagram Figure 1 An example circuit diagram of a portion of a memory circuit.

[0010] Figure 3 Illustrations are shown according to some embodiments Figure 1 Example circuit diagram of a decoder for a memory circuit.

[0011] Figure 4 The following are illustrations based on some embodiments. Figure 1 The waveforms of various signals propagating on the memory circuit.

[0012] Figure 5 An example flowchart of a method for operating a memory circuit according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0015] Integrated circuits typically include static random access memory (SRAM) circuitry to provide on-chip data storage. SRAM circuitry is usually configured to meet specific design requirements associated with the surrounding circuitry attached to it. One common type of SRAM circuitry provides one port for reading or writing data stored within the SRAM circuitry. The address input of this type of circuitry is typically shared for both read and write access. Another common type of SRAM circuitry, called a dual-port SRAM circuitry, provides two ports for accessing the data stored within the SRAM circuitry. Dual-port SRAM circuitry typically restricts all read accesses to one port and all write accesses to the second port. Each port of a dual-port SRAM circuitry is typically able to access the data stored in the SRAM circuitry asynchronously and independently, allowing dual-port SRAM circuitry to be incorporated into a variety of different applications with different usage patterns.

[0016] Dual-port SRAM circuits allow designers to implement system performance levels that are typically higher than those using only single-port SRAM circuits. However, for a given number of memory bits, existing dual-port SRAM circuits require approximately twice the area of ​​single-port SRAM circuits. Therefore, in integrated circuits where SRAM circuitry occupies a large portion of the overall die area, using dual-port SRAM circuits can be an extremely expensive design choice.

[0017] One approach to reducing the die area cost associated with using dual-port SRAM circuitry is to replace each dual-port SRAM cell with a single-port SRAM cell (e.g., a six-transistor SRAM cell) that operates with sequential read and write accesses. For example, one read access and one write access can be performed per clock cycle, allowing the SRAM circuitry to provide two external ports, each capable of performing one transaction per clock cycle. Typically, two clock pulses are generated based on a single clock signal, one for read access and the other for write access. This type of SRAM circuitry is sometimes referred to as a dual-pump SRAM circuit. Existing dual-pump SRAM circuits typically rely on separate decoder circuits that provide their respective decoded address signals: a read decoder circuit and a write decoder circuit. Implementing these separate decoder circuits requires a large number of metal tracks to carry these decoded address signals, which disadvantageously occupies a significant amount of prior space on the substrate. Furthermore, the read decoder circuit and the write decoder circuit operate with different clock pulses. However, the timing between these clock pulses needs to be precisely configured, which can be technically challenging. Therefore, existing dual-pump SRAM circuits are not entirely satisfactory in some respects.

[0018] This disclosure provides various embodiments of a memory circuit having multiple decoder circuits, each of which can be configured to perform read and write operations on multiple memory cells. As a non-limiting example, each of the disclosed decoder circuits can sequentially decode a first address signal associated with a first memory cell configured for reading and a second address signal associated with a second memory cell configured for writing. Each memory cell may include a single-port SRAM cell (e.g., a six-transistor (6T) SRAM cell), while other types of memory can also be utilized. In various embodiments of this disclosure, the decoder circuit may include a first decoder, a second decoder, and a third decoder. The first to third decoders may be configured together for read and write operations, and are sometimes collectively referred to as a hybrid address decoder.

[0019] The first decoder can receive a first pulse configured for a read operation and a second pulse configured for a write operation. Furthermore, the first decoder can receive a first portion of a first address signal and a first portion of a second address signal. The first decoder may include multiple logic gates. Based on the corresponding logic states of the first pulse, the second pulse, the first portion of the first address signal, and the first portion of the second address signal, the first decoder can generate a first decoded signal. The second decoder can receive either a second portion of the first address signal or a second portion of the second address signal to generate a second decoded signal; the third decoder can receive either a third portion of the first address signal or a third portion of the second address signal to generate a third decoded signal. According to some embodiments, the first decoder may sometimes be referred to as being directly driven by pulses, while the second and third decoders may sometimes be referred to as being indirectly driven by pulses.

[0020] As disclosed herein, the decoder circuitry may further include a multiplexer configured to receive a selection signal configured to cause the second and third decoders to process the address signal for a read or write operation. For example, based on the selection signal provided in a first logic state operatively corresponding to a read operation, the multiplexer may provide a second portion of the first address signal to the second decoder and a third portion of the first address signal to the third decoder. Based on the selection signal provided in a second logic state operatively corresponding to a write operation, the multiplexer may provide a second portion of the second address signal to the second decoder and a third portion of the second address signal to the third decoder. In other words, when the selection signal is provided in the first logic state, the multiplexer can select the second and third portions of the first address signal (e.g., for reading one of the memory cells); and when the selection signal is provided in the second logic state, the multiplexer can select the second and third portions of the second address signal (e.g., for writing to the other memory cell).

[0021] By combining the first to third decoded signals, a write level (WL) coupled to one or more corresponding memory cells can be asserted. For example, the first decoded signal can be used as a dual-pump decoded signal, which can be logically combined with a logical combination of the second and third decoded signals to assert the WL. Since read and write operations share the same decoder circuitry, the large number of metal tracks operably coupled to the WL can be reduced. Advantageously, the disclosed memory circuitry can be formed on a substrate with a significantly reduced area.

[0022] Figure 1 A schematic diagram of a memory system or circuit 100 according to various embodiments is shown. The memory system 100 is implemented as an integrated circuit. Figure 1As shown, the storage system 100 includes a storage controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits, memory cells, memory bits, or bit cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 can be accessed via a plurality of access lines. For example, each memory cell 125 may be connected to a corresponding word line WL and a corresponding pair of bit lines BL. Each word line WL and bit line BL may be implemented as one or more metal rails. The storage controller 105 may write data to or read data from the memory array 120 according to electrical signals transmitted through the word line WL and bit line BL. In other embodiments, the storage system 100 includes a larger... Figure 1 The disclosure may include more, fewer, or different components, while still remaining within the scope of this disclosure.

[0023] Memory array 120 is a hardware component for storing data. In various embodiments, memory array 120 is implemented as a semiconductor memory device. Memory array 120 includes a plurality of storage circuits or memory cells 125. In some embodiments, memory array 120 includes word lines WL0, WL1…WL, each extending along a first direction. J and their respective bit lines BL0, BL1...BL extending along the second direction K The word line WL and bit line BL may each include multiple metal rails. Each memory cell 125 is connected to a corresponding word line WL and a corresponding pair of bit lines BL, and can operate according to the voltage or current passing through the corresponding word line WL and the corresponding pair of bit lines BL. Each memory cell 125 may be a static random access memory (SRAM) cell. For example, memory cell 125 may be implemented as a six-transistor (6T) SRAM cell or a single-port SRAM cell. However, it should be understood that memory cell 125 may be implemented in any of a variety of other memory configurations while still within the scope of this disclosure. In some embodiments, memory array 120 includes additional lines (e.g., sense lines, reference lines, reference control lines, power rails, etc.).

[0024] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes BL controller 112, WL controller 114, and decoder circuitry 116. In one configuration, WL controller 114 is circuitry that provides voltage or current signals to assert one or more word lines WL of memory array 120, and BL controller 112 is circuitry that provides voltage or current signals through one or more bit lines BL in memory array 120 and senses voltage or current from memory array 120 through one or more bit lines BL. WL controller 114 may include multiple portions, each configured to assert one or more corresponding word lines WL. This portion of WL controller 114 may be referred to herein as a WL driver.

[0025] As will be discussed in further detail below, decoder circuitry 116 may include a dual-pump generator (sometimes referred to as a pulse generator), a first decoder, a second decoder, a third decoder, and a port multiplexer (sometimes referred to as a multiplexer). The dual-pump generator may sequentially generate a first pulse signal and a second pulse signal based on a received clock signal. The first pulse signal may be configured to perform a first operation (e.g., a read operation) on memory array 120, and the second pulse signal may be configured to perform a second operation (e.g., a write operation) on memory array 120. The port multiplexer may determine whether to select a first address signal or a second address signal to the second and third decoders based on the logic state of a selection signal. The first address signal corresponds to one of the memory cells 125 configured to perform a first (e.g., a read) operation, and the second address signal corresponds to another memory cell 125 configured to perform a second (e.g., a write) operation. The first decoder may provide a first logic state for the selection signal based on the first and second pulse signals being asserted and deasserted, respectively; and provide a second logic state for the selection signal based on the first and second pulse signals being deasserted and asserted, respectively. After receiving the second address signal from the port multiplexer, the second and third decoders can each provide a decoding signal to assert the word line WL connected to the memory cell 125 to be read. Similarly, after receiving the third address signal from the port multiplexer, the second and third decoders can each provide a decoding signal to assert the word line WL connected to the memory cell 125 to be written.

[0026] BL controller 112 can be connected to the bit line BL of memory array 120, and WL controller 114 can be connected to the word line WL of memory array 120. In one example, to write data to memory cell 125, WL controller 114 is configured to apply a voltage or current signal (sometimes referred to as a WL signal) to memory cell 125 via the corresponding word line WL connected to memory cell 125, and BL controller 112 is configured to apply voltage or current information corresponding to the data to be stored to memory cell 125 via a pair of bit lines BL connected to memory cell 125. To read data from memory cell 125, WL controller 114 is configured to apply a WL signal to memory cell 125 via the corresponding word line WL connected to memory cell 125, and BL controller 112 is configured to sense the voltage or current corresponding to the data to be stored by memory cell 125 via the bit lines connected to memory cell 125. In some embodiments, memory controller 105 may include a voltage or current corresponding to the data to be stored by memory cell 125. Figure 1 The disclosure may include more, fewer, or different components, while still remaining within the scope of this disclosure.

[0027] Figure 2 An example schematic diagram of a portion of a memory system 100 according to some embodiments (e.g., WL controller 114 and decoder circuitry 116) is shown. As shown, decoder circuitry 116 may include a pulse generator configured to generate pulse signals, such as CKP1 and CKP2, to a first decoder and to generate port selection signals, such as PSEL, to a port multiplexer that receives inputs from a first latch and a second latch, respectively. Such inputs may be further provided to the first decoder. The port multiplexer may provide outputs to a second decoder and a third decoder, respectively. The first, second, and third decoders may provide corresponding decoding signals to the WL decoder of WL controller 114 to assert the WL. The following will... Figure 2A The example circuit implementation is discussed below.

[0028] Figure 2A Example circuit diagrams are shown, including a portion of decoder circuitry 116 and a portion of WL controller 114 (or a WL driver), according to some embodiments. The circuit diagram of decoder circuitry 116 is based on... Figure 2 A schematic diagram is provided. As described above, the decoder circuit 116 can be coupled to multiple WL drivers. The decoder circuit 116 can provide corresponding combinations of first to third decoded signals to each WL driver of the WL controller 114 through the first to third decoders to assert the corresponding word line WL.

[0029] As shown, the decoder circuit 116 includes a pulse generator 202, a first latch 204, a second latch 206, a multiplexer 208, a first decoder 210, a second decoder 212, and a third decoder 214; the WL controller 114 (or a WL driver) includes a NOR gate 240, a NAND gate 242, and inverters 244, 246, and 248. It should be understood that, for illustrative purposes, Figure 2A The circuit diagram has been simplified. Therefore, the decoder circuit 116 and the WL controller 114 can each have any other suitable components, while still remaining within the scope of this disclosure.

[0030] The pulse generator 202, comprising various components discussed below, can generate a first pulse signal (e.g., CKP1) and a second pulse signal or variations thereof (e.g., CKP2, CKP2_WL, CKP2UNBUF) based on various control signals (e.g., REB, CLK, WEB). In some embodiments, the pulse generator 202 may assert or otherwise provide the CKP1 signal, and then assert or otherwise provide the CKP2 signal (or variations thereof). The CKP2 signal is asserted in the time domain after the CKP1 signal. Figure 2A In the current example (and the discussion below), the CKP1 signal can be configured for a read operation, and the CKP2 signal can be configured for a write operation. In other words, the memory system 100 can be configured to perform a read operation first and then a write operation.

[0031] For example, when the REB signal is provided with logic 0, the first clock generator (CKG1) 222 can be activated to provide the CKP1 signal based on the received CLK signal; and when the WEB signal is provided with logic 0, the second clock generator (CKG2) 226 can be activated to provide the CKP2 signal based on the received CLK signal. In some embodiments, the period of the CLK signal may correspond to the pulse width of the CKP1 signal and the pulse width of the CKP2 signal. The CKP2 signal will not be asserted (e.g., pulled up to logic 1) until the CKP1 signal is deasserted (e.g., pulled down to logic 0). That is, the write operation will not begin until the read operation is complete. Specifically, CKG2 226 can provide a leading variant of the CKP2 signal, namely the CKP2UNBUF signal, which has a pulse leading the CKP2 signal pulse. In another example, there may be no read operation before the write operation. Therefore, the conversion clock generator (CKG_TK) 224 can replace CKG1 222 to provide a conversion pulse signal (not shown) similar to the CKP1 signal, thereby allowing CKG2 226 to identify when to assert the CKP2 signal.

[0032] The logical combination of the CKP2 and CKP2UNBUF signals, through NOR gates 226 and inverters 228-230, determines the logical state of the selection signal PSEL, which is configured to control multiplexer 208. Specifically, when both the CKP2 and CKP2UNBUF signals are provided with logic 0, the PSEL signal is provided with logic 1; and after either the CKP2 or CKP2UNBUF signal is asserted (e.g., pulled up to logic 1), the PSEL signal can be converted to logic 0. In some embodiments, when the PSEL signal is provided (or output) as logic 1, multiplexer 208 is configured to select a portion of the address signal to be read to the second decoder 212 and the third decoder 214; and when the PSEL signal is provided (or output) as logic 0, multiplexer 208 is configured to select a portion of the address signal to be written to the second decoder 212 and the third decoder 214, as will be discussed below. CKG2 226 can also provide the first decoder 210 with another variant of the CKP2 signal, CKP2_WL, which is delayed by delay chain 232.

[0033] The first latch 204 can receive a first address signal (e.g., RADR) corresponding to one of the memory cells 125 configured to be read, and is therefore referred to as the R latch. The RADR signal is sometimes referred to as the read address signal. The first latch 204 can selectively provide the RADR signal to the multiplexer 208 based on the control signal RCKT. In response to a transition in the logic state of the RCKT signal (e.g., a rising edge), the first latch 204 can provide its output signal following the RADR signal. Otherwise, the RADR signal is latched by the first latch 204. The second latch 206 can receive a second address signal (e.g., WADR) corresponding to another of the memory cells 125 configured to be written, and is therefore referred to as the W latch. The WADR signal is sometimes referred to as the write address signal. The second latch 206 can selectively provide the WADR signal to the multiplexer 208 based on the control signal WCKT. In response to recognizing a transition in the logic state of the WCKT signal (e.g., a rising edge), the second latch 206 can provide its output signal following the WADR signal. Otherwise, the WADR signal is latched by the second latch 206. In some embodiments, the RCKT and WCKT signals can transition to logic 1 simultaneously. Therefore, the multiplexer 208 can simultaneously receive the RADR and WADR signals.

[0034] After latches 204 and 206 provide the RADR and WADR signals respectively, multiplexer 208 can determine whether to forward the RADR or WADR signal to decoders 212 and 214 based on the logic state of the PSEL signal. As a non-limiting example, the RADR and WADR signals may each have 8 bits, for example, RADR<7:0> and WADR<7:0>. According to various embodiments of this disclosure, in addition to the CKP1 and CKP2_WL signals, the first decoder 210 may also receive a first portion of the RADR signal, such as RADR<1:0>, and a second portion of the WADR signal, such as WADR<1:0>.

[0035] Figure 3 An example circuit diagram of a first decoder 210 including AND-OR-NOT (AOI) logic gates is shown. Therefore, the first decoder 210 can generate a first decoded signal DEC_X0 based on a combination of the logic states of RADR<1:0>, WADR<1:0>, CKP1 signals, and CKP2_WL signals. The first decoded signal can have 4 bits, such as DEC_X0<3:0>. Based on the number of bits in its input and output signals, the first decoder 210 is sometimes referred to as a 2-4 decoder. A second decoder 212 can generate a second decoded signal DEC_X1B based on a second portion (e.g., RADR<7:5>) or a second portion (e.g., WADR<7:5>) of the RADR signal received from multiplexer 208. The second decoded signal can have 8 bits, such as DEC_X1B<7:0>. Based on the number of bits in its input and output signals, the second decoder 212 is sometimes referred to as a 3-8 decoder. The third decoder 214 can generate a third decoded signal DEC_X2B based on the third part of the RADR signal received from the multiplexer 208, such as RADR<4:2>, or the third part of the WADR signal, such as WADR<4:2>. The third decoded signal can have 8 bits, such as DEC_X2B<7:0>. Based on the number of bits in its input and output signals, the third decoder 214 is sometimes referred to as a 3-8 decoder.

[0036] According to some embodiments, the WL driver (of WL controller 114) can assert word lines WL using first to third decoded signals DEC_X0, DEC_X1B, and DEC_X2B. Each WL driver may include logic components 240 to 248 coupled to the corresponding word line WL. Logic components 240 to 248 may sometimes be referred to as WL decoders. In other words, the first to third decoders 210 to 214 (of decoder circuitry 116) can be operatively shared by multiple WL drivers (of WL controller 114), and each WL driver is configured to assert at least one corresponding word line WL coupled to a memory cell to be read or written. Compared to existing decoding schemes for dual-pump memory circuits, the number of metal tracks coupling decoder circuitry 116 to WL controller 114 can be significantly reduced, thus advantageously reducing the area occupied by the disclosed memory system 100. Specifically, DEC_X1B (second decoding signal) and DEC_X2B (third decoding signal) can be NORed by the NOR gate 240 of the corresponding WL driver to become DECL signal. The DECL signal is further NANDed by the NAND gate 242 of the corresponding WL driver with the DEC_X0 signal so as to assert word line WL through the inverters 244 to 248 of the corresponding WL driver.

[0037] Figure 3 Illustrations are shown according to some embodiments Figure 2A An example circuit diagram of the first decoder 210 is shown. As shown, the first decoder 210 includes AND gates 310 and 320 and a NOR gate 330. AND gate 310 has two inputs configured to receive the RADR<1:0> and CKP1 signals, respectively; AND gate 320 has two inputs configured to receive the WADR<1:0> and CKP2_WL signals, respectively. NOR gate 330 has two inputs configured to receive the outputs (e.g., ANDed) provided by AND gates 310 and 320. Therefore, NOR gate 330 can provide the first decoded signal DEC_X0.

[0038] Figure 4 The following diagram illustrates the time-varying behavior of a memory system 100 (a portion of which is in) according to some embodiments. Figure 2A Example waveforms of various signals propagating are shown below. For example, signals CKP1, CKP2UNBUF, CKP2, RCKT, WCKT, PSEL, and DECL are shown. Furthermore, the output signals provided by latches 204 and 206 are shown, respectively. It should be understood that... Figure 4 The waveforms shown are simplified for illustrative and exemplary purposes and are not intended to limit the scope of this disclosure. For example, the logic state of a signal can be changed... Figure 2AThe logic gates of the decoder circuit 116 and WL controller 114 shown in the figure vary.

[0039] When memory system 100 is started to perform a read-before-write operation, the CKP1 and CKP2 signals (and their variant CKP2UNBUF signal) may first be provided at logic 0, which may cause the PSEL signal to transition from logic 0 to logic 1. Next, the CKP1 signal can be asserted and transitioned to logic 1, followed by the RCKT signal transitioning to logic 1. In some embodiments, the WCKT signal may be transitioned to logic 1 simultaneously with the RCKT signal transition. After recognizing the rising edge of the RCKT signal, the first latch 204 may output the RADR signal, as indicated by symbolic arrow 401. Similarly, after recognizing the rising edge of the WCKT signal, the second latch 206 may output the WADR signal, as indicated by symbolic arrow 403. Since the PSEL signal has been pulled up to logic 1 (assuming the CKP2 and CKP2UNBUF signals are both held at logic 0), which corresponds to a read operation performed on memory array 120, the second decoder 212 and the third decoder 214 can provide decoding signals DEC_X1B and DEC_X2B respectively to provide the DECL signal. The DECL signal can correspond to the RADR signal, as indicated by symbolic arrow 405.

[0040] Next, the CKP1 signal can transition to logic 0, as indicated by arrow 407, pulling up the CKP2UNBUF signal. In some embodiments, the PSEL signal will not transition from logic 1 to logic 0, for example, it will not transition from a read operation to a write operation until the CKP1 signal transitions from logic 1 to logic 0. After the CKP2UNBUF signal transitions from logic 0 to logic 1, the PSEL signal can be pulled down to logic 0, as indicated by arrow 409. When the PSEL signal is provided at logic 0, the write operation is configured to be performed on memory array 120. Therefore, the second decoder 212 and the third decoder 214 can provide decoded signals DEC_X1B and DEC_X2B, respectively, to provide the DECL signal. The DECL signal can correspond to the WADR signal, as indicated by arrow 411. After the CKP2UNBUF signal, the CKP2 signal can be pulled up to logic 1 and then pulled down to logic 0. After recognizing the falling edge of the CKP2 signal (where the CKP2UNBUF signal has been pulled down to logic 0), the PSEL signal can be pulled up to logic 1, as shown by symbolic arrow 413. Simultaneously with the PSEL signal transitioning to logic 1, the WCKT signal can be pulled down to logic 0, as shown by symbolic arrow 415. The memory system 100 can then wait for the next read-before-write operation.

[0041] Figure 5A flowchart of an example method 500 for operating a storage system according to some embodiments is shown. For example, at least some operations (or steps) of method 500 can be performed by at least one of the above (e.g. Figure 2A Therefore, some of the reference figures mentioned above can be reused. It should be noted that method 500 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 5 Additional operations are provided before, during, and / or after Method 500, and this document may only briefly describe some of these other operations.

[0042] Method 500 begins with operation 510, which provides a selection signal for transitioning between a first logic state and a second logic state. In some embodiments, the first logic state of the selection signal corresponds to a first operating mode, and the second logic state of the selection signal corresponds to a second operating mode.

[0043] use Figure 2A As a representative example, a selection signal (e.g., a PSEL signal) can be provided based on a logical combination of the CKP2 and CKP2UNBUF signals. The CKP2 signal corresponding to the second operating mode (e.g., write operation) may appear after the CKE1 signal corresponding to the first operating mode (e.g., read operation). Multiplexer 208 can receive the PSEL signal. Multiplexer 208 can select either a first address signal (corresponding to a first memory cell configured for reading) or a second address signal (corresponding to a second memory cell configured for writing), and provide the selected address signal to the downstream decoder based on the logical state of the PSEL signal to assert the corresponding word line WL.

[0044] Method 500 continues to operation 520, in response to identifying the transition edge of the first pulse signal, providing a first combination of a first decoding signal, a second decoding signal, and a third decoding signal based on a first address signal corresponding to the first operating mode. Continuing the above example, the first pulse signal is implemented as a CKP1 signal, the first address signal is implemented as a RADR signal, and the second address signal is implemented as a WADR signal.

[0045] Combination Figure 4 refer to Figure 2ACKG1 222 asserts the CKP1 signal to pull up the CKP1 signal using the rising edge, which can pull up the RCKT and WCKT signals. After the RCKT and WCKT signals are pulled up, the first latch 204 and the second latch 206 can provide the RADR and WADR signals, respectively. Then, the first portion of the RADR signal (e.g., RADR<1:0>) and the first portion of the WADR signal (e.g., WADR<1:0>) are provided to the first decoder 210. Assuming the PSEL signal is provided as logic 1 (e.g., both the CKP2 and CKP2UNBUF signals are held at logic 0), the multiplexer 208 can provide the second portion of the RADR signal (e.g., RADR<7:5>) and the third portion of the RADR signal (e.g., RADR<4:2>) to the second decoder 212 and the third decoder 214, respectively. Therefore, the first decoder 210, the second decoder 212 and the third decoder 214 can jointly provide a first combination of the first to third decoded signals (e.g., DEC_X0, DEC_X1B and DEC_X2B).

[0046] Method 500 continues to operation 530, asserting a first word line connected to a first memory cell configured for a first operating mode based on a first combination of the first to third decoded signals. Still using the example above, DEC_X0 (the first decoded signal) can be provided as one of the inputs to NAND gate 242 (of the first WL driver), and DEC_X1B (the second decoded signal) and DEC_X2B (the third decoded signal) can be NORed by NOR gate 240 (of the first WL driver) to provide a DECL signal, which is provided as the other input to NAND gate 242. Therefore, based on a first logical combination of the first to third decoded signals DEC_X0, DEC_X1B, and DEC_X2B, the first WL driver can assert a connection to the corresponding word line WL of the first memory cell configured for a read operation.

[0047] Method 500 continues to operation 540, in response to identifying the transition edge of the second pulse signal, providing a second combination of the first decoding signal, the second decoding signal, and the third decoding signal based on the second address signal corresponding to the second operation mode. Continuing the above example, the second pulse signal is implemented as the CKP2 signal.

[0048] Combination Figure 4 refer to Figure 2AAfter the CKP1 signal is converted to logic 0, CKG2 226 asserts the CKP2 signal (and the CKP2UNBUF signal) to pull up the CKP2 signal (and the CKP2UNBUF signal) using the rising edge, which can pull down the PSEL signal. Assuming the PSEL signal is provided at logic 0 (e.g., one of the CKP2 signal or the CKP2UNBUF signal is provided at logic 0, or both the CKP2 signal and the CKP2UNBUF signal are provided at logic 1), multiplexer 208 can provide the second portion (e.g., WADR<7:5>) and the third portion (e.g., WADR<4:2>) of the WADR signal to the second decoder 212 and the third decoder 214, respectively. The first decoder 210 can still receive the first portion (e.g., RADR<1:0>) and the first portion (e.g., WADR<1:0>) of the RADR signal, but the logic combination of the CKP1 signal and the CKP2 signal is different. Therefore, the first decoder 210, the second decoder 212 and the third decoder 214 can jointly provide a second combination of the first to third decoded signals (e.g., DEC_X0, DEC_X1B and DEC_X2B).

[0049] Method 500 continues to operation 550, asserting a second word line connected to a second memory cell configured for a second operating mode based on a second combination of the first to third decoded signals. Still using the example above, DEC_X0 (the first decoded signal) can be provided as one of the inputs to NAND gate 242 (of the second WL driver), and DEC_X1B (the second decoded signal) and DEC_X2B (the third decoded signal) can be NORed by NOR gate 240 (of the second WL driver) to provide a DECL signal, which is provided as the other input to NAND gate 242. Therefore, based on the second logical combination of the first to third decoded signals DEC_X0, DEC_X1B, and DEC_X2B, the second WL driver can assert a corresponding word line WL connected to a second memory cell configured for write operations.

[0050] In one aspect of this disclosure, a memory circuit is disclosed. The circuit includes: a memory cell and a word line (WL), access to the memory cell being controlled by the WL; a WL driver coupled to the WL and configured to assert the WL; and a controller operatively coupled to the WL driver and configured to provide a plurality of decoding signals, the decoding signals being collectively configured to assert the WL. The controller includes: a first decoder configured to receive a first clock pulse signal, a second pulse signal, a first portion of a first address signal, and a first portion of a second address signal, and generate a first decoded signal among a plurality of decoded signals based on the first clock pulse signal, the second pulse signal, the first portion of the first address signal, and the first portion of the second address signal; a second decoder configured to receive a second portion of the first address signal or a second portion of the second address signal to generate a second decoded signal among a plurality of decoded signals; a third decoder configured to receive a third portion of the first address signal or a third portion of the second address signal to generate a third decoded signal among a plurality of decoded signals; and a multiplexer configured to (i) receive a selection signal; (ii) when a selection signal is provided in a first logic state, provide a second portion of the first address signal to the second decoder and provide a third portion of the first address signal to the third decoder; and (iii) when a selection signal is provided in a second logic state, provide a second portion of the second address signal to the second decoder and provide a third portion of the second address signal to the third decoder.

[0051] In some embodiments, the first decoder includes an AND-OR-Inverting (AOI) gate consisting of a first AND gate, a second AND gate, and a NOR gate.

[0052] In some embodiments, a first AND gate is configured to receive a first portion of a first clock pulse signal and a first address signal, and generate a first intermediate signal; a second AND gate is configured to receive a second pulse signal and a first portion of a second address signal, and generate a second intermediate signal; and a NOR gate is configured to receive the first intermediate signal and the second intermediate signal, and generate a first decoded signal.

[0053] In some embodiments, the first logic state of the selection signal corresponds to a first operating mode, and the second logic state of the selection signal corresponds to a second operating mode.

[0054] In some embodiments, a first pulse signal is provided in a first logic state to cause the selection signal to be in the first logic state, and a second pulse signal is provided in the first logic state to cause the selection signal to be in the second logic state.

[0055] In some embodiments, the memory circuitry further includes a clock generation circuit configured to generate a first pulse signal and a second pulse signal, respectively, at different timing assertions.

[0056] In some embodiments, the clock generation circuit is further configured to generate a leading second pulse signal for transitioning the selection signal from a first logic state to a second logic state.

[0057] In some embodiments, the leading second pulse signal precedes the second pulse signal in the time domain.

[0058] In some embodiments, the WL driver includes NOR gates, NAND gates, and multiple inverters.

[0059] In some embodiments, a NOR gate is configured to receive a second decoded signal and a third decoded signal and generate a first intermediate signal; a NAND gate is configured to receive a first decoded signal and a first intermediate signal and generate a second intermediate signal; and an inverter is configured to generate a WL assertion signal for asserting WL based on the second intermediate signal.

[0060] In another aspect of this disclosure, a memory circuit is disclosed. The circuit includes a controller operatively coupled to a plurality of word line (WL) drivers and a memory array, wherein the controller is configured to provide a plurality of decoding signals, the decoding signals being collectively configured to assert one of the plurality of WLs of the memory array via a corresponding one of the WL drivers. The controller includes: a first decoder configured to generate a first decoded signal in the decoded signal based on a first clock pulse signal, a second pulse signal, a first portion of a first address signal, and a first portion of a second address signal, wherein the first address signal and the second address signal correspond to a first operating mode of the memory array and a second operating mode of the memory array, respectively; a second decoder configured to generate a second decoded signal in the decoded signal based on a second portion of the first address signal or a second portion of the second address signal; a third decoder configured to generate a third decoded signal in the decoded signal based on a third portion of the first address signal or a third portion of the second address signal; and a multiplexer configured to (i) receive a selection signal having a first logic state corresponding to the first operating mode or a second logic state corresponding to the second operating mode; (ii) in response to the selection signal being equal to the first logic state, provide a second portion of the first address signal to the second decoder and provide a third portion of the first address signal to the third decoder; and (iii) in response to the selection signal being equal to the second logic state, provide a second portion of the second address signal to the second decoder and provide a third portion of the second address signal to the third decoder.

[0061] In some embodiments, the second pulse signal is not asserted until the first clock pulse signal is deasserted.

[0062] In some embodiments, the first decoder includes an AND-OR inverting (AOI) gate consisting of a first AND gate, a second AND gate, and a NOR gate.

[0063] In some embodiments, a first AND gate is configured to receive a first portion of a first clock pulse signal and a first address signal, and generate a first intermediate signal; a second AND gate is configured to receive a second pulse signal and a first portion of a second address signal, and generate a second intermediate signal; and a NOR gate is configured to receive the first intermediate signal and the second intermediate signal, and generate a first decoded signal.

[0064] In some embodiments, a first pulse signal is provided in a first logic state to cause the selection signal to be in the first logic state, and a second pulse signal is provided in the first logic state to cause the selection signal to be in the second logic state.

[0065] In some embodiments, the memory circuitry further includes a clock generation circuit configured to generate a first pulse signal and a second pulse signal asserted at different timings.

[0066] In some embodiments, the clock generation circuit is further configured to generate a leading second pulse signal for transitioning the selection signal from a first logic state to a second logic state, wherein the leading second pulse signal precedes the second pulse signal in the time domain.

[0067] In another aspect of this disclosure, a method for operating a memory circuit is disclosed. The method includes: providing a selection signal that transitions between a first logic state and a second logic state, the first logic state of the selection signal corresponding to a first operating mode, and the second logic state of the selection signal corresponding to a second operating mode. The method includes: in response to identifying a transition edge of a first pulse signal, providing a first combination of a first decoding signal, a second decoding signal, and a third decoding signal based on a first address signal corresponding to the first operating mode. The method includes: based on the first combination of the first to third decoding signals, asserting a first word line connected to a first memory cell, the first memory cell being configured in the first operating mode. The method includes: in response to identifying a transition edge of a second pulse signal occurring after the first pulse signal, providing a second combination of the first decoding signal, the second decoding signal, and the third decoding signal based on a second address signal corresponding to the second operating mode. The method includes: based on the second combination of the first to third decoding signals, asserting a second word line connected to a second memory cell, the second memory cell being configured in the second operating mode.

[0068] In some embodiments, the method further includes: in response to identifying another transition edge of the first pulse signal that occurs before the transition edge of the second pulse signal, transitioning the selection signal from a first logic state to a second logic state.

[0069] In some embodiments, both the first memory unit and the second memory unit include a single-port static random access memory unit.

[0070] As used herein, the terms “approximately” and “around” generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “approximately” can refer to a given quantity that varies, for example, within a range of 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0071] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A memory circuit, comprising: Memory cells and word lines, wherein access to the memory cells is controlled by the word lines; A word line driver, coupled to the word line and configured to assert the word line; A controller, operably coupled to the word line driver, is configured to provide a plurality of decoding signals that are collectively configured to assert the word line; The controller includes: A first decoder is configured to receive a first clock pulse signal, a second pulse signal, a first portion of a first address signal, and a first portion of a second address signal, and to generate a first decoded signal from a plurality of decoded signals based on the first clock pulse signal, the second pulse signal, the first portion of the first address signal, and the first portion of the second address signal. The second decoder is configured to receive a second portion of the first address signal or a second portion of the second address signal to generate a second decoded signal among the plurality of decoded signals. A third decoder is configured to receive a third portion of the first address signal or a third portion of the second address signal to generate a third decoded signal among the plurality of decoded signals, and A multiplexer is configured to (i) receive a selection signal; and (ii) when the selection signal is provided in a first logic state, provide the second portion of the first address signal to the second decoder and the third portion of the first address signal to the third decoder. (iii) When the selection signal is provided in the second logic state, the second portion of the second address signal is provided to the second decoder, and the third portion of the second address signal is provided to the third decoder.

2. The memory circuit according to claim 1, wherein, The first decoder includes an AND-OR-inverting gate composed of a first AND gate, a second AND gate, and a NOR gate.

3. The memory circuit according to claim 2, wherein, The first AND gate is configured to receive the first portion of the first clock pulse signal and the first address signal, and generate a first intermediate signal; The second AND gate is configured to receive the first portion of the second pulse signal and the second address signal, and generate a second intermediate signal; and The NOR gate is configured to receive the first intermediate signal and the second intermediate signal, and generate the first decoded signal.

4. The memory circuit according to claim 1, wherein, The first logic state of the selection signal corresponds to a first operating mode, and the second logic state of the selection signal corresponds to a second operating mode.

5. The memory circuit according to claim 4, wherein, The first pulse signal is provided in the first logic state, so that the selection signal is in the first logic state, and the second pulse signal is provided in the first logic state, so that the selection signal is in the second logic state.

6. The memory circuit according to claim 1 further includes a clock generation circuit, the clock generation circuit being configured to generate the first pulse signal and the second pulse signal respectively with different timing assertions.

7. The memory circuit according to claim 6, wherein, The clock generation circuit is also configured to generate a leading second pulse signal for switching the selection signal from the first logic state to the second logic state.

8. The memory circuit according to claim 1, wherein, The word line driver includes NOR gates, NAND gates, and multiple inverters.

9. A memory circuit, comprising: A controller and a memory array operably coupled to a plurality of word line drivers, wherein the controller is configured to provide a plurality of decoding signals, the decoding signals being collectively configured to assert one of the plurality of word lines of the memory array via a respective one of the word line drivers; The controller includes: The first decoder is configured to generate a first decoded signal in the decoded signal based on a first clock pulse signal, a second pulse signal, a first part of a first address signal, and a first part of a second address signal, wherein the first address signal and the second address signal correspond to a first operating mode of the memory array and a second operating mode of the memory array, respectively. The second decoder is configured to generate a second decoded signal in the decoded signal based on a second portion of the first address signal or a second portion of the second address signal; A third decoder is configured to generate a third decoded signal in the decoded signal based on a third portion of the first address signal or a third portion of the second address signal; and A multiplexer is configured to (i) receive a selection signal having a first logic state corresponding to a first operating mode or a second logic state corresponding to a second operating mode; (ii) in response to the selection signal being equal to the first logic state, provide a second portion of the first address signal to a second decoder and provide a third portion of the first address signal to a third decoder; and (iii) in response to the selection signal being equal to the second logic state, provide a second portion of the second address signal to the second decoder and provide a third portion of the second address signal to the third decoder.

10. A method of operating a memory circuit, comprising: A selection signal is provided for transitioning between a first logic state and a second logic state, wherein the first logic state of the selection signal corresponds to a first operating mode and the second logic state of the selection signal corresponds to a second operating mode. In response to identifying the transition edge of the first pulse signal, a first combination of a first decoding signal, a second decoding signal, and a third decoding signal is provided based on a first address signal corresponding to the first operating mode; Based on the first combination of the first decoding signal to the third decoding signal, assert the first word line connected to the first memory cell, the first memory cell being configured in the first operating mode; In response to identifying a transition edge of a second pulse signal that appears after the first pulse signal, a second combination of the first decoding signal, the second decoding signal, and the third decoding signal is provided based on a second address signal corresponding to the second operating mode; as well as Based on the second combination of the first to the third decoding signals, an assertion is made about the second word line connected to the second memory cell, which is configured in the second operating mode.

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