Semiconductor structure and method of operation thereof, semiconductor device

Abstract

Embodiments of the present application provide a semiconductor structure and an operating method thereof, and a semiconductor device. The semiconductor structure includes a memory array configured to perform a first operation and a peripheral circuit coupled to the memory array. The memory array includes a memory string. A first end of the memory string is connected to a source line and a second end of the memory string is connected to a bit line. The memory string includes a plurality of memory cells and a plurality of dummy cells. The plurality of memory cells includes a first memory cell and a second memory cell. A first word line is coupled to the first memory cell and a second word line is coupled to the second memory cell. A third word line is coupled to the plurality of dummy cells. The peripheral circuit is configured to perform a first programming operation on the first memory cell, perform a second programming operation on the plurality of dummy cells, apply a first pass voltage to the second word line, apply a second pass voltage different from the first pass voltage to the third word line, and obtain a first current passing through the memory string.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its operation method, and a semiconductor device. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor structure, its operation method, and a semiconductor device.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure including a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; the plurality of memory cells include a first memory cell and a second memory cell; a first word line is coupled to the first memory cell, a second word line is coupled to the second memory cell, and a third word line is coupled to the plurality of dummy memory cells; the peripheral circuitry is configured to: perform a first programming operation on the first memory cell; perform a second programming operation on the plurality of dummy cells; apply a first through voltage to the second word line; apply a second through voltage different from the first through voltage to the third word line; and acquire a first current through the memory string.

[0005] In some embodiments, the peripheral circuit is configured such that: when the first current is less than a first preset value, the second programming operation is completed.

[0006] In some embodiments, the peripheral circuit is configured to: increase the programming voltage of the second programming operation according to the first current being greater than or equal to the first preset value, and continue to execute the second programming operation; continue to apply the first through voltage to the second word line and the second through voltage to the third word line to obtain the corresponding first current; and complete the second programming operation when the first current is less than the first preset value.

[0007] In some embodiments, the peripheral circuitry is configured to: apply a programming voltage to a first word line by applying a plurality of first step pulse voltages during the execution of a first programming operation; the difference between two adjacent first step pulse voltages is a first step long voltage; and apply a programming voltage to a third word line by applying a plurality of second step pulse voltages during the execution of a second programming operation; the difference between two adjacent second step pulse voltages is a second step long voltage; wherein the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, or the second step long voltage is less than the first step long voltage.

[0008] In some embodiments, the peripheral circuitry is further configured to: apply a read voltage to the first word line, apply a first pass voltage to the second word line, and apply a first operating voltage less than the second pass voltage to the third word line during a read operation on a memory cell coupled to the first word line, such that the plurality of dummy cells operate in the linear region.

[0009] In some embodiments, the peripheral circuitry is further configured to: perform a first programming operation, wherein a memory cell coupled to a first word line has a first threshold voltage; perform a second programming operation, wherein one of a plurality of dummy cells has a second threshold voltage; the second threshold voltage is greater than the first threshold voltage; and during a read operation performed on a memory cell coupled to the first word line, apply a read voltage to the first word line, apply a first pass voltage to the second word line, and apply a second operating voltage to the third word line; the second operating voltage is less than the first pass voltage.

[0010] In some embodiments, the peripheral circuitry is further configured to: apply a read voltage to the first word line, a third pass voltage to the second word line, and a third operating voltage to the third word line during a first read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is in a first position in the memory string; and apply a read voltage to the first word line, a fourth pass voltage to the second word line, and a third operating voltage to the third word line during a second read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is in a second position in the memory string; wherein the first position is closer to the bit line than the second position, and the third pass voltage is greater than the fourth pass voltage.

[0011] In some embodiments, the plurality of dummy cells include a bottom dummy cell located between the source line and the plurality of memory cells, or a top dummy cell located between the bit line and the plurality of memory cells.

[0012] In some embodiments, a first end of a plurality of memory strings located in the same column is connected to a source line and a second end is connected to a bit line; a first word line is coupled to a corresponding memory cell in the same column of the plurality of memory strings; the peripheral circuit is further configured to: perform a read operation on the corresponding memory cell coupled to the first word line, obtain a second current through the bit line, and obtain the result of a first operation based on the second current.

[0013] In some embodiments, the third word line includes a first portion and a plurality of second portions connected to the first portion; a first end of each second portion is connected to the gate terminal of a corresponding dummy cell; a second end of each second portion is connected to the first portion; wherein the first portion is configured to receive a second pass voltage.

[0014] Secondly, embodiments of this application provide a semiconductor structure including a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; wherein the plurality of memory cells are coupled to a plurality of first gate layers; the plurality of dummy cells are coupled to a plurality of second gate layers; the first ends of the plurality of second gate layers are respectively coupled to the plurality of dummy cells, and the second ends are in common contact and electrically connected to a connection structure; the connection structure includes a conductive material.

[0015] In some embodiments, the plurality of dummy cells include a bottom dummy cell located between the source line and the plurality of memory cells, or a top dummy cell located between the bit line and the plurality of memory cells.

[0016] In some embodiments, a first end of a plurality of memory strings located in the same column is connected to a source line and a second end is connected to a bit line; a first gate layer is coupled to a corresponding memory cell located in the same column of the plurality of memory strings.

[0017] Thirdly, embodiments of this application provide a semiconductor structure, the semiconductor structure comprising: a stacked structure including a gate layer and an insulating layer spaced apart; the stacked structure including a plurality of gate layers; the plurality of gate layers including a plurality of first gate layers and a plurality of second gate layers; a memory structure extending through the stacked structure, including a plurality of memory cells and a plurality of dummy cells; the memory cells being coupled to the first gate layers; the dummy cells being coupled to the second gate layers; and a connection structure including a conductive material, contacting and electrically connecting to the plurality of second gate layers.

[0018] In some embodiments, the connection structure includes: a first connection line located on the stacked structure; a plurality of first contact structures, each having a first end extending through and connected to a second gate layer, and a second end commonly connected to the first connection line; or, a second contact structure having a first end extending through at least a portion of the plurality of second gate layers and connected to the plurality of second gate layers, and a second end connected to the first connection line.

[0019] In some embodiments, the plurality of second gate layers include a bottom second gate layer located at the bottom of the stacked structure, or a top second gate layer located at the top of the stacked structure.

[0020] Fourthly, embodiments of this application provide a semiconductor device comprising: one or more semiconductor structures of any one of the first aspects, any one of the second aspects, or any one of the third aspects; and a processing circuit bonded to the semiconductor structure and configured to convert analog computation information obtained by performing a first operation on the semiconductor structure into digital information, and to perform a second operation on the digital information; the analog computation information includes a first current passing through a memory string of the semiconductor structure.

[0021] In some embodiments, the processing circuit includes an analog-to-digital converter circuit and a data processing circuit; the analog-to-digital converter circuit is configured to convert analog calculation information into digital information; and the data processing circuit is configured to perform a second operation on the digital information.

[0022] In some embodiments, the processing circuit further includes a first interface circuit and a controller; the first interface circuit is configured to output the result of the second operation performed by the digital processing circuit to an external device; the controller is configured to control the semiconductor structure to perform the first operation.

[0023] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0024] In some embodiments, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0025] Fifthly, embodiments of this application provide an operation method for a semiconductor structure, the operation method comprising: performing a first programming operation on a memory cell coupled to a first word line among a plurality of memory cells of the semiconductor structure; performing a second programming operation on a plurality of dummy cells of the semiconductor structure; applying a first through voltage to a second word line; applying a second through voltage different from the first through voltage to a third word line; and acquiring a first current through a memory string; wherein the semiconductor structure includes a memory array configured to perform the first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; the plurality of memory cells include a first memory cell and a second memory cell; a first word line is coupled to a first memory cell, a second word line is coupled to a second memory cell; and a third word line is coupled to a plurality of dummy memory cells.

[0026] In some embodiments, the operation method includes: when the first current is less than a first preset value, completing the second programming operation.

[0027] In some embodiments, the operation method includes: increasing the programming voltage of the second programming operation according to the first current being greater than or equal to a first preset value, and continuing to perform the second programming operation; and continuing to apply a first through voltage to the second word line and a second through voltage to the third word line to obtain a corresponding first current; and completing the second programming operation when the first current is less than the first preset value.

[0028] In some embodiments, the operation method includes: during the execution of a first programming operation, applying a programming voltage to a first word line in a manner that applies a plurality of first step pulse voltages; the difference between two adjacent first step pulse voltages is a first step long voltage; during the execution of a second programming operation, applying a programming voltage to a third word line in a manner that applies a plurality of second step pulse voltages; the difference between two adjacent second step pulse voltages is a second step long voltage; wherein the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, or the second step long voltage is less than the first step long voltage.

[0029] In some embodiments, the operation method further includes: during a read operation on a memory cell coupled to a first word line, applying a read voltage to the first word line, applying a first pass voltage to the second word line, and applying a first operating voltage less than the second pass voltage to the third word line, such that the plurality of dummy cells operate in the linear region.

[0030] In some embodiments, the operation method further includes: performing a first programming operation, wherein a memory cell coupled to a first word line has a first threshold voltage; performing a second programming operation, wherein one of a plurality of dummy cells has a second threshold voltage; the second threshold voltage is greater than the first threshold voltage; and during a read operation performed on a memory cell coupled to the first word line, applying a read voltage to the first word line, applying a first pass voltage to the second word line, and applying a second operating voltage to the third word line; the second operating voltage is less than the first pass voltage.

[0031] In some embodiments, the operation method further includes: applying a read voltage to the first word line, a third pass voltage to the second word line, and a third operating voltage to the third word line during a first read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is located at a first position in the memory string; applying a read voltage to the first word line, a fourth pass voltage to the second word line, and a third operating voltage to the third word line during a second read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is located at a second position in the memory string; wherein the first position is closer to the bit line than the second position, and the third pass voltage is greater than the fourth pass voltage.

[0032] In some embodiments, the plurality of dummy cells include a bottom dummy cell located between the source line and the plurality of memory cells, or a top dummy cell located between the bit line and the plurality of memory cells.

[0033] In some embodiments, the operation method further includes: performing a read operation on a corresponding memory cell located in the same column that is coupled to the first word line, obtaining a second current through the bit line, and determining the result of the first operation based on the second current; wherein, a first end of a plurality of memory strings located in the same column is connected to a source line and a second end is connected to a bit line; the first word line is coupled to a corresponding memory cell located in the same column of the plurality of memory strings.

[0034] In some embodiments, the third word line includes a first portion and a plurality of second portions connected to the first portion; a first end of each second portion is connected to the gate terminal of a corresponding dummy cell; a second end of each second portion is connected to the first portion; wherein the first portion is configured to receive a second pass voltage.

[0035] In various embodiments of this application, the memory string includes dummy units and the number of dummy units is multiple. The dummy units are programmed to a non-erasable programmed state. When the memory string is in the on state, the equivalent resistance corresponding to the dummy unit can avoid or reduce the influence of the equivalent resistance corresponding to the memory unit coupled to the non-selected word line on the current on the bit line. When the selected word line is located in different positions, the current change on the corresponding bit line is zero or small, which can improve the current consistency on the bit line during the execution of the first operation and reduce or clear the error rate during the execution of the first operation. Attached Figure Description

[0036] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0037] Figure 2 A schematic diagram of a semiconductor structure including peripheral circuits and a memory array provided for embodiments of this application. Figure 1 ;

[0038] Figure 3 A schematic diagram of a semiconductor structure including peripheral circuits and a memory array provided for embodiments of this application. Figure 2 ;

[0039] Figure 4 A schematic diagram of a semiconductor structure including peripheral circuits and a memory array provided for embodiments of this application. Figure 3 ;

[0040] Figure 5 A cross-sectional schematic diagram of a storage array including memory strings provided for an embodiment of this application;

[0041] Figure 6 A schematic diagram showing the distribution of a memory array with a semiconductor structure provided in an embodiment of this application;

[0042] Figure 7 A schematic diagram of the distribution of storage blocks in a storage array provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of the distribution of memory strings for a storage block provided in an embodiment of this application;

[0044] Figure 9A A schematic diagram of a memory block provided for embodiments of this application, showing the storage weight of the memory cell corresponding to the target word line, the input voltage input by the top selected gate line, and the output current output by the bit line;

[0045] Figure 9B A schematic diagram illustrating the binary multiplication operation formed by the weights stored in the memory cells of the memory string provided in this application embodiment and the input voltage of the corresponding memory string top select gate line input;

[0046] Figure 9C A schematic diagram showing the weights stored in the storage unit corresponding to the read target word line provided in the embodiments of this application;

[0047] Figure 10 This is a schematic diagram of multiple memory strings coupled to bit lines, provided in an embodiment of this application.

[0048] Figure 11 This is one of the schematic diagrams of a memory string provided in an embodiment of this application, where the first end is connected to the source line and the second end is connected to the bit line;

[0049] Figure 12 for Figure 11 A schematic diagram of the equivalent circuit of the memory string;

[0050] Figure 13 for Figure 11 A schematic diagram of the current-voltage characteristic curves of the target word line of the memory string at different positions;

[0051] Figure 14 A second schematic diagram of a memory string with its first end connected to the source line and its second end connected to the bit line, provided as an embodiment of this application;

[0052] Figure 15 for Figure 14 A schematic diagram of the equivalent circuit of the memory string;

[0053] Figure 16 for Figure 14 A schematic diagram of the current-voltage characteristic curves of the target word line of the memory string at different positions;

[0054] Figure 17 A third schematic diagram of a memory string whose first end is connected to the source line and the second end is connected to the bit line, provided as an embodiment of this application;

[0055] Figure 18 for Figure 17 A schematic diagram of the current-voltage characteristic curves of the dummy word lines of the memory string in different programming states;

[0056] Figure 19 To Figure 17 A flowchart illustrating the programming process of virtual cells in a memory string;

[0057] Figure 20A To Figure 17 A waveform diagram illustrating the erasure operation of the memory cells and dummy cells in the memory string;

[0058] Figure 20B for Figure 20A A waveform diagram verifying the erasure operation;

[0059] Figure 20C To Figure 17 A waveform diagram illustrating programming operations performed on the storage units of a memory string;

[0060] Figure 20D for Figure 20C A waveform diagram illustrating the verification of programming operations;

[0061] Figure 20E To Figure 17 A waveform diagram illustrating the programming operation performed on the virtual cells of the memory string;

[0062] Figure 20F for Figure 20E A waveform diagram illustrating the verification of the programming operation;

[0063] Figure 20G To Figure 17 A waveform diagram illustrating the read operation of a memory string's storage cells;

[0064] Figure 20H A schematic diagram comparing the threshold voltage distribution of the memory cell in erase / programmable state and the threshold voltage distribution of the dummy cell in programming state, as provided in the embodiments of this application;

[0065] Figure 21 Fourth schematic diagram of a memory string with its first end connected to the source line and its second end connected to the bit line, provided for an embodiment of this application;

[0066] Figure 22 for Figure 21 A schematic diagram of the current-voltage characteristic curves of the dummy word lines of the memory string in different programming states;

[0067] Figure 23 To Figure 21 A flowchart illustrating the programming process of virtual cells in a memory string;

[0068] Figure 24 A schematic diagram of some memory strings whose first end is connected to the source line and the second end is connected to the bit line, provided for embodiments of this application;

[0069] Figure 25 A schematic diagram showing the common connection of multiple dummy word lines coupled to multiple dummy cells to a memory string in a connection structure, as provided in an embodiment of this application.

[0070] Figure 26 One of the schematic cross-sectional views of a semiconductor structure including a connection structure provided in this application embodiment;

[0071] Figure 27 A second schematic cross-sectional view of a semiconductor structure including a connection structure provided for an embodiment of this application;

[0072] Figure 28 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0073] Figure 29 A schematic diagram of an exemplary system with a storage computing device provided in the embodiments of this application;

[0074] Figure 30 This is a flowchart illustrating the operation method of the semiconductor structure provided in the embodiments of this application. Detailed Implementation

[0075] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0077] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0078] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0079] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0081] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0082] With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, the Computing in Memory (CIM) chip architecture has emerged. Its basic idea is to embed computing functions into memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computing performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0083] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will provide a detailed introduction to NAND flash memory.

[0084] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application. (Reference) Figure 1 The semiconductor structure 300 includes a memory array 301 configured to perform a first operation and peripheral circuitry 302 coupled to the memory array 301. In some embodiments, the semiconductor structure includes a first semiconductor structure stacked together. Figure 1 (not shown) and second semiconductor structure ( Figure 1 (Not shown), the first semiconductor structure may include a memory array and some peripheral circuitry, and the second semiconductor structure may include another portion of the peripheral circuitry. That is, a portion of the peripheral circuitry is formed in the first semiconductor structure, and another portion is formed in the second semiconductor structure. For example, in this embodiment, a page buffer, for instance, may be formed in the first semiconductor structure. In other embodiments, the semiconductor structure includes a stacked first semiconductor structure and a second semiconductor structure, with the memory array formed in the first semiconductor structure and the peripheral circuitry formed in the second semiconductor structure.

[0085] Figure 2 A schematic diagram of a semiconductor structure including peripheral circuits and a memory array provided for embodiments of this application. Figure 1 . refer to Figure 1 and Figure 2The peripheral circuitry 302 may include control logic 512, a digital-to-analog converter 501 coupled to the control logic 512 and the memory array 301, and an analog-to-digital converter 502 coupled to the memory array 301 and the control logic 512. When performing the first operation using the semiconductor structure, the digital-to-analog converter 501 can convert the digital signal into a voltage signal required by the memory array 301 in the semiconductor structure. The analog-to-digital converter 502 can convert the current signal output by the memory array 301 into a digital signal. The control logic 512 may be coupled to the peripheral circuitry and configured to control the operation of the peripheral circuitry. The control logic 512 can also be used to receive input data sent by external devices. Here, the digital-to-analog converter 501 is a one-bit digital-to-analog converter (DAC), and the analog-to-digital converter 502 is a one-bit analog-to-digital converter (ADC).

[0086] Figure 3 A schematic diagram of a semiconductor structure including peripheral circuits and a memory array provided for embodiments of this application. Figure 2 . refer to Figure 1 , Figure 2 and Figure 3 ,remove Figure 2 In addition to the circuit structure shown, the peripheral circuitry 302 may also include a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a register 514, and a data bus 518. It should be understood that in some examples, it may also include... Figure 3 as well as Figure 3 Additional peripheral circuitry not shown.

[0087] like Figure 3 As shown, control logic 512 can be coupled to other circuit structures in the peripheral circuits described above, excluding control logic 512, and is configured to control the operation of the peripheral circuits. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0088] like Figure 3 and Figure 4As shown, the page buffer / sensor amplifier 504 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 512. In one example, the page buffer / sensor amplifier 504 can store programming data (write data) to be programmed into memory cells 306 of the memory array 301. In another example, the page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cells 306 coupled to target word lines 318. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and to select one or more NAND memory strings 308 by applying a bit line voltage obtained from the voltage generator 510.

[0089] like Figure 3 and Figure 4 As shown, the line decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and to select / deselect word lines 318 of memory blocks 304. The line decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages obtained from voltage generator 510. In some embodiments, the line decoder / word line driver 508 can also select / deselect and drive bottom select gate (BSG) 315 and top select gate (TSG) 313. As described in detail below, the line decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more target word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to acquire word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc., input voltage), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0090] Figure 4 A schematic diagram of a semiconductor structure including peripheral circuits and a memory array provided for embodiments of this application. Figure 3 . refer to Figure 1 and Figure 4The semiconductor structure 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory cells 306 are NAND memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically. In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0091] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0092] like Figure 4As shown, each memory string 308 may include a bottom select transistor 310 at its source end and a top select transistor 312 at its drain end. The bottom select transistor 310 and the top select transistor 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the source ends of the memory strings 308 in the same memory block 304 may be coupled via a common source line (CSL) 314. In other words, all memory strings 308 in the same memory block 304 have an array common source (ACS) (also referred to herein as a source line / common source line). According to some embodiments, the top select transistor 312 of each memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top selection transistor 312) or a deselection voltage (e.g., 0V) to the corresponding top selection transistor 312 via one or more top selection gate lines 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom selection transistor 310) or a deselection voltage (e.g., 0V) to the corresponding bottom selection transistor 310 via one or more bottom selection gate lines 315.

[0093] like Figure 4 As shown, the memory string 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase a memory cell 306 in a selected memory block, an erase voltage bias can be used to couple the common source line 314 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select a row of memory cells 306 for read or program operations.

[0094] Figure 5 This is a cross-sectional schematic diagram of a storage array including memory strings, provided for an embodiment of this application. (See attached diagram.) Figure 5As shown, the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0095] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select gate line, and the gate layer 411 extending laterally between the top select gate line and the bottom select gate line may serve as a word line.

[0096] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0097] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0098] Return to reference Figure 4 The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, bottom select gate line 315, and top select gate line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, bottom select gate line 315, and top select gate line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology.

[0099] Figure 6 This is a schematic diagram showing the distribution of a memory array with a semiconductor structure provided in an embodiment of this application. (Reference) Figure 6 Here, a three-dimensional NAND flash memory semiconductor structure is used as an example for explanation. Here and below, the first direction is parallel to the direction in which the word lines extend; the second direction is parallel to the direction in which the bit lines extend, and the first and second directions intersect (e.g., are perpendicular); the third direction is parallel to the direction in which the memory string extends. Exemplarily, the first and second directions are perpendicular, and the third direction is perpendicular to both the first and second directions. The first direction can be the X direction in the figures, the second direction can be the Y direction in the figures, and the third direction can be the Z direction in the figures.

[0100] like Figure 6 As shown, a storage array may include multiple storage planes. For example, a storage array may include storage planes Plane0, Plane1, Plane2, and Plane3, for a total of four storage planes. Each storage plane includes multiple storage cells, and each storage cell includes multiple storage blocks. For example, storage plane Plane0 includes storage blocks Block0, Block1, ..., BlockN-1, for a total of N storage blocks, where N is a natural number. In optional embodiments, the number of storage planes in the storage array may be less than four (e.g., two) or more than four (e.g., five).

[0101] Figure 7 This is a schematic diagram showing the distribution of storage blocks in a storage array provided in an embodiment of this application. (Reference) Figure 7The memory array consists of several rows of parallel, staggered memory strings (understand as rows of memory strings arranged along the row direction) parallel to the gate line slits (GLS). Every four rows of memory strings are separated by gate line slits and select gate line slits. Each memory string row includes multiple memory strings arranged along the X direction. Figure 7 The diagram shows one memory cell in each memory string, with the remaining memory cells arranged along the Z-direction. The select gate isolation structure here can be a top select gate isolation structure (TSG CUT), which divides the top select gate (TSG) into multiple top select gate lines. The select gate isolation structure can also be a bottom select gate isolation structure (BSG CUT). Figure 7 (Not shown), the bottom selected gate isolation structure BSG CUT will cut the bottom selected gate BSG ( Figure 7 (Not shown) is divided into multiple bottom select gate lines. The gate isolation structure may include a first gate isolation structure GLS1 and a second gate isolation structure GLS2. The first gate isolation structure GLS1 divides the memory array into multiple memory blocks, and the multiple second gate isolation structures GLS2 can divide the memory blocks into multiple finger memory regions. A select gate isolation structure placed in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. In practical applications, the number of finger memory regions contained in a memory block can be adjusted according to the actual situation, such as 2, 3, 4, 5, etc. In practical applications, the number of finger memory chips contained in a memory block can be adjusted according to the actual situation, such as 2, 4, 6, 8, 10, 12, 14, 16, etc. Figure 7 Only one storage block of the memory is shown as an example, but the memory includes multiple such blocks. Figure 7 The memory blocks shown are separated by a first gate isolation structure GLS1, and multiple memory blocks can be arranged along the Y direction.

[0102] It should be noted that, Figure 7 The number of memory rows between the gate isolation structure and the selected gate isolation structure given is merely an example and is not intended to limit the number of memory rows contained in a single memory region of the three-dimensional NAND memory in this application. In practical applications, the number of memory rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0103] Figure 8 This is a schematic diagram showing the distribution of memory strings in a storage array provided in an embodiment of this application. Figure 8 It can be understood as Figure 7 The diagram shows an enlarged view of region PZ, illustrating the bit lines and the second end of the memory string connected to the bit lines. (See diagram for example.) Figure 8 As shown, the second gate isolation structure GLS2 and the top selected gate isolation structure TSG CUT divide the memory block into multiple memory chips, such as 6 memory chips. Figure 8 The diagram shows four memory chips, namely memory chip String0, memory chip String1, memory chip String2, and memory chip String3. Different memory chips can be selected through their respective top selection gates TSG. That is, memory chips String0, String1, String2, and String3 can be selected / deselected through top selection gates TSG0, TSG1, TSG2, and TSG3, respectively.

[0104] like Figure 8 As shown, the first end of the memory string in the memory array is connected to the source line (or the array common source), and the second end is connected to the bit line. A memory chip includes multiple memory strings Str0, and the second ends of these multiple memory strings Str0 are respectively connected to the corresponding bit lines. For example, N different memory strings Str0 in the memory chip are respectively connected to bit lines BL0 to BLN-1. Along the extension direction of the bit lines, each bit line is connected to a memory string in a different memory chip String0. For example, bit line BL0 is connected to the second ends of memory strings Str0 of memory chip String0, Str1 of memory chip String1, Str2 of memory chip String2, and Str3 of memory chip String3.

[0105] Figure 9A This is a schematic diagram of a memory block provided in an embodiment of the present application, in which the memory cell corresponding to the target word line stores the weight, the top select gate line inputs the input voltage, and the bit line outputs the output current. Figure 9B This is a schematic diagram illustrating a binary multiplication operation between the weights stored in the memory cells of the memory string provided in this application embodiment and the input voltage of the corresponding memory string top select gate line input. Figure 9C This is a schematic diagram of the weights stored in the storage unit corresponding to the read target word line provided in the embodiments of this application. Figure 10 This is a schematic diagram of multiple memory strings coupled to bit lines, provided in an embodiment of this application. It should be noted that... Figure 9A and Figure 10 The number of bit lines, the number of memory strings coupled to each bit line, and the number of memory cells in each memory string shown are merely examples, and this application does not limit the specific number of each structure.

[0106] The following example, using the bit line as the analog signal output terminal, illustrates the specific process of the first operation.

[0107] like Figure 9A As shown, in the first operation stage using the memory array, the peripheral circuit is configured to apply a first read voltage V to the target word line WLn coupled to the target memory block. rd A corresponding input voltage is applied to each of the multiple top select gate lines coupled to the target memory block. For example, an input voltage V can be applied to the top select gate lines TSG0, TSG1, and TSG2 coupled to the target memory block. in0 V in1 V in2 Apply a pass voltage V to the non-target word line coupled to the target memory block. pass For example, a voltage V can be applied to word line WLn+1. pass A pass voltage V is applied to the bottom select gate line coupled to the target memory block by connecting the memory cell that is not coupled to the target word line. BSG For example, a pass voltage V can be applied to the bottom select gate line BSG. BSG The bottom selection transistor is turned on. Analog calculation information can be obtained by sensing the current on the bit lines coupled to the target memory block, for example, sensing the currents I0, I1, and I2 on bit lines BL0, BL1, and BL2 can obtain analog calculation information.

[0108] like Figure 9B and Figure 9C As shown, the input voltage V received by the top select gate line TSG0, which is coupled to the target memory block, is... in0 Input voltage V in0 This turns on the top selection transistor, and the input voltage V in0 The corresponding element is logic "1", and the input voltage is V. in0 This causes the top selection transistor to turn off, and the input voltage V in0 The corresponding element is logic "0". The weight w stored in the target memory cell of the memory string coupled to the top select gate line TSG0. 00 The read voltage V received by the target word line coupled to the target memory cell rd Read voltage V rd This enables the target storage unit to conduct, and the read weight w 00 For logic "1", read voltage V rd Turn off the target storage unit and read the weight w. 00 It is logic "0".

[0109] Continue to refer to Figure 9A By sensing the current I0 on the bit line BL0 and converting the current I0, the input voltage V can be obtained. in0 Corresponding elements and weights w 00 The product of the input voltage V in1Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The product of these three is the sum of the current I0 on the sensing bit line BL0, which is I0 = V. in0 *w 00 +V in1 *w 10 +V in2 *w 20 Similarly, the current I1 = V on the sensing bit line BL1 can be obtained. in0 *w 01 +V in1 *w 11 +V in2 *w 21 The current I2 = V on the sensing bit line BL2 in0 *w 02 +V in1 *w 12 +V in2 *w 22 Thus, the current I on the sensing bit line Bly... y It satisfies the following formula (1):

[0110] I y =∑V inx *w xy =V in0 *w 00 +V in1 *w 10 +…V inx *w x0 (1)

[0111] In formula (1), (x+1) represents the number of memory strings connected to a single bit line in the target memory block for the first operation, and (y+1) represents the number of bit lines in the target memory block for the first operation. In some embodiments, the first operation includes a multiply-accumulate operation.

[0112] like Figure 10As shown, in some embodiments, taking a target memory block comprising eight memory strings (memory strings Str0 to Str7) coupled to bit line BL0 as an example, four of the eight memory cells coupled to the target word line WLn are in a first memory state (erase state E), and the other four are in a second memory state (programming state P). Input data can be input from the eight top select gate lines TSG0 to TSG7. Specifically, the input data can be an input vector comprising eight elements, which may include five "1"s and three "0"s. A digital-to-analog converter can convert each element of the input vector into a corresponding voltage signal, and a voltage generator can convert the voltage signal into an input voltage to be applied to the top select gate line. The input voltage is then transmitted to the top select gate line via a driver coupled to the top select gate line. Specifically, the eight input voltages can be applied to the eight top select gate lines simultaneously. The input voltage corresponding to "1" includes V... in0 V in1 V in4 V in5 and V in6 This allows the top-select transistors coupled to the top-select gate lines TSG0, TSG1, TSG4, TSG5, and TSG6 to be turned on, respectively. The input voltages corresponding to "0" include V. in2 V in3 V in7 This allows the top-select transistors coupled to the top-select gate lines TSG2, TSG3, and TSG7 to be turned off, respectively.

[0113] like Figure 10As shown, in some embodiments, the current I0 on bit line BL0 is the sum of the output currents of the eight memory strings coupled to bit line BL0. The input voltage on the top select gate line coupled to memory strings Str0, Str1, Str4, Str5 and Str6 causes the top select transistor coupled to the top select gate lines TSG0, TSG1, TSG4, TSG5 and TSG6 to be in the on state. The eight memory cells in memory strings Str0 to Str7 coupled to the target word line WLn have a first memory state (erase state E), a second memory state (programmable state P), an erase state E, a programmable state P, an erase state E, an erase state E, a programmable state P and a programmable state P, respectively. The input voltage on the top select gate lines coupled to memory strings Str0, Str4, and Str5 causes the top select transistors coupled to the top select gate lines TSG0, TSG4, and TSG5 to be in the on state. The memory cells in memory strings Str0, Str4, and Str5 coupled to the target word line WLn have a first memory state (erasure state E). Therefore, memory strings Str0, Str4, and Str5 are turned on and can generate a current greater than or equal to a preset current. The current I0 on the bit line BL0 is approximately equal to the sum of the output currents of memory strings Str0, Str4, and Str5. The multiple of current I0 relative to the current generated by any one of the memory strings Str0, Str4, and Str5 is approximately equal to 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory strings coupled to the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3. Here, the result "3" is represented in decimal, but it can also be represented in binary, for example, by a two-digit binary number "10".

[0114] Based on the specific example above, when there are y memory strings coupled to bit line BLx in the target memory block, the y elements corresponding to the input voltages input by the y first selection lines are α0, α1...α... y-1 The weights stored in the y memory cells coupled to the target word line WLn are w0, w1, ..., w1, respectively. y-1 Then, the current I on the bit line Bly y The equivalent analog calculation information for the output current that is greater than or equal to the preset current can satisfy Formula I. y =α 0* w0+α 1* w1+……+α y-1* w y-1 .

[0115] In some embodiments, the peripheral circuitry can be configured to apply a first read voltage V to the target word lines coupled to each of the plurality of memory blocks of the memory bank. rd Apply a pass voltage V to non-target word lines in multiple memory banks. pass A corresponding input voltage V is applied to each of the multiple top select gate lines coupled to the multiple memory blocks of the memory bank. in0 ~V inN ; Sensing the current I0~I on the bit lines coupled to multiple memory blocks of the memory bank. y Specifically, a first read voltage V can be applied simultaneously to the target word lines coupled to each of multiple memory blocks (Block0 to BlockN) in the memory bank. rd Simultaneously, a corresponding input voltage V is applied to the multiple top select gate lines coupled to each of the multiple memory blocks Block0 to BlockN. in0 ~V inN It senses the current on the bit lines coupled to multiple memory blocks Block0 to BlockN, and the currents I0 to Iy on the bit lines BL0 to Bly. y This refers to the simulated computation information obtained after performing the first operation on all memory strings coupled to this bit line. Therefore, multiple memory blocks can perform the first operation in parallel, thereby further improving the computational efficiency and power of the semiconductor device.

[0116] Figure 11 This is one of the schematic diagrams of a memory string provided in an embodiment of this application, where the first end is connected to the source line and the second end is connected to the bit line. Figure 12 for Figure 11 One of the equivalent circuit diagrams of a memory string. Figure 13 for Figure 11 One of the schematic diagrams of the current-voltage characteristic curves of a memory string with the target word line located at different positions.

[0117] refer to Figure 11 The memory string comprises multiple memory cells, with (n+1) cells, where n is a natural number greater than 1. Each memory cell is coupled to a corresponding word line WL0, WL1, WL2, WL3, ..., word line WLn-2, ​​WLn-1, and WLn. The first end of each memory cell is coupled to the source line ACS via a bottom select transistor, and the second end is coupled to the bit line BL via a top select transistor. The gate of the top select transistor is connected to the top select gate line TSG, and the gate of the bottom select transistor is connected to the bottom select gate line BSG.

[0118] refer to Figure 12When the memory string is in the ON state, the equivalent resistance corresponding to the memory cell located between the selected memory cell (the memory cell coupled to the selected word line selWL) and the source line ACS is the first equivalent resistance R. S The equivalent resistance corresponding to the memory cell located between the selected memory cell and the bit line BL is the second equivalent resistance R. D It should be noted that, in the following description, the equivalent circuit diagram of the memory string located between the bit line BL and the source line ACS can ignore the influence of the equivalent resistance of the bottom select transistor and the top select transistor, or can be considered as constant values.

[0119] refer to Figure 13 When the memory string is in the ON state, the current I on the bit line BL is d The gate voltage V received by the selected word line selWL g The characteristic curves are as follows: Curve line 0 can be understood as the current-voltage characteristic curve measured when all memory cells in the memory string are in the erase state. Curve line 1 can be understood as the current-voltage characteristic curve measured when at least some memory cells in the memory string are in the programming state, where the selected word line selWL is the word line closest to the source line ACS, for example, word line WL2. Curve line 2 can be understood as the current-voltage characteristic curve measured when at least some memory cells in the memory string are in the programming state, where the selected word line selWL is the word line closest to the bit line BL, for example, word line WLn-2.

[0120] Reference Figure 11 , Figure 12 and Figure 13 When the memory string is in the ON state (e.g., when the selected word line is located at different positions, the same pass voltage is applied to all non-selected word lines), compared to the selected word line selWL being a word line close to bit line BL (e.g., the selected word line selWL is word line WLn-2, ​​corresponding to reference...), Figure 13 The curve line2), select word line selWL as the word line closest to the source line ACS (for example, select word line selWL as word line WL2, see reference). Figure 13 When the curve is line 1), the first equivalent resistance R S With the second equivalent resistance R D The sum is relatively small, and the current I on the bit line BL is relatively small. d Larger. For example... Figure 13 As shown, the current difference ΔI between curves line1 and line2 in the linear region LR0 The current difference ΔI between curves line1 and line2 in the saturation region is relatively large. SR0 Larger.

[0121] Because the memory string is configured to perform the first operation, it needs to sense the current on the bit lines and has high requirements for the current changes on the bit line BL (e.g., requiring small current changes). When the target word line (selected word line) is located in different positions, the equivalent resistance of the memory cells coupled to the non-selected word lines is different, which has a significant impact on the current changes on the bit lines. Since the target word line (selected word line) is located in different positions, the current changes on the corresponding bit lines are large, which is detrimental to improving the current consistency on the bit lines during the execution of the first operation and to reducing or clearing the error rate during the execution of the first operation.

[0122] In view of the above, embodiments of this application provide a semiconductor structure, its operation method, and a semiconductor device.

[0123] In a first aspect, embodiments of this application provide a semiconductor structure including a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; the plurality of memory cells include a first memory cell and a second memory cell; a first word line is coupled to the first memory cell, a second word line is coupled to the second memory cell, and a third word line is coupled to the plurality of dummy memory cells; the peripheral circuitry is configured to: perform a first programming operation on the first memory cell; perform a second programming operation on the plurality of dummy cells; apply a first through voltage to the second word line; apply a second through voltage different from the first through voltage to the third word line; and acquire a first current through the memory string.

[0124] In this embodiment, the memory string includes multiple dummy units, and the dummy units are programmed to a non-erasable programmed state. When the memory string is in the on state, the equivalent resistance corresponding to the dummy unit can avoid or reduce the influence of the equivalent resistance corresponding to the memory unit coupled to the non-selected word line on the current on the bit line. When the selected word line is located in different positions, the current change on the corresponding bit line is zero or small, which can improve the consistency of the current on the bit line during the execution of the first operation and reduce or clear the error rate during the execution of the first operation.

[0125] Here and below, the semiconductor structure of the memory array and its peripheral circuitry can be referenced from the above. Figures 1 to 10The relevant descriptions will be understood and will not be repeated here. Specifically, the semiconductor structure is configured to perform the first operation, which requires replacing some storage cells in the memory string with dummy cells, and there are multiple dummy cells. Furthermore, the dummy cells can be programmed to a non-erasable programmed state. This can be done through software settings, where some storage cells in the memory string are set as dummy cells not used for storing weights, or through hardware settings during the semiconductor structure manufacturing process, where dummy cells not used for storing weights are set in the memory string.

[0126] Here and below, the first word line can be understood as the target word line or selected word line among multiple word lines coupled to multiple memory cells, and the first memory cell can be understood as the memory cell coupled to the target word line or selected word line. The second word line can be connected as a non-target word line or non-selected word line among multiple word lines coupled to multiple memory cells, and the second memory cell can be understood as the memory cell coupled to the non-target word line or non-selected word line. The third word line can be understood as including multiple dummy word lines coupled to multiple dummy cells, each dummy word line having a first end connected to the gate of a corresponding dummy cell and a second end coupled to a corresponding line decoder / word line driver, each of the multiple dummy word lines being able to independently receive driving circuitry (e.g., a second pass voltage); or, the third word line can be understood as including a first portion and multiple second portions connected to the first portion; the first end of each second portion is connected to the gate of a corresponding dummy cell; the second ends of each second portion are commonly connected to the first end of the first portion; wherein the second ends of the first portion are connected to the corresponding line decoder / word line driver, and the second ends of the first portion are configured to receive driving circuitry (e.g., a second pass voltage).

[0127] Figure 14 This is a second schematic diagram of a memory string whose first end is connected to the source line and the second end is connected to the bit line, as provided in an embodiment of this application. Figure 15 for Figure 14 The equivalent circuit diagram of the memory string. Figure 16 for Figure 14 This is a schematic diagram showing the current-voltage characteristic curves of the target word line of the memory string at different locations. It should be noted that... Figure 14 The memory string shown can be understood as... Figure 11 Two or more memory cells in the memory string shown are set as dummy cells that are not used for storing weights, and the word lines coupled to the dummy cells are dummy word lines.

[0128] refer to Figure 14The memory string comprises multiple memory cells and multiple dummy cells. The number of memory cells is (n-2), where n is a natural number greater than 2. Each memory cell is coupled to a corresponding word line WL3, ..., word line WLn-2, ​​word line WLn-1, and word line WLn. The number of dummy cells is 3, and each dummy cell is coupled to a corresponding dummy word line dumWL0, dumWL1, and dumWL2. The memory cells and dummy cells are coupled to the bit line BL via a top select transistor and to the source line ACS via a bottom select transistor. The gate of the top select transistor is connected to the top select gate line TSG, and the gate of the bottom select transistor is connected to the bottom select gate line BSG.

[0129] refer to Figure 15 When the memory string is in the ON state, the equivalent resistance of the memory cell located between the selected memory cell (the memory cell coupled to the selected word line selWL) and the source line ACS is the first equivalent resistance R. S1 The equivalent resistance corresponding to the dummy cell located between the selected memory cell and the source line ACS is the third equivalent resistance R. dum1 The equivalent resistance corresponding to the memory cell located between the selected memory cell and the bit line BL is the second equivalent resistance R. D1 .

[0130] refer to Figure 16 When the memory string is in the ON state, the current I on the bit line BL is... d The gate voltage V received by the selected word line selWL g The current-voltage characteristic curves are shown below. Curve line 0 can be understood as the current-voltage characteristic curve measured when all memory cells in the memory string are in the erase state. Curve line 1 can be understood as the current-voltage characteristic curve measured when at least some memory cells in the memory string are in the programming state, where the selected word line selWL is the word line closest to the source line ACS, for example, word line WL2. Curve line 2 can be understood as the current-voltage characteristic curve measured when at least some memory cells in the memory string are in the programming state, where the selected word line selWL is the word line closest to the bit line BL, for example, word line WLn-2.

[0131] Reference Figure 14 , Figure 15 and Figure 16 Compared to Figure 13 The current difference ΔI in the linear region shown LR0 , Figure 16 The current difference ΔI between curves line1 and line2 in the linear region is shown. LR1 Smaller, i.e., current difference ΔI LR1 Less than the current difference ΔILR0 Compared to Figure 13 The current difference ΔI in the linear region shown SR0 , Figure 16 The current difference ΔI between curves line1 and line2 in the saturation region is shown. SR1 Smaller, i.e., current difference ΔI SR1 Less than the current difference ΔI SR0 .

[0132] Figure 17 This is the third schematic diagram of a memory string whose first end is connected to the source line and the second end is connected to the bit line, as provided in the embodiments of this application. Figure 18 for Figure 17 This is a schematic diagram showing the current-voltage characteristic curves of the dummy word lines of the memory string in different programming states. It should be noted that... Figure 17 The memory string shown can be understood as Figure 14 The memory strings shown here and below, for ease of description, are compared to... Figure 14 The memory string shown, Figure 17 The word lines coupled to the memory cells shown are numbered sequentially as word line WL0, word line WL1, ..., word line WLn-1 and word line WLn. Figure 17 The dummy word lines coupled to the dummy units shown are numbered sequentially as dummy word line dumWL0, dumWL1, ...

[0133] refer to Figure 17 The memory string has its first end connected to the source line ACS and its second end connected to the bit line BL. The memory string includes multiple memory cells and multiple dummy cells. The number of memory cells is (n+1), where n is a natural number. Each memory cell is coupled to a corresponding word line WL0, word line WL1, ..., word line WLn-2, ​​word line WLn-1, and word line WLn. The number of dummy cells is 3, and each dummy cell is coupled to a corresponding dummy word line dumWL0, dummy word line dumWL1, and dummy word line dumWL2. In an optional embodiment, the number of dummy cells can be 2 or greater than 3 (e.g., 4, 5, or 6). Thus, setting a larger number of dummy cells can improve the current consistency on the bit lines during the execution of the first operation, reducing or clearing the error rate during the execution of the first operation. Correspondingly, setting a larger number of dummy cells will also reduce the storage capacity of the semiconductor structure. A trade-off needs to be struck between current consistency and storage capacity, and an appropriate number of dummy cells, such as 2, 4, or 6, should be set.

[0134] refer to Figure 18 When the memory string is in the ON state, the current I on the bit line BL is... d The gate voltage V received by multiple dummy word lines dumWLg The current-voltage characteristic curves are shown. Curve line 0 can be understood as the current-voltage characteristic curve measured when multiple dummy cells of the memory string are in the erase state E. Curve line 1 can be understood as the current-voltage characteristic curve measured when multiple dummy cells of the memory string are in the first programming state P1. Curve line 2 can be understood as the current-voltage characteristic curve measured when multiple dummy cells of the memory string are in the nth programming state Pn. Among these, compared to multiple dummy cells in the first programming state P1, when multiple dummy cells are in the nth programming state Pn, the equivalent resistance of the multiple dummy cells in the working state is larger, resulting in a larger current I on the bit line BL. d Smaller. The programmable range of multiple dummy units can be understood as the threshold voltage range between the minimum threshold voltage of the first programming state P1 and the maximum threshold voltage of the nth programming state Pn. The semiconductor structure is configured to perform the first operation, and a voltage is also applied to multiple dummy word lines. This voltage is greater than the maximum threshold voltage of the programming state in which the multiple dummy units are located, in order to turn on the multiple dummy units, putting them into an operational state.

[0135] Figure 19 This is a schematic flowchart illustrating the programming of virtual cells in a memory string according to an embodiment of this application. It should be understood that... Figure 19 Steps S101, S102, S103 and S104 shown are not exclusive, and other steps may be performed before, after or between any of the steps shown in the operation. Figure 19 The steps shown can be adjusted in order according to actual needs.

[0136] Figure 20A To Figure 17 A waveform diagram illustrating the erasure operation of the memory cells and dummy cells in the memory string; Figure 20B for Figure 20A A waveform diagram for verifying the erasure operation. Figure 20C To Figure 17 A waveform diagram illustrating programming operations on the storage units of a memory string; Figure 20D for Figure 20C A waveform diagram for verifying the programming operation. Figure 20E To Figure 17 A waveform diagram illustrating the programming operation performed on the virtual cells of the memory string; Figure 20F for Figure 20E A waveform diagram for verifying the programming operation. Figure 20G To Figure 17 A waveform diagram illustrating the read operation of a memory string's storage cells.

[0137] The following combination Figure 17 , Figure 18 and Figure 19 ,as well as Figures 20A to 20G This section provides a detailed explanation of the process for completing the second programming operation, as well as the associated erase and read operations.

[0138] In some embodiments, an erasure operation is performed before step S101, and the peripheral circuitry is configured to perform an erasure operation on a plurality of memory cells and a plurality of dummy cells. The erasure operation can employ a full word-line erasure method, an odd-even erasure method, or other erasure methods. In a full word-line erasure method, the memory cells connected to each word line and the dummy cells connected to each dummy word line in the memory block are erased simultaneously in an erase-verify iteration, and full word-line verification is performed after the full word-line erasure, wherein the memory cells connected to each word line and the dummy cells connected to each dummy word line undergo verification testing simultaneously in the erase-verify iteration. In an odd-even erasure method, the memory cells connected to odd-numbered lines and the dummy cells connected to odd-numbered dummy word lines are erased separately from the memory cells connected to even-numbered lines and the dummy cells connected to even-numbered dummy word lines. In one odd-even erasure method, the memory cells connected to odd-numbered lines and the dummy cells connected to odd-numbered dummy word lines undergo verification testing separately from the memory cells connected to even-numbered lines and the dummy cells connected to even-numbered dummy word lines. In another parity-even erase method, the memory cells connected to each word line and the dummy cells connected to each dummy word line are simultaneously verified during erase-verify iterations. The erase operation involves one or more erase-verify iterations, also known as erase cycles, during which an erase voltage can be applied using incremental step pulse erase (ISPE). In this way, multiple memory cells and multiple dummy cells in the memory string are all in an erased state.

[0139] refer to Figure 20A For example, the erase operation includes applying a voltage V to the top select gate line TSG and the bottom select gate line BSG. ers To increase the channel potential of the memory string, a voltage V is applied to multiple word lines WL (e.g., word lines WL0 to WLn). SS (e.g., 0V) Apply a voltage V to multiple dummy word lines dumWL (e.g., dummy word lines dumWL0 to dummy word lines dumWL2). SS (e.g., 0V), apply voltage V to bit line BL. ers (e.g., 20V) Apply a voltage V to the source line ACS. ers (e.g., 20V) to perform erase operations on multiple memory cells and multiple dummy cells.

[0140] refer to Figure 20BVerification is performed after erasure. The verification of the erasure operation includes applying voltage V to the top select gate line (TSG) and the bottom select gate line (BSG), respectively. TSG Voltage V BSG By turning on the top select transistor and the bottom select transistor, a verification voltage V is applied to multiple word lines WL (e.g., word lines WL0 to WLn) and multiple dummy word lines dumWL (e.g., dummy word lines dumWL0 to dummy word lines dumWL2). ver (e.g., 1.5V) to verify memory cells coupled to multiple word lines and dummy cells coupled to multiple dummy word lines, applying a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. SS (e.g., 0V). Memory cells coupled to multiple word lines and dummy cells coupled to multiple dummy word lines undergo verification testing simultaneously in the erase-verify iteration. Passing the verification test completes the erase operation on both memory cells and dummy cells. Thus, the memory string's multiple memory cells and dummy cells are in an erased state.

[0141] In some embodiments, the programming operation involves one or more programming-verification iterations, also known as programming cycles. During programming, a programming voltage may be applied using an incremental step pulse program (ISPP). Verification is performed after programming, where memory cells coupled to selected word lines undergo verification tests simultaneously during the programming-verification iterations. Passing the verification tests completes the programming operation on the memory cells coupled to the selected word lines.

[0142] In some embodiments, step S101 is performed, in which the peripheral circuitry is configured to perform a first programming operation on a plurality of memory cells.

[0143] refer to Figure 20C For example, programming in the first programming operation includes applying voltage V to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V SS Apply a programming voltage V to the selected word line selWL (e.g., word line WLn). pgm (e.g., 16V) to program memory cells coupled to selected word lines, and to apply a pass voltage V to unselWL (e.g., word lines WL0 to WLn-1) unselWL. pass (e.g., 3V) conducts to unselected memory cells coupled to unselected word lines, applying a pass voltage to multiple dummy word lines dumWL (e.g., dummy word lines dumWL0 to dummy word lines dumWL2). Vpass (For example, 3V) turns on multiple dummy cells coupled to multiple dummy word lines, applying a voltage V to the bit line BL.BL (e.g., 3V) Apply a voltage V to the source line ACS. DD (e.g., 3V).

[0144] refer to Figure 20D After programming, verification is performed. The verification of the first programming operation includes applying voltage V to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V BSG By turning on the top select transistor and the bottom select transistor, a verification voltage V is applied to the selected word line selWL (e.g., word line WLn). ver (e.g., 1.5V) to verify memory cells coupled to selected word lines, and to apply a pass voltage V to unselWL (e.g., word lines WL0 to WLn-1) of non-selected word lines. pass (For example, 3V) conducts to unselected memory cells coupled to unselected word lines, applying a pass voltage V to multiple dummy word lines dumWL (e.g., dummy word lines dumWL0 to dummy word lines dumWL2). pass (For example, 3V) turns on multiple dummy cells coupled to multiple dummy word lines, applying a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. SS (e.g., 0V). Memory cells coupled to a selected word line undergo verification testing simultaneously during the programming-verification iteration. Passing the verification test completes the first programming operation for the memory cell coupled to the selected word line. Similarly, the first programming operation is performed sequentially on the memory cells coupled to word lines WLn-1 through WL0. In this way, multiple memory cells in the memory string store corresponding weights.

[0145] In some embodiments, step S102 is performed, in which the peripheral circuit is configured to perform a second programming operation on a plurality of dummy units.

[0146] refer to Figure 20E For example, the programming of the second programming operation includes applying voltage V to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V SS A programming voltage Vpgm (e.g., 16V) is applied to multiple dummy word lines dumWL (e.g., dumWL0 to dumWL2) to program multiple dummy cells coupled to the multiple dummy word lines, and a pass voltage V is applied to multiple word lines WL (e.g., word lines WL0 to WLn) coupled to multiple memory cells. pass (For example, 3V) turns on multiple memory cells and applies a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. DD (e.g., 3V).

[0147] refer to Figure 20F After programming, verification is performed. The verification of the second programming operation includes applying voltage V to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V BSG By turning on the top select transistor and the bottom select transistor, a verification voltage Vver (e.g., 1.5V) is applied to multiple dummy word lines dumWL (e.g., dumWL0 to dumWL2) to verify multiple dummy cells coupled to the multiple dummy word lines. A pass voltage V is applied to multiple word lines WL (e.g., word lines WL0 to WLn) coupled to the multiple memory cells. pass (For example, 3V) turns on multiple memory cells and applies a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. SS (e.g., 0V). Multiple dummy cells coupled to multiple dummy word lines undergo verification testing simultaneously in the programming-verification iteration. Passing the verification test completes the second programming operation for the multiple dummy cells coupled to the multiple dummy word lines. In this way, multiple dummy cells of the memory string are all programmed into the programming state.

[0148] In some embodiments, the peripheral circuitry is configured to: apply a programming voltage to a first word line by applying a plurality of first step pulse voltages during the execution of a first programming operation; the difference between two adjacent first step pulse voltages is a first step long voltage; and apply a programming voltage to a third word line by applying a plurality of second step pulse voltages during the execution of a second programming operation; the difference between two adjacent second step pulse voltages is a second step long voltage; wherein the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, or the second step long voltage is less than the first step long voltage. In an optional embodiment, the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, and the second step long voltage is less than the first step long voltage.

[0149] Since the memory cells are used to store weights, the distribution of threshold voltages between different memory states (including erase and program states) of the memory cells needs to satisfy a certain read window, such as... Figure 9B As shown, there is an interval (also called a read window) between the maximum value of the threshold voltage distribution when the memory cell is in the erase state and the minimum value of the threshold voltage distribution when it is in the programming state. The read voltage V is the weight of the read memory cell. rd Set within this interval.

[0150] In contrast to multiple storage cells used for storing weights, multiple dummy cells are not used for storing weights. The threshold voltage of the dummy cells changes to alter the equivalent resistance of the multiple dummy cells in their on-state. The threshold voltage of the multiple dummy cells is within a programmable range (e.g., ...). Figure 18 As shown, it is sufficient to consider the threshold voltage distribution of multiple dummy cells in different programming states to meet the requirement of a certain read window. In this way, the compensation accuracy of multiple dummy cells can be guaranteed, so as to adjust their equivalent resistance more finely to reduce the current variation on the bit line.

[0151] In some embodiments, step S103 is performed, wherein the peripheral circuitry is configured to: apply a first through voltage to a non-selected word line among a plurality of word lines coupled to a plurality of memory cells, apply a second through voltage to a plurality of dummy word lines, and acquire a first current through the memory string.

[0152] For example, a voltage V is applied to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V BSG By turning on the top select transistor and the bottom select transistor, a first pass voltage V is applied to multiple word lines (e.g., word lines WL0 to WLn) coupled to multiple memory cells. pass1 (For example, 3V) turns on multiple memory cells, applying a second pass voltage V to multiple dummy word lines (for example, dummy word lines dumWL0 to dumWL2). pass2 (e.g., 1.5V) Multiple dummy cells are turned on, applying a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. SS (e.g., 0V) to enable the current I on the memory serial-parallel sensing bit line BL.

[0153] In an optional embodiment, voltage V is applied to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V BSG By turning on the top select transistor and the bottom select transistor, a read voltage V is applied to the selected word line (e.g., word line WLn). rd (e.g., 1.5V) to turn on the selected memory cell coupled to the selected word line, and apply a first pass voltage V to the non-selected word lines (e.g., word lines WL0 to WLn-1). pass1 (For example, 3V) conducts to unselected memory cells coupled to unselected word lines, and applies a second pass voltage V to multiple dummy word lines (for example, dummy word lines dumWL0 to dumWL2). pass2 (e.g., 1.5V) Multiple dummy cells are turned on, applying a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. SS (e.g., 0V) to enable the current I on the memory serial-parallel sensing bit line BL. Refer to the reference. Figure 18The higher the programming state of multiple dummy units (e.g., the nth programming state Pn is higher than the first programming state P1), the greater the equivalent resistance of the multiple dummy units, resulting in a smaller first current flowing through the memory string when the memory string is on. Thus, the magnitude of the first current flowing through the memory string is adjusted according to the different programming states of the multiple dummy units in the memory string.

[0154] refer to Figure 19 In some embodiments, the second programming operation involves one or more programming-verification iterations. During the programming process of the second operation, a programming voltage can be applied using incremental step-pulse programming. The programming voltage is increased depending on whether the acquired first current is less than a first preset value. In some embodiments, the first preset value can be an empirical value or a default value configured at the factory for the semiconductor structure (or semiconductor device), which is derived from extensive simulation experiments. Exemplarily, the first preset value can be in the range of 30nA to 50nA, for example, it can be 32nA, 34nA, 35nA, 36nA, 37nA, 38nA, 39nA, 40nA, 41nA, 42nA, 43nA, 44nA, 55nA, 46nA, or 48nA. For example, if the first current is less than the first preset value, no further programming operation is performed; if the first current is greater than or equal to the first preset value, the next programming voltage is obtained by increasing the previous programming voltage by one step voltage (as described below as the second step voltage), and the next programming operation is performed.

[0155] refer to Figure 19 In some embodiments, the peripheral circuit is configured to perform steps S103 to S104: the first current is less than a first preset value, and the second programming operation is completed.

[0156] refer to Figure 19 In some embodiments, the peripheral circuit is configured to perform steps S103, S102, and S103 to S104: increasing the programming voltage of the second programming operation based on the first current being greater than or equal to the first preset value, and continuing to perform the second programming operation; continuing to apply the first through voltage to the second word line and the second through voltage to the third word line to obtain the corresponding first current; and completing the second programming operation when the first current is less than the first preset value.

[0157] In this way, if the first current is less than the first preset value, the current variation on the bit line can be reduced while ensuring that the first operation can be performed. This can improve the current consistency on the bit line during the execution of the first operation and reduce or clear the error rate during the execution of the first operation.

[0158] In some embodiments, after performing step S104, the peripheral circuitry is configured to perform a read operation on the memory cell coupled to the first word line.

[0159] refer to Figure 20G For example, the read operation includes applying voltage V to the top select gate line TSG and the bottom select gate line BSG, respectively. TSG Voltage V BSG By turning on the top select transistor and the bottom select transistor, a read voltage V is applied to the selected word line selWL (e.g., word line WLn). rd (e.g., 1.5V) to read memory cells coupled to selected word lines, and to apply a first pass voltage V to unselWL (e.g., word lines WL0 to WLn-1) of non-selected word lines. pass1 (For example, 3V) turns on the unselected memory cell coupled to the unselected word line, and applies a voltage less than the second pass voltage V to multiple dummy word lines dumWL (for example, dummy word lines dumWL0 to dummy word lines dumWL2). pass2 (e.g., 3V) First operating voltage V work1 (For example, 2.5V) turns on multiple dummy cells coupled to multiple dummy word lines, applying a voltage V to the bit line BL. BL (e.g., 3V) Apply a voltage V to the source line ACS. SS (e.g., 0V) to conduct the current I on the memory string-parallel sensing bit line BL. In this way, the weights stored in multiple memory cells of the memory string are read.

[0160] refer to Figure 18 In some embodiments, the peripheral circuitry is further configured to: during a read operation on a memory cell coupled to the first word line, apply a read voltage to the first word line, apply a first pass voltage to the second word line, and apply a first operating voltage less than a second pass voltage to a plurality of third word lines, such that the plurality of dummy cells operate in the linear region. Here, the first operating voltage is greater than the maximum threshold voltage of the threshold voltage distribution of the programming state in which the plurality of dummy cells are located, and less than the saturation region initiation voltage of the dummy cells; the second pass voltage is greater than or equal to the saturation region initiation voltage. For example, refer to... Figure 18 The nth programming state Pn of multiple dummy units, the first operating voltage V work1 The maximum threshold voltage is greater than the threshold voltage distribution of the nth programmed state Pn and less than the saturation region initiation voltage V of the nth programmed state Pn. satn Optionally, in the first programming state P1 of the multiple dummy units, the first operating voltage is greater than the maximum threshold voltage of the threshold voltage distribution of the first programming state P1 and less than the saturation region initiation voltage V of the first programming state P1. sat1 .

[0161] It should be noted that the operating state (conduction state) of a dummy cell can be divided into a linear region operating state and a saturation region operating state. The saturation region threshold voltage is the critical voltage distinguishing between the linear and saturation regions. In the operating state of a dummy cell, if the operating voltage received by the dummy word line coupled to the dummy cell is less than the saturation region threshold voltage, the dummy cell operates in the linear region; if the operating voltage received by the dummy word line coupled to the dummy cell is greater than or equal to the saturation region threshold voltage, the dummy cell operates in the saturation region. A dummy cell operating in the linear region can be considered to have a relatively small equivalent resistance that remains constant with changes in the voltage across its source and drain sides. A dummy cell operating in the saturation region can be considered to have a relatively large equivalent resistance that changes with changes in the voltage across its source and drain sides.

[0162] In this way, compared to multiple dummy cells operating in the saturation region, multiple dummy cells operating in the linear region result in a smaller equivalent resistance of multiple dummy cells in the operating state, which remains essentially unchanged with the voltage changes on both the source and drain sides of the dummy cells. This ensures the stability of multiple dummy cells in the operating state. During the read operation, the current changes on the bit lines caused by multiple dummy cells can be avoided or reduced. This can reduce the current changes on the bit lines, thereby improving the current consistency on the bit lines during the execution of the first operation and reducing or clearing the error rate during the execution of the first operation.

[0163] Figure 20H This is a schematic diagram comparing the threshold voltage distribution of the memory cell in erase / programmable state and the threshold voltage distribution of the dummy cell in programmable state, as provided in the embodiments of this application.

[0164] refer to Figure 20H In some embodiments, the peripheral circuitry is further configured to: perform a first programming operation, wherein the memory cell coupled to the first word line has a first threshold voltage; perform a second programming operation, wherein one of the plurality of dummy cells has a second threshold voltage; the second threshold voltage is greater than the first threshold voltage; during a read operation on the memory cell coupled to the first word line, a read voltage is applied to the first word line, a first pass voltage is applied to the second word line, and a second operating voltage is applied to the plurality of third word lines; the second operating voltage is less than the first pass voltage. Here, the first threshold voltage is within the threshold voltage distribution of the programmed state of the memory cell, the second threshold voltage is within the threshold voltage distribution of the programmed state of the dummy cell, the maximum threshold voltage of the threshold voltage distribution of the programmed state of the memory cell is less than the minimum threshold voltage of the threshold voltage distribution of the programmed state of the dummy cell, and the second operating voltage V work2 First through voltage V pass1 All are greater than the maximum threshold voltage of the threshold voltage distribution in the programmed state of the dummy cell.

[0165] refer to Figure 20HThe memory cell is in either the programming state P or the erasure state E. The minimum threshold voltage of the threshold voltage distribution of the memory cell in the programming state P is greater than the maximum threshold voltage of the threshold voltage distribution of the memory cell in the erasure state E. The dummy cell is in the programming state Pn. The minimum threshold voltage of the threshold voltage distribution of the dummy cell in the programming state Pn is greater than the maximum threshold voltage of the threshold voltage distribution of the memory cell in the programming state P.

[0166] In this way, compared to a memory cell, the dummy cell is programmed to a higher threshold voltage (e.g., the dummy cell's programming state Pn), and a lower pass voltage (e.g., less than a first pass voltage V) is applied to the dummy word line coupled to the dummy cell during a read operation. pass1 The second operating voltage V work2 This ensures that the equivalent resistance of the dummy cell is large in the working state. By adding the equivalent resistance of the large dummy cell, the influence of the equivalent resistance of the memory cell corresponding to the non-selected word line coupled to the bit line on the current can be diluted. Moreover, while ensuring that the first operation can be executed, the current on the bit line can be reduced.

[0167] Figure 21 This is the fourth schematic diagram of a memory string whose first end is connected to the source line and the second end is connected to the bit line, as provided in the embodiments of this application. Figure 22 for Figure 21 A schematic diagram of the current-voltage characteristic curves of the dummy word lines of the memory string in different programming states. Figure 23 To Figure 21 This is a flowchart illustrating the programming process using virtual cells in a memory string. It should be noted that... Figure 21 The memory string shown can be understood as... Figure 17 The memory string shown is compared to the one for... Figure 17 Perform a read operation on the memory string shown. Figure 21 The memory string shown is read from, and the pass voltage applied to the non-selected word lines is different.

[0168] refer to Figure 22 When the memory string is in the ON state, the equivalent resistance of the memory cell located between the selected memory cell (the memory cell coupled to the selected word line selWL) and the source line ACS is the first equivalent resistance R. S2 The equivalent resistance corresponding to the dummy cell located between the selected memory cell and the source line ACS is the third equivalent resistance R. dum2 The equivalent resistance corresponding to the memory cell located between the selected memory cell and the bit line BL is the second equivalent resistance R. D2 .

[0169] refer to Figure 23 When the memory string is in the ON state, the current I on the bit line BL is dThe gate voltage V received by the selected word line selWL g The current-voltage characteristic curves are shown below. Curve line 0 can be understood as the current-voltage characteristic curve measured when all memory cells in the memory string are in the erase state. Curve line 1 can be understood as the current-voltage characteristic curve measured when at least some memory cells in the memory string are in the programming state, where the selected word line selWL is the word line closest to the source line ACS, for example, word line WL2. Curve line 2 can be understood as the current-voltage characteristic curve measured when at least some memory cells in the memory string are in the programming state, where the selected word line selWL is the word line closest to the bit line BL, for example, word line WLn-2.

[0170] Reference Figure 21 , Figure 22 and Figure 23 Compared to Figure 13 The current difference ΔI in the linear region shown LR0 , Figure 23 The current difference ΔI between curves line1 and line2 in the linear region is shown. LR2 Smaller, i.e., current difference ΔI LR2 Less than the current difference ΔI LR0 Compared to Figure 13 The current difference ΔI in the linear region shown SR0 , Figure 23 The current difference ΔI between curves line1 and line2 in the saturation region is shown. SR2 Smaller, i.e., current difference ΔI SR2 Less than the current difference ΔI SR0 .

[0171] refer to Figure 21 , Figure 22 and Figure 23 In some embodiments, the peripheral circuitry is further configured to: apply a read voltage to the first word line, a third pass voltage to the second word line, and a third operating voltage to a plurality of third word lines during a first read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is in a first position in the memory string; and apply a read voltage to the first word line, a fourth pass voltage to the second word line, and a third operating voltage to a plurality of third word lines during a second read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is in a second position in the memory string; wherein the first position is closer to the bit line than the second position, and the third pass voltage is greater than the fourth pass voltage.

[0172] In some embodiments, both the third and fourth pass voltages are greater than or equal to the first pass voltage. In optional embodiments, the third pass voltage is greater than the fourth pass voltage, and the fourth pass voltage is greater than the first pass voltage. In some embodiments, the specific values ​​of the third and fourth pass voltages can be empirical values ​​or default values ​​configured at the factory for the semiconductor structure (or semiconductor device), which are derived from extensive simulation experiments. For example, the specific values ​​of the third and fourth pass voltages depend on actual measurement results, the driving capability of the line decoder / word line driver, etc.

[0173] Reference Figure 21 , Figure 22 and Figure 23 Compared to Figure 16 The current shown by curve line1, Figure 23 The current shown by curve line 1 is relatively large; compared to Figure 16 The current shown by curve line2, Figure 23 The current shown by curve line 2 is relatively large. For example, when in the first position, the peripheral circuitry is configured to perform a first read operation on a memory cell coupled to a selected word line. The first read operation includes applying a read voltage V to the selected word line selWL (e.g., word line WLn). rd (e.g., 1.5V) to read memory cells coupled to selected word lines, and to apply a voltage greater than the first pass voltage V to unselWL (e.g., word lines WL0 to WLn-1) of non-selected word lines. pass1 A third pass voltage (e.g., 3.2V) is applied to turn on the unselected memory cell coupled to the unselected word line; when in the second position, the peripheral circuitry is configured to perform a second read operation on the memory cell coupled to the selected word line, the second read operation including applying a read voltage V to the selected word line selWL (e.g., word line WLn). rd (e.g., 1.5V) to read memory cells coupled to selected word lines, and to apply a first pass voltage greater than or equal to V to non-selected word lines unselWL (e.g., word lines WL0 to WLn-1). pass1 A fourth pass voltage (e.g., 3V) that is less than the third pass voltage (e.g., 3.2V) turns on the unselected memory cell coupled to the unselected word line.

[0174] In this way, compared to the second read operation, the first read operation applies a larger through voltage to the unselected word lines (e.g., word lines WL0 to WLn-1), which can increase the current on the bit lines. This is equivalent to reducing the difference between the current on the bit lines and the current on the bit lines in the second read operation, diluting the influence of the equivalent resistance of the memory cell coupled to the unselected word lines on the current on the bit lines, and reducing the current on the bit lines while ensuring that the first operation can be performed.

[0175] Figure 24 This is a schematic diagram of some memory strings whose first end is connected to the source line and the second end is connected to the bit line, as provided in the embodiments of this application. Figure 24 (a) Figure 24 (b) Figure 24 (c) and Figure 24 (d) are examples of different memory strings. Although, Figure 24 (a) Figure 24 (b) Figure 24 (c) and Figure 24 (d) shows the number of dummy units as 2, 2, 4, and 3, respectively; however, the number of dummy units is not limited to this. Figure 24 The number of dummy units shown can be greater than 4 (e.g., 5 or 6).

[0176] In some embodiments, the location of each dummy unit in the memory string can be configured; the dummy unit can be close to the bit line BL or the source line ACS, or it can be far from the bit line BL or the source line ACS. Figure 11 The (n+1) word lines shown are used as a reference. Since word lines WL0 to WLn are sequentially numbered from the source line ACS to the bit line BL, their positions relative to the bit line BL or the source line ACS are already reflected. Figure 11 The target number (a natural number greater than 1) of the (n+1) word lines shown are replaced with dummy word lines, and the memory cells coupled to the dummy word lines are replaced with dummy cells. This yields the following result: Figure 24 memory string or with Figure 24 Similar memory strings.

[0177] refer to Figure 24 In some embodiments, such as Figure 24 As shown in (a), the multiple dummy cells include bottom dummy cells located between the source line and the multiple memory cells, or, as... Figure 24 As shown in (b), a top dummy cell is located between the bit line and multiple memory cells. In an alternative embodiment, as... Figure 24 As shown in (c), the plurality of dummy cells includes a bottom dummy cell located between the source line and the plurality of memory cells and a top dummy cell located between the bit line and the plurality of memory cells. In other embodiments, such as Figure 24 As shown in (d), the multiple dummy cells include a central dummy cell located far from the source line and far from the bit line.

[0178] In some embodiments, the bottom dummy cell has a greater impact on the current variation on the bit line than the top dummy cell, and the compensation effect of the bottom dummy cell is more obvious. In read operations, the current variation on the bit line caused by multiple dummy cells can be avoided or reduced more effectively, thereby reducing the current variation on the bit line, improving the current consistency on the bit line during the execution of the first operation, and reducing or clearing the error rate during the execution of the first operation.

[0179] In some embodiments, a first end of a plurality of memory strings located in the same column is connected to a source line and a second end is connected to a bit line; a first word line is coupled to a corresponding memory cell in the same column of the plurality of memory strings; the peripheral circuit is further configured to: perform a read operation on the corresponding memory cell coupled to the first word line, obtain a second current through the bit line, and obtain the result of a first operation based on the second current.

[0180] For details on the execution of the first operation, please refer to [link / reference]. Figure 10 To understand the relevant instructions, it is necessary to include Figure 10 The target number (a natural number greater than 1) of word lines from word line WL0 to word line WLend are replaced with dummy word lines, and the memory cells coupled to the dummy word lines are replaced with dummy cells. The cases of multiple dummy word lines and multiple dummy cells coupled to multiple dummy word lines can be understood by referring to the above embodiments, and will not be repeated here.

[0181] In some embodiments, the third word line includes the first portion (reference). Figure 25 (For understanding the connection structure 108 in the text) and multiple second parts connected to the first part (refer to...) Figure 25 (The second gate layer dumGL0, the second gate layer dumGL1, and the second gate layer dumGL2 are understood in this context); the first end of each second part is connected to the gate end of a corresponding dummy cell; the second end of each second part is connected to the first part; wherein the first part is configured to receive a second pass voltage.

[0182] The first ends of the multiple second portions of the third word line are respectively coupled to multiple dummy cells. The second ends of the multiple second portions are in common contact and electrically connected to the first portion of the third word line to combine the gate ends of the multiple dummy cells together. The line decoder / word line driver can pass the corresponding voltage (e.g., the programming voltage applied to the gate ends of the multiple dummy cells in the second programming operation, the second pass voltage applied to the gate ends of the multiple dummy cells in the first current acquisition operation, or, for example, the first working voltage or the second working voltage applied to the gate ends of the multiple dummy cells in the read operation) to the gate ends of the multiple dummy cells through the first portion of the third word line, which can reduce the number of line decoders / word line drivers and save costs.

[0183] Since the threshold voltage of a dummy cell is highly sensitive to drift (for example, the threshold voltage of a dummy cell is very sensitive to drift when it is operating in the linear region compared to when it is operating in the saturation region), merging the gate terminals of multiple dummy cells together helps to avoid or reduce lateral charge loss of the dummy cells and improves the cell retention characteristics of the dummy cells.

[0184] Figure 25 This is a schematic diagram of a memory string in an embodiment of the present application, in which multiple second gate layers coupled to multiple dummy cells are connected to a common interconnect structure. Figure 26 This is one of the cross-sectional schematic diagrams of a semiconductor structure including a connection structure provided in an embodiment of this application. Figure 27 This is a second schematic cross-sectional view of a semiconductor structure including a connection structure, provided as an embodiment of this application. It should be noted that... Figure 26 (a) Figure 26 (b) are schematic diagrams of different cross-sections of the semiconductor structure. Figure 27 (a) Figure 27 (b) are schematic diagrams of different cross-sections of the semiconductor structure. Figure 26 (a) Figure 27 (a) illustrates, for example, that the first end of the memory string is connected to the source line via a top select transistor, and the second end is connected to the bit line via a bottom select transistor. This provides a simplified illustration of the channel structure of the memory string. For a more detailed diagram of the channel structure of the memory string, please refer to the above. Figure 5 Understand the relevant descriptions.

[0185] Reference Figure 25 and Figure 26 or in conjunction with references Figure 25 and Figure 27 Secondly, embodiments of this application provide another semiconductor structure, which includes a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; wherein the plurality of memory cells are coupled to a plurality of first gate layers; the plurality of dummy cells are coupled to a plurality of second gate layers; the first ends of the plurality of second gate layers are respectively coupled to the plurality of dummy cells, and the second ends are in common contact and electrically connected to a connection structure; the connection structure includes a conductive material.

[0186] For example, the first end of the memory string is connected to the source line ACS via a bottom select transistor, and the second end is connected to the bit line BL via a top select transistor. The gate of the top select transistor is connected to the top select gate line TSG, and the gate of the bottom select transistor is connected to the bottom select gate line BSG. The memory string includes multiple memory cells and multiple dummy cells. The multiple memory cells are coupled to the first gate layer 1041_0, the first gate layer 1041_1, ..., the first gate layer 1041_n1 and the first gate layer 1041_n. The multiple dummy cells are coupled to the first ends of the second gate layer 1042_0, the second gate layer 1042_1 and the second gate layer 1042_2. The second ends of the second gate layer 1042_0, the second gate layer 1042_1 and the second gate layer 1042_2 are in common contact and electrically connected to the connection structure 108.

[0187] In some embodiments, the conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. In some embodiments, the material of the connection structure is the same as or similar to the material of the second gate layer. In some embodiments, the material of the connection structure includes a metal layer, such as a tungsten layer.

[0188] Although, Figure 25 The number of dummy units shown is 3, but the number of dummy units is not limited to this. Figure 25 The number shown indicates that the number of dummy units can be 2 or more (e.g., 4, 5, or 6). Although, Figure 25 The multiple dummy units shown are arranged adjacently; however, multiple dummy units can also be arranged at intervals. Figure 25 (Not shown), multiple dummy units are partially spaced apart and partially adjacent ( Figure 25 (Not shown). Although, Figure 25 The dummy cell shown is located at the bottom of the memory string between the source line and multiple memory cells; however, the location of the dummy cell is not limited to this. Figure 25 As shown, the dummy cell can also be located at the top of the memory string between the bit line and multiple memory cells. Figure 25 (Not shown). In other embodiments, the dummy cell may also be located in the middle of the memory string, away from the source line and away from the bit line ( Figure 25 (Not shown).

[0189] It should be noted that, Figure 25 The memory string shown can also be referenced. Figures 14 to 24 To understand the relevant explanations, it is necessary to include the above... Figures 14 to 24 The second ends of the dummy word lines of the memory string shown are connected together to the connection structure for understanding, where, Figures 14 to 24The first end of the dummy word line of the memory string shown is connected to the gate of the corresponding dummy cell. Figure 25 The cases of multiple second gate layers and multiple dummy cells coupled to the multiple second gate layers shown can be understood by referring to the cases of multiple dummy word lines and multiple dummy cells coupled to the multiple dummy word lines in the above embodiments, and will not be repeated here.

[0190] The first ends of multiple second gate layers are respectively coupled to multiple dummy units, and the second ends of multiple second gate layers are in common contact and electrically connected to the connection structure to combine multiple second gate layers together. The line decoder / word line driver can pass the corresponding voltage (e.g., the programming voltage applied to the second gate layer in the second programming operation, the second through voltage applied to the second gate layer in the first current acquisition operation, or the first working voltage or the second working voltage applied to the second gate layer in the read operation) to multiple second gate layers through the connection structure, which can reduce the number of line decoders / word line drivers and save costs.

[0191] Since the threshold voltage of a dummy cell is highly sensitive to drift (for example, the threshold voltage of a dummy cell is very sensitive to drift when it is operating in the linear region compared to when it is operating in the saturation region), merging multiple second gate layers together helps to avoid or reduce lateral charge loss of the dummy cells and improves cell retention.

[0192] In some embodiments, the plurality of dummy cells include bottom dummy cells located between the source line and the plurality of memory cells, or top dummy cells located between the bit line and the plurality of memory cells. In some embodiments, bottom dummy cells have a greater impact on current variations on the bit line than top dummy cells, and the compensation effect of bottom dummy cells is more significant.

[0193] In some embodiments, a first end of a plurality of memory strings located in the same column is connected to a source line and a second end is connected to a bit line; a first gate layer is coupled to a corresponding memory cell located in the same column of the plurality of memory strings.

[0194] Here, referring to the above Figures 14 to 24 The second ends of the dummy word lines of the memory string shown are connected to the connection structure for understanding. For the case of multiple dummy word lines and multiple dummy cells coupled to multiple dummy word lines, please refer to the above. Figures 14 to 24 The various embodiments shown are for reference only and will not be described in detail here.

[0195] Although, Figure 25 The number of dummy units shown is 3, but the number of dummy units is not limited to this. Figure 25The number shown can be 2 or more than 3 (e.g., 4, 5 or 6).

[0196] Although, Figure 25 The multiple dummy units shown are arranged adjacently; however, multiple dummy units can also be arranged at intervals. Figure 25 (Not shown), multiple dummy units are partially spaced apart and partially adjacent ( Figure 25 (Not shown).

[0197] Although, Figure 25 The dummy cell shown is located at the bottom of the memory string between the source line and multiple memory cells; however, the location of the dummy cell is not limited to this. Figure 25 As shown, the dummy cell can also be located at the top of the memory string between the bit line and multiple memory cells. Figure 25 (Not shown). In other embodiments, the dummy cell may also be located in the middle of the memory string, away from the source line and away from the bit line ( Figure 25 (Not shown).

[0198] Thirdly, embodiments of this application provide yet another semiconductor structure, referencing Figure 26 and Figure 27 The semiconductor structure 100 includes: a stacked structure 101, including a gate layer and an insulating layer 102 spaced apart; the stacked structure 101 includes a plurality of gate layers; the plurality of gate layers include a plurality of first gate layers (e.g., first gate layers 1041_0 to 1041_n) and a plurality of second gate layers (e.g., second gate layers 1042_0 to 1042_2); a memory structure ( Figure 26 and Figure 27 (Not shown), a stacked structure includes multiple memory cells and multiple dummy cells; the memory cells are coupled to a first gate layer; the dummy cells are coupled to a second gate layer; a connection structure 108, including a conductive material, contacts and electrically connects to the multiple second gate layers. Thus, the first ends of the multiple second gate layers are respectively coupled to the dummy cells, and the second ends of the multiple second gate layers are commonly contacted and electrically connected to the connection structure to combine the multiple second gate layers together. The line decoder / word line driver can be coupled to the multiple second gate layers through a connection structure, which can reduce the number of line decoders / word line drivers and save costs.

[0199] Here, the storage structure of the stacked structure 101 and the memory string can be referred to the above. Figure 5 The relevant descriptions will be understood and will not be repeated here.

[0200] Here, the first region AR0 can be understood as the memory array, the second region AR1 can be understood as the area where the junction between the memory array and the lead-out region is located, and the third region AR2 can be understood as the lead-out region of the gate layer. The first region is connected in the row direction, and the lead-out region is connected in the row direction.

[0201] In some embodiments, Figure 26 (b) Figure 27 (b) may be a schematic diagram of a cross-section perpendicular to the extension direction of the gate isolation structure GLS, which extends along the XZ plane.

[0202] In some embodiments, the memory string CH is located in the first region AR0. The first end of the memory string CH is connected to the source line ACS via a bottom select transistor, and the second end is connected to the bit line BL via a top select transistor and a bit line contact BLCT. The gate of the top select transistor is connected to the top select gate line TSG, and the gate of the bottom select transistor is connected to the bottom select gate line BSG. The memory string includes multiple memory cells and multiple dummy cells. The multiple memory cells are coupled to the first gate layers 1041_0, 1041_1, ..., 1041_n1 and 1041_n. The multiple dummy cells are coupled to the first ends of the second gate layers 1042_0, 1042_1, and 1042_2. The second ends of the second gate layers 1042_0, 1042_1, and 1042_2 are in common contact and electrically connected to the connection structure 108. In some embodiments, the dummy memory string DCH is located in the second region AR1 and is not used for storing data. Although the dummy memory string (DCH) can be coupled to the corresponding first gate layer and second gate layer, the first end of the dummy memory string (DCH) does not need to be connected to the source line ACS, or the second end does not need to be connected to the bit line BL.

[0203] In some embodiments, the stacked structure 101 within the third region AR2 further includes a dielectric layer 103 and an insulating layer 102 spaced apart. For example, the dielectric layer 103 is made of silicon nitride, and the insulating layer 102 is made of silicon oxide.

[0204] In some embodiments, the top select gate line (TSG) and bottom select gate line (BSG) are made of polysilicon. In some embodiments, the bit line (BL) and bit line contact (BLCT) are made of a metal layer, such as a tungsten layer.

[0205] refer to Figure 26 and Figure 27 In some embodiments, the semiconductor structure includes a memory cell array located in a first region AR0 and a connection structure located in a third region AR2. Figure 26 and Figure 27 (The connection structure corresponding to multiple first gate layers is not shown.) The connection structure is used to bring out the gate layers of the memory cell array. It should be noted that, to clearly show the case where multiple second gate layers are jointly brought out to a single connection structure, Figure 26 , Figure 27 The diagram illustrates the electrical connection between a connection structure and multiple second gate layers, but does not show the case where each of the multiple first gate layers is independently led out. The case where each first gate layer is independently led out can be found in [reference needed]. Figure 26 The situation regarding the lead-out of each second gate layer is understood. For example, the first gate layer 1041_0 may extend and be electrically connected to a first extension component (see reference). Figure 26 (For understanding the first extension member 1084 shown), the first extension member extends and is electrically connected to a first contact structure (see reference). Figure 26 (For understanding the first contact structure 1082 shown), this first contact structure extends and is electrically connected to the first connecting line (refer to...). Figure 26 (For understanding the first connection line 1081 shown), the first connection line is located on the stacked structure 101.

[0206] In some embodiments, a plurality of first gate layers are coupled to a plurality of memory cells and extend along the row direction of the memory cell array, and a plurality of second gate layers are coupled to a plurality of dummy cells and extend along the row direction of the memory array. The first gate layers and the second gate layers may extend within a first region AR0, through a second region AR1, and into a third region AR2, where they are led out by corresponding connection structures. For example, the plurality of second gate layers are coupled to a plurality of dummy cells and extend along the row direction of the memory cell array, through a first region AR0, through a second region AR1, and into a third region AR2, where they are led out by corresponding connection structures 108.

[0207] refer to Figure 26In some embodiments, the connection structure 108 includes: a first connection line 1081 located on the stacked structure 101; and a plurality of first contact structures 1082, each having a first end extending and connected to a second gate layer, and a second end commonly connected to the first connection line 1081. Exemplarily, the first end of a first contact structure 1082 extends and connects to a corresponding second gate layer, and the second ends of the plurality of first contact structures 1082 are commonly connected to the first connection line 1081 to merge multiple second gate layers (e.g., second gate layers 1042_0 to 1042_2) together. Exemplarily, the connection structure 108 also includes a first extension member 1084 corresponding to the plurality of first contact structures 1082. A vertically extending first contact structure 1082 can be connected to a corresponding second gate layer via a horizontally extending first extension member 1084, and the second ends of the plurality of first contact structures 1082 are commonly connected to the first connection line 1081 to merge the plurality of second gate layers together.

[0208] refer to Figure 27 In some embodiments, the connection structure 108 includes: a first connection line 1081 located on the stacked structure 101; and a second contact structure 1083, with a first end extending through at least a portion of the plurality of second gate layers and connected to the plurality of second gate layers (e.g., second gate layers 1042_0 to 1042_2), and a second end connected to the first connection line 1081. Exemplarily, the connection structure 108 further includes second extension members 1085 corresponding to the plurality of second gate layers. The first end of the second contact structure 1083 can be connected to the corresponding plurality of second gate layers through the plurality of second extension members 1085, and the second end of the second contact structure 1083 is connected to the first connection line 1081 to merge the plurality of second gate layers together.

[0209] In some embodiments, the plurality of second gate layers include a bottom dummy gate layer located at the bottom of the stacked structure. Figure 26 and Figure 27 (not shown), or, a top dummy gate layer located on top of the stacked structure ( Figure 26 and Figure 27 (Not shown).

[0210] The embodiments of this application can be understood as exemplary implementations of how the second ends of the plurality of second gate layers of the semiconductor structure provided in the second aspect are contacted and electrically connected to the connection structure. The semiconductor structure provided in the embodiments of this application is similar to the semiconductor structure provided in the second aspect described above. For technical features not disclosed in detail in the embodiments of this application, please refer to the above embodiments for understanding, and will not be repeated here.

[0211] Figure 28 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0212] Fourthly, embodiments of this application provide a semiconductor device, with reference to... Figure 28 The semiconductor device includes: one or more semiconductor structures of any one of the first aspects, any one of the second aspects, or any one of the third aspects; and processing circuitry bonded to the semiconductor structure and configured to convert analog computation information obtained from a first operation performed by the semiconductor structure into digital information, and to perform a second operation on the digital information; the analog computation information includes a first current passing through a memory string of the semiconductor structure.

[0213] Reference Figure 28 The semiconductor device includes a processing circuit 200 and a semiconductor structure 300; the processing circuit 200 and the semiconductor structure 300 are bonded together.

[0214] In some embodiments, the processing circuit includes an analog-to-digital converter circuit and a data processing circuit; the analog-to-digital converter circuit is configured to convert analog calculation information into digital information; and the data processing circuit is configured to perform a second operation on the digital information.

[0215] In some embodiments, the processing circuit 200 includes an analog-to-digital converter circuit and a data processing circuit; the semiconductor structure 300 includes a memory array 301 for performing a first operation and at least a portion of peripheral circuitry 302 coupled to the memory array 301; the analog-to-digital converter circuit is configured to convert analog computation information obtained by the memory array 301 performing the first operation into digital information; and the data processing circuit is configured to perform a second operation on the digital information.

[0216] In some embodiments, the processing circuitry 200 and the semiconductor structure 300 are in different planes and stacked on top of each other. Furthermore, the memory array 301 and the peripheral circuitry 302 in the semiconductor structure 300 can be in different planes and stacked on top of each other, thereby reducing the planar dimensions of the semiconductor device.

[0217] In some embodiments, the processing circuit 200 and the semiconductor structure 300 can be formed in parallel on different substrates. For example, the processing circuit 200 can be formed on a first substrate, the memory array 301 on a second substrate, and the peripheral circuit 302 on a third substrate. They are then stacked together using various bonding techniques, such as hybrid bonding and transfer bonding. In some embodiments, the memory array 301 on the second substrate and the peripheral circuit 302 on the third substrate can be coupled together via a first bonding layer 201 to obtain the semiconductor structure 300; the semiconductor structure 300 and the processing circuit 200 on the first substrate can be coupled together via a second bonding layer 202.

[0218] In this embodiment, by vertically integrating the processing circuit 200 and the semiconductor structure 300, and by vertically separating the processing circuit 200, the memory array 301, and the peripheral circuit 302 into different planes, the chip size can be reduced and the storage density can be increased.

[0219] In this embodiment, the semiconductor structure 300 includes a first semiconductor structure on which a memory array 301 is formed and a second semiconductor structure on which at least a portion of peripheral circuitry 302 is formed. In some embodiments, a portion of the peripheral circuitry is formed in the second semiconductor structure, and another portion is formed in the first semiconductor structure. In other words, the peripheral circuitry of the memory array can be divided into two parts, one part of which is formed together with the memory array in the first semiconductor structure, and the other part is formed in the second semiconductor structure. In other embodiments, the peripheral circuitry can be entirely formed in the second semiconductor structure. In the following examples, the peripheral circuitry is entirely formed in the second semiconductor structure as an example.

[0220] In this embodiment, the semiconductor structure 300 further includes a first connection structure 320 that penetrates the memory array 301 and connects to the bit line and the second bonding layer; wherein the memory array 301 is connected to the analog-to-digital converter circuit 210 through the bit line, the first connection structure 320, and the second bonding layer 202. In a specific example, the first connection structure 320 is a through-array contact (TAC). In some embodiments, one end of the first connection structure 320 is connected to the bit line, and the other end is connected to the second bonding layer. The bit line can be connected to the analog-to-digital converter circuit 210 through the first connection structure 320 and the second bonding layer, thereby transmitting analog computing information to the analog-to-digital converter circuit 210.

[0221] In some embodiments, the processing circuit further includes a first interface circuit and a controller; the first interface circuit is configured to output the result of the second operation performed by the digital processing circuit to an external device; the controller is configured to control the semiconductor structure to perform the first operation.

[0222] In some embodiments, the first operation includes a multiplication-accumulation operation.

[0223] In this embodiment, the first interface circuit 230 is configured to receive and transmit data between the semiconductor device and other external devices. Specifically, the first interface circuit 230 is configured to output the result of the second operation performed by the data processing circuit 220 to the external device. The controller 240 can be configured to control the operation of the processing circuit 200 and the semiconductor structure 300. That is, the controller 240 can act as a memory controller managing data storage and transmission in the semiconductor structure 300 and an operation controller managing data operation and transmission in the processing circuit 200. In some embodiments, the controller 240 is also configured to control data transmission between the processing circuit 200 and the semiconductor structure 300. In some embodiments, the controller 240 is also configured to receive input data sent by the external device and send the input data to the semiconductor structure 300.

[0224] In some embodiments, controller 240 is coupled to semiconductor structure 300 and an external device (e.g., a host device) and configured to control semiconductor structure 300. Controller 240 can manage data stored in semiconductor structure 300 and communicate with external devices.

[0225] In some embodiments, controller 240 may also be configured to manage various functions relating to data stored or to be stored in semiconductor structure 300, wherein these functions include, but are not limited to, bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, controller 240 is also configured to process error correction codes (ECCs) relating to data read from or written to semiconductor structure. In some embodiments, controller 240 may also perform any other suitable functions, such as formatting semiconductor structure.

[0226] In some embodiments, the first interface circuit 230 may be configured in the controller 240, and an interface protocol may be used as the first interface circuit between the controller 240 and an external device. Thus, the controller 240 can communicate with the external device through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc. The first interface circuit 230 here may also be referred to as a front-end interface. In some embodiments, the controller 240 interacts with the semiconductor structure 300 via multiple configured channels for command / data exchange. These channels are also referred to as back-end interfaces.

[0227] In this embodiment, the semiconductor structure 300 further includes a fourth connection structure 330 that penetrates the memory array 301; one end of the fourth connection structure 330 is connected to the second semiconductor structure, and the other end is connected to the first interface circuit 230 through the second bonding layer 202. Thus, the peripheral circuit 302 in the semiconductor structure can be connected to the first interface circuit 230 through the fourth connection structure 330, and can transmit data with other external devices through the first interface circuit 230.

[0228] It should be noted that, Figure 28 The dashed arrows in the diagram represent the fourth connection structure 330, and the number of dashed arrows is merely an example and not intended to limit this application. It should also be noted that the bonding layer (second bonding layer 202) between the processing circuit 200 and the memory array 301 further includes an interconnect structure coupled to the fourth connection structure 330, thereby enabling the interconnect structure to connect the fourth connection structure 330 to the first interface circuit 230.

[0229] In this embodiment, the second semiconductor structure further includes a second interface circuit 516. Specifically, the second semiconductor structure also includes a second interface circuit 516; the semiconductor structure 300 is also connected to the processing circuit 200 through the second interface circuit 516. That is, the second interface circuit 516 here is the interface coupled to the back-end interface of the aforementioned controller, that is, the second interface circuit 516 can also be the interface for communication between the semiconductor structure and the processing circuit. The second interface circuit 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay it to the host. The second interface circuit 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory array 301.

[0230] In some embodiments, the data processing circuit 220 in the processing circuit 200 includes a processor, which may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), visual processing unit (VPU), neural processing unit (NPU), collaborative processing unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the data processing circuit is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations.

[0231] In some embodiments, the second operation includes one or more of the following operations: compensation, activation, shifting, or pooling.

[0232] In one specific example, the semiconductor structure in the semiconductor device is configured to store a weight matrix to perform multiplication-accumulation operations and output analog calculation information; the processing circuit in the semiconductor device is configured to convert the analog calculation information output by the semiconductor structure into digital information, and to perform activation operations on the digital information to obtain the output result. In some embodiments, the activation operation can be implemented by an activation function stored in the NPU, which may include, but is not limited to, a step function, a correction function, a sigmoid function, a hyperbolic tangent (tanh) function, and a softplus function (also known as a smoothing correction).

[0233] The semiconductor structure provided in this application embodiment is similar to the semiconductor structure provided in the first, second, and third aspects described above. For technical features not disclosed in detail in this application embodiment, please refer to the embodiments of the first, second, and third aspects described above for understanding. Here, they will not be repeated.

[0234] like Figure 29 The diagram illustrates an exemplary system with a memory computing device according to an embodiment of this application. System 700 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with a memory computing device. System 700 may include one or more memory computing devices 600 and one or more other types of chips 800. Exemplarily, chips 800 include, but are not limited to, sensor chips, memory chips, logic chips, etc. One or more memory computing devices 600 and one or more other types of chips 800 can be integrated in a package, such as a PCB (Printed Circuit Board) package. Thus, system 700 can be applied to different scenarios.

[0235] Figure 30 This is a flowchart illustrating the operation method of the semiconductor structure provided in the embodiments of this application.

[0236] Fifthly, embodiments of this application provide an operation method for a semiconductor structure, with reference to... Figure 30 The operation method includes the following steps:

[0237] Step S201: Perform a first programming operation on the memory cell coupled to the first word line among the multiple memory cells of the semiconductor structure;

[0238] Step S202: Perform a second programming operation on multiple dummy cells of the semiconductor structure;

[0239] Step S203: Apply a first through voltage to the second word line and apply a second through voltage different from the first through voltage to the third word line, and obtain the first current through the memory string;

[0240] The semiconductor structure includes a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes multiple memory cells and multiple dummy cells; the multiple memory cells include a first memory cell and a second memory cell; a first word line is coupled to the first memory cell, a second word line is coupled to the second memory cell, and a third word line is coupled to the multiple dummy memory cells.

[0241] In some embodiments, the operation method includes: when the first current is less than a first preset value, completing the second programming operation.

[0242] In some embodiments, the operation method includes: increasing the programming voltage of the second programming operation according to the first current being greater than or equal to a first preset value, and continuing to perform the second programming operation; and continuing to apply a first through voltage to the second word line and a second through voltage to the third word line to obtain a corresponding first current; and completing the second programming operation when the first current is less than the first preset value.

[0243] In some embodiments, the operation method includes: during the execution of a first programming operation, applying a programming voltage to a first word line in a manner that applies a plurality of first step pulse voltages; the difference between two adjacent first step pulse voltages is a first step long voltage; during the execution of a second programming operation, applying a programming voltage to a third word line in a manner that applies a plurality of second step pulse voltages; the difference between two adjacent second step pulse voltages is a second step long voltage; wherein the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, or the second step long voltage is less than the first step long voltage.

[0244] In some embodiments, the operation method further includes: during a read operation on a memory cell coupled to a first word line, applying a read voltage to the first word line, applying a first pass voltage to the second word line, and applying a first operating voltage less than the second pass voltage to the third word line, such that the plurality of dummy cells operate in the linear region.

[0245] In some embodiments, the operation method further includes: performing a first programming operation, wherein a memory cell coupled to a first word line has a first threshold voltage; performing a second programming operation, wherein one of a plurality of dummy cells has a second threshold voltage; the second threshold voltage is greater than the first threshold voltage; and during a read operation performed on a memory cell coupled to the first word line, applying a read voltage to the first word line, applying a first pass voltage to the second word line, and applying a second operating voltage to the third word line; the second operating voltage is less than the first pass voltage.

[0246] In some embodiments, the operation method further includes: applying a read voltage to the first word line, a third pass voltage to the second word line, and a third operating voltage to the third word line during a first read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is located at a first position in the memory string; applying a read voltage to the first word line, a fourth pass voltage to the second word line, and a third operating voltage to the third word line during a second read operation performed on the memory cell coupled to the first word line, depending on whether the memory cell coupled to the first word line is located at a second position in the memory string; wherein the first position is closer to the bit line than the second position, and the third pass voltage is greater than the fourth pass voltage.

[0247] In some embodiments, the plurality of dummy cells include a bottom dummy cell located between the source line and the plurality of memory cells, or a top dummy cell located between the bit line and the plurality of memory cells.

[0248] In some embodiments, the operation method further includes: performing a read operation on a corresponding memory cell located in the same column that is coupled to the first word line, obtaining a second current through the bit line, and determining the result of the first operation based on the second current; wherein, a first end of a plurality of memory strings located in the same column is connected to a source line and a second end is connected to a bit line; the first word line is coupled to a corresponding memory cell located in the same column of the plurality of memory strings.

[0249] In some embodiments, the third word line includes a first portion and a plurality of second portions connected to the first portion; a first end of each second portion is connected to the gate terminal of a corresponding dummy cell; a second end of each second portion is connected to the first portion; wherein the first portion is configured to receive a second pass voltage.

[0250] The semiconductor structure used in the operation method of the semiconductor structure provided in this application is the same as or similar to the memory device in the embodiments of the first, second, and third aspects described above. For technical features not disclosed in detail in this application, please refer to the semiconductor structure in the embodiments of the first, second, and third aspects described above for understanding, and will not be repeated here.

[0251] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0252] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, The device includes a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; the plurality of memory cells includes a first memory cell and a second memory cell; The first word line is coupled to the first memory cell, and the second word line is coupled to the second memory cell; The third word line is coupled to the plurality of virtual storage units; The peripheral circuit is configured as follows: Perform a first programming operation on the first storage unit; Perform a second programming operation on the plurality of virtual units; A first pass voltage is applied to the second word line; a second pass voltage, different from the first pass voltage, is applied to the third word line; and Obtain the first current passing through the memory string.

2. The semiconductor structure according to claim 1, characterized in that, The peripheral circuit is configured as follows: If the first current is less than the first preset value, the second programming operation is completed.

3. The semiconductor structure according to claim 1, characterized in that, The peripheral circuit is configured as follows: If the first current is greater than or equal to the first preset value, increase the programming voltage of the second programming operation and continue to execute the second programming operation; Continue applying the first through voltage to the second word line and the second through voltage to the third word line to obtain the corresponding first current; If the first current is less than the first preset value, the second programming operation is completed.

4. The semiconductor structure according to claim 1, characterized in that, The peripheral circuit is configured as follows: During the execution of the first programming operation, a programming voltage is applied to the first word line in such a way as applying a plurality of first step pulse voltages; the difference between two adjacent first step pulse voltages is the first step long voltage; During the execution of the second programming operation, a programming voltage is applied to the third word line in such a way as applying a plurality of second step pulse voltages; the difference between two adjacent second step pulse voltages is the second step voltage; Wherein, the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, or the second step voltage is less than the first step voltage.

5. The semiconductor structure according to claim 1, characterized in that, The peripheral circuit is also configured to: During a read operation on a memory cell coupled to the first word line, a read voltage is applied to the first word line, a first pass voltage is applied to the second word line, and a first operating voltage less than the second pass voltage is applied to the third word line, causing the plurality of dummy cells to operate in the linear region.

6. The semiconductor structure according to claim 1, characterized in that, The peripheral circuit is also configured to: When the first programming operation is performed, the memory cell coupled to the first word line has a first threshold voltage; The second programming operation is performed, wherein one of the plurality of dummy units has a second threshold voltage; the second threshold voltage is greater than the first threshold voltage; During a read operation on a memory cell coupled to the first word line, a read voltage is applied to the first word line, a first pass voltage is applied to the second word line, and a second operating voltage is applied to the third word line; the second operating voltage is less than the first pass voltage.

7. The semiconductor structure according to claim 1, characterized in that, The peripheral circuit is also configured to: According to the memory cell coupled to the first word line being located at a first position in the memory string, during the execution of a first read operation on the memory cell coupled to the first word line, a read voltage is applied to the first word line, a third pass voltage is applied to the second word line, and a third operating voltage is applied to the third word line; According to the memory cell coupled to the first word line being located at a second position in the memory string, during the second read operation performed on the memory cell coupled to the first word line, the read voltage is applied to the first word line, the fourth pass voltage is applied to the second word line, and the third operating voltage is applied to the third word line; Wherein, the first position is closer to the bit line than the second position, and the third through voltage is greater than the fourth through voltage.

8. The semiconductor structure according to claim 1, characterized in that, The plurality of dummy cells include bottom dummy cells located between the source line and the plurality of memory cells, or top dummy cells located between the bit line and the plurality of memory cells.

9. The semiconductor structure according to claim 1, characterized in that, The first end of a plurality of memory strings located in the same column is connected to the source line, and the second end is connected to the bit line; the first word line is coupled to a corresponding memory cell in the same column of the plurality of memory strings; the peripheral circuit is further configured to: A read operation is performed on the corresponding memory cell coupled to the first word line to obtain the second current passing through the bit line, and the result of the first operation is obtained based on the second current.

10. The semiconductor structure according to claim 1, characterized in that, The third word line includes a first portion and a plurality of second portions connected to the first portion; a first end of each second portion is connected to the gate terminal of a corresponding dummy cell; a second end of each second portion is connected to the first portion; wherein the first portion is configured to receive the second through voltage.

11. A semiconductor structure, characterized in that, It includes a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes multiple memory cells and multiple dummy cells; wherein, The plurality of memory cells are coupled to a plurality of first gate layers; the plurality of dummy cells are coupled to a plurality of second gate layers; the first ends of the plurality of second gate layers are respectively coupled to the plurality of dummy cells, and the second ends are in common contact and electrically connected to a connection structure; the connection structure includes a conductive material.

12. The semiconductor structure according to claim 11, characterized in that, The plurality of dummy cells include bottom dummy cells located between the source line and the plurality of memory cells, or top dummy cells located between the bit line and the plurality of memory cells.

13. The semiconductor structure according to claim 11, characterized in that, The first end of the plurality of memory strings located in the same column is connected to the source line and the second end is connected to the bit line; the first gate layer coupling includes corresponding memory cells located in the same column of the plurality of memory strings.

14. A semiconductor structure, characterized in that, include: A stacked structure includes gate layers and insulating layers spaced apart; the stacked structure includes a plurality of gate layers; the plurality of gate layers includes a plurality of first gate layers and a plurality of second gate layers; A storage structure, extending through the stacked structure, includes multiple storage cells and multiple dummy cells; the storage cells are coupled to the first gate layer; the dummy cells are coupled to the second gate layer; The connection structure includes a conductive material and is in contact with and electrically connected to a plurality of second gate layers.

15. The semiconductor structure according to claim 14, characterized in that, The connection structure includes: The first connecting line is located on the stacked structure; Multiple first contact structures, each with its first end extending and connected to the second gate layer, and its second end commonly connected to the first connection line; or... The second contact structure has a first end that extends through at least a portion of the plurality of second gate layers and is connected to the plurality of second gate layers, and a second end that is connected to the first connection line.

16. The semiconductor structure according to claim 14, characterized in that, The plurality of second gate layers include a bottom second gate layer located at the bottom of the stacked structure, or a top second gate layer located at the top of the stacked structure.

17. A semiconductor device, characterized in that, include: One or more semiconductor structures as described in any one of claims 1 to 10, semiconductor structures as described in any one of claims 11 to 13, or semiconductor structures as described in any one of claims 14 to 16; as well as A processing circuit, bonded to the semiconductor structure, is configured to convert analog computation information obtained from a first operation performed on the semiconductor structure into digital information, and to perform a second operation on the digital information; the analog computation information includes a first current through a memory string of the semiconductor structure.

18. The semiconductor device according to claim 17, characterized in that, The processing circuit includes an analog-to-digital conversion circuit and a data processing circuit; The analog-to-digital converter circuit is configured to convert the analog calculation information into the digital information. The data processing circuit is configured to perform the second operation on the digital information.

19. The semiconductor device according to claim 18, characterized in that, The processing circuit also includes a first interface circuit and a controller; The first interface circuit is configured to output the result of the second operation performed by the digital processing circuit to an external device; The controller is configured to control the semiconductor structure to perform the first operation.

20. The semiconductor device according to claim 17, characterized in that, The first operation includes multiplication and addition operations.

21. The semiconductor device according to claim 17, characterized in that, The second operation includes one or more of the following operations: compensation, activation, shift, or pooling.

22. A method for operating a semiconductor structure, characterized in that, The operation method includes: A first programming operation is performed on the memory cell coupled to the first word line among the plurality of memory cells of the semiconductor structure; Perform a second programming operation on multiple dummy units of the semiconductor structure; Apply a first through voltage to the second word line; apply a second through voltage different from the first through voltage to the third word line; and acquire a first current through the memory string; The semiconductor structure includes a memory array configured to perform a first operation and peripheral circuitry coupled to the memory array; the memory array includes a memory string; a first end of the memory string is connected to a source line and a second end is connected to a bit line; the memory string includes a plurality of memory cells and a plurality of dummy cells; the plurality of memory cells includes a first memory cell and a second memory cell; a first word line is coupled to the first memory cell, a second word line is coupled to the second memory cell, and a third word line is coupled to the plurality of dummy memory cells.

23. The operating method according to claim 22, characterized in that, The operation method includes: If the first current is less than the first preset value, the second programming operation is completed.

24. The operating method according to claim 22, characterized in that, The operation method includes: Based on the first current being greater than or equal to a first preset value, the programming voltage of the second programming operation is increased, and the second programming operation continues to be executed; and Continue applying the first through voltage to the second word line and the second through voltage to the third word line to obtain the corresponding first current; If the first current is less than the first preset value, the second programming operation is completed.

25. The operating method according to claim 22, characterized in that, The operation method includes: During the execution of the first programming operation, a programming voltage is applied to the first word line in such a way as applying a plurality of first step pulse voltages; the difference between two adjacent first step pulse voltages is the first step long voltage; During the execution of the second programming operation, a programming voltage is applied to the third word line in such a way as applying a plurality of second step pulse voltages; the difference between two adjacent second step pulse voltages is the second step voltage; Wherein, the pulse width of the second step pulse voltage is less than the pulse width of the first step pulse voltage, or the second step voltage is less than the first step voltage.

26. The operating method according to claim 22, characterized in that, The operation method further includes: During a read operation on a memory cell coupled to the first word line, a read voltage is applied to the first word line, a first pass voltage is applied to the second word line, and a first operating voltage less than the second pass voltage is applied to the third word line, causing the plurality of dummy cells to operate in the linear region.

27. The operating method according to claim 22, characterized in that, The operation method further includes: When the first programming operation is performed, the memory cell coupled to the first word line has a first threshold voltage; The second programming operation is performed, wherein one of the plurality of dummy units has a second threshold voltage; the second threshold voltage is greater than the first threshold voltage; During a read operation on a memory cell coupled to the first word line, a read voltage is applied to the first word line, a first pass voltage is applied to the second word line, and a second operating voltage is applied to the third word line; the second operating voltage is less than the first pass voltage.

28. The operating method according to claim 22, characterized in that, The operation method further includes: According to the memory cell coupled to the first word line being located at a first position in the memory string, during the execution of a first read operation on the memory cell coupled to the first word line, a read voltage is applied to the first word line, a third pass voltage is applied to the second word line, and a third operating voltage is applied to the third word line; According to the memory cell coupled to the first word line being located at a second position in the memory string, during the second read operation performed on the memory cell coupled to the first word line, the read voltage is applied to the first word line, the fourth pass voltage is applied to the second word line, and the third operating voltage is applied to the third word line; Wherein, the first position is closer to the bit line than the second position, and the third through voltage is greater than the fourth through voltage.

29. The operating method according to claim 22, characterized in that, The plurality of dummy cells include bottom dummy cells located between the source line and the plurality of memory cells, or top dummy cells located between the bit line and the plurality of memory cells.

30. The operating method according to claim 22, characterized in that, The operation method further includes: A read operation is performed on the corresponding memory cell in the same column coupled to the first word line to obtain the second current passing through the bit line, and the result of the first operation is determined based on the second current; In this configuration, the first end of a plurality of memory strings located in the same column is connected to the source line, and the second end is connected to the bit line; the first word line is coupled to the corresponding memory cell located in the same column of the plurality of memory strings.

31. The operating method according to claim 22, characterized in that, The third word line includes a first portion and a plurality of second portions connected to the first portion; a first end of each second portion is connected to the gate terminal of a corresponding dummy cell; a second end of each second portion is connected to the first portion; wherein the first portion is configured to receive the second through voltage.

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