Semiconductor device and operating method thereof, and computing and storage device

Abstract

The present disclosure provides a semiconductor device and an operating method thereof, and a storage-computing device. The semiconductor device comprises: a memory cell array comprising a plurality of memory strings; wherein each memory string comprises a plurality of memory cells connected in series; a peripheral circuit coupled to the memory cell array through a plurality of word lines and a plurality of bit lines; the plurality of word lines comprises at least one first word line and at least one second word line; the peripheral circuit is configured to: perform a first programming operation on the memory cells coupled to the first word line; after performing the first programming operation, perform a first reading operation to obtain a first current passing through a single memory string; perform a second programming operation on the memory cells coupled to the second word line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device and its operating method, and a memory computing device. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] This disclosure provides a semiconductor device, its operation method, and a memory computing device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including:

[0005] A storage cell array comprising multiple storage strings; wherein each storage string comprises multiple storage cells connected in series;

[0006] The peripheral circuitry is coupled to the memory cell array via multiple word lines and multiple bit lines; the multiple word lines include at least one first word line and at least one second word line; the peripheral circuitry is configured as follows:

[0007] Perform a first programming operation on the memory cell coupled to the first word line;

[0008] After performing the first programming operation, a first read operation is performed to obtain the first current passing through a single memory string;

[0009] Perform a second programming operation on the memory cell coupled to the second word line.

[0010] In some embodiments, the peripheral circuit is specifically configured as follows:

[0011] In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cell coupled to the second word line;

[0012] After performing the second programming operation, the first read operation is performed again until the first current passing through each of the storage strings during the first read operation is less than or equal to the preset value.

[0013] In some embodiments, the peripheral circuit is specifically configured as follows:

[0014] In response to a first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the second word line on the memory strings where the first current is greater than the preset value.

[0015] And perform a programmable disable operation on the memory cells coupled to the second word line on the memory string whose first current is less than or equal to the preset value.

[0016] In some embodiments, the word lines include M second word lines; where M is an integer greater than 1; the peripheral circuitry is specifically configured as follows:

[0017] After performing the second programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤j≤M-1;

[0018] In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the (j+1)th second word line on the memory strings where the first current is greater than the preset value, and the first read operation is performed again until the first current passing through each memory string during the first read operation is less than or equal to the preset value.

[0019] In some embodiments, the second programming operation includes N sub-programming operations; where N is an integer greater than 1; the peripheral circuit is specifically configured as follows:

[0020] After performing the i-th subprogramming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤i≤N-1;

[0021] In response to the first current passing through at least one of the memory strings being greater than a preset value, an (i+1)th subprogramming operation is performed on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, and the first read operation is performed again; wherein the voltage applied to the second word line by the (i+1)th subprogramming operation is greater than the voltage applied to the second word line by the ith subprogramming operation.

[0022] After performing the second programming operation for the memory cell coupled to the j-th second word line for the Nth time, and performing the first read operation again, in response to the first current passing through at least one of the memory strings being greater than a preset value, a first sub-programming operation is performed on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value.

[0023] In some embodiments, the voltage applied to the j-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line.

[0024] In some embodiments, the peripheral circuit is specifically configured as follows:

[0025] A first voltage is applied to the second word line to turn on the memory cell coupled to the second word line in order to perform the first read operation;

[0026] A second voltage is applied to the second word line to perform a verification operation of the second programming operation; wherein the first voltage is greater than the second voltage.

[0027] In some embodiments, the plurality of word lines further includes at least one third word line; the peripheral circuitry is specifically configured as follows:

[0028] A first voltage is applied to the second word line during a first time period, and a third voltage is applied to the third word line during a second time period to obtain a first current passing through the memory string during the second time period; wherein the start time of the second time period is later than the start time of the first time period, or the start time of the second time period is the same as the start time of the first time period;

[0029] A fourth voltage is applied to the first word line and the third word line to turn on the memory cell coupled to the first word line and the third word line to perform the second programming operation; wherein the fourth voltage is greater than the third voltage.

[0030] In some embodiments, the peripheral circuit is further configured to:

[0031] Based on the first current passing through the storage string during the first read operation, the voltage applied to the second word line during the second programming operation is determined.

[0032] In some embodiments, multiple memory strings located in the same column are coupled to the same bit line; each memory string further includes a selection transistor; the peripheral circuitry is further configured to:

[0033] The first programming operation is performed on the storage unit coupled to the first word line based on the weight information;

[0034] In response to the first current passing through each of the memory strings during the first read operation being less than or equal to the preset value, a third read operation is performed to control the selection transistors of each of the memory strings to be turned off or on based on the input data, and to determine the second current output by the bit line.

[0035] The simulation calculation information is determined based on the second current.

[0036] Secondly, embodiments of this disclosure provide a method for operating a semiconductor device, the semiconductor device comprising:

[0037] A storage cell array comprising multiple storage strings; wherein each storage string comprises multiple storage cells connected in series;

[0038] The peripheral circuitry is coupled to the memory cell array via multiple word lines and multiple bit lines; the multiple word lines include at least one first word line and at least one second word line.

[0039] The operation method includes:

[0040] Perform a first programming operation on the memory cell coupled to the first word line;

[0041] After performing the first programming operation, a first read operation is performed to obtain the first current passing through a single memory string;

[0042] A second programming operation is performed on the memory cell coupled to the second word line.

[0043] In some embodiments, the operating method further includes:

[0044] In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cell coupled to the second word line;

[0045] After performing the second programming operation, the first read operation is performed again until the first current passing through each of the storage strings during the first read operation is less than or equal to the preset value.

[0046] In some embodiments, performing a second programming operation on the memory cell coupled to the second word line in response to a first current passing through at least one of the memory strings being greater than a preset value includes:

[0047] In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the second word line on the memory strings where the first current is greater than the preset value;

[0048] The operation method further includes:

[0049] A programmable disable operation is performed on the memory cell coupled to the second word line on the memory string whose first current is less than or equal to the preset value.

[0050] In some embodiments, the word lines include M second word lines; where M is an integer greater than 1; the operation method specifically includes:

[0051] After performing the second programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤j≤M-1;

[0052] In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the (j+1)th second word line on the memory strings where the first current is greater than the preset value, and the first read operation is performed again until the first current passing through each memory string during the first read operation is less than or equal to the preset value.

[0053] In some embodiments, the second programming operation includes N sub-programming operations; where N is an integer greater than 1; the operation method specifically includes:

[0054] After performing the i-th subprogramming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤i≤N-1;

[0055] In response to the first current passing through at least one of the memory strings being greater than a preset value, an (i+1)th subprogramming operation is performed on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, and the first read operation is performed again; wherein the voltage applied to the second word line by the (i+1)th subprogramming operation is greater than the voltage applied to the second word line by the ith subprogramming operation.

[0056] After performing the second programming operation for the memory cell coupled to the j-th second word line for the Nth time, and performing the first read operation again, in response to the first current passing through at least one of the memory strings being greater than a preset value, a first sub-programming operation is performed on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value.

[0057] In some embodiments, the voltage applied to the j-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line.

[0058] In some embodiments, the operation method specifically includes:

[0059] A first voltage is applied to the second word line to turn on the memory cell coupled to the second word line in order to perform the first read operation;

[0060] A second voltage is applied to the second word line to perform a verification operation of the second programming operation; wherein the first voltage is greater than the second voltage.

[0061] In some embodiments, the plurality of character lines further includes at least one third character line; the operation method specifically includes:

[0062] A first voltage is applied to the second word line during a first time period, and a third voltage is applied to the third word line during a second time period to obtain a first current passing through the memory string during the second time period; wherein the start time of the second time period is later than the start time of the first time period, or the start time of the second time period is the same as the start time of the first time period;

[0063] A fourth voltage is applied to the first word line and the third word line to turn on the memory cell coupled to the first word line and the third word line to perform the second programming operation; wherein the fourth voltage is greater than the third voltage.

[0064] In some embodiments, the operating method further includes:

[0065] Based on the first current passing through the storage string during the first read operation, the voltage applied to the second word line during the second programming operation is determined.

[0066] In some embodiments, multiple memory strings located in the same column are coupled to the same bit line; each memory string further includes a selection transistor; the operation method further includes:

[0067] The first programming operation is performed on the storage unit coupled to the first word line based on the weight information;

[0068] In response to the first current passing through each of the memory strings during the first read operation being less than or equal to the preset value, a third read operation is performed, the selection transistors of each of the memory strings are controlled to turn off or on based on the input data, and the current output by the bit line is determined;

[0069] The simulation calculation information is determined based on the current output from the bit line.

[0070] Thirdly, embodiments of this disclosure provide an in-memory computing device, comprising: one or more semiconductor devices as described in the above embodiments; the semiconductor devices are configured to: perform a first operation on weight information and input data to obtain analog computing information;

[0071] A processing circuit, coupled to the semiconductor device; the processing circuit is configured to determine the calculation result based on the analog calculation information.

[0072] In some embodiments, the processing circuit includes:

[0073] An analog-to-digital converter circuit is coupled to the semiconductor device; the analog-to-digital converter circuit is configured to convert the analog calculation information into digital information.

[0074] A data processing circuit is coupled to the analog-to-digital conversion circuit; the data processing circuit is configured to perform a second operation on the digital information to determine the operation result.

[0075] In some embodiments, the processing circuit further includes:

[0076] A control circuit is coupled to the semiconductor device; the control circuit is configured to control the semiconductor device to perform the first operation.

[0077] In this embodiment, after the peripheral circuit performs a first programming operation on the memory cells on the first word line to input weight information, it performs a first read operation to obtain the first current passing through each memory string. Then, it performs a second programming operation on the memory cells on the second word line to compensate for the current differences between the memory strings. In this way, the peripheral circuit can make the current passing through each memory string as consistent as possible during memory computation, thereby improving the inference accuracy of memory computation. Attached Figure Description

[0078] Figure 1 A schematic diagram of an exemplary in-memory computing device provided in an embodiment of this disclosure;

[0079] Figure 2 A schematic diagram of an exemplary semiconductor device provided in an embodiment of this disclosure;

[0080] Figure 3 This is a schematic diagram of the structure of a three-dimensional NAND-type memory cell array provided in an embodiment of the present disclosure;

[0081] Figure 4 A schematic diagram of a memory cell array including multiple memory surfaces is provided for an embodiment of this disclosure;

[0082] Figure 5 A cross-sectional schematic diagram of an exemplary memory cell array including memory strings, provided for an embodiment of this disclosure;

[0083] Figure 6 A schematic diagram of an exemplary peripheral circuit provided in an embodiment of this disclosure;

[0084] Figure 7 Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 1 ;

[0085] Figure 8 Schematic diagram of a semiconductor device provided in an embodiment of this disclosure Figure 2 ;

[0086] Figure 9 A schematic diagram of the threshold voltage distribution state of a memory cell provided in an embodiment of this disclosure. Figure 1 ;

[0087] Figure 10 A schematic diagram of the threshold voltage distribution state of a memory cell provided in an embodiment of this disclosure. Figure 2 ;

[0088] Figure 11 The operation steps for compensating the target storage string current provided in an embodiment of this disclosure are as follows: Figure 1 ;

[0089] Figure 12 The operation steps for compensating the target storage string current provided in an embodiment of this disclosure are as follows: Figure 2 ;

[0090] Figure 13 A schematic diagram of the voltage waveform during the compensation of storage string current provided in an embodiment of this disclosure. Figure 1 ;

[0091] Figure 14 A schematic diagram of the voltage waveform during the compensation of storage string current provided in an embodiment of this disclosure. Figure 2 ;

[0092] Figure 15 A flowchart illustrating the steps of an operation method for a semiconductor device provided in an embodiment of this disclosure;

[0093] Figure 16 This is a three-dimensional structural schematic diagram of a memory computing device provided in an embodiment of the present disclosure;

[0094] Figure 17 A schematic diagram of an exemplary system with a storage computing device provided in an embodiment of this disclosure. Detailed Implementation

[0095] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0096] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0097] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0098] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0099] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0100] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0101] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will provide a detailed introduction to NAND flash memory.

[0102] Figure 1This is a schematic diagram of an exemplary in-memory computing device 100 provided in an embodiment of the present disclosure. The in-memory computing device 100 includes a processing circuit 200 and a semiconductor device 300. The processing circuit 200 and the semiconductor device 300 can be connected by bonding; wherein, the processing circuit 200 may include an analog-to-digital converter circuit and a data processing circuit; the semiconductor device 300 includes a memory cell array 301 and at least a portion of peripheral circuitry 302 coupled to the memory cell array 301; the analog-to-digital converter circuit is configured to convert analog computation information obtained by the semiconductor device 300 performing operations into digital information; the data processing circuit is configured to determine the operation result based on the analog computation information.

[0103] In some embodiments, the processing circuit 200 and the semiconductor device 300 are in different planes and stacked on top of each other. Furthermore, the memory cell array 301 and the peripheral circuit 302 in the semiconductor device 300 can be in different planes and stacked on top of each other, thereby reducing the planar size of the semiconductor device.

[0104] In some embodiments, the processing circuit 200 and the semiconductor device 300 may be formed in parallel on different substrates, for example, the processing circuit 200 may be formed on a first substrate, the memory cell array 301 may be formed on a second substrate, and the peripheral circuit 302 may be formed on a third substrate. They are then stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding.

[0105] In this embodiment of the disclosure, by vertically integrating the processing circuit 200 and the semiconductor device 300, and by vertically separating the processing circuit 200, the memory cell array 301 and the peripheral circuit 302 into different planes, the chip size can be reduced and the storage density can be increased.

[0106] In embodiments of this disclosure, the semiconductor device 300 includes a first semiconductor structure having a memory cell array 301 and a second semiconductor structure having at least a portion of peripheral circuitry 302. In some embodiments, a portion of the peripheral circuitry is formed in the second semiconductor structure, and another portion is formed in the first semiconductor structure. In other words, the peripheral circuitry can be divided into two parts, one part of which is formed together with the memory cell array in the first semiconductor structure, and the other part is formed in the second semiconductor structure. Exemplarily, in embodiments of this disclosure, a page buffer, for example, in the peripheral circuitry can be formed in the first semiconductor structure.

[0107] In other embodiments, the peripheral circuitry may be entirely formed within the second semiconductor structure. It should be noted that this disclosure uses the example of the peripheral circuitry being entirely formed within the second semiconductor structure for illustration.

[0108] Figure 2This is a schematic diagram of an exemplary semiconductor device 300 including peripheral circuitry 302 and a memory cell array 301, provided for embodiments of this disclosure. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 305 are NAND memory cells, provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0109] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0110] like Figure 2As shown, each memory string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of memory strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0111] like Figure 2 As shown, memory strings 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0112] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, bottom select line 309, and top select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory cell array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0113] Figure 3 This is a schematic diagram of the structure of a three-dimensional NAND-type memory cell array provided in an embodiment of this disclosure.

[0114] Among them, the word line WL, bit line BL, common source pole line CSL, bottom select line BSL, and top select line TSL can be referenced. Figure 2 The corresponding embodiments will be understood and will not be repeated here. Furthermore, the memory cell array may also include dummy word lines, such as the top dummy word line Top_DMY and the bottom dummy word line Btm_DMY. It should be noted that dummy word lines are not limited to being located at the top and bottom of the memory cell array; they can also be located in the middle area of ​​the memory cell array.

[0115] Figure 4 This is a schematic diagram of a memory cell array including multiple storage surfaces, provided as an embodiment of this disclosure. Here, a three-dimensional NAND memory cell array is used as an example for illustration. Figure 4 As shown, a storage cell array can include multiple storage planes, such as four storage planes: Plane0, Plane1, Plane2, and Plane3. Each storage plane includes multiple storage blocks, such as n storage blocks from Block0 to Blockn-1.

[0116] Figure 5 This is a cross-sectional schematic diagram of an exemplary storage cell array 301 including storage strings 304, provided as an embodiment of this disclosure. Figure 5 As shown, the stacked structure 320 includes a plurality of gate layers 321 and a plurality of insulating layers 322 alternately stacked in sequence, and a memory string 304 perpendicularly penetrating the gate layers 321 and the insulating layers 322. The gate layers 321 and the insulating layers 322 can be stacked alternately, and two adjacent gate layers 321 are separated by an insulating layer 322. The number of memory cells included in the memory cell array is mainly related to the number of pairs of gate layers 321 and insulating layers 322 in the stacked structure 320.

[0117] The constituent materials of the gate layer 321 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 321 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 321 includes a doped polysilicon layer. Each gate layer 321 may include a control gate surrounding a memory cell. The gate layer 321 at the top of the stack 320 may extend laterally as a top select line, the gate layer 321 at the bottom of the stack 320 may extend laterally as a bottom select line, and the gate layer 321 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0118] In some embodiments, the stacked structure 320 may be disposed on the semiconductor layer 330. The semiconductor layer 330 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include the semiconductor layer.

[0119] In some embodiments, the memory string 304 includes a channel structure extending vertically through the stacked structure 320. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0120] Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register set 406, a flash memory interface 407 (I / F), and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6Additional peripheral circuitry not shown. Peripheral circuitry 302 can be coupled to memory cell array 301 via bit lines, word lines, source lines, BSL and TSL, etc.

[0121] Page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory cell array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory strings by applying a bit line voltage generated from voltage generator 404.

[0122] The line decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of the memory cell array 301 and to select / deselect word lines of the memory blocks. The line decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the line decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the line decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0123] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register set 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bitline driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0124] In some embodiments, reference Figures 1 to 3 The semiconductor device 300 can perform a first operation on the weight information and input data to obtain analog calculation information. For example, the peripheral circuit 302 can program the memory cells 305 coupled to each word line 312 based on the weight information, so that each memory cell 305 stores the corresponding calculation weights. For example, multiple memory cells 305 in the memory cell array 301 can be used to store a weight matrix. The peripheral circuit 302 can also control the on or off of the top selection transistor 306 in the corresponding memory string 304 based on the input data. For example, the value of each bit of the input data ("0" or "1") can correspond to a top selection transistor of a memory string 304. The opening or closing of 306 allows for the input of data and weight information to the memory cell array 301. The peripheral circuit 302 then performs a read operation to determine the current flowing through the bit line 311 coupled to multiple memory strings 304. This means the multiple memory strings 304 on the bit line 311 operate in parallel, thus performing addition based on Kirchhoff's laws. Next, the peripheral circuit 302 determines analog calculation information based on the current flowing through the bit line 311. For example, the sensing amplifier 401 in the peripheral circuit 302 can be used to convert the current output from the bit line 311 into analog calculation information. It should be noted that the threshold voltage distribution state of the memory cell 305 can include an erase state and at least one programmed state. The resistance value of the memory cell 305 differs between the erase state and each programmed state. Therefore, the memory cell 305 can be programmed into various programmed states to store the corresponding calculation weights.

[0125] The processing circuit 200 can determine the final calculation result based on the analog calculation information output by the semiconductor device 300. The processing circuit 200 includes an analog-to-digital conversion circuit, a data processing circuit, and a control circuit. For example, the analog-to-digital conversion circuit can convert the received analog calculation information into digital information; the data processing circuit can perform a second operation on the digital information to generate a calculation result, such as the second operation including at least one of compensation, activation, shift, or pooling operations; the control circuit can be used to control the semiconductor device 300 to perform the aforementioned first operation, for example, the control circuit controls the semiconductor device 300 to perform programming, reading, or other operations on the corresponding memory units.

[0126] Understandably, the above addition operation is implemented by multiple memory strings 304 operating in parallel. The more memory strings 304 coupled to a single bit line 311, the higher the computing power. However, due to factors such as the different weights stored in each memory string 304, the differences in physical performance of each memory string 304 caused by the manufacturing process of the memory cell array 301, and the reliability of the semiconductor device 300, the current passing through each memory string 304 will differ when performing a read operation to implement the addition operation. This widens the current distribution and ultimately leads to a decrease in the accuracy of the memory operation.

[0127] like Figure 7 As shown, this disclosure provides a semiconductor device 500, including: a memory cell array 501, including a plurality of memory strings 504; wherein each memory string 504 includes a plurality of memory cells 505 connected in series; peripheral circuitry 502, coupled to the memory cell array 501 via a plurality of word lines 512 and a plurality of bit lines 511; the plurality of word lines 512 include at least one first word line 512a and at least one second word line 512b; the peripheral circuitry 502 is configured to: perform a first programming operation on the memory cell 505 coupled to the first word line 512a; after performing the first programming operation, perform a first read operation to obtain a first current passing through a single memory string 504; and perform a second programming operation on the memory cell 505 coupled to the second word line 512b.

[0128] In this embodiment, the semiconductor device 500 includes a memory cell array 501 and peripheral circuits 502. Here, the memory cell array 501 is described as a three-dimensional NAND type memory cell array. The memory cell array 501 and peripheral circuits 502 can be understood by referring to the memory cell array 301 and peripheral circuits 302 in the above embodiments, and will not be described again here.

[0129] Multiple memory cells 505 in the memory cell array 501 can be coupled to the peripheral circuit 502 by at least one first word line 512a and at least one second word line 512b. The memory cell 505 coupled to the first word line 512a can be used to store computational weights, while the memory cell 505 coupled to the second word line 512b is not used to store computational weights. The memory cell 505 coupled to the second word line 512b can be programmed to at least one programmed state to compensate for the various memory strings 504, making the current flowing through each memory string 504 as consistent as possible during computation. In some embodiments, the second word line 512b can be a dummy word line or a core word line.

[0130] For example, the peripheral circuit 502 can perform a first programming operation on a plurality of memory cells 505 coupled to the first word line 512a based on weight information, thereby causing each memory cell 505 to store a corresponding calculated weight. After performing the first programming operation, the peripheral circuit 502 can perform a first read operation to determine the first current passing through each memory string 504 one by one. In some embodiments, the first read operation may include L sub-read operations, each of which corresponds to L memory strings 504, and each sub-read operation is used to determine the first current passing through a corresponding memory string 504, where L is a positive integer. In this way, the peripheral circuit 502 can perform a second programming operation on the memory cells 505 coupled to the second word line 512b based on the first current passing through each memory string 504, ultimately making the first current passing through each memory string 504 as consistent as possible, for example, making the first current passing through each memory string 504 decrease to almost the same current value. It should be noted that after the memory cell 505 is programmed (such as the second programming operation mentioned above), its threshold voltage will increase, the resistance of the memory cell 505 itself will increase, and therefore the first current passing through the corresponding memory string 504 will decrease.

[0131] In this embodiment, after performing a first programming operation on the memory cell 505 on the first word line 512a to input weight information, the peripheral circuit 502 performs a first read operation to obtain the first current passing through each memory string 504. Then, it performs a second programming operation on the memory cell 505 on the second word line 512b to compensate for the current differences between the memory strings 504. In this way, the peripheral circuit 502 can make the current passing through each memory string 504 as consistent as possible during memory computation, thereby improving the inference accuracy of memory computation.

[0132] In some embodiments, before performing a first programming operation on the plurality of memory cells 505 coupled to the first word line 512a to input weight information, the peripheral circuit 502 may also perform an erase operation on all memory cells 505 coupled to the second word line 512b, so that all memory cells 505 coupled to the second word line 512b are restored to the erased state.

[0133] In some embodiments, the peripheral circuit 502 is specifically configured to: perform a second programming operation on the memory cell 505 coupled to the second word line 512b in response to the first current passing through at least one of the memory strings 504 being greater than a preset value; and after performing the second programming operation, perform the first read operation again until the first current passing through each of the memory strings 504 during the first read operation is less than or equal to the preset value.

[0134] In this embodiment, when the first current flowing through at least one memory string 504 is greater than a preset value, the peripheral circuit 502 performs a second programming operation on the memory cell 505 coupled to the second word line 512b. Exemplarily, after performing the first programming operation, the peripheral circuit 502 can perform a first read operation to determine the first current flowing through each memory string 504, thereby identifying memory strings 504 whose first current is greater than a preset value (e.g., 40nA). Thus, the peripheral circuit 502 can perform a second programming operation on the memory cells 505 coupled to the second word line 512b on memory strings 504 whose first current is greater than the preset value, ultimately making the first current flowing through each memory string 504 close to the preset value, i.e., the current flowing through each memory string 504 is as consistent as possible.

[0135] After performing a second programming operation on the memory cell 505 coupled to the second word line 512b, the peripheral circuit 502 can perform a first read operation again to determine that among the one or more memory strings 504 corresponding to the memory cell 505 after the second programming operation, the first current passing through them is still greater than a preset value. Thus, the peripheral circuit 502 can perform the second programming operation again on the memory strings 504 whose first current still exceeds the preset value until the first current passing through each memory string 504 during the first read operation is less than or equal to the preset value. In other words, the peripheral circuit 502 can repeatedly perform the second programming operation and the first read operation until the first current passing through each memory string 504 during the first read operation is less than or equal to the preset value, ensuring that the current passing through each memory string 504 is as consistent as possible, thereby improving the inference accuracy of the memory operation.

[0136] In some embodiments, the storage string 504 detected in each first read operation is the storage string 504 whose first current was greater than a preset value in the previous first read operation. For storage strings 504 whose first current was less than or equal to the preset value in the previous first read operation, there is no need to perform the second programming operation and the first read operation again, thereby improving storage efficiency and saving energy.

[0137] In some embodiments, the peripheral circuit 502 is specifically configured to: in response to a first current passing through at least one of the memory strings 504 being greater than a preset value, perform a second programming operation on the memory cells 505 coupled to the second word line 512b on the memory strings 504 where the first current is greater than the preset value, and perform a disabling programming operation on the memory cells 505 coupled to the second word line 512b on the memory strings 504 where the first current is less than or equal to the preset value.

[0138] In this embodiment, the peripheral circuit 502 can determine the first current flowing through each memory string 504 through a first read operation. In response to the first current flowing through at least one memory string 504 being greater than a preset value, the peripheral circuit 502 performs a second programming operation on the memory cells 505 coupled to the second word line 512b on the memory string 504 whose first current is greater than the preset value, thereby further reducing the first current flowing through the memory string 504 whose first current is greater than the preset value. The peripheral circuit 502 also performs a disable programming operation on the memory cells 505 coupled to the second word line 512b on the memory string 504 whose first current is less than or equal to the preset value, thereby preventing the first current flowing through the memory string 504 whose first current is less than or equal to the preset value from further decreasing. Thus, after one or more rounds of the second programming operation and the first read operation, the first current flowing through each memory string 504 during the first read operation is less than or equal to the preset value, ensuring that the current flowing through each memory string 504 is as consistent as possible.

[0139] In some embodiments, the word line 512 includes M second word lines 512b; wherein M is an integer greater than 1; the peripheral circuit 502 is specifically configured as follows:

[0140] After performing the second programming operation on the storage cell 505 coupled to the j-th second word line 512b on the storage string 504 where the first current is greater than the preset value, the first read operation is performed again; where 1≤j≤M-1;

[0141] In response to the first current passing through at least one of the memory strings 504 being greater than a preset value, the second programming operation is performed on the memory cell 505 coupled to the (j+1)th second word line 512b on the memory string 504 where the first current is greater than the preset value, and the first read operation is performed again until the first current passing through each memory string 504 during the first read operation is less than or equal to the preset value.

[0142] In the embodiments disclosed herein, such as Figure 8 As shown, word line 512 includes M second word lines 512b. After performing the first programming operation, peripheral circuit 502 can perform a first read operation to obtain the first current passing through each memory string 504. When the first current passing through at least one memory string 504 is greater than a preset value, peripheral circuit 502 performs a second programming operation on the memory cell 505 coupled to the first second word line 512b and the target memory string 504a, thereby causing the memory cell 505 coupled to the first second word line 512b and the target memory string 504a to change from an erase state to a programming state. It should be noted that here, target memory string 504a refers to all memory strings 504 whose first current is greater than the preset value determined in each first read operation. For ease of understanding, Figure 8 Only one target storage string 504a is shown as an example, and is not intended to limit the scope of protection of this disclosure.

[0143] After performing a second programming operation on the memory cell 505 coupled to the first second word line 512b, the peripheral circuit 502 can perform a first read operation again. If the first current flowing through at least one memory string 504 is still greater than a preset value, the peripheral circuit 502 can perform a second programming operation on the memory cell 505 coupled to the second second word line 512b and the target memory string 504a, thereby causing the memory cell 505 coupled to the second second word line 512b and the target memory string 504a to change from an erased state to a programmed state. After one or more rounds of the second programming operation and the first read operation, the first current flowing through each memory string 504 can be made less than or equal to a preset value.

[0144] In some embodiments, when the second word-line coupled memory cell is configured as SLC, refer to Figure 9 The memory cell can be transitioned from erase state E to programmed state P1 via a second programming operation. When the memory cell coupled to the second word line is configured as MLC, TLC, QLC, or more levels, refer to... Figure 10 The memory cell can be transformed from the erase state E to the programmed state P1, P2...P through a second programming operation. NIt is understandable that the second programming operation can include multiple sub-programming operations. Each sub-programming operation is used to program the memory cell from a lower state to an adjacent higher state, such as E to P1, P1 to P2, and so on. N-1 To P N .

[0145] In some embodiments, the second programming operation may include a programming operation and a programming verification operation, wherein the programming verification operation is used to verify whether the memory cell has reached the corresponding programming state. In other embodiments, the second programming operation may also include only the programming operation and exclude the programming verification operation; that is, the efficiency of memory computation can be further improved by omitting the programming verification operation.

[0146] In some embodiments, a first read operation may be performed after each programming verification operation, and subsequent programming operations may be stopped if the first current on all memory strings is less than or equal to a preset value. That is, even if the memory cell is not programmed to the next programming state, subsequent programming can be stopped as long as the first current of the memory string reaches the preset value.

[0147] In some embodiments, such as Figure 8 As shown, the j-th second word line 512b and the (j+1)-th second word line 512b can be two physically adjacent second word lines 512b. For example, in the vertical direction, the j-th second word line 512b is located above the (j+1)-th second word line 512b. In other embodiments, the j-th second word line and the (j+1)-th second word line may not be physically adjacent, and the actual position and order of the 1st to Mth second word lines in the memory cell array can be adjusted according to design requirements. This disclosure does not impose excessive limitations.

[0148] In some embodiments, the voltage applied to the j-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line.

[0149] In this disclosure embodiment, reference is made to Figure 9 The memory cell coupled to the second word line can be configured as SLC, which includes two threshold voltage distribution states: erase state E and program state P1. (See also...) Figure 8After performing a second programming operation on a memory cell 505 coupled to a certain second word line 512b (such as the j-th second word line) (transforming the memory cell from erase state E to programming state P1), if the first current of at least one memory string 504 is still greater than a preset value, then the second programming operation continues to be performed on the memory cell 505 coupled to the next second word line 512b (such as the (j+1)-th second word line). It can be understood that, regardless of which second word line 512b, the second programming operation is to program the memory cell from erase state E to programming state P1. Therefore, the programming voltage of any two second word lines 512b is the same; that is, the voltage applied to the j-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the (j+1)-th second word line.

[0150] In this way, the peripheral circuit does not need to program the memory cell to a programming state above programming state P1, which helps to reduce the operation time of compensating for the storage string current, thereby improving the efficiency of storage and computing.

[0151] In some embodiments, the second programming operation includes N sub-programming operations; where N is an integer greater than 1; the peripheral circuit 502 is specifically configured as follows:

[0152] After performing the i-th subprogramming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤i≤N-1;

[0153] In response to the first current passing through at least one of the memory strings being greater than a preset value, an (i+1)th subprogramming operation is performed on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, and the first read operation is performed again; wherein the voltage applied to the second word line by the (i+1)th subprogramming operation is greater than the voltage applied to the second word line by the ith subprogramming operation.

[0154] After performing the second programming operation for the memory cell coupled to the j-th second word line for the Nth time, and performing the first read operation again, in response to the first current passing through at least one of the memory strings being greater than a preset value, a first sub-programming operation is performed on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value.

[0155] In this disclosure embodiment, reference is made to Figure 10The memory cell coupled to the second word line can be configured as MLC, TLC, QLC or more levels, that is, including two or more threshold voltage distribution states: erase state E, programming state P1, P2...P N At this point, the second programming operation includes N sub-programming operations. The first sub-programming operation is used to program the memory cell from the erase state E to the programming state P1, the second sub-programming operation is used to program the memory cell from the programming state P1 to the programming state P2, the third sub-programming operation is used to program the memory cell from the programming state P2 to the programming state P3, and so on. The Nth sub-programming operation is used to program the memory cell from the programming state P1 to the programming state P2. N-1 Programming to Programming State P N It should be noted that, Figure 10 and Figure 9 The programming state P1 shown can be different programming states, meaning that the threshold voltage ranges of the two are not the same.

[0156] After performing the first programming operation, the peripheral circuit 502 can perform a first read operation to obtain the first current passing through each memory string 504. In response to the first current passing through at least one memory string 504 being greater than a preset value, the peripheral circuit 502 performs a first sub-programming operation on the memory cell 505 coupled to the first second word line 512b and the target memory string 504a, thereby causing the memory cell 505 coupled to the first second word line 512b and the target memory string 504a to change from the erase state E to the programming state P1. After the first sub-programming operation, the peripheral circuit 502 performs the first read operation again. In response to the first current passing through at least one memory string 504 being greater than a preset value, the peripheral circuit 502 performs the second sub-programming operation on the memory cell 505 coupled to the first second word line 512b and the target memory string 504a, thereby causing the memory cell 505 coupled to the first second word line 512b and the target memory string 504a to change from programming state P1 to programming state P2... Thus, if the Nth sub-programming operation is performed on the memory cell 505 coupled to the first second word line 512b and the target memory string 504a (i.e., the memory cell 505 coupled to the first second word line 512b and the target memory string 504a has been programmed to the highest programming state P), the operation continues. N If, at least one memory string 504 still has a first current exceeding a preset value, the peripheral circuit 502 can perform a first sub-programming operation on the memory cell 505 coupled to the second word line 512b and the target memory string 504a. By repeating the above sub-programming operation and first read operation, the first current passing through each memory string 504 can be made less than or equal to the preset value.

[0157] In other words, in this embodiment of the present disclosure, a first sub-programming operation (programming from erase state E to programming state P1) can be performed on the memory cell 505 coupled to a certain second word line 512b (the j-th second word line). If at least one memory string 504 still has a first current greater than a preset value, then a second sub-programming operation (programming from programming state P1 to programming state P2) is performed on the memory cell 505 coupled to the second word line 512b (the j-th second word line)... until the Nth sub-programming operation (programming from programming state P1 to programming state P2) is performed on the memory cell 505 coupled to the second word line 512b (the j-th second word line). N-1 Programming to Programming State P N If at least one memory string 504 still has a first current greater than a preset value, then the first subprogramming operation is performed on the memory cell 505 coupled to the next second word line 512b (the (j+1)th second word line). Then, the above-mentioned second to Nth subprogramming operations are repeated on the memory cell 505 coupled to the next second word line 512b (the (j+1)th second word line) (assuming that the first current of at least one memory string is greater than a preset value in the first read operation after each subprogramming operation) until the first current on the target memory string is less than or equal to the preset value.

[0158] It is understandable that, since the first to Nth sub-programming operations are respectively used to program the memory unit to programming state P1 and programming state P... N Therefore, the programming voltage applied to the second word line by the (i+1)th sub-programming operation is greater than the programming voltage applied to the second word line by the ith sub-programming operation. This improves the current compensation accuracy of the memory string, which is beneficial for further improving the inference accuracy of memory computing.

[0159] In some embodiments, the type of storage unit can be configured according to actual design requirements, such as SLC, MLC, TLC, QLC, etc., that is, how many threshold voltage distribution states the storage unit will be programmed to during the second programming operation, thereby meeting the requirements for storage accuracy and storage efficiency in different scenarios. It can be understood that the more levels of storage units, the higher the current compensation accuracy of the storage string and the higher the storage accuracy; the fewer levels of storage units, the faster the programming process during current compensation of the storage string and the higher the storage efficiency.

[0160] For ease of understanding, Figure 11 and Figure 12 The following examples illustrate the operation steps of the peripheral circuit compensating for the current of the target memory string when the memory cell is configured as MLC, TLC, QLC or more levels, and when the memory cell is configured as SLC. The specific process has been described in detail in the above embodiments and will not be repeated here.

[0161] In some embodiments, the peripheral circuit is specifically configured to: apply a first voltage Vpass* to the second word line to turn on the memory cell coupled to the second word line to perform the first read operation; apply a second voltage Vpv to the second word line to perform a verification operation of the second programming operation; wherein the first voltage is greater than the second voltage.

[0162] In the embodiments disclosed herein, such as Figure 13 The diagram shows a voltage waveform during the compensation of the memory string current when the memory cell is configured as SLC. Figure 14 The diagram shows the voltage waveform during the compensation of memory string current when the memory cells are configured as MLC, TLC, QLC, or more levels. (Reference) Figure 13 The peripheral circuitry can apply a first voltage Vpass* to the second word line, turning on the memory cell coupled to the second word line to perform a first read operation, thereby determining the first current flowing through the corresponding memory string. Here, the first voltage Vpass* can be the voltage across the memory cell coupled to the second word line. The peripheral circuitry can also apply a second voltage Vpv to the second word line to perform a verification operation for the second programming operation, thereby determining whether the memory cell coupled to the second word line has reached programming state P1. Here, the second voltage Vpv can be the programming verification voltage corresponding to programming state P1. It is understood that, referring to... Figure 9 The first voltage, Vpass*, should be greater than the highest voltage of the programming state P1 to turn on the corresponding memory cell. The second voltage, Vpv, needs to be close to the lowest voltage of the programming state P1 to measure whether the memory cell has reached the second distribution state. Therefore, the first voltage, Vpass*, which serves as the pass voltage, is greater than the second voltage, Vpv, which serves as the programming verification voltage. It should be noted that, for ease of understanding, Figure 14 Only the programming phase of the second programming operation is shown, but the second programming operation may still include a programming phase and a programming verification phase.

[0163] In some embodiments, such as Figure 9 As shown, the plurality of word lines 512 further includes at least one third word line 512c; the peripheral circuit 502 is specifically configured to: apply a first voltage to the second word line 512b in a first time period, and apply a third voltage to the third word line 512c in a second time period to obtain a first current passing through the memory string during the second time period; wherein the start time of the second time period is later than the start time of the first time period, or the start time of the second time period is the same as the start time of the first time period; apply a fourth voltage to the first word line 512a and the third word line 512c to turn on the memory cell 505 coupled to the first word line 512a and the third word line 512c to perform the second programming operation; wherein the fourth voltage is greater than the third voltage.

[0164] In this embodiment of the disclosure, the peripheral circuit 502 can control the start of the first read operation by applying a corresponding voltage to the third word line 512c. For example, refer to... Figure 13 and Figure 14 The peripheral circuit can apply a first voltage Vpass* to each second word line in the first time period t1 to turn on the memory cells coupled to the target memory string, and apply the same or different fifth voltage Vpass_v to each first word line to turn on the memory cells coupled to the target memory string (the fifth voltage Vpass_v applied to any two first word lines can be the same or different). In the second time period t2, the peripheral circuit applies a third voltage Vrd* to the third word line to turn on the memory cells coupled to the target memory string. During the second time period t2, all memory cells on the entire target memory string are turned on, and the peripheral circuit acquires the first current passing through the target memory string during the second time period t2. It can be understood that the start time of the second time period t2 is later than the start time of the first time period t1, or the start time of the second time period t2 is the same as the start time of the first time period t1. This ensures that the peripheral circuit starts acquiring the first current passing through the target memory string when the memory cells coupled to the target memory string on the third word line are turned on.

[0165] In some embodiments, the peripheral circuitry may also apply a bit line read disable voltage (e.g., VSS, 0V) to the unselected bit line during a first time period t1 to prevent the first read operation from being performed on the unselected bit line; apply a first turn-on voltage Vtsg_v to the selected top select gate during the first time period t1 to turn on the selected top select gate; and apply a turn-off voltage (e.g., VSS, 0V) to the unselected top select gate during the first time period t1 to turn off the unselected top select gate. The peripheral circuitry may also apply a bit line read voltage Vbl to the selected bit line during a second time period t2 to obtain the first current passing through the target memory string via the selected bit line during the second time period t2.

[0166] In some embodiments, reference Figure 13 and Figure 14The peripheral circuitry can also apply a fourth voltage, Vpass*_P, to the first and third word lines to turn on the memory cells coupled to each of the first and third word lines; apply a bit line programming voltage (e.g., VSS, 0V) to the selected bit lines, apply a bit line disable programming voltage (e.g., VDD) to the unselected bit lines, apply a second turn-on voltage, Vtsg_p, to the selected top select gate to turn on the selected top select gate, apply a turn-off voltage (e.g., VSS, 0V) to the unselected top select gate; and apply a programming voltage, Vpgm, to the target second word line to perform a second programming operation. It is understood that the fourth voltage, Vpass*_P, is greater than the third voltage, Vrd*, meaning the word line pass voltage is greater than the word line read voltage. Furthermore, the fourth voltage, Vpass*_P, is also greater than or equal to the largest of several different fifth voltages, Vpass_v.

[0167] For example, the voltage generator in the peripheral circuit can be used to generate a variety of voltages, including the first voltage, second voltage, third voltage, fourth voltage, fifth voltage, first turn-on voltage and second turn-on voltage mentioned above.

[0168] In some embodiments, the programming voltage Vpgm can be a step-programming voltage or a fixed value; this disclosure does not impose excessive limitations.

[0169] In some embodiments, such as Figure 7 As shown, the peripheral circuit 502 is further configured to: determine the voltage applied to the second word line 512b in the second programming operation based on the first current passing through the memory string 504 in the first read operation.

[0170] In this embodiment of the disclosure, if the first current flowing through the storage string 504 during the first read operation is greater than a preset value, the peripheral circuit 502 can also determine the programming voltage (such as the programming voltage Vpgm in the above embodiment) applied to the second word line 512b during the second programming operation based on the magnitude of the first current flowing through the storage string 504 obtained from the first read operation. For example, if the difference between the first current flowing through the storage string 504 and the preset value is large, the peripheral circuit 502 can set the voltage applied to the second word line 512b during the next second programming operation to be relatively large; conversely, if the difference between the first current flowing through the storage string 504 and the preset value is small, the peripheral circuit 502 can set the programming voltage applied to the second word line 512b during the next second programming operation to be relatively small.

[0171] In some embodiments, such as Figure 7As shown, multiple memory strings 504 located in the same column are coupled to the same bit line 511; each memory string 504 also includes a selection transistor TSG / BSG; the peripheral circuit 502 is further configured to: perform a first programming operation on the memory cells 505 coupled to the first word line 512a based on weight information; perform a third read operation in response to the first current passing through each memory string 504 during the first read operation being less than or equal to the preset value, to control the selection transistor TSG of each memory string 504 to be turned off or on based on input data, and determine a second current output by the bit line 511; and determine analog calculation information based on the second current.

[0172] In this embodiment, the peripheral circuit 502 first programs the weight information into the corresponding storage cell 505 through a first programming operation; then, the peripheral circuit 502 compensates the current of each storage string 504 by performing a first read operation and a second programming operation, so that the current passing through each storage string 504 is as consistent as possible; then, the peripheral circuit 502 performs a third read operation, and controls the selection of transistor TSG / BSG in the corresponding storage string 504 to turn on or off based on the input data, and determines the second current output by the bit line 511, that is, to perform addition operation based on Kirchhoff's laws; finally, the peripheral circuit 502 determines the analog calculation information based on the second current output by the bit line 511.

[0173] Based on the above-described semiconductor device, this disclosure also provides an operation method for the semiconductor device, the semiconductor device comprising: a memory cell array including multiple memory strings; wherein each memory string includes multiple memory cells connected in series; peripheral circuitry coupled to the memory cell array via multiple word lines and multiple bit lines; the multiple word lines including at least one first word line and at least one second word line; such as Figure 15 As shown, the operation method includes the following steps:

[0174] Step S10: Perform a first programming operation on the memory cell coupled to the first word line;

[0175] Step S20: After performing the first programming operation, perform the first read operation to obtain the first current passing through a single memory string;

[0176] Step S30: Perform a second programming operation on the memory cell coupled to the second word line.

[0177] It should be understood that Figure 15 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 15 The steps shown can be adjusted in order according to actual needs.

[0178] In this embodiment, after the peripheral circuit performs a first programming operation on the memory cells on the first word line to input weight information, it performs a first read operation to obtain the first current passing through each memory string. Then, it performs a second programming operation on the memory cells on the second word line to compensate for the current differences between the memory strings. In this way, the peripheral circuit can make the current passing through each memory string as consistent as possible during memory computation, thereby improving the inference accuracy of memory computation.

[0179] In some embodiments, the operation method further includes: performing a second programming operation on the memory cell coupled to the second word line in response to the first current passing through at least one of the memory strings being greater than a preset value; and performing the first read operation again after performing the second programming operation until the first current passing through each of the memory strings during the first read operation is less than or equal to the preset value.

[0180] In some embodiments, performing a second programming operation on the memory cell coupled to the second word line in response to the first current passing through at least one of the memory strings being greater than a preset value includes: performing the second programming operation on the memory cell coupled to the second word line on the memory string where the first current is greater than the preset value in response to the first current passing through at least one of the memory strings being greater than the preset value; the operation method further includes: performing a disabling programming operation on the memory cell coupled to the second word line on the memory string where the first current is less than or equal to the preset value.

[0181] In some embodiments, the word line includes M second word lines; where M is an integer greater than 1; the operation method specifically includes: after performing a second programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, performing the first read operation again; where 1≤j≤M-1; in response to the first current passing through at least one memory string being greater than the preset value, performing the second programming operation on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value, and performing the first read operation again, until the first current passing through each memory string during the first read operation is less than or equal to the preset value.

[0182] In some embodiments, the second programming operation includes N sub-programming operations; where N is an integer greater than 1; the operation method specifically includes: after performing the i-th sub-programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, performing the first read operation again; where 1≤i≤N-1; in response to the first current passing through at least one memory string being greater than the preset value, performing the (i+1)-th sub-programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, and performing the first read operation again; where the voltage applied to the second word line by the (i+1)-th sub-programming operation is greater than the voltage applied to the second word line by the i-th sub-programming operation; after performing the N-th second programming operation on the memory cell coupled to the j-th second word line, and performing the first read operation again, in response to the first current passing through at least one memory string being greater than the preset value, performing the first sub-programming operation on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value.

[0183] In some embodiments, the voltage applied to the j-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line.

[0184] In some embodiments, the operation method specifically includes: applying a first voltage to the second word line to turn on the memory cell coupled to the second word line to perform the first read operation; applying a second voltage to the second word line to perform a verification operation of the second programming operation; wherein the first voltage is greater than the second voltage.

[0185] In some embodiments, the plurality of word lines further includes at least one third word line; the operation method specifically includes: applying a first voltage to the second word line in a first time period, and applying a third voltage to the third word line in a second time period to acquire a first current passing through the memory string during the second time period; wherein the start time of the second time period is later than the start time of the first time period, or the start time of the second time period is the same as the start time of the first time period; applying a fourth voltage to the first word line and the third word line to turn on the memory cell coupled to the first word line and the third word line to perform the second programming operation; wherein the fourth voltage is greater than the third voltage.

[0186] In some embodiments, the operation method further includes: determining the voltage applied to the second word line in the second programming operation based on the first current passing through the memory string in the first read operation.

[0187] In some embodiments, multiple memory strings located in the same column are coupled to the same bit line; each memory string further includes a selection transistor; the operation method further includes: performing a first programming operation on the memory cells coupled to the first word line based on weight information; performing a third read operation in response to a first current passing through each memory string during the first read operation being less than or equal to a preset value; controlling the selection transistors of each memory string to turn off or on based on input data; and determining the current output by the bit line; and determining analog calculation information based on the current output by the bit line.

[0188] The operation method of the semiconductor device mentioned in the above embodiments has been described in detail in the foregoing embodiments concerning semiconductor devices, and will not be repeated here for the sake of brevity.

[0189] Based on the above-described semiconductor devices, this disclosure also provides an in-memory computing device, comprising: one or more semiconductor devices as described in the above embodiments; the semiconductor devices being configured to: perform a first operation on weight information and input data to obtain simulated computation information; and a processing circuit coupled to the semiconductor devices; the processing circuit being configured to: determine the computation result based on the simulated computation information.

[0190] In some embodiments, the processing circuit includes: an analog-to-digital converter coupled to the semiconductor device; the analog-to-digital converter configured to convert the analog calculation information into digital information; and a data processing circuit coupled to the analog-to-digital converter; the data processing circuit configured to perform a second operation on the digital information to determine the operation result.

[0191] In some embodiments, the processing circuit further includes a control circuit coupled to the semiconductor device; the control circuit is configured to control the semiconductor device to perform the first operation.

[0192] like Figure 16 The diagram shown is a three-dimensional structural schematic of a memory computing device 600 provided in this disclosure. The memory computing device 600 includes a semiconductor device 500 composed of a memory cell array 501 and peripheral circuits 502, and a processing circuit 200 composed of an analog-to-digital converter 201, a data processing circuit 202, and a control circuit 203. The processing circuit 200 and the semiconductor device 500 can be understood with reference to the above embodiments, and will not be described again here.

[0193] like Figure 17The diagram illustrates an exemplary system with a memory computing device provided in this disclosure. System 700 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory computing device. System 700 may include one or more memory computing devices 600 and one or more other types of chips 800. Exemplarily, chip 800 includes, but is not limited to, sensor chips, memory chips, logic chips, etc. One or more memory computing devices 600 and one or more other types of chips 800 can be integrated in a package, such as a PCB (Printed Circuit Board) package. Thus, system 700 can be applied to different scenarios.

[0194] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0195] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0196] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A storage cell array comprising multiple storage strings; wherein each storage string comprises multiple storage cells connected in series; The peripheral circuitry is coupled to the memory cell array via multiple word lines and multiple bit lines; the multiple word lines include at least one first word line and at least one second word line; the peripheral circuitry is configured as follows: Perform a first programming operation on the memory cell coupled to the first word line; After performing the first programming operation, a first read operation is performed to obtain the first current passing through a single memory string; Perform a second programming operation on the memory cell coupled to the second word line.

2. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is specifically configured as follows: In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cell coupled to the second word line; After performing the second programming operation, the first read operation is performed again until the first current passing through each of the storage strings during the first read operation is less than or equal to the preset value.

3. The semiconductor device according to claim 2, characterized in that, The peripheral circuit is specifically configured as follows: In response to a first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the second word line on the memory strings where the first current is greater than the preset value. And perform a programmable disable operation on the memory cells coupled to the second word line on the memory string whose first current is less than or equal to the preset value.

4. The semiconductor device according to claim 3, characterized in that, The word line includes M second word lines; where M is an integer greater than 1; the peripheral circuit is specifically configured as follows: After performing the second programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤j≤M-1; In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the (j+1)th second word line on the memory strings where the first current is greater than the preset value, and the first read operation is performed again until the first current passing through each memory string during the first read operation is less than or equal to the preset value.

5. The semiconductor device according to claim 4, characterized in that, The second programming operation includes N sub-programming operations; where N is an integer greater than 1; the peripheral circuit is specifically configured as follows: After performing the i-th subprogramming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤i≤N-1; In response to the first current passing through at least one of the memory strings being greater than a preset value, an (i+1)th subprogramming operation is performed on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, and the first read operation is performed again; wherein the voltage applied to the second word line by the (i+1)th subprogramming operation is greater than the voltage applied to the second word line by the ith subprogramming operation. After performing the second programming operation for the memory cell coupled to the j-th second word line for the Nth time, and performing the first read operation again, in response to the first current passing through at least one of the memory strings being greater than a preset value, a first sub-programming operation is performed on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value.

6. The semiconductor device according to claim 4, characterized in that, When performing the second programming operation on the memory cell coupled to the j-th second word line, the voltage applied to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line.

7. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is specifically configured as follows: A first voltage is applied to the second word line to turn on the memory cell coupled to the second word line in order to perform the first read operation; A second voltage is applied to the second word line to perform a verification operation of the second programming operation; wherein the first voltage is greater than the second voltage.

8. The semiconductor device according to claim 1, characterized in that, The plurality of word lines also includes at least one third word line; the peripheral circuitry is specifically configured as follows: A first voltage is applied to the second word line during a first time period, and a third voltage is applied to the third word line during a second time period to obtain a first current passing through the memory string during the second time period; wherein the start time of the second time period is later than the start time of the first time period, or the start time of the second time period is the same as the start time of the first time period; A fourth voltage is applied to the first word line and the third word line to turn on the memory cell coupled to the first word line and the third word line to perform the second programming operation; wherein the fourth voltage is greater than the third voltage.

9. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is also configured to: Based on the first current passing through the storage string during the first read operation, the voltage applied to the second word line during the second programming operation is determined.

10. The semiconductor device according to claim 1, characterized in that, Multiple memory strings located in the same column are coupled to the same bit line; each memory string also includes a selection transistor; the peripheral circuitry is further configured to: The first programming operation is performed on the storage unit coupled to the first word line based on the weight information; In response to the first current passing through each of the memory strings during the first read operation being less than or equal to the preset value, a third read operation is performed to control the selection transistors of each of the memory strings to be turned off or on based on the input data, and to determine the second current output by the bit line. The simulation calculation information is determined based on the second current.

11. A method of operating a semiconductor device, characterized in that, The semiconductor device includes: A storage cell array comprising multiple storage strings; wherein each storage string comprises multiple storage cells connected in series; The peripheral circuitry is coupled to the memory cell array via multiple word lines and multiple bit lines; the multiple word lines include at least one first word line and at least one second word line. The operation method includes: Perform a first programming operation on the memory cell coupled to the first word line; After performing the first programming operation, a first read operation is performed to obtain the first current passing through a single memory string; A second programming operation is performed on the memory cell coupled to the second word line.

12. The operating method according to claim 11, characterized in that, The operation method further includes: In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cell coupled to the second word line; After performing the second programming operation, the first read operation is performed again until the first current passing through each of the storage strings during the first read operation is less than or equal to the preset value.

13. The operating method according to claim 12, characterized in that, The second programming operation performed on the memory cell coupled to the second word line in response to the first current passing through at least one of the memory strings being greater than a preset value includes: In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the second word line on the memory strings where the first current is greater than the preset value; The operation method further includes: A programmable disable operation is performed on the memory cell coupled to the second word line on the memory string whose first current is less than or equal to the preset value.

14. The operating method according to claim 13, characterized in that, The word lines include M second word lines; where M is an integer greater than 1; the operation method specifically includes: After performing the second programming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤j≤M-1; In response to the first current passing through at least one of the memory strings being greater than a preset value, the second programming operation is performed on the memory cells coupled to the (j+1)th second word line on the memory strings where the first current is greater than the preset value, and the first read operation is performed again until the first current passing through each memory string during the first read operation is less than or equal to the preset value.

15. The operating method according to claim 14, characterized in that, The second programming operation includes N sub-programming operations; where N is an integer greater than 1; the operation method specifically includes: After performing the i-th subprogramming operation on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, the first read operation is performed again; where 1≤i≤N-1; In response to the first current passing through at least one of the memory strings being greater than a preset value, an (i+1)th subprogramming operation is performed on the memory cell coupled to the j-th second word line on the memory string where the first current is greater than the preset value, and the first read operation is performed again; wherein the voltage applied to the second word line by the (i+1)th subprogramming operation is greater than the voltage applied to the second word line by the ith subprogramming operation. After performing the second programming operation for the memory cell coupled to the j-th second word line for the Nth time, and performing the first read operation again, in response to the first current passing through at least one of the memory strings being greater than a preset value, a first sub-programming operation is performed on the memory cell coupled to the (j+1)-th second word line on the memory string where the first current is greater than the preset value.

16. The operating method according to claim 14, characterized in that, When performing the second programming operation on the memory cell coupled to the j-th second word line, the voltage applied to the j-th second word line is equal to the voltage applied to the (j+1)-th second word line when performing the second programming operation on the memory cell coupled to the j-th second word line.

17. The operating method according to claim 11, characterized in that, The specific operation method includes: A first voltage is applied to the second word line to turn on the memory cell coupled to the second word line in order to perform the first read operation; A second voltage is applied to the second word line to perform a verification operation of the second programming operation; wherein the first voltage is greater than the second voltage.

18. The operating method according to claim 11, characterized in that, The plurality of character lines also includes at least one third character line; the operation method specifically includes: A first voltage is applied to the second word line during a first time period, and a third voltage is applied to the third word line during a second time period to obtain a first current passing through the memory string during the second time period; wherein the start time of the second time period is later than the start time of the first time period, or the start time of the second time period is the same as the start time of the first time period; A fourth voltage is applied to the first word line and the third word line to turn on the memory cell coupled to the first word line and the third word line to perform the second programming operation; wherein the fourth voltage is greater than the third voltage.

19. The operating method according to claim 11, characterized in that, The operation method further includes: Based on the first current passing through the storage string during the first read operation, the voltage applied to the second word line during the second programming operation is determined.

20. The operating method according to claim 11, characterized in that, Multiple memory strings located in the same column are coupled to the same bit line; each memory string further includes a selection transistor; the operation method further includes: The first programming operation is performed on the storage unit coupled to the first word line based on the weight information; In response to the first current passing through each of the memory strings during the first read operation being less than or equal to the preset value, a third read operation is performed, the selection transistors of each of the memory strings are controlled to turn off or on based on the input data, and the current output by the bit line is determined; The simulation calculation information is determined based on the current output from the bit line.

21. A storage computing device, characterized in that, include: One or more semiconductor devices as described in any one of claims 1 to 10; The semiconductor device is configured to perform a first operation on the weight information and input data to obtain analog calculation information; A processing circuit, coupled to the semiconductor device; the processing circuit is configured to determine the calculation result based on the analog calculation information.

22. The storage computing device according to claim 21, characterized in that, The processing circuit includes: An analog-to-digital converter circuit is coupled to the semiconductor device; the analog-to-digital converter circuit is configured to convert the analog calculation information into digital information. A data processing circuit is coupled to the analog-to-digital conversion circuit; the data processing circuit is configured to perform a second operation on the digital information to determine the operation result.

23. The memory computing device according to claim 22, characterized in that, The processing circuit further includes: A control circuit is coupled to the semiconductor device; the control circuit is configured to control the semiconductor device to perform the first operation.

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