NAND flash memory structure, method of manufacturing the same, and electronic device

Abstract

The application provides a NAND flash memory structure, a preparation method thereof and an electronic device. The NAND flash memory structure comprises: a memory cell region comprising even memory strings and odd memory strings, the even memory strings and the odd memory strings being respectively provided with even bit lines and odd bit lines; even selection transistors and odd selection transistors integrated in the memory cell region and respectively used for controlling the conduction state of the even bit lines and the odd bit lines; and a page buffer region coupled to the memory cell region through the even selection transistors and the odd selection transistors to program data signals into the memory cell region or read data signals from the memory cell region. The application can effectively reduce the number of high-voltage transistors required by the page buffer region, thereby significantly reducing the overall layout area of the NAND flash memory structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a NAND flash memory structure, its preparation method and electronic device. Background Technology

[0002] In today's information society, the importance of data storage is becoming increasingly prominent. As a key component of non-volatile memory (NVM), NAND Flash has captured more than 90% of the NVM market share. It is widely used in various electronic products, from everyday smartphones and tablets to enterprise-level data center storage devices and security monitoring systems, all of which rely on the support of NAND Flash.

[0003] With the continuous evolution of technology, to meet the market demand for high-capacity storage at low cost, high-capacity NAND Flash generally adopts a vertical stacking architecture, namely 3D NAND Flash. This architecture, by stacking storage cells vertically, greatly saves chip area, thereby effectively reducing costs. Compared with the traditional planar architecture, 3D stacking technology can pack more storage cells per unit area, significantly increasing storage capacity. However, for small and medium capacity NAND Flash (such as less than 128G), the planar architecture (Plane NAND Flash or 2D NAND Flash) still dominates. This is because within this capacity range, the planar architecture performs better in terms of cost control, while providing performance that meets specific application scenarios.

[0004] The physical characteristics of memory chips dictate that their chip area is directly proportional to their storage capacity, due to the limitation of the smallest storage cell. 3D NAND Flash can cleverly utilize vertical space by stacking storage cells to reduce chip area. However, 2D NAND Flash, constrained by its planar structure, cannot utilize vertical space to reduce chip area. Therefore, to maintain price competitiveness in the market, 2D NAND Flash typically achieves its goal of reducing chip area by optimizing its chip architecture.

[0005] In NAND Flash chip architecture, the page buffer architecture is crucial. Currently, the mainstream NAND Flash page buffer architectures are mainly of two types: interleaving architecture and all-bitline architecture. The outstanding advantage of the interleaving architecture lies in its efficient use of chip area, enabling more functions to be implemented within a limited chip space, thereby reducing costs. The all-bitline architecture, on the other hand, excels in read and write speeds, allowing for rapid data read and write operations. In applications where read and write speed requirements are not high, but cost is extremely sensitive, the more area-efficient interleaving architecture becomes a better choice. These devices typically do not require high-speed data read and write operations, but rather focus on achieving the largest possible storage capacity within a limited cost.

[0006] While interleaved architectures offer advantages in area utilization, existing interleaved architectures still suffer from excessive area consumption. With the increasing market demand for miniaturized, highly integrated products, further optimizing interleaved architectures to minimize chip area while maintaining cost advantages has become a crucial issue that urgently needs to be addressed in the current NAND Flash technology field.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a NAND flash memory structure, its fabrication method and electronic device, to solve the problem of excessive area occupied by the NAND flash memory structure in the prior art.

[0009] To achieve the above and other related objectives, the present invention provides a NAND flash memory structure, comprising: a memory cell region including even memory strings and odd memory strings, wherein the even memory strings and odd memory strings are respectively provided with an even number of bit lines and an odd number of bit lines; an even selection transistor and an odd selection transistor, integrated within the memory cell region, respectively used to control the conduction state of the even number of bit lines and the odd number of bit lines; and a page buffer, coupled to the memory cell region through the even selection transistor and the odd selection transistor, to program data signals into or read from the memory cell region.

[0010] Optionally, the even-numbered and odd-numbered memory strings each include a plurality of memory transistors, a source-select transistor, and a drain-select transistor. The plurality of memory transistors are configured in the form of a NAND string. The gate of the source-select transistor is connected to a source-select signal, the first terminal is connected to the first terminal of the plurality of memory transistors, and the second terminal is connected to a common-source line. The gate of the drain-select transistor is connected to a drain-select signal, the first terminal is connected to the second terminal of the plurality of memory transistors, and the second terminal is connected to one of the even-numbered bit lines and the odd-numbered bit lines.

[0011] Optionally, the page buffer includes multiple high-voltage transistors, each of which is simultaneously connected to a set of even-select transistors and odd-select transistors.

[0012] Optionally, the even storage string and the odd storage string are arranged alternately, and the even bit line and the odd bit line are arranged alternately.

[0013] Optionally, any adjacent even-select transistors and odd-select transistors are arranged in a staggered manner relative to the selection signal line. The gates of multiple even-select transistors are connected to an even-select signal line, and the gates of multiple odd-select transistors are connected to an odd-select signal line. The even-select signal line and the odd-select signal line are arranged in parallel.

[0014] Optionally, during a read operation, only one of the even-select transistor group and the odd-select transistor group is selected for each read operation.

[0015] Optionally, during the programming operation, only one of the even-selection transistor group and the odd-selection transistor group is selected in a single programming operation.

[0016] Optionally, the even and odd memory strings in the memory cell area adopt a two-dimensional planar architecture.

[0017] The present invention also provides a method for fabricating a NAND flash memory structure, the method comprising: fabricating even memory strings and odd memory strings in a memory cell region, wherein the even memory strings and odd memory strings are respectively provided with an even number of bit lines and an odd number of bit lines; fabricating even selection transistors and odd selection transistors in the edge region of the memory cell region, wherein the even selection transistors and odd selection transistors are respectively used to control the conduction state of the even number of bit lines and the odd number of bit lines; and fabricating a page buffer, wherein the page buffer is coupled to the memory cell region through even selection transistors and odd selection transistors to program data signals into or read data signals from the memory cell region.

[0018] The present invention also provides an electronic device comprising a NAND flash memory structure according to any of the above schemes.

[0019] As described above, the NAND flash memory structure, its fabrication method, and electronic device of the present invention have the following beneficial effects:

[0020] This patent proposes a novel interleaving architecture NAND flash memory structure. By integrating even-select transistors and odd-select transistors at the edges of the memory cell area, which control the switching of corresponding even-numbered and odd-numbered bit lines respectively, the page buffer only requires one set of high-voltage transistors. Each high-voltage transistor simultaneously controls one set of even-select transistors and one set of odd-select transistors, significantly reducing the number of high-voltage transistors required for the page buffer and thus significantly reducing the overall layout area of ​​the NAND flash memory structure. The novel interleaving architecture NAND flash memory structure proposed in this invention reduces the page buffer area by 20% compared to traditional interleaving architectures and by 50% compared to traditional full-word-line architectures. Attached Figure Description

[0021] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0022] Figure 1 The diagram shows the circuit principle of a NAND flash memory structure with a full bit-line structure and page buffer architecture.

[0023] Figure 2 This diagram shows the layout of a NAND flash memory structure with a full bit-line structure and page buffer architecture.

[0024] Figure 3 The diagram shows the circuit principle of a NAND flash memory structure with an interleaved page buffer architecture.

[0025] Figure 4 This diagram shows the layout of a NAND flash memory structure with an interleaved page buffer architecture.

[0026] Figure 5 The diagram shown is a schematic diagram of the NAND flash memory structure circuit of the interleaved page buffer architecture according to an embodiment of the present invention.

[0027] Figure 6 The diagram shows a layout schematic of a NAND flash memory structure with an interleaved page buffer architecture, as shown in an embodiment of the present invention.

[0028] Component designation explanation

[0029] 10 storage areas

[0030] 11. Page buffer with full bitline structure

[0031] 12 Decoding Circuit Area

[0032] 20 storage areas

[0033] 21. Page buffers in an interleaved architecture

[0034] 22 Decoding Circuit Area

[0035] 30 Memory Cell Area

[0036] 301 memory transistor

[0037] 302 Source Selection Transistor

[0038] 303 Drain Select Transistor

[0039] 304 Common Source Pole

[0040] 305 Virtual Memory Transistors

[0041] 306 Even-Select Transistor

[0042] 307 Odd-Select Transistor

[0043] 31-page buffer

[0044] 311 High Voltage Transistor

[0045] 32 Decoding Circuit Area Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0048] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0049] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0050] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0051] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0053] The NAND Flash page buffer architecture is as follows: Figures 1-2 The All Bitline Architecture shown, and as... Figures 3-4 The diagram illustrates two types of NAND flash architectures: A full-bit-line NAND flash includes a storage area 10, a full-bit-line page buffer 11, and a decoding circuit area 12; an interleaved NAND flash includes a storage area 20, an interleaved page buffer 21, and a decoding circuit area 22. The full-bit-line architecture excels in read / write speeds, enabling rapid data read / write operations. The interleaved architecture's key advantage lies in its efficient use of chip area, allowing for more functionality within a limited chip space, thus reducing costs. However, in practical applications, different scenarios prioritize these two characteristics differently. For applications with lower read / write speed requirements but high cost sensitivity, the more area-efficient interleaved architecture becomes a better choice. Nevertheless, despite the area utilization advantage of the interleaved architecture, with the increasing market demand for miniaturized, highly integrated products, this invention aims to provide an interleaved NAND flash memory structure to further reduce chip area while maintaining cost advantages.

[0054] like Figures 5-6As shown, this embodiment provides a NAND flash memory structure, which includes: a memory cell region 30, including even memory strings and odd memory strings, each with an even number of bit lines and an odd number of bit lines; an even selection transistor 306 and an odd selection transistor 307, integrated in the edge region of the memory cell region 30, used to control the conduction state of the even number of bit lines and the odd number of bit lines, respectively; and a page buffer 31, coupled to the memory cell region 30 through the even selection transistor 306 and the odd selection transistor 307, to program data signals into or read from the memory cell region.

[0055] In one embodiment, the even and odd memory strings in the memory cell area 30 adopt a two-dimensional planar architecture, consisting of alternating even and odd memory strings.

[0056] In one embodiment, the even-numbered memory string and the odd-numbered memory string each include a plurality of memory transistors 301, a source select transistor 302, and a drain select transistor 303. The plurality of memory transistors 301 are configured in the form of a NAND string. The control gate of the plurality of memory transistors 301 is connected to the word line WL. The gate of the source select transistor 302 is connected to the source select signal SGS. The first terminal is connected to the first terminal of the plurality of memory transistors 301, and the second terminal is connected to the common source line 304. The gate of the drain select transistor 303 is connected to the drain select signal SGD. The first terminal is connected to the second terminal of the plurality of memory transistors 301, and the second terminal is connected to one of the even-numbered bit line and the odd-numbered bit line.

[0057] For example, even-numbered and odd-numbered memory strings can each consist of a NAND string composed of 16 floating-gate memory transistors connected in series. The gate structure of the floating-gate memory transistor can include, in sequence, a tunneling oxide layer, a floating-gate polysilicon layer, a gate dielectric layer (such as a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride / silicon oxide (ONO) composite dielectric layer), and a control gate (such as a polysilicon or metal layer). It should be noted that the number of floating-gate memory transistors can be extended to 32, 64, or more, and is not limited to the examples listed here. The thickness of the tunneling oxide layer can be 5nm to 10nm, the thickness of the floating-gate polysilicon layer can be 20nm to 50nm, the thickness of the gate dielectric layer can be 80nm to 100nm, and the thickness of the control gate can be 100nm to 300nm.

[0058] The source select transistor 302 and the drain select transistor 303 can be respectively located at the two ends of the even memory string and the odd memory string. The gate of the source select transistor 302 is connected to the source select signal to control the switching of the source select transistor 302. The first end is connected to the first end of the plurality of memory transistors 301, and the second end is connected to the common source line 304. The gate of the drain select transistor 303 is connected to the drain select signal to control the switching of the drain select transistor 303. The first end is connected to the second end of the plurality of memory transistors 301, and the second end is connected to one of the even bit line and the odd bit line.

[0059] In one embodiment, even and odd memory strings are arranged alternately, as are even and odd bit lines. This alternating arrangement of even and odd bit lines effectively reduces crosstalk between adjacent bit lines, decreases the coupling capacitance between adjacent bit lines, and improves read accuracy.

[0060] In one embodiment, such as Figure 5 and Figure 6 As shown, virtual memory transistors (DUMMY) 305 are also provided on both sides of the even and odd memory strings.

[0061] In one embodiment, any adjacent even-select transistors 306 and odd-select transistors 307 are arranged in a staggered manner relative to the routing direction of the selection signal line, for example, as... Figure 5 and Figure 6 As shown, the odd-select transistor 307 can be positioned closer to the memory cell region, and the even-select transistor 306 can be positioned further away from the memory cell region. Alternatively, the even-select transistor 306 can be positioned closer to the memory cell region, and the odd-select transistor 307 can be positioned further away from the memory cell region. The gates of multiple even-select transistors 306 are connected to an even-select signal line (Even Switch) to control the switching of the even-select transistors 306. The gates of multiple odd-select transistors 307 are connected to an odd-select signal line (Odd Switch) to control the switching of the odd-select transistors 307. The even-select signal line and the odd-select signal line are arranged in parallel, with a spacing of, for example, 100nm to 200nm. This staggered arrangement of the even-select transistors 306 and the odd-select transistors 307 facilitates the routing of the even-select signal lines, preventing interference, and effectively reduces parasitic capacitance drop, thus reducing signal delay.

[0062] The operating voltage and area of ​​even-select transistor 306 and odd-select transistor 307 are significantly lower than those of the high-voltage transistor 311 in the page cache. Even-select transistor 306 and odd-select transistor 307 can be NMOS transistors, including a source, drain, and gate. The gate includes a gate dielectric layer and a gate electrode layer, such as an oxide layer (thickness can be, for example, 3nm to 10nm) or a high-k dielectric (such as HfO2). The gate electrode layer can be, for example, a polysilicon layer or a metal gate layer (such as TiN / TaN). The operating voltage of even-select transistor 306 and odd-select transistor 307 can be, for example, no greater than 5V. Even-select transistor 306 and odd-select transistor 307 can be fabricated using the same process as the memory cell region.

[0063] In one embodiment, during a read operation, a single read operation selects only one group of even-select transistors 306 and odd-select transistors 307 for gating. Specifically, as... Figure 5 As shown, during the read operation, one of the even selection transistor 306 and the odd selection transistor 307 is selected by the even selection signal line or the odd selection signal line, and the high voltage transistor 311 of the corresponding page buffer 31 is selected to select one of the even memory string and the odd memory string. The memory state is read by the output current of the corresponding bit line of the read output.

[0064] In one embodiment, during a programming operation, only one group of even-select transistors 306 and odd-select transistors 307 is selected in a single programming operation. Specifically, as shown... Figure 5 As shown, during the write operation, one of the even selection transistor 306 and the odd selection transistor 307 is selected by the even selection signal line or the odd selection signal line, and the high voltage transistor 311 of the corresponding page buffer 31 is selected to select one of the even memory string and the odd memory string. By applying a voltage to the control gate of the memory transistor 301, electrons tunnel into the floating gate polysilicon layer, or by applying a voltage to both the control gate and the drain of the memory transistor 301, electrons enter the floating gate polysilicon layer through the thermionic effect, thus realizing the write operation of the even memory string and the odd memory string. During the erase operation, one of the even selection transistor 306 and the odd selection transistor 307 is selected by the even selection signal line or the odd selection signal line, and one of the even memory string and the odd memory string is selected by the high voltage transistor 311 of the corresponding page buffer 31. By applying voltage to the control gate of the memory transistor 301, electrons in the floating gate polysilicon layer tunnel into the substrate, or by applying voltage to both the control gate of the memory transistor 301 and the substrate, electrons in the floating gate polysilicon layer tunnel into the substrate, thus realizing the erase operation of the even memory string and the odd memory string.

[0065] In one embodiment, such as Figure 5and Figure 6 As shown, the page buffer 31 includes multiple high-voltage transistors 311, each of which is simultaneously connected to a set of even-select transistors 306 and odd-select transistors 307.

[0066] In one embodiment, the NAND flash memory structure further includes a decoding circuit region 32. The gate of the high-voltage transistor 311 is connected to a high-voltage switching signal, the first end is connected to the common output of a set of even-select transistors 306 and odd-select transistors 307, and the other end is connected to the decoding circuit region 32.

[0067] For example, the voltage rating of the high-voltage transistor 311 can be above 20V, and the high-voltage transistor 311 can adopt a structure such as LDMOS (laterally diffused metal-oxide semiconductor).

[0068] Please see Figure 3 and Figure 5 , Figure 3 The page buffer structure requires two sets of high-voltage transistors 311, one for even memory strings and one for odd memory strings, and these high-voltage transistors 311 require a relatively large area. For example... Figure 5 As shown, this invention proposes a novel interleaving architecture NAND flash memory structure. By integrating even-select transistors 306 and odd-select transistors 307 at the edge of the memory cell area, which control the switching of corresponding even-numbered bit lines and odd-numbered bit lines respectively, the page buffer 31 only needs to be equipped with one set of high-voltage transistors 311. Each high-voltage transistor 311 simultaneously controls one set of even-select transistors 306 and odd-select transistors 307, thus greatly reducing the number of high-voltage transistors required for the page buffer 31 (compared to...). Figure 3 The structure is reduced by 50%, and the even-select transistor 306 and odd-select transistor 307 are low-voltage transistors, whose total occupied area is much smaller than that occupied by the high-voltage transistor 311, thus significantly reducing the overall layout area of ​​the NAND flash memory structure. This invention proposes a novel interleaved NAND flash memory structure, whose page buffer 31 area can be reduced by 20% compared to the traditional interleaved architecture and by 50% compared to the traditional full-word-line architecture. Taking a 1G capacity two-dimensional NAND Flash as an example, replacing the full-word-line architecture design with the novel interleaved architecture page buffer design proposed in this invention can reduce the chip area by approximately 8%, and increase the number of chips per wafer by approximately 70.

[0069] This embodiment also provides a method for fabricating a NAND flash memory structure. The method includes: fabricating even-numbered memory strings and odd-numbered memory strings in a memory cell region 30, wherein even-numbered memory strings and odd-numbered memory strings are respectively provided with an even number of bit lines and an odd number of bit lines; fabricating an even-selection transistor 306 and an odd-selection transistor 307 in the edge region of the memory cell region 30, wherein the even-selection transistor 306 and the odd-selection transistor 307 are respectively used to control the conduction state of the even-numbered bit lines and the odd-numbered bit lines; and fabricating a page buffer 31, wherein the page buffer 31 is coupled to the memory cell region 30 through the even-selection transistor 306 and the odd-selection transistor 307 to program data signals into or read data signals from the memory cell region.

[0070] In one embodiment, even-select transistor 306 and odd-select transistor 307 can be fabricated using the same process as the memory cell region.

[0071] This embodiment also provides an electronic device that includes the NAND flash memory structure as described in the above embodiment.

[0072] For example, electronic devices can be solid-state drives, mobile devices (such as smartphones), PCs or laptops, tablets, smart homes, new energy vehicles, and IoT terminals.

[0073] As described above, the NAND flash memory structure, its fabrication method, and electronic device of the present invention have the following beneficial effects:

[0074] This patent proposes a novel interleaving architecture NAND flash memory structure. By integrating even-select transistors 306 and odd-select transistors 307 at the edge of the storage cell area, which control the switching of the corresponding even-numbered bit lines and odd-numbered bit lines respectively, the page buffer 31 only needs to be equipped with a set of high-voltage transistors 311. Each high-voltage transistor 311 controls a set of even-select transistors 306 and odd-select transistors 307 at the same time, which greatly reduces the number of high-voltage transistors required for the page buffer 31, thereby significantly reducing the overall layout area of ​​the NAND flash memory structure.

[0075] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A NAND flash memory structure, characterized in that, The NAND flash memory structure includes: The memory cell area includes an even memory string and an odd memory string, wherein the even memory string and the odd memory string are respectively provided with an even number of bit lines and an odd number of bit lines; Even-select transistors and odd-select transistors are integrated within the memory cell area and are used to control the conduction state of the even-numbered bit lines and odd-numbered bit lines, respectively. The page buffer is coupled to the memory cell area via the even-select transistor and the odd-select transistor to program data signals into or read from the memory cell area.

2. The NAND flash memory structure according to claim 1, characterized in that: The even-numbered memory string and the odd-numbered memory string each include a plurality of memory transistors, a source select transistor, and a drain select transistor. The plurality of memory transistors are configured in the form of a NAND string. The gate of the source select transistor is connected to a source select signal, the first terminal is connected to the first terminal of the plurality of memory transistors, and the second terminal is connected to a common source line. The gate of the drain select transistor is connected to a drain select signal, the first terminal is connected to the second terminal of the plurality of memory transistors, and the second terminal is connected to one of the even-numbered bit lines and the odd-numbered bit lines.

3. The NAND flash memory structure according to claim 1, characterized in that: The page buffer includes multiple high-voltage transistors, each of which is simultaneously connected to a set of even-select transistors and an odd-select transistor.

4. The NAND flash memory structure according to claim 1, characterized in that: The even storage string and the odd storage string are arranged alternately, and the even bit line and the odd bit line are arranged alternately.

5. The NAND flash memory structure according to claim 1, characterized in that: The routing directions of any adjacent even-select transistors and odd-select transistors relative to the selection signal line are staggered. The gates of multiple even-select transistors are connected to an even-select signal line, and the gates of multiple odd-select transistors are connected to an odd-select signal line. The even-select signal line and the odd-select signal line are arranged in parallel.

6. The NAND flash memory structure according to claim 1, characterized in that: During a read operation, only one of the even-select transistor group and the odd-select transistor group is selected in a single read operation.

7. The NAND flash memory structure according to claim 1, characterized in that: During a programming operation, only one of the even-selection transistor group and the odd-selection transistor group is selected in a single programming operation.

8. The NAND flash memory structure according to claim 1, characterized in that: The even and odd storage strings in the memory cell area adopt a two-dimensional planar architecture.

9. A method for fabricating a NAND flash memory structure as described in any one of claims 1 to 8, characterized in that, The preparation method includes: Even memory strings and odd memory strings are prepared in the memory cell area. The even memory strings and odd memory strings are respectively provided with an even number of bit lines and an odd number of bit lines. Even selection transistors and odd selection transistors are prepared in the edge region of the memory cell area. The even selection transistors and odd selection transistors are respectively used to control the conduction state of the even number of bit lines and the odd number of bit lines. A page buffer is prepared, which is coupled to the memory cell area through the even-select transistor and the odd-select transistor to program data signals into or read from the memory cell area.

10. An electronic device, characterized in that, The electronic device includes the NAND flash memory structure as described in any one of claims 1 to 8.

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