Storage circuit, configuration method of storage circuit, chip, electronic device, and apparatus

Abstract

Embodiments of the present disclosure disclose a storage circuit, a configuration method of the storage circuit, a chip, an electronic device and an apparatus, wherein the storage circuit comprises: a storage array comprising a plurality of columns of storage components, each column of storage components comprising a preset number of stacked memory banks; the plurality of columns of storage components comprise a main storage component and a redundant storage component; and a logic control circuit comprising: a chip select distribution unit for each column; and a first number of data input / output selection units; wherein the chip select distribution unit corresponding to any storage component is configured to distribute a chip select signal to a memory bank corresponding to a logical layer number of the memory bank in the storage component according to a preconfigured logical layer number of the memory bank; and the data input / output selection unit corresponding to the main storage component is configured to select a data input / output terminal of a corresponding target storage component according to the chip select signal and preconfigured selection enable information, thereby effectively improving the yield of the storage circuit on the basis of a smaller circuit area overhead.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a memory circuit, a method for configuring the memory circuit, a chip, an electronic device, and an apparatus. Background Technology

[0002] In the field of 3D DRAM (3-Dimensional Dynamic Random Access Memory) technology, multiple single-layer memory banks (i.e., banks or array banks) are typically vertically stacked to form multi-layer stacked banks (or simply stacked banks or memory components). Multiple stacked banks can then form a memory array, which is then combined with address bus, data bus, memory controller, etc., to package it into a 3D DRAM chip to improve memory performance. However, for 3D DRAM chips (hereinafter referred to as chips) to achieve mass production, the chip yield needs to meet expected conditions. Related technologies typically improve chip yield by adding bank repair hardware to the 3D DRAM. One repair method involves treating the multi-layered stacked banks as a whole, sharing the data bus and address bus TSVs (Through Silicon Vias) and memory controller. Based on dividing all stacked banks into multiple groups, a redundant stacked bank is introduced into each group as the basis for bank repair. Taking a 4-layer stack as an example, if the yield of each single-layer bank is P = 98%, then the yield of each 4-layer stacked bank is P0. 4 =92.2%. If each bank group includes eight 4-layer stacked banks and one redundant 4-layer stacked bank, then the yield of selecting eight usable stacked banks from nine stacked banks (i.e., the yield of one bank group) is 92.2% raised to the power of 8, or 52.2%. If the chip includes 32 bank groups, then the chip's yield is the bank group yield of 52.2% raised to the power of 32, resulting in approximately 0.5%, which clearly cannot meet mass production standards. How to effectively improve the chip's yield has become an urgent technical problem to be solved. Summary of the Invention

[0003] The embodiments of this disclosure provide a storage circuit, a method for configuring the storage circuit, a chip, an electronic device, and an apparatus that can effectively improve the yield of the storage circuit with a smaller circuit area overhead, thereby improving the yield of the storage chip.

[0004] According to one aspect of the present disclosure, a storage circuit is provided, comprising: a storage array including multiple columns of storage components, each column of storage components including a stacked storage body of a preset number of layers; the multiple columns of storage components including a first number of primary storage components and a second number of redundant storage components; and a logic control circuit including: a chip select allocation unit corresponding to each of the storage components; and a data input / output selection unit corresponding to each of the primary storage components; wherein the chip select allocation unit corresponding to any storage component is configured to allocate a chip select signal to the storage component corresponding to the logic layer number according to a pre-configured logic layer number of the storage body. The storage unit; multiple selection terminals of the data input / output selection unit corresponding to any of the main storage components are respectively connected to the data input / output terminals of the main storage component and the data input / output terminals of at least one storage component on the first side of the main storage component; the data input / output selection unit corresponding to the main storage component is configured to select the data input / output terminal of the main storage component and the at least one storage component on the first side of the main storage component that corresponds to the selection enable information, according to the chip select signal and the pre-configured selection enable information, so as to input or output data through the data input / output terminal of the target storage component.

[0005] According to another aspect of the present disclosure, a method for configuring a storage circuit is provided, comprising: acquiring the state of each memory bank in the storage circuit; the state being obtained by testing the storage circuit; the state of each memory bank including an available state or an unavailable state; determining a logical layer number corresponding to each memory bank based on the state of each memory bank, such that the number of unavailable logical memory banks in each layer of the storage array is less than or equal to a second number, wherein the physical layer number corresponding to any memory bank is the same as or different from the logical layer number; the physical layer number representing the layer number of the memory bank in the storage array; determining selection enable information of a data input / output selection unit corresponding to each of the main storage components; and configuring the logical layer number and the selection enable information to the storage circuit.

[0006] According to another aspect of the present disclosure, a chip is provided, including: the memory circuit provided in any of the above embodiments.

[0007] According to another aspect of the present disclosure, a chip is provided, comprising: a processor; and a storage circuit provided in any of the above embodiments; the processor is configured to acquire executable instructions and execute the instructions to implement the configuration method of the storage circuit provided in any of the above embodiments, so as to configure the storage circuit.

[0008] According to another aspect of the present disclosure, an electronic device is provided, comprising: a chip provided in any of the foregoing embodiments.

[0009] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the configuration method of the storage circuit described in any of the above embodiments.

[0010] The storage circuit, storage circuit configuration method, chip, electronic device, and apparatus provided in the above embodiments of this disclosure, through a chip select allocation unit, can allocate the chip select signal of a layer to the storage cell corresponding to the pre-configured logical layer number of the storage cell. This allows the chip select signal of the i-th layer to be allocated to the storage cell of the j-th layer, and the chip select signal of the j-th layer to be allocated to the k-th layer, thereby realizing the logical exchange of storage cells of different layers during use. That is, the storage cell of the j-th layer is used as the storage cell of the i-th layer. Through this exchange, unusable storage cells of any layer in the storage array can be exchanged with available storage cells of other layers, ensuring the logical exchange of storage cells in the storage array. The number of unavailable memory units in each layer is less than or equal to the number of redundant memory units in that layer (i.e., the second number). This allows each layer to select the required number of memory units from all memory units in that layer, ensuring that the layer can function properly. For example, if each layer includes one redundant memory unit, and each layer needs to use 8 memory units during the operation of the storage array, and the number of unavailable memory units in the storage array is less than or equal to the number of layers in the storage array, logical switching of memory units can ensure that each layer has at most one unavailable memory unit. Thus, 8 available memory units can be selected from 9 memory units, ensuring the availability of each layer. This logical exchange of memory cells is achieved through configured logical layer numbers. Further, it combines the data input / output selection units corresponding to each main memory component to select the required number of available memory cells from all memory cells in each layer. For example, if a memory cell in a certain column of a layer is unavailable according to its logical layer number, it can be replaced by a memory cell in the next column. Subsequent columns in that layer are used in a staggered manner. The data input / output selection unit can select the specific column to use, thereby improving the availability of the entire memory array and effectively increasing the yield of the memory circuit. The memory chip can include one or more memory arrays according to this disclosure, further improving the overall yield of the memory chip. Furthermore, the memory arrays of this disclosure are suitable for multi-layer memory cells sharing data bus, address bus, memory controller, etc., thereby effectively improving chip yield while ensuring a small circuit area overhead.

[0011] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0012] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0013] Figure 1 This is an exemplary application scenario of the storage circuit in this disclosure embodiment;

[0014] Figure 2 This is a schematic diagram of the structure of a storage circuit provided in an exemplary embodiment of the present disclosure;

[0015] Figure 3 This is a schematic diagram of the structure of a chip select allocation unit provided in an exemplary embodiment of this disclosure;

[0016] Figure 4 This is a schematic diagram of the structure of a dispenser provided in another exemplary embodiment of this disclosure;

[0017] Figure 5 This is a schematic diagram of the structure of a storage circuit provided in another exemplary embodiment of this disclosure;

[0018] Figure 6 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of the present disclosure;

[0019] Figure 7 This is a schematic diagram of the structure of an enable information selection unit provided in an exemplary embodiment of this disclosure;

[0020] Figure 8 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of the present disclosure;

[0021] Figure 9 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of this disclosure;

[0022] Figure 10 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of the present disclosure;

[0023] Figure 11 This is a schematic diagram of the initial logical layer number and memory bank state of a memory array provided in an exemplary embodiment of this disclosure;

[0024] Figure 12 This is a schematic diagram of a logical layer number determined by an algorithm according to an exemplary embodiment of this disclosure;

[0025] Figure 13This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of this disclosure;

[0026] Figure 14 This is a schematic diagram of the selection enable information provided in an exemplary embodiment of this disclosure;

[0027] Figure 15 This is a schematic diagram of the logical layer number and selection enable information provided in an exemplary embodiment of this disclosure;

[0028] Figure 16 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of the present disclosure;

[0029] Figure 17 This is a schematic flowchart of a method for configuring a storage circuit provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0030] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0031] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0032] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0033] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0034] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0035] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0036] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0037] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0038] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0039] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0040] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0041] This disclosure outlines

[0042] Figure 1 This is an exemplary application scenario of the storage circuit according to an embodiment of this disclosure. For example... Figure 1 As shown, 3D DRAM typically requires one or more... Figure 1The storage array in this disclosure refers to a bank consisting of m columns and n layers, or a storage array consisting of m columns and n layers, where m and n are positive integers. Using the storage circuit of this disclosure, the storage circuit can include one or more storage arrays and logic control circuitry. Each column of n-layer stacked banks is considered as a whole, called a storage component. Each layer can share a data bus, address bus, memory controller, etc. That is, the storage array includes multiple columns of storage components, and each column of storage components includes a predetermined number of stacked storage units (i.e., n layers), such as bank11, bank12, ..., bank1n in the first column. The multiple columns of storage components include a specified number of redundant storage components, for example, one or more columns of redundant storage components used to replace unusable storage units in other storage components. For example, if m = 9, and the storage array requires 8 columns of storage components for normal use, then the storage array includes one column of redundant storage components. The specific number of redundant storage components is not limited. The logic control circuit may include chip select allocation units corresponding to each storage component, and a specified number of data input / output selection units, the specified number being the same as the number of memory cells required for each layer of the storage array. Alternatively, the storage array may be represented as a first number of primary storage components and a second number of redundant storage components, where the first number is the number of columns required for normal operation of the storage array, and the second number is the number of redundant columns. The data input / output selection units may include data input / output selection units corresponding to each primary storage component. The chip select allocation unit is configured to allocate a chip select signal to the memory cell corresponding to the logical layer number within the storage component according to a pre-configured logical layer number. Multiple selection terminals of any data input / output selection unit are connected to the data input / output terminals of multiple adjacent storage components. The data input / output selection unit is configured to select the data input / output terminal of the target storage component corresponding to the selection enable information from the multiple selection terminals according to the chip select signal and pre-configured selection enable information, so as to input or output data through the data input / output terminal of the target storage component, thereby selecting the required number of available memory cells from all memory cells in each layer. By using the chip select allocation unit and the data input / output selection unit, the availability of the memory array can be ensured when the number of unusable memory cells in the memory array is less than or equal to the total number of redundant memory cells (i.e., the product of the number of redundant memory cells in each layer and the number of layers). This can effectively improve the yield of the memory array, thereby improving the yield of the memory chip and enabling the memory chip to meet mass production standards.

[0043] Exemplary Structure

[0044] Figure 2This is a schematic diagram of a storage circuit provided in an exemplary embodiment of this disclosure. The various components of this storage circuit can be integrated into a single chip or disposed in discrete components, with data communication links established between these discrete components. For example... Figure 2 As shown, the storage circuit 20 may include: a storage array 21 (the array composed of gray modules in the figure) and a logic control circuit 22 (the white modules in the figure).

[0045] The storage array 21 includes multiple columns of storage components. Each column of storage component 21d (d = 1, 2, ..., m, where m is the total number of columns in the storage array) includes a preset number of stacked storage cells (which can be represented as n). A single-layer storage cell is called a bank. The multiple columns of storage components include a first number of main storage components and a second number of redundant storage components.

[0046] The logic control circuit 22 includes: chip select allocation units 22d corresponding to each memory component 21d, and data input / output selection units 23e corresponding to each main memory component 21e (e = 1, 2, ..., mf, f represents the second quantity).

[0047] Where f can be 1, 2, 3, etc. Figure 2 Taking f=1 as an example, the number of selection terminals of each data input / output selection unit 23e is 2. If f=2, the number of selection terminals of the data input / output selection unit 23e is 3. If f=3, the number of selection terminals of the data input / output selection unit 23e is 4.

[0048] The chip select allocation unit 22d corresponding to any storage component 21d is configured to allocate the chip select signal to the storage bank in the storage component corresponding to the logical layer number according to the pre-configured logical layer number of the storage bank.

[0049] Multiple selection terminals of the data input / output selection unit 23e corresponding to any main storage component 21e (e = 1, 2, ..., mf) are respectively connected to the data input / output terminals of the main storage component 21e and the data input / output terminals of at least one storage component on the first side of the main storage component 21d; the data input / output selection unit 23e corresponding to the main storage component 21e is configured to select the data input / output terminals of the target storage component corresponding to the selection enable information in the main storage component 21e and at least one storage component on the first side of the main storage component 21e according to the chip select signal and the pre-configured selection enable information, so as to input or output data through the data input / output terminals of the target storage component.

[0050] The first and second quantities can be set to any number according to actual needs. For example, the first quantity can be 4, 5, 8, 16, etc., and the second quantity can be 1, 2, 3, etc. Since the second quantity represents the number of columns of redundant memory, it increases circuit area overhead. Furthermore, the more columns of redundant memory, the more complex the logic for repairing the bank becomes. Therefore, the second quantity can be set based on the overall performance requirements of the memory chip. It should be noted that "primary memory component" and "redundant memory component" here only indicate that the number of columns of memory components included in the memory array is greater than the actual number of columns needed by the memory array; they are not limitations on the specific columns of memory components. That is, if all the memory cells in the first number of columns of the memory array are available, then the first number of columns are used; if some of the memory cells in the first number of columns are unavailable, redundant memory cells can be partially used.

[0051] In some optional embodiments, the chip select allocation unit 22d can be implemented using one or more allocators. For example, one allocator corresponds to each layer, used to allocate the chip select signal of that layer to the memory bank corresponding to that logical layer number according to a pre-configured logical layer number. For example, taking a 4-layer system, if the pre-configured logical layer number corresponding to the 1st layer is 3, then the chip select signal will be allocated to the memory bank of the 3rd layer, that is, the memory bank of the 3rd layer will be used as the memory bank of the 1st layer. The logical layer number is determined based on the state of each memory bank in the memory array 21. The state of each memory bank is obtained through testing. The state of the memory bank includes an available state (which can be represented as good, or GOOD, or 1) and an unavailable state (which can be represented as bad, or BAD, or 0). The logical layer number can be calculated based on the bank repair algorithm of the embodiments of this disclosure. The purpose of configuring the logical layer number is to ensure that the number of unavailable memory banks in each layer is less than or equal to the number of redundant memory banks in that layer, ensuring that a sufficient number of available memory banks (represented as good banks) can be selected from the memory banks in that layer. For example, if a layer has only one redundant storage bank, and there are two unusable storage banks (i.e., bad banks) in a certain layer's storage bank (which can be called physical storage bank), the layer will not function properly. By configuring the logical layer number, the initial logical layer number of a storage bank in that layer can be exchanged with the initial logical layer number of a storage bank in another layer that does not have a bad bank. The initial logical layer number can be the physical layer number of the storage bank. In this way, logically, each layer has at most one bad bank, and the normal operation of the layer can be ensured by a redundant storage bank.

[0052] In some alternative embodiments, the first side of the main storage component 21e is, for example, Figure 2The data input / output selection unit 23e is located on the right side of the main storage component 21e. It can be implemented using a selector. For example, in a storage array containing one column of redundant memory banks, if a column of memory banks in a certain layer is unavailable, the selector can select the memory bank in the next column, and so on, ensuring that all memory banks used in that layer are in good bank condition. Selection enable information is used to determine which column of memory banks the data input / output selection unit 23e should specifically select. This selection enable information is pre-calculated based on the state of the memory banks corresponding to the logical layer number. The state of the memory cell corresponding to the logical layer number is the state of the physical memory cell in the same layer as that logical layer number. For example, using the physical layer number (initial logical layer number) of the memory cell in layer 3 as the logical layer number of the memory cell in layer 1 is equivalent to logically swapping the memory cells in layer 3 and layer 1. Layer 1 uses the memory cells in layer 3, and layer 3 uses the memory cells in layer 1. If the memory cell in layer 1 is a "bad" memory cell and the memory cell in layer 3 is a "good" memory cell, after the swap, the state of the memory cell corresponding to the logical layer number in layer 1 is "good," and the state of the memory cell in layer 3 is "bad." Therefore, the "bad" memory cell in layer 3 needs to use the memory cell in the next column. The enable information of the data input / output selection unit in the column containing the "bad" memory cell is the enable information for selecting the next column. Since each layer shares a data bus, the selection terminal of the data input / output selection unit can be connected to the data input / output terminal of the corresponding column's memory component. Layers are selected via chip select signals, and columns are selected via enable information, thereby collaboratively achieving memory array repair and ensuring the availability of the memory array.

[0053] The storage circuit provided in this embodiment, through a chip select allocation unit, can allocate the chip select signal of a layer to the storage cell corresponding to the pre-configured logical layer number of the storage cell. This allows the chip select signal of layer i to be allocated to the storage cell of layer j, and the chip select signal of layer j to be allocated to layer k, thereby realizing the logical exchange of storage cells of different layers during use. That is, the storage cell of layer j is used as the storage cell of layer i. Through this exchange, unavailable storage cells of any layer in the storage array can be exchanged with available storage cells of other layers, ensuring that the number of unavailable storage cells in each layer of the storage array is less than or equal to the number of redundant storage cells in that layer (i.e., the second number). This allows each layer to select the required number of storage cells from all storage cells in that layer, ensuring that the layer can work normally. For example, if each layer includes one redundant storage cell, and each layer needs to use 8 storage cells during the operation of the storage array, when the number of unavailable storage cells in the storage array is less than or equal to the number of layers in the storage array, the logical exchange of storage cells can ensure that each layer has at most one unavailable storage cell, and thus 8 available storage cells can be selected from 9 storage cells, ensuring the availability of each layer. This logical exchange of memory cells is achieved through configured logical layer numbers. Further, it combines the data input / output selection units corresponding to each main memory component to select the required number of available memory cells from all memory cells in each layer. For example, if a memory cell in a certain column of a layer is unavailable according to its logical layer number, it can be replaced by a memory cell in the next column. Subsequent columns in that layer are used in a staggered manner. The data input / output selection unit can select the specific column to use, thereby improving the availability of the entire memory array and effectively increasing the yield of the memory circuit. The memory chip can include one or more memory arrays according to this disclosure, further improving the overall yield of the memory chip. Furthermore, the memory arrays of this disclosure are suitable for multi-layer memory cells sharing data bus, address bus, memory controller, etc., thereby effectively improving chip yield while ensuring a small circuit area overhead.

[0054] Figure 3 This is a schematic diagram of the structure of a chip select allocation unit provided in an exemplary embodiment of this disclosure.

[0055] In some alternative embodiments, in the above... Figure 2 Based on the illustrated embodiments, as Figure 3 As shown, the chip select allocation unit 22d (d = 1, 2, ..., m, where m is the total number of columns in the memory array) may include:

[0056] A preset number of allocators 22di (i = 1, 2, ..., n) are used; the preset number is the same as the preset number of layers, i.e., the preset number is n. The first input terminal of each allocator 22di is connected to a first output terminal of the chip select decoder 231. Multiple second output terminals of each allocator 22di are respectively connected to the memory banks (e.g., bankd1, bankd2, ..., bankdn) of each layer in the storage component 21di. Each allocator 22di is configured to allocate the chip select signal output from a first output terminal of the chip select decoder 231 to the memory bank in the storage component 21d corresponding to the pre-configured logical layer number of the memory bank. For example, if the pre-configured logical layer number of allocator 22d1 is 3, then the chip select signal is allocated to bankd3, indicating that bankd3 is used as the memory bank of the d-th column, layer 1. In this case, the corresponding allocator 22d3 will allocate the chip select signal to other memory banks, such as bankd1. The logical layer numbers of the allocators for different layers are different.

[0057] In some alternative embodiments, the distributor 22di is a 1 to n distributor, meaning that an input chip select signal can be assigned to a specified terminal among n output terminals.

[0058] In the embodiments of this disclosure, for each column of memory, a distributor is provided for each layer, so that each distributor can allocate the chip select signal of the layer to the memory corresponding to the logical layer number. Thus, by configuring the logical layer number, memory of different layers can be logically swapped, so that the number of bad banks included in each layer is less than or equal to the number of redundant memory of that layer, ensuring that the layer has the required number of good banks.

[0059] Figure 4 This is a schematic diagram of the structure of a distributor provided in another exemplary embodiment of this disclosure.

[0060] In some alternative embodiments, any allocator 22di may include: a first register 22di1, a decoder 22di2, and a preset number of switches 22di3.

[0061] The first register 22di1 is configured to store the logic layer number; the decoder 22di2 is connected to the first register 22di1; a preset number of switches 22di3 are respectively connected to a preset number of output terminals of the decoder 22di2 and the storage cells of each layer in the storage component 21d.

[0062] Decoder 22di2 is configured to decode the logic layer number and control the state of each switch 22di3 through a preset number of output terminals to allocate the chip select signal to the memory bank corresponding to the logic layer number.

[0063] The state of switch 22di3 includes an on state and an off state. When it is on, the chip select signal can be transmitted to the corresponding memory bank. When it is off, the chip select signal will not be transmitted to the corresponding memory bank.

[0064] In some optional embodiments, the logic layer number can be represented as a multi-bit binary value, and the number of bits can be set according to the specific number of layers. For example, in a 4-layer bank, the logic layer number can be 2 bits, such as 00 for layer 1, 01 for layer 2, 10 for layer 3, and 11 for layer 4. This is decoded by a decoder into control signals for each switch 22di3, controlling the state of each switch 22di3. For example, if a switch 22di3 is turned on when the control signal is 1 and turned off when the control signal is 0, then one output terminal of the decoder 22di2 will output a signal of 1, and the other output terminals will output signals of 0. Based on this, the logic layer number is decoded into the result of the corresponding switch's control signal being 1. For example, if the logic layer number is 3, then a control signal of 1 is output to the 3rd switch 22di3, turning the switch on and allocating the chip select signal to bankd3. The control signals for the other switches are 0, and the switches are in the off state.

[0065] In the embodiments of this disclosure, the logic layer number is stored in a register, and then the logic layer number is decoded into control signals for each switch by a decoder. By controlling the on or off of each switch, the chip select signal is allocated to the memory bank corresponding to the logic layer number, effectively realizing the logical exchange of the memory bank and providing effective technical support for improving the yield of each layer.

[0066] In some optional embodiments, the allocator may not include the first register, that is, the allocator 22d1 includes the decoder 22di2 and a preset number of switches 22di3. The input of the decoder 22di2 is connected to a preset memory. The preset memory may be a one-time programmable memory in the chip, which may be implemented by any of the following: efuse, OTP (One Time Programmable) module, etc. The logic layer number is stored in the preset memory.

[0067] In some alternative embodiments, based on any of the above embodiments, the storage circuit 20 may further include a first memory configured to store the logic layer number corresponding to each distributor. The first memory is a one-time programmable memory, which may be implemented, for example, by any of efuse or OTP modules.

[0068] In some alternative embodiments, the logic layer number can be calculated by an electronic device outside the storage circuit according to a certain algorithm, and then written into the first memory, for example, by burning the logic layer number into efuse or other one-time programmable memory.

[0069] The embodiments of this disclosure store the logic layer number through a one-time programmable memory, which can prevent it from being erased when the storage circuit or chip is powered off. On the one hand, it can avoid setting up hardware circuits for calculating the logic layer number in the storage circuit, further reducing circuit area overhead. On the other hand, it can avoid calculating the logic layer number through the CPU (Central Processing Unit), reducing the occupation of CPU resources.

[0070] Figure 5 This is a schematic diagram of the structure of a storage circuit provided in another exemplary embodiment of this disclosure.

[0071] In some alternative embodiments, based on any of the above embodiments, such as Figure 5 As shown, the storage circuit 20 may further include: a controller 24

[0072] The controller 24 is configured to: receive logical layer number configuration information from a processor (e.g., CPU); and configure logical layer numbers in the first register 22di1 of each allocator 22di in the chip select allocation unit 22d according to the logical layer number configuration information.

[0073] In some optional embodiments, the processor can determine the logical layer number corresponding to each memory bank according to the state of each memory bank in the memory array 21 obtained by testing, according to a pre-configured algorithm, and then send logical layer number configuration information to the controller 24 based on the obtained logical layer number. The controller 24 configures the corresponding logical layer number to the first register 22di1 of each allocator 22di in each chip select allocation unit 22d according to the logical layer number configuration information.

[0074] In embodiments of this disclosure, the logic layer number is configured by the processor to the register of the allocator, so that the logic layer number can be calculated by the processor or an external electronic device, avoiding the need to set up hardware repair circuits for calculating the logic layer number in the storage circuit or chip, and further reducing circuit area overhead.

[0075] Figure 6 This is a schematic diagram of the structure of a storage circuit provided in another exemplary embodiment of the present disclosure.

[0076] In some alternative embodiments, based on any of the above embodiments, such as Figure 6 As shown, the logic control circuit 22 may further include an enable information selection unit 251.

[0077] The multiple second input terminals of the enable information selection unit 251 are respectively connected to the first output terminals of the chip select decoder, i.e., input chip select signals; the multiple third input terminals of the enable information selection unit 251 are respectively used to input the selection enable information of each layer, i.e. Hshift[mf:1][i] in the figure, i = 1, 2, ..., n; the third output terminal of the enable information selection unit 251 is connected to the enable control terminal of each data input / output selection unit 23e (e = 1, 2, ..., mf), and is used to provide selection enable information (or selection enable signals) to each data input / output selection unit.

[0078] Where Hshift[mf:1][i] represents the enable selection information corresponding to each of the first to mf columns of the i-th layer.

[0079] In some alternative embodiments, the enable information selection unit 251 can be implemented using an n-to-1 selector. For example, Figure 7 This is a schematic diagram of the structure of an enable information selection unit provided in an exemplary embodiment of this disclosure, as shown below. Figure 7 As shown, taking a preset number of layers of 4 and a first quantity of 8 as an example, the enable information selection unit 251 may include 4 switches K. The control signal terminal of the switch K is input with the chip select signal of the corresponding layer. The chip select signal controls the switch K to be turned on or off, thereby providing the selection enable information of the corresponding layer to each data input / output selection unit. In the figure, hshift[7:0][i] (or represented as hshift[8:1][i]) represents the enable selection information corresponding to the 1st to 8th columns of the i-th layer (i = 1, 2, 3, 4). In this way, when the chip select signal selects the memory of the 1st layer, the switch K corresponding to the 1st layer is turned on, and the selection enable information of the 1st layer is provided to each data input / output selection unit, so that each data input / output selection unit selects the memory used by the 1st layer to read data from or write data to each memory. Here, the memory used by the 1st layer is the memory corresponding to the logical layer number, that is, the memory allocated by the allocator. For example, the memory of the 3rd layer in a certain column is used as the memory of the 1st layer.

[0080] Figure 8 This is a schematic diagram of the structure of a storage circuit provided in another exemplary embodiment of the present disclosure.

[0081] In some alternative embodiments, based on the above embodiments, such as Figure 8As shown, the enable information selection unit 251 may include selection sub-units 251e corresponding to each data input selection unit 23e. Each second input terminal of each selection sub-unit 251e is used to input the chip select signal, and each third input terminal of each selection sub-unit 251e is used to input the selection enable information for each layer in the e-th column. In the figure, Hshift[e][i] represents the selection enable information corresponding to the i-th layer in the e-th column, where e = 1, 2, ..., mf, and i = 1, 2, ..., n. The specific structure of each selection sub-unit is as follows... Figure 7 The structures shown are similar and will not be described in detail here.

[0082] In some optional embodiments, each data input / output selection unit 23e may include the aforementioned enable information selection subunit 251e (or denoted as 23e1) and a selector (MUX) 23e2. The selector 23e2 can be a selector from f+1 to 1, where f is a second quantity, i.e., the number of redundant columns. For example, if f=1, then the selector 23e2 is a 2-to-1 selector, selecting the column to be used from two adjacent columns. For example, for a certain layer, if the state of the memory bank in the second column is bad, then the selector 2322 corresponding to the second column selects the third column, that is, the memory bank in the third column of that layer is used as the memory bank in the second column, and the subsequent columns are staggered in turn, so that the memory bank in the fourth column of that layer is used as the memory bank in the third column, ensuring that the memory bank used in each layer is a good bank. For f=2, each layer is allowed to have a maximum of 2 bad banks. If there are 2 bad banks in a certain layer, they are staggered in turn according to the above principle, which is equivalent to logically removing the unusable memory bank in the original memory bank of that layer. The specific principle will not be elaborated in detail.

[0083] The embodiments of this disclosure enable the selection of enable information for each layer through an enable information selection unit, thereby providing accurate and effective enable information for the data input / output selection unit and providing effective technical support for the normal operation of the storage array.

[0084] In some optional embodiments, the storage circuit 20 or logic control circuit 22 may include a second register, which may be connected to each of the third inputs of the enable information selection unit 251; the second register is configured to store selection enable information. Figure 6 Hshift[mf:1][i] can be stored in the second register, where i = 1, 2, ..., n.

[0085] In some optional embodiments, the storage circuit 20 may further include a second memory connected to each of the third input terminals of the enable information selection unit; the second memory is configured to store selection enable information, and the second memory is a one-time programmable memory, which may be implemented, for example, by any of efuse, OTP module, etc.

[0086] The second memory is similar to the first memory mentioned above; it can obtain the selection enable information in advance and write it into the second memory.

[0087] In some alternative embodiments, the selection enable information can be determined by an external electronic device of the storage circuit according to a pre-configured algorithm, and then written into a second memory.

[0088] In some alternative embodiments, the storage circuit 20 or logic control circuit 22 may further include: a controller 24, such as Figure 5 The controller 24 is shown in the diagram. Control register 24 can be connected to a second register. Controller 24 is configured to: receive selection enable information configuration information from the processor; and configure selection enable information into the second register according to the selection enable information configuration information.

[0089] The configuration principle for selecting enable information is similar to that for logical layer numbers, and will not be elaborated here.

[0090] In some optional embodiments, after determining the logical layer number corresponding to each memory bank in the memory array 21, the processor may further determine the selection enable information based on the state of the memory bank corresponding to each logical layer number, according to a pre-configured algorithm for determining selection enable information, so as to select the required number (i.e., the first number) of available memory banks from the memory banks of each layer.

[0091] In some alternative embodiments, the second register may also be located in the enable information selection unit 251.

[0092] In embodiments of this disclosure, by configuring the processor to select enable information, it is possible to avoid setting up a hardware repair circuit for calculating the selection enable information in the storage circuit 20 or the storage chip, thereby further reducing circuit area overhead.

[0093] Figure 9 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of this disclosure.

[0094] In some alternative embodiments, based on any of the above embodiments, such as Figure 9 As shown, the storage circuit 20 or logic control circuit 22 may further include a chip select decoder 231. The chip select decoder 231 is configured to decode a specified address bit of the input row address into a chip select signal, and to output the chip select signal to each chip select allocation unit 22d. Figure 9In the code, Row_addr_msb<1:0> represents the highest two bits of the row address, which specifies that the address bits are the highest two bits. Here, we only take 2 bits as an example. For example, in a 4-layer stacked storage array, the selection of each layer can be achieved by using 2 bits. In practical applications, it is not limited to the highest two bits. The specific number of bits can be determined according to the number of layers in the storage array 21.

[0095] In some alternative embodiments, the chip select decoder 231 may be implemented using any decoder that can be implemented in the related art, and this disclosure does not limit the embodiments.

[0096] The embodiments of this disclosure decode the chip select signal through the chip select decoder, which enables the selection of layers of the memory array and provides an effective chip select signal reference for the chip select allocation unit and the data input / output selection unit of this disclosure, so as to ensure that the chip select allocation unit and the data input / output selection unit can work together effectively to select the required number of available memory cells from each layer of memory cells in the memory array.

[0097] Figure 10 This is a schematic diagram of the structure of a storage circuit provided in another exemplary embodiment of the present disclosure.

[0098] In some alternative embodiments, based on any of the above embodiments, such as Figure 10 As shown, the storage circuit 20 or logic control circuit 22 in this embodiment may further include: a logic layer number determination circuit 26, configured to:

[0099] The state of each memory bank in the storage array 21 is obtained; the state of the memory bank is obtained by testing the storage circuit 20; the state of each memory bank includes an available state (or simply available) or an unavailable state (or simply unavailable); based on the state of each memory bank, the logical layer number corresponding to each memory bank is determined, so that the number of unavailable logical memory banks in each layer of the storage array is less than or equal to a second number, and the physical layer number corresponding to any memory bank is the same as or different from the logical layer number; the physical layer number represents the layer number of the memory bank in the storage array.

[0100] Here, logical memory refers to the memory that actually corresponds to the logical layer number. For example, if the logical layer number corresponding to the memory in the first column of the first layer is determined to be 2, then the memory in the second column of the first layer is taken as the logical memory in the first column of the first layer. That is, the chip select signal of the first column of the first layer is actually allocated to the memory in the second column of the first layer.

[0101] In some optional embodiments, the state of each memory bank in the memory circuit 20 can be obtained by testing the memory circuit 20 or the memory chip (e.g., a 3D DRAM chip) in which the memory circuit 20 is located. The testing method may include Built-in Self Test (BIST) or other methods, and the specific testing method is not limited.

[0102] In some optional embodiments, the states of each memory bank obtained from the test can be stored in a one-time programmable memory on the storage circuit 20 or the storage chip, such as in the fuse or OTP module. Taking a preset number of layers of 4 and a total number of columns of 9 as an example, the fuse only needs to store 4*6 bits of content, that is, it records which banks out of 36 banks are in a bad state through 4*6 bits of data, and then obtains the state of each bank through an algorithm. The logic layer number determination circuit 26 can read the test results from the one-time programmable memory and determine the state of each memory bank based on the read results. Then, based on the state of each memory bank, it determines the logic layer number corresponding to each memory bank, so that the number of unusable logic memory banks in each layer of the storage array is less than or equal to a second number, that is, the number of unusable memory banks in each layer of the storage array constructed according to the determined logic layer numbers is less than the number of redundant columns.

[0103] For example, Figure 11 This is a schematic diagram of the initial logical layer number and memory bank state of a memory array provided in an exemplary embodiment of this disclosure, as shown below. Figure 11 As shown, taking a 4-layer, 9-column storage array as an example, the storage array includes one column of redundant storage cells, meaning that 8 available storage cells need to be selected for use in each row. The initial logical layer number is the same as the physical layer number, that is, the initial logical layer numbers of each column are 1, 2, 3, and 4 respectively. GOOD indicates that the storage cell is in an available state, and BAD indicates that the storage cell is in an unavailable state. The logical layer number of each storage cell is determined according to its state as follows: Figure 12 As shown, Figure 12 This is a schematic diagram illustrating the logical layer number determined by the algorithm according to an exemplary embodiment of this disclosure. In column 6, the logical layer number of the storage cell in layer 1 becomes 2, corresponding to a BAD state, and the logical layer number of layer 2 becomes 1, corresponding to a GOOD state. That is, logically, layer 1 and layer 2 have been swapped. Figure 11 The second layer has two bad banks; after the exchange, Figure 12 The number of BAD banks in each layer becomes 1, so that each row can have 8 available memory banks through the storage circuit of this embodiment.

[0104] In some optional embodiments, the logic layer number determination circuit 26 can be implemented by hardware devices such as controllers, registers, comparators, and selectors, or by a combination of hardware and software. The specific implementation can be set according to actual needs, and this disclosure does not limit it.

[0105] The embodiments of this disclosure determine the logical layer number corresponding to each memory bank based on the state of each memory bank in the storage array, so that the number of unusable memory banks in each row of logical memory banks is less than or equal to the number of redundant memory banks in that row, thereby ensuring that each row can select the required number of memory banks, effectively improving the yield of the storage circuit.

[0106] In some optional embodiments, the second quantity is 1, and the logic layer number determination circuit is configured as follows:

[0107] The physical layer number corresponding to each storage unit is determined as the initial logical layer number for each storage unit; the layer state value corresponding to each layer is determined as the initial layer state value; the storage units in each storage component are traversed column by column and layer by layer. For the current storage unit encountered, in response to the current storage unit's state being unavailable and the column containing the current storage unit being the first column encountered with an unavailable state, the layer state value of the current storage unit's layer is updated from the initial layer state value to the first layer state value, which is the column number of the current storage unit's column plus 1; in response to the current storage unit's state being unavailable and the column containing the current storage unit not being the first column encountered... In the column of unavailable state memory, traverse the corresponding layer state value of each layer layer by layer. In response to the current layer's corresponding layer state value being the initial layer state value, update the current layer's corresponding layer state value to the second layer state value, which is the column number of the current memory's column plus 1. In response to the current layer not being the layer of the current memory, swap the initial logical layer number of the current memory with the initial logical layer number of the first memory in the same column as the current memory in the current layer to obtain the updated logical layer numbers of the current memory and the first memory. In response to the completion of the memory array traversal, obtain the logical layer number corresponding to each memory. Write the logical layer number corresponding to each memory into the corresponding first register.

[0108] The physical layer number is the actual layer number of the memory bank within the storage array. This physical layer number is used as the initial logical layer number of the memory bank. The layer state value corresponding to each layer indicates whether there are any unusable memory banks in that layer. The initial layer state value for each layer can be set to a preset value (e.g., 0).

[0109] In some optional embodiments, a status variable Flag[d][i] can be assigned to each column and each layer of storage (also called a physical bank), where d represents the d-th column and i represents the i-th layer. The value of Flag[d][i] indicates the status of the storage bank in the d-th column and i-th layer, for example, 1 represents good and 0 represents bad. A variable Vmux[d][i] can also be assigned to each column and each layer of storage to store the final logical layer number of the bank, where d represents the d-th column and i represents the i-th layer. The final logical layer number of the bank can be represented using multiple bits of data, with the value range determined by the number of bits. For example, a 4-layer storage array can be represented using 2 bits of data, with a value range of 0 to 3. A layer status variable Status[i] can be assigned to each layer to record the layer status value, indicating whether a bad bank exists in the i-th layer. For example, Status[i] being 0 indicates that there is no bad bank in the i-th layer, and Status[i] not being 0 indicates that there is a bad bank in the i-th layer. Furthermore, when Status[i] is not 0, the column with a bad bank in this layer can be recorded using Status[i]. For example, Status[i] = d + 1, where d represents the d-th column, meaning that the d-th column has a bad bank. The initial value of Status[i] (i.e., the initial layer status value) is set to 0.

[0110] In some optional embodiments, the storage array 21 is traversed column-by-column and layer-by-layer, that is, each layer of storage in each storage component is traversed column-by-column and layer-by-layer. Specifically, the storage in each layer of the first column is traversed first, then the storage in each layer of the second column is traversed, and so on. The currently traversed storage is called the current storage. If the current storage is available, the next storage continues to be traversed. If the current storage is unavailable, and the column containing the current storage is the first column traversed containing an unavailable storage, the layer status value of the current storage is updated from the initial layer status value to the first layer status value. For example, if the current storage is the storage in the ith layer of the d-th column, the layer status value Status[i] of the ith layer is updated from 0 to d+1. (See reference...) Figure 11 In the process, the storage bank in the second layer of the fourth column is unavailable, and the fourth column is the first column with a bad bank encountered during the traversal. Therefore, the layer status value Status[2] of the second layer is updated from 0 to 4+1=5. Then, the traversal continues to the next storage bank. The storage bank in the fourth row of the fourth column is also unavailable, so the layer status value Status[4] of the fourth layer is updated from 0 to 5.

[0111] If the current storage cell is unavailable, and the column containing the current storage cell is not the first column encountered that contains an unavailable storage cell, for example... Figure 11 The storage body in column 6, level 2, is traversed layer by layer, with each level being treated as the current level. If the current level's state value is the initial state value (e.g., 0), it indicates that the current level does not currently have a bad bank. The current level's state value can be updated from the initial state value to the second-level state value, which is the column number of the current storage body plus 1. For example, if the current storage body is... Figure 11 The storage body in the 6th column of the second layer needs to traverse the layer status value of each layer. When traversing to the 1st layer, the 1st layer is the current layer, and the layer status value of the 1st layer is the initial layer status value, indicating that there is no bad bank in the 1st layer. The layer status value Status[1] of the 1st layer is updated to 6+1=7. If the current layer is not the layer where the current storage body is located, the initial logical layer number of the current storage body is compared with the first storage body in the same column as the current storage body in the current layer (e.g., the first storage body in the same column as the current storage body). Figure 11 The initial logical layer number of the memory bank in the 6th column of the first layer is swapped. The initial logical layer number of the first memory bank is used as the logical layer number of the current memory bank, and vice versa. If the current layer is the same as the layer containing the current memory bank, no swap is needed. The traversal of layer state values ​​ends, and the traversal continues to the next memory bank. For example, Figure 11 In the process of traversing the memory bank in column 7, layer 3, the layer state value traversal is entered again. At this time, the layer state values ​​of layers 1 and 2 have been updated, and the layer state value of layer 3 is the initial layer state value, which is exactly the layer where the current memory bank is located. The layer state value of layer 3 is updated from the initial layer state value to 7 + 1 = 8, without any swapping, and the traversal of the next memory bank continues. This process continues until all memory banks in the memory array have been traversed, and the final logical layer number of each memory bank is obtained, such as... Figure 12 As shown. Then, the logical layer number corresponding to each memory bank can be written into the chip select allocation unit, specifically into the first register in the chip select allocation unit.

[0112] The embodiments of this disclosure traverse each memory bank column by column and layer by layer, and adjust the bad bank logic in the same layer that exceeds the number of redundant columns to other layers according to the state of the memory bank, so that the number of bad banks in each layer is less than or equal to the number of redundant columns (i.e., the second number), effectively improving the yield of memory circuits and memory chips.

[0113] In some optional embodiments, for the case where the second quantity is greater than 1, the approach to determining the logical layer number is similar to that when the second quantity is 1. Taking the case where the second quantity is 2 as an example, the purpose of determining the logical layer number is to ensure that the number of bad banks in each layer is less than or equal to 2. For example, based on the redundancy of the above column 1, other variables can be added to record the two bad bank columns of each layer, as well as the variable to record the number of bad banks in each layer. By traversing each storage unit column by column and layer by layer, for each bad bank in the first column where a bad bank exists, the logical layer number can be left unchanged; only the existence and number of bad banks in each layer can be recorded. For each bad bank in the second column where a bad bank exists, the logical layer number can also be left unchanged; only the existence and number of bad banks in each layer can be updated. For the bad bank in the third column where a bad bank exists, the logical layer number is adjusted according to the number of bad banks in each layer. For example, if the layer where the current bad bank is located already has two bad banks, the number of bad banks in each layer is traversed, and a layer with fewer than two bad banks is found (called the current layer). The number of bad banks in the current layer is incremented by 1, and the current column of the current layer is recorded as having a bad bank. The initial logical layer number of a bank is swapped with the initial logical layer number of the bank in the same column of the current layer to move bad banks in each layer that exceed the number of redundant columns to other layers. Specifically, when determining a layer with fewer than two bad banks, it can also be determined whether the bank in the same column as the current bad bank in that layer is also a bad bank. If it is, the logical layer number is not swapped, and the process continues to iterate through the number of bad banks in the next layer to ensure that the state corresponding to the logical layer number of the current bad bank after the swap is "good". For example, in a 4-layer system with 8 bad banks, the determined logical layer numbers ensure that there are 2 bad banks in each row.

[0114] For cases where the second quantity is 3, 4, etc., the specific approach to determining the logical layer number is similar to that when the second quantity is 2, and will not be elaborated further. In general, based on the state of each memory bank, the logical layer number of each memory bank is adjusted so that the number of unusable logical memory banks in each layer after adjustment is less than or equal to the second quantity.

[0115] Figure 13 This is a schematic diagram of the structure of a storage circuit provided in yet another exemplary embodiment of this disclosure.

[0116] In some alternative embodiments, based on any of the above embodiments, such as Figure 13As shown, the storage circuit 20 or logic control circuit 22 may further include: a selection enable information determination circuit 27.

[0117] The enable information determination circuit 27 is configured as follows:

[0118] The process iterates through the layer state values ​​corresponding to each layer. For the current layer, if the layer state value is the initial layer state value, the selection enable information of each memory bank in the current layer is determined to be a first preset value. If the layer state value is not the initial layer state value, the selection enable information of the memory bank located on the second side of the unavailable memory bank in the current layer is determined to be the first preset value, and the selection enable information of the unavailable memory bank and the memory bank located on the first side of the unavailable memory bank is determined to be the second preset value. After the traversal of each layer is completed, the selection enable information corresponding to each memory bank is obtained. The selection enable information corresponding to each memory bank is written into the second register.

[0119] The layer state values ​​corresponding to each layer are determined during the process of determining the logical layer number. For example, the value of Status[i] above represents the layer state value of the i-th layer. That is, in Figure 12 Based on the logical memory bank shown, determine the selection enable information corresponding to each memory bank.

[0120] For the current layer being traversed, if the layer state value of the current layer is the initial layer state value, it means that there is no bad bank in the current layer. The first preset value is the value of the column with the smaller column number. For example, if the two selection terminals of the MUX in the data input / output selection unit are connected to the data input / output terminals of the k-th (k = 1, 2, ..., mf) and k+1-th columns respectively, when the selection enable information is 0, the MUX selects the k-th column; when the selection enable information is 1, the MUX selects the k+1-th column. Therefore, the first preset value is 0, meaning that if there is no bad bank in the current layer, the storage of the first mf columns in the current layer can be directly selected. If the layer state value of the current layer is not the initial layer state value, it means that there is a bad bank (i.e., storage in an unavailable state) in the current layer. The second side of the unavailable storage can be the side with a column number smaller than that of the unavailable storage. For example... Figure 12 The second side of column 4 refers to the left side of column 4, such as columns 1, 2, and 3. The selection enable information for the storage bank located on the second side of the unavailable storage bank in the current layer is set to a first preset value (e.g., 0 as mentioned above), indicating that columns before the bad bank in the current layer can use their own storage banks without needing to be misaligned. The selection enable information for the bad bank and the storage bank on the first side of the bad bank is set to a second preset value, such as 1, indicating that starting from this bad bank, misalignment is required, meaning this layer does not use the bad bank. For example... Figure 12 In the second layer, the selection enable information corresponding to columns 1, 2, and 3 is all 0, and the selection enable information corresponding to columns 4 to 7 is all 1. This means that in the second layer, the storage in column 5 is used as the storage in column 4, the storage in column 6 is used as the storage in column 5, ..., and the storage in column 9 is used as the storage in column 8. Thus, 8 usable storages are selected from 9 storages to meet the storage requirements of this layer.

[0121] For example, Figure 14 This is a schematic diagram of selection enable information provided in an exemplary embodiment of this disclosure, such as... Figure 14 As shown, in Figure 12 Based on the logical layer number shown, the selection enable information Hshift corresponding to each memory bank in the first 8 columns is shown in the figure. The 9th column is a redundant column. There are a total of 8 MUXs, so the selection enable information in the 9th column does not need to be determined.

[0122] In the embodiments of this disclosure, an enable information determination circuit is used to determine the enable information for each memory bank in each layer according to the layer state value corresponding to each layer. This enables the data input / output selection unit to select the available memory bank in each layer, ensuring that the storage circuit can function normally.

[0123] In some optional embodiments, for cases where the second quantity is greater than 1, based on the state of the logical memory bank after determining the logical layer number, the selection enable information corresponding to each memory bank is determined according to the method of skipping unavailable memory banks described above. For example, Figure 15 This is a schematic diagram illustrating the logical layer number and selection enable information provided in an exemplary embodiment of this disclosure, such as... Figure 15As shown, taking a second quantity of 2, a preset number of 4 layers, and a total number of 10 columns as an example, there are 2 bad banks in the first layer, namely the bad banks in columns 6 and 8. The column selection enable information before the first bad bank (e.g., column 6 in the first layer of the figure) is 0. The selection enable information of the column one column before the first bad bank (e.g., column 8 in the first layer of the figure) (column 6) is 1, that is, the selection enable information Hshift = 1 for column 6 in the first layer. The selection enable information from the column before the second bad bank (e.g., column 8 in the first layer of the figure) to the last non-redundant column is Hshift = 2. That is, if there are non-redundant columns after the second bad bank, the selection enable information of the non-redundant columns after the second bad bank is also Hshift = 2. In this way, when the storage array is working, in Layer 1, columns 1 through 5 select and use the memory cells in their respective columns. Column 6 is offset by one column, meaning it uses the memory cells in column 7. Columns 7 and 8 are offset by two columns because column 8 is a bad bank, so column 7 cannot use it. Therefore, column 7 uses the memory cells in column 9, and column 8 uses the memory cells in column 10. Thus, in Layer 1, 8 usable memory cells can be selected from 10. The other layers are similar to Layer 1 and will not be described in detail here.

[0124] In some optional embodiments, when the second quantity is greater than 1, the selection enable information can be represented by multiple bits. For example, if the second quantity is 2, 2 bits can be used to represent the selection enable information. For example, 00, 01, and 10 correspond to the three selection terminals of the MUX, and the three selection terminals of the MUX are connected to the data input and output terminals of three adjacent columns. The control principle of the MUX will not be elaborated.

[0125] In some alternative embodiments, Figure 16 This is a schematic diagram of the structure of a storage circuit provided in another exemplary embodiment of this disclosure. For example... Figure 16As shown, the storage array 21 includes 4 layers and 9 columns. Bank(d, i) represents the bank in the d-th column and i-th row, where d = 0, 1, 2, ..., 7, and i = 0, 1, 2, 3. In practical applications, d and i can also start from 1, as described in the previous embodiment. 2to4CSDecoder represents a 2-to-4 chip select signal decoder, and row_addr_msb<1:0> represents the highest 2 bits of the row address. The decoder outputs the chip select signal. <0> , <1> , <2> , <3> These represent the layers corresponding to the output, and hshift[7:0][i] represents the 8 selection enable information for the i-th layer. Each MUX selects the left column when the selection enable information is 0, and selects the right column when the selection enable information is 1. WD <0> / RD <0> Indicates input / output data, WD indicates write (i.e., input) data, and RD indicates read (i.e., output) data.

[0126] The relevant technologies include the following two bank repair solutions:

[0127] The first approach treats the multi-layered stacked banks as a whole, sharing the data bus and address bus TSVs (Through Silicon Vias) and memory controller. Based on this, all stacked banks are divided into multiple groups, with each group introducing a redundant stacked bank as the basis for bank repair. Taking a 4-layer stack as an example, if the yield of each single-layer bank is P = 98%, then the yield of each 4-layer stacked bank is P0. 4 =92.2%. If each bank group includes 8 four-layer stacked banks and 1 redundant four-layer stacked bank, then the yield of selecting 8 usable stacked banks from 9 stacked banks (i.e., the yield of a bank group) is 92.2% raised to the power of 8, which is 52.2%. If the number of bank groups included in the chip is 32, then the yield of the chip is the yield of the bank group 52.2% raised to the power of 32, which is about 0.5%. Obviously, this cannot meet the mass production standard.

[0128] The second approach involves not treating the four-layer stacked banks as a single unit. Banks on different layers no longer share databus, address bus, and memory controllers. Each layer's data bus and address bus signals are provided independently via TSVs. The memory controller is also no longer shared across the four layers; each bank layer has its own independent memory controller. This reduces the number of banks in each bank group from nine four-layer stacked banks to 36 single-layer, non-stacked banks. 32 usable banks need to be selected from these 36 single-layer banks, and then this selection is done in four separate steps, achieving the effect of eight stacked banks. Based on the same yield estimates, the chip yield can reach 97.7%, meeting mass production requirements. However, as analyzed above, this approach comes at a significant cost: the number of TSVs for data and address buses, as well as the number of memory controllers, is four times that of the first approach. Furthermore, the hardware logic for bank repair is more complex, resulting in a substantial, even unacceptable, area overhead in the logic layer.

[0129] Regarding the two solutions mentioned above, the storage circuit of this disclosure embodiment can simultaneously take into account the circuit area advantage of the first solution and the yield advantage of the second solution. That is, with extremely low area overhead, the yield of 3D DRAM can be greatly improved, ensuring that 3D DRAM can be mass-produced at an acceptable cost.

[0130] The various embodiments and optional examples disclosed herein can be implemented individually or in any combination without conflict, and can be set according to actual needs.

[0131] Exemplary methods

[0132] Figure 17 This is a schematic flowchart illustrating a configuration method for a storage circuit provided in an exemplary embodiment of this disclosure. The method of this embodiment can be used to configure the storage circuit 20 of any of the above embodiments. This method can be applied to a processor, an electronic device, or related dedicated circuits in the storage circuit 20. The electronic device can be, for example, any device with processing capabilities such as a server, computer, or mobile phone. The processor can be the CPU on the chip where the storage circuit is located. Related dedicated circuits in the storage circuit 20 may include, for example, the logic layer number determination circuit and the selection enable information determination circuit described above. Figure 17 As shown, the method of this disclosure embodiment may include the following steps:

[0133] Step 510: Obtain the state of each memory cell in the memory circuit.

[0134] The state of the memory bank can be obtained by testing the memory circuit; the state of each memory bank includes an available state or an unavailable state.

[0135] Step 520: Determine the logical layer number corresponding to each memory bank based on the state of each memory bank, so that the number of unavailable logical memory banks in each layer of the storage array is less than or equal to the second number.

[0136] In this context, the physical layer number and logical layer number corresponding to any memory bank may be the same or different; the physical layer number represents the layer number of the memory bank in the memory array.

[0137] Step 530: Determine the selection enable information of the data input / output selection unit corresponding to each main storage component.

[0138] Optionally, the selection enable information corresponding to each storage bank in each main storage component can be determined based on the layer state value of each layer after adjusting the logical layer number.

[0139] Step 540: Configure the logic layer number and selection enable information into the memory circuit.

[0140] The logic layer number can be configured into the first register or the first memory in the storage circuit, and the selection enable information can be configured into the second register or the second memory in the storage circuit.

[0141] For details on the specific operations of each of the above steps, please refer to the relevant embodiments of the aforementioned storage circuit 20, which will not be repeated here.

[0142] In some optional embodiments, step 520, which determines the logical layer number corresponding to each memory bank based on the state of each memory bank, may include:

[0143] The physical layer number corresponding to each storage unit is determined as the initial logical layer number corresponding to each storage unit; the layer state value corresponding to each layer is determined as the initial layer state value; the storage units in each storage component are traversed column by column and layer by layer. For the current storage unit encountered, in response to the current storage unit's state being unavailable and the column containing the current storage unit being the first column containing an unavailable storage unit, the layer state value of the layer containing the current storage unit is updated from the initial layer state value to the first layer state value, which is the column number of the current storage unit's column plus 1; in response to the current storage unit's state being unavailable and the column containing the current storage unit being the first column containing an unavailable storage unit, the layer state value of the layer containing the current storage unit is updated from the initial layer state value to the first layer state value, which is the column number of the current storage unit's column plus 1; If the column is not the first column containing an unavailable memory cell, the system iterates through each layer, checking the corresponding layer state value. If the current layer's state value is the initial layer state value, the current layer's state value is updated to the second layer state value, which is the column number of the current memory cell's column plus 1. If the current layer is not the layer containing the current memory cell, the initial logical layer number of the current memory cell is swapped with the initial logical layer number of the first memory cell in the same column as the current memory cell, resulting in updated logical layer numbers for both the current and first memory cells. Once the memory array traversal is complete, the logical layer number corresponding to each memory cell is obtained.

[0144] In some optional embodiments, step 530, determining the selection enable information of the data input / output selection unit corresponding to each main storage component, may include:

[0145] The layer state values ​​corresponding to each layer are traversed layer by layer. For the current layer, if the layer state value of the current layer is the initial layer state value, the selection enable information of each memory bank in the current layer is determined as the first preset value. If the layer state value of the current layer is not the initial layer state value, the selection enable information of the memory bank located on the second side of the unavailable memory bank in the current layer is determined as the first preset value, and the selection enable information of the unavailable memory bank and the memory bank located on the first side of the unavailable memory bank is determined as the second preset value. After the traversal of each layer is completed, the selection enable information corresponding to each memory bank is obtained.

[0146] In some alternative embodiments, step 540, configuring the logic layer number and selection enable information to the memory circuit, may include:

[0147] Write the logic layer number corresponding to each memory bank into the corresponding first register in the storage circuit; write the selection enable information into the second register in the storage circuit; or write the logic layer number and the selection enable information into a one-time programmable memory in the storage circuit, such as the first memory and the second memory in the aforementioned embodiments.

[0148] The specific operations of each step in the above method embodiments can be found in the corresponding content of the aforementioned storage circuit embodiments, and will not be repeated here.

[0149] The various embodiments and optional examples disclosed herein can be implemented individually or in any combination without conflict, and can be set according to actual needs.

[0150] This disclosure also provides a chip, including the storage circuit 20 provided in any of the above embodiments.

[0151] This disclosure also provides a chip, including a processor; and a storage circuit 20 provided in any of the above embodiments; the processor is configured to acquire executable instructions and execute the instructions to implement the configuration method of the storage circuit provided in any of the above embodiments, so as to configure the storage circuit 20.

[0152] This disclosure also provides an electronic device including the chip provided in any of the above embodiments.

[0153] This disclosure also provides an electronic device, including: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the configuration method of the storage circuit described in any of the above embodiments. This electronic device can be any device with processing capabilities, such as a server, mobile phone, or computer.

[0154] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0155] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0156] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0157] The circuits or apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps of the method in the circuit is for illustrative purposes only, and the steps of the method of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the method according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the method according to this disclosure.

[0158] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0159] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0160] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A storage circuit, comprising: The storage array includes multiple columns of storage components, each column of storage components including a predetermined number of stacked storage cells; The multi-column storage component includes a primary storage component with a first number of columns and a redundant storage component with a second number of columns; Logic control circuit, including: Each of the aforementioned storage components corresponds to a chip select allocation unit; Each of the main storage components has a corresponding data input / output selection unit; Wherein, the chip select allocation unit corresponding to any storage component is configured to allocate the chip select signal to the storage bank in the storage component that corresponds to the logical layer number according to the pre-configured logical layer number of the storage bank; The multiple selection terminals of the data input / output selection unit corresponding to any of the main storage components are respectively connected to the data input / output terminals of the main storage component and the data input / output terminals of at least one storage component on the first side of the main storage component; the data input / output selection unit corresponding to the main storage component is configured to select the data input / output terminal of the main storage component and the at least one storage component on the first side of the main storage component that corresponds to the selection enable information according to the chip select signal and the pre-configured selection enable information, so as to input or output data through the data input / output terminal of the target storage component.

2. The storage circuit according to claim 1, wherein, The chip selection allocation unit includes: A preset number of allocators; the preset number is the same as the preset number of layers; the first input terminal of each allocator is connected to a first output terminal of a chip select decoder; the multiple second output terminals of each allocator are connected to the memory cells of each layer in the storage component; each allocator is configured to allocate the chip select signal output by a first output terminal of the chip select decoder to the memory cell in the storage component corresponding to the logical layer number, according to the pre-configured logical layer number of the memory cell.

3. The storage circuit according to claim 2, wherein, The distributor includes: The first register is configured to store the logical layer number; A decoder is connected to the first register; A preset number of switches are connected to a preset number of output terminals of the decoder and to the memory cells of each layer in the memory component; The decoder is configured to decode the logic layer number and control the state of each switch through a preset number of output terminals to allocate the chip select signal to the memory bank corresponding to the logic layer number.

4. The storage circuit according to claim 2, wherein, The storage circuit further includes a first memory configured to store the logic layer number corresponding to each of the distributors, wherein the first memory is a one-time programmable memory.

5. The storage circuit according to claim 3, wherein, The storage circuit also includes: The controller is configured as follows: Receive logical layer number configuration information from the processor; The logical layer number is configured in the first register of each of the allocators according to the logical layer number configuration information.

6. The storage circuit according to claim 1, wherein, The logic control circuit also includes: An enable information selection unit is provided; multiple second input terminals of the enable information selection unit are respectively connected to the first output terminals of each chip select decoder; multiple third input terminals of the enable information selection unit are respectively used to input the selection enable information of each layer; the third output terminal of the enable information selection unit is connected to the enable control terminal of each data input / output selection unit, and is used to provide selection enable information to each data input / output selection unit.

7. The storage circuit according to claim 6, wherein, Also includes: The second register is connected to each of the third input terminals of the enable information selection unit; The second register is configured to store the selection enable information; or, The storage circuit further includes a second memory connected to each of the third input terminals of the enable information selection unit; the second memory is configured to store the selection enable information, and the second memory is a one-time programmable memory.

8. The storage circuit according to claim 7, wherein, Also includes: The controller is configured as follows: Receive selection enable information and configuration information from the processor; Configure the selection enable information into the second register according to the selection enable information configuration information.

9. The storage circuit according to any one of claims 1-8, wherein, Also includes: The chip select decoder is configured to decode a specified address bit of the input row address into a chip select signal and output the chip select signal to each of the chip select allocation units.

10. The storage circuit according to any one of claims 1-8, wherein, Also includes: The logic layer number determination circuit is configured as follows: Obtain the state of each memory cell in the storage array; The state is obtained by testing the storage circuit; the state of each storage element includes an available state or an unavailable state; Based on the state of each memory cell, the logical layer number corresponding to each memory cell is determined, so that the number of unavailable logical memory cells in each layer of the storage array is less than or equal to the second number, and the physical layer number and logical layer number corresponding to any memory cell are the same or different. The physical layer number indicates the layer number of the storage unit in the storage array.

11. The storage circuit according to claim 10, wherein, The second quantity is 1, and the logic layer number determination circuit is configured as follows: The physical layer number corresponding to each memory bank is determined as the initial logical layer number corresponding to each memory bank. Determine the initial layer state value for each layer; The storage units in each storage component are traversed in a column-by-column and layer-by-layer order. For the current storage unit that is traversed, in response to the current storage unit being in an unavailable state and the column where the current storage unit is located being the first column where an unavailable storage unit is traversed, the layer status value of the layer where the current storage unit is located is updated from the initial layer status value to the first layer status value, where the first layer status value is the column number of the column where the current storage unit is located plus 1. In response to the current memory bank being in an unavailable state, and the column containing the current memory bank is not the first column traversed to contain an unavailable memory bank, the system iterates through each layer to find the corresponding layer state value. In response to the current layer being traversed and finding that the current layer's corresponding layer state value is the initial layer state value, the current layer's corresponding layer state value is updated to the second layer state value, which is the column number of the current memory bank's column plus 1. In response to the current layer not being the layer containing the current memory bank, the initial logical layer number of the current memory bank is swapped with the initial logical layer number of the first memory bank in the same column as the current memory bank in the current layer, to obtain the updated logical layer numbers of the current memory bank and the first memory bank. In response to the completion of the traversal of the storage array, the logical layer number corresponding to each of the storage cells is obtained; Write the logical layer number corresponding to each of the memory banks into the corresponding first register.

12. The storage circuit according to claim 11, wherein, Also includes: The enable information determination circuit is configured as follows: The layer state values ​​corresponding to each layer are traversed layer by layer. For the current layer, in response to the current layer state value being the initial layer state value, the selection enable information of each memory bank in the current layer is determined as the first preset value. In response to the fact that the current layer state value is not the initial layer state value, the selection enable information of the storage cell located on the second side of the unavailable storage cell in the current layer is determined to the first preset value, and the selection enable information of the unavailable storage cell and the storage cell located on the first side of the unavailable storage cell is determined to the second preset value. In response to the completion of each layer traversal, the selection enable information corresponding to each of the aforementioned storage entities is obtained; Write the selection enable information corresponding to each of the aforementioned memory banks into the second register.

13. A method for configuring a storage circuit, used in any one of the storage circuits according to claims 1-12, the method comprising: Obtain the state of each memory cell in the storage circuit; The state is obtained by testing the storage circuit; The state of each storage unit includes an available state or an unavailable state; Based on the state of each memory cell, the logical layer number corresponding to each memory cell is determined, so that the number of unavailable logical memory cells in each layer of the storage array is less than or equal to the second number. The physical layer number corresponding to any memory cell may be the same as or different from the logical layer number; the physical layer number represents the layer number of the memory cell in the storage array. Determine the selection enable information of the data input / output selection unit corresponding to each of the main storage components; Configure the logic layer number and the selection enable information into the storage circuit.

14. The method according to claim 13, wherein, The step of determining the logical layer number corresponding to each of the memory banks based on their states includes: The physical layer number corresponding to each memory bank is determined as the initial logical layer number corresponding to each memory bank. Determine the initial layer state value for each layer; The storage units in each storage component are traversed in a column-by-column and layer-by-layer order. For the current storage unit that is traversed, in response to the current storage unit being in an unavailable state and the column where the current storage unit is located being the first column where an unavailable storage unit is traversed, the layer status value of the layer where the current storage unit is located is updated from the initial layer status value to the first layer status value, where the first layer status value is the column number of the column where the current storage unit is located plus 1. In response to the current memory bank being in an unavailable state, and the column containing the current memory bank is not the first column traversed to contain an unavailable memory bank, the system iterates through each layer to find the corresponding layer state value. In response to the current layer being traversed and finding that the current layer's corresponding layer state value is the initial layer state value, the current layer's corresponding layer state value is updated to the second layer state value, which is the column number of the current memory bank's column plus 1. In response to the current layer not being the layer containing the current memory bank, the initial logical layer number of the current memory bank is swapped with the initial logical layer number of the first memory bank in the same column as the current memory bank in the current layer, to obtain the updated logical layer numbers of the current memory bank and the first memory bank. In response to the completion of the traversal of the storage array, the logical layer number corresponding to each of the storage cells is obtained.

15. The method according to claim 14, wherein, The step of determining the selection enable information of the data input / output selection unit corresponding to each of the main storage components includes: The layer state values ​​corresponding to each layer are traversed layer by layer. For the current layer, in response to the current layer state value being the initial layer state value, the selection enable information of each memory bank in the current layer is determined as the first preset value. In response to the fact that the current layer state value is not the initial layer state value, the selection enable information of the storage cell located on the second side of the unavailable storage cell in the current layer is determined to the first preset value, and the selection enable information of the unavailable storage cell and the storage cell located on the first side of the unavailable storage cell is determined to the second preset value. In response to the completion of each layer traversal, the selection enable information corresponding to each of the aforementioned storage entities is obtained.

16. The method according to any one of claims 13-15, wherein, The step of configuring the logic layer number and the selection enable information to the storage circuit includes: Write the logic layer number corresponding to each of the memory banks into the corresponding first register in the memory circuit; Write the selection enable information into the second register in the storage circuit; or... The logic layer number and the selection enable information are written into the one-time programmable memory in the storage circuit.

17. A chip comprising the memory circuit according to any one of claims 1-12.

18. A chip, comprising: processor; And the storage circuit according to any one of claims 1-12; The processor is configured to acquire executable instructions and execute the instructions to implement the configuration method of the memory circuit according to any one of claims 13-16, so as to configure the memory circuit.

19. An electronic device comprising: The chip according to claim 17 or 18.

20. An electronic device, comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the configuration method of the memory circuit according to any one of claims 13-16.

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