Integrated circuit with built-in self-repair and method thereof

Abstract

The present disclosure relates to an integrated circuit providing built-in self-repair and a method thereof. The integrated circuit includes hardware resources. An example integrated circuit includes at least one first flip-flop configured to latch scan data output from the integrated circuit in a first mode and to latch repair data in a second mode, and a control circuit configured to repair a defective resource among the hardware resources based on the repair data latched by the at least one first flip-flop in the second mode.

Description

Technical Field

[0001] This disclosure relates to providing integrated circuits with built-in self-healing and methods thereof. Background Technology

[0002] Integrated circuits can exhibit errors caused by a variety of factors. For example, each wafer and the chips within it may exhibit different characteristics due to the semiconductor manufacturing process. Therefore, it is possible to produce integrated circuits that fail to provide the designed functionality and / or performance. If all integrated circuits that fail testing are discarded, the overall yield of integrated circuits in the semiconductor manufacturing process can be significantly reduced. Summary of the Invention

[0003] In some implementations, an integrated circuit including multiple hardware resources includes: at least one first trigger configured to latch scan data in a first mode and latch repair data in a second mode, the scan data being output from the integrated circuit; and control circuitry configured to repair defective resources among the multiple hardware resources based on the repair data latched by the at least one first trigger in the second mode.

[0004] In some implementations, a method performed by an integrated circuit including multiple hardware resources includes: latching scan data via at least one first trigger in a first mode, the scan data being output from the integrated circuit; latching repair data via the at least one first trigger in a second mode; and repairing a defective resource among the hardware resources based on the repair data latched in the at least one first trigger in the second mode.

[0005] In some implementations, a method for providing a built-in self-healing integrated circuit, executed by at least one processor, includes: acquiring input data defining a plurality of hardware resources included in the integrated circuit; and generating output data defining the integrated circuit based on the input data. Generating the output data includes: adding information to the input data defining at least one first trigger, the at least one first trigger configured to latch scan data in a first mode and latch repair data in a second mode; adding information to the input data defining a repair circuit configured to provide the repair data to the at least one first trigger in the second mode; and adding information to the input data defining a control circuit configured to repair defective resources among the plurality of hardware resources based on the repair data latched by the at least one first trigger. Attached Figure Description

[0006] These and / or other aspects, features, and advantages of this disclosure will become clear and more readily apparent from the following description of exemplary embodiments taken in conjunction with the accompanying drawings.

[0007] Figure 1 An example of an integrated circuit is shown.

[0008] Figure 2 An example of a flipflop is shown.

[0009] Figure 3A and Figure 3B An example of a function block is shown.

[0010] Figure 4 An example of an integrated circuit is shown.

[0011] Figure 5 An example of a control circuit is shown.

[0012] Figure 6 An example of an integrated circuit is shown.

[0013] Figure 7A , Figure 7B and Figure 7C An example of a multiplexing circuit is shown.

[0014] Figure 8 An example of the system is shown.

[0015] Figure 9 This is a flowchart illustrating an example of a built-in self-healing method.

[0016] Figure 10 This is a flowchart illustrating an example of a built-in self-healing method.

[0017] Figure 11 This is a flowchart illustrating an example of a built-in self-healing method.

[0018] Figure 12 This is a flowchart illustrating an example of a method for manufacturing integrated circuits.

[0019] Figure 13 This is a flowchart illustrating an example of a built-in self-healing method.

[0020] Figure 14 This is a block diagram illustrating an example of a System-on-Chip (SoC).

[0021] Figure 15 This is a block diagram illustrating an example of a computing system including memory for storing programs. Detailed Implementation

[0022] Figure 1An example of integrated circuit 10 is shown. Integrated circuit 10 can be any device manufactured using semiconductor manufacturing processes. For example, integrated circuit 10 can be included in a chip diced from a wafer and can be packaged separately or together with at least one other chip. Figure 1 As shown, integrated circuit 10 may include functional block 11, hardware resources 12, repair circuitry 13, and control circuitry 14. Similar to control circuitry 14, the blocks shown herein can have any structure designed to perform a given function. For example, the block may include at least one processor for executing software, such as a central processing unit (CPU), graphics processing unit (GPU), and neural processing unit (NPU); hardware intellectual property (hardware IP) designed to perform a fixed function, such as a hardware accelerator; or reconfigurable components, such as a field-programmable gate array (FPGA).

[0023] Functional block 11 can be designed to perform the functions required by integrated circuit 10. For example, functional block 11 can be designed to process digital signals and can include various types of logic circuits, including combinational logic and / or sequential logic. In some embodiments, as will be referred to later... Figure 12 As described, function block 11 can be implemented through logic synthesis. For example... Figure 1 As shown, functional block 11 may include a scan flip-flop SF and a function flip-flop FF as sequential logic. Here, the scan flip-flop SF may be referred to as the first flip-flop, and the function flip-flop FF may be referred to as the second flip-flop.

[0024] Functional block 11 can use hardware resource 12 to perform its functions. In some embodiments, hardware resource 12 may include a computation block, and functional block 11 may use the computation block to perform computations. In some embodiments, hardware resource 12 may include a storage unit, and functional block 11 can perform its functions by writing data to or reading data from the storage unit.

[0025] Each of the multiple wafers can exhibit different characteristics due to the semiconductor manufacturing process used to manufacture integrated circuit 10. Multiple chips within a wafer can also exhibit different characteristics, and the hardware resources 12 included in the integrated circuit can also exhibit different characteristics. Therefore, hardware resources 12 can include defective resources, i.e., resources that do not provide the designed functionality and / or performance. When functional block 11 uses defective resources, integrated circuit 10 may exhibit errors, and these defective resources can be tested to detect them. When all integrated circuits that fail the test are discarded, the yield of integrated circuit 10 in the semiconductor manufacturing process can be significantly reduced. As described below, integrated circuit 10 can provide built-in self-healing to repair defective resources. Hardware resources 12 can include redundant resources, and built-in self-healing can be performed by replacing defective resources with redundant resources. Built-in self-healing can improve the reliability and yield of integrated circuit 10.

[0026] Repair circuit 13 can provide repair data REP to functional block 11. Repair data REP can refer to data required to repair defective resources included in hardware resource 12. For example, repair data REP can include information about defective and / or redundant resources in the hardware resources. Figure 1 As shown, the repair circuit 13 may include a non-volatile memory (NVM), and the NVM may store repair data (REP). Therefore, the repair data (REP) will not be lost even when the power supply to the integrated circuit 10 is cut off. In some embodiments, the NVM may include a one-time programmable memory (OTP memory) such as an eFuse. (See reference...) Figure 8 As described below, the repair data REP can be written to the non-volatile memory NVM while the integrated circuit 10 is being tested.

[0027] Function block 11 can be set to either scan mode or normal mode. For example, function block 11 can be set to scan mode or normal mode based on signals received from outside integrated circuit 10. Here, scan mode can be referred to as the first mode, and normal mode can be referred to as the second mode. In scan mode, integrated circuit 10 can output scan data (i.e., data stored in the timing logic of function block 11) to the outside via the scan chain at a given time (e.g., a specific clock cycle) to check the state of function block 11 or debug function block 11. Scan flip-flops SF and function flip-flops FF can be included in the scan chain and can latch scan data in scan mode.

[0028] Function block 11 can execute its designed function in normal mode. In normal mode, the function trigger FF can latch function data, i.e., data generated as function block 11 executes its designed function. Function block 11 can operate based on the data latched in the function trigger FF, and the generated data can also be latched in the function trigger FF. In normal mode, the scan trigger SF can latch repair data REP. For example, the scan trigger SF can latch the repair data REP provided by repair circuit 13 and provide the latched repair data REP to control circuit 14. Unlike the function trigger FF used for the operation of function block 11 in normal mode, the scan trigger SF can latch the repair data REP and hold the repair data REP to be provided to control circuit 14.

[0029] Control circuit 14 can repair defective resources in hardware resource 12 based on repair data REP provided by function block 11. For example, control circuit 14 can receive repair data REP from scan trigger SF of function block 11 in normal mode. Control circuit 14 can identify defective and / or redundant resources in hardware resources based on repair data REP. Control circuit 14 can switch function block 11's access to defective resources to access redundant resources. Repair circuit 13 and control circuit 14 can generally be referred to as built-in self-healing circuits.

[0030] A scan trigger SF can be inserted in scan mode to observe the operation of function block 11. The scan trigger SF can be inserted regardless of the function of function block 11 to facilitate observation of its state or debugging, and it enhances the observability of function block 11. Therefore, while the scan trigger SF can be used to latch scan data in scan mode, it may not be used for the operation of function block 11 in normal mode. In normal mode, control circuitry 14 may require consistent repair data REP and may need a latch to hold the repair data REP in normal mode. As described above, the scan trigger SF inserted to observe the operation of function block 11 can be used to hold the repair data REP in normal mode, eliminating the need for an additional latch to hold the repair data REP. Therefore, built-in self-healing in integrated circuit 10 can be implemented at a reduced cost, and the efficiency of integrated circuit 10 can be improved.

[0031] Figure 2 An example of trigger 20 is shown. For example, Figure 2 Trigger 20 can be Figure 1 Examples of scan triggers SF and function triggers FF. Figure 1 The scan trigger SF and the function trigger FF are not limited to Figure 2Trigger 20. Refer to below. Figure 1 describe Figure 2 .

[0032] refer to Figure 2 The flip-flop 20 may include a data input D, a scan input SI, a scan enable input SE, a clock input CK, and a data output Q. When the scan enable input SE is deactivated, i.e., when the integrated circuit 10 is in normal mode, the flip-flop 20 can latch the data input D based on the clock input CK and output the latched data input D as the data output Q. When the scan enable input SE is activated, i.e., when the integrated circuit 10 is in scan mode, the flip-flop 20 can latch the scan input SI based on the clock input CK and output the latched scan input SI as the data output Q.

[0033] In some implementations, each of the scan trigger SF and the function trigger FF can receive the data output of the preceding trigger in the scan chain as a scan input SI. In some implementations, each scan trigger SF can receive a bit of the repair data REP as a data input D, and each function trigger FF can receive the output bit of the combinational logic of function block 11 as a data input D.

[0034] Figure 3A and Figure 3B An example of a function block is shown. For example, Figure 3A Function block 30a in scan mode is shown, while Figure 3B Function block 30b in normal mode is shown. For example... Figure 3A and Figure 3B As shown, function blocks 30a and 30b may include first scan triggers SF1 to fifth scan triggers SF5 and first function triggers FF1 to ninth function triggers FF9.

[0035] refer to Figure 3A Function block 30a can be set to scan mode, and scan data SCA can be transmitted through the scan chain. For example... Figure 3A As shown, the first scan triggers SF1 to the fifth scan triggers SF5 and the first function triggers FF1 to the ninth function triggers FF9 can be chained together. Scan data SCA can be output as the final output from function block 30a. In some embodiments, with... Figure 3A As shown, scan triggers and function triggers can be included in different scan chains. For example, a scan trigger can be included in a first scan chain, and a function trigger can be included in a second scan chain.

[0036] refer to Figure 3BFunction block 30b can be set to normal mode, and the first scan triggers SF1 to the fifth scan triggers SF5 and the first function triggers FF1 to the ninth function triggers FF9 can execute their own functions. For example... Figure 3B As shown, each of the first scan triggers SF1 to the fifth scan trigger SF5 can latch and output the bits of the repair data REP. Additionally, the first function trigger FF1 to the ninth function trigger FF9 can latch the bits required to execute the designed function of function block 30b. (See above reference...) Figure 1 As mentioned above, since the first scan trigger SF1 to the fifth scan trigger SF5 are used to latch repair data REP in normal mode, built-in self-repair can be achieved at a reduced cost.

[0037] Figure 4 An example of integrated circuit 40 is shown. For example, Figure 4 An integrated circuit 40 including a memory cell is shown as... Figure 1 Example of hardware resource 12. (e.g.) Figure 4 As shown, the integrated circuit 40 may include a memory cell array 41, a row decoder 42, an input / output circuit (I / O circuit) 43, and a control circuit 44.

[0038] The storage cell array 41 may include a plurality of storage cells. A storage cell may store at least one bit and may be simply referred to herein as a cell. In some embodiments, a storage cell may be a volatile storage cell, such as a dynamic random access memory (DRAM) cell or a static random access memory (SRAM) cell, or a non-volatile storage cell, such as a flash memory cell or a resistive random access memory (RRAM) cell.

[0039] The memory cell array 41 may include both normal cells and defective cells caused by the semiconductor manufacturing process. The memory cell array 41 may include redundant cells for repairing defective cells. For example, such as... Figure 4 As shown, the storage cell array 41 may include at least one first redundant column C1 and at least one second redundant column C2. In some embodiments, with Figure 4 As shown, the storage cell array 41 may include at least one redundant row. Hereinafter, the storage cell array 41 including redundant columns will be described primarily; however, the exemplary embodiments of this disclosure are not limited thereto.

[0040] The row decoder 42 can be connected to multiple memory cells via multiple word lines and receives the row address RA from the control circuit 44. The row decoder 42 can select one word line from the multiple word lines based on the row address RA and activate the selected word line. Among the multiple memory cells, the memory cell connected to the activated word line can be selected, and data can be written to or read from the selected memory cell.

[0041] Input / output circuitry 43 can be connected to multiple memory cells via multiple bit lines and receives column address CA from control circuitry 44. Input / output circuitry 43 may include a column decoder, which can select one or more columns from multiple columns of memory cell array 41 based on column address CA. Input / output circuitry 43 can write data by applying a signal (e.g., voltage and / or current) to the bit line corresponding to the selected column based on data signal DQ. Additionally, input / output circuitry 43 can read data by detecting signals (e.g., voltage and / or current) received from the selected column.

[0042] Control circuit 44 can receive address ADD and repair data REP. As described above with reference to the accompanying drawings, repair data REP can be received from the scan trigger of the function block in normal mode. Control circuit 44 can extract row address RA and column address CA from address ADD. In some embodiments, control circuit 44 can identify the address of a redundant column based on repair data REP. When address ADD requests access to a defective cell, control circuit 44 can generate column address CA and provide column address CA to input / output circuit 43 to access the redundant column. Therefore, access to a defective cell can be switched to access to a redundant cell, and self-repair can be completed.

[0043] Figure 5 An example of control circuit 50 is shown. For example, Figure 5 A control circuit 50 is shown below, which switches access to defective cells to access to redundant cells in the memory cell array. (See above reference...) Figure 4 The control circuit 50 can receive address ADD and repair data REP and generate row address RA and column address CA. (The rest of the text is omitted.) Figure 5 and Figure 4 The descriptions overlap.

[0044] refer to Figure 5The repair data (REP) may include a cell repair enable (CRE) and a fault cell address (FCA). The cell repair enable (CRE) indicates whether a cell needs repair, and the fault cell address (FCA) indicates the address of a redundant cell (or redundant column). While the fault cell address (FCA) can indicate the address of a redundant cell when the cell repair enable (CRE) has an active value, the fault cell address (FCA) corresponding to the cell repair enable (CRE) may be independent of the address of the redundant cell when the cell repair enable (CRE) has a deactivated value. In some implementations, the fault cell address (FCA) may be multi-bit.

[0045] When the cell repair enable (CRE) has an active value, the control circuit 50 can generate a column address (CA) based on the fault cell address (FCA). In some implementations, refer to, for example, the following... Figure 6 As will be described in the accompanying diagram, the cell repair enable (CRE) and fault cell address (FCA) can be generated by processing the repair data (REP) stored in the scan trigger. Here, the cell repair enable (CRE) can be referred to as the first data, and the fault cell address (FCA) can be referred to as the second data.

[0046] Figure 6 An example of integrated circuit 60 is shown. For example, Figure 6 An integrated circuit 60 is shown, including control circuitry 63 that switches access to defective cells to access to redundant cells in the memory cell array. Figure 6 As shown, integrated circuit 60 may include functional block 61, multiplexing circuit 62, and control circuit 63. (The remaining text is omitted.) Figure 6 Descriptions that overlap with those provided above with reference to the accompanying drawings.

[0047] The control circuit 63 can receive a first unit repair enable CRE1, a first fault unit address FCA1, a second unit repair enable CRE2, and a second fault unit address FCA2. The control circuit 63 can selectively use the first fault unit address FCA1 based on the first unit repair enable CRE1, and can selectively use the second fault unit address FCA2 based on the second unit repair enable CRE2.

[0048] In some implementations, at least one of the scan triggers included in function block 61 can be shared to repair defective cells in the memory cell (i.e., hardware resource). That is, the number of bits for the first cell repair enable CRE1, the first fault cell address FCA1, the second cell repair enable CRE2, and the second fault cell address FCA2 can be greater than the number of bits for the repair data REP provided by function block 61. For this purpose, multiplexing circuit 62 can generate the first cell repair enable CRE1, the first fault cell address FCA1, the second cell repair enable CRE2, and the second fault cell address FCA2 from the repair data REP provided by function block 61. In some implementations, see below. Figure 7C The multiplexing circuit 62 can generate additional pairs of cell repair enable and fault cell address. An example of the multiplexing circuit 62 will be referenced below. Figures 7A to 7C describe.

[0049] Figure 7A , Figure 7B and Figure 7C An example of a multiplexing circuit is shown. (Refer to the above reference.) Figure 6 The multiplexing circuits 70a, 70b and 70c can generate cell repair enable and fault cell address to be provided to the control circuit from the repair data REP provided by the function block. Figure 6 Multiplexing circuit 62 is not limited to Figures 7A to 7C Examples will be omitted below. Figures 7A to 7C Redundant details in the description.

[0050] refer to Figure 7A The multiplexing circuit 70a can generate the first unit repair enable CRE1, the first fault unit address FCA1[1:3], the second unit repair enable CRE2, and the second fault unit address FCA2[1:3] from N bits of repair data REP[1:N]. N can be a positive integer greater than 1 and less than 8, where 8 is the total number of bits in the first unit repair enable CRE1, the first fault unit address FCA1[1:3], the second unit repair enable CRE2, and the second fault unit address FCA2[1:3]. For example... Figure 7A As shown, the multiplexing circuit 70a may include combinational logic circuit 71 and first multiplexer MUX1 to sixth multiplexer MUX6.

[0051] Combinational logic circuit 71 can generate first internal signals INT1 to sixth internal signals INT6 from a portion of the repair data REP[1:N] REP[3:N]. In some embodiments, combinational logic circuit 71 can generate first internal signals INT1 to sixth internal signals INT6 from a portion of the repair data REP[1:N] REP[3:N] based on semiconductor manufacturing process trends. For example, defective cells may exhibit correlations caused by semiconductor manufacturing processes, and combinational logic circuit 71 can generate first internal signals INT1 to sixth internal signals INT6 from a portion of the repair data REP[1:N] REP[3:N] based on the analyzed correlations between defective cells. In some embodiments, at least two of the first internal signals INT1 to sixth internal signals INT6 may correspond to the same signal.

[0052] When the first REP[1] of the repair data corresponding to the first unit repair enable CRE1 is activated, that is, when the repair of the faulty unit is indicated, the first multiplexer MUX1 to the third multiplexer MUX3 can output the first internal signal INT1 to the third internal signal INT3 as the first faulty unit address FCA1[1:3]. In addition, when the first REP[1] of the repair data is deactivated, the first multiplexer MUX1 to the third multiplexer MUX3 can output the first REP[1] of the repair data as the first faulty unit address FCA1[1:3]. Similarly, when the second REP[2] of the repair data corresponding to the second unit repair enable CRE2 is activated, that is, when the repair of the faulty unit is indicated, the fourth multiplexer MUX4 to the sixth multiplexer MUX6 can output the fourth internal signal INT4 to the sixth internal signal INT6 as the second faulty unit address FCA2[1:3]. In addition, when the second bit of the repair data REP[2] is deactivated, the fourth multiplexer MUX4 to the sixth multiplexer MUX6 can output the second bit of the repair data REP[2] as the second fault unit address FCA2[1:3].

[0053] refer to Figure 7B The multiplexing circuit 70b can generate the first unit repair enable CRE1, the first fault unit address FCA1[1:3], the second unit repair enable CRE2, and the second fault unit address FCA2[1:3] from the 5-bit repair data REP[1:5]. For example... Figure 7B As shown, the multiplexing circuit 70b may include a first multiplexer MUX1 to a sixth multiplexer MUX6.

[0054] When the first REP[1] of the repair data corresponding to the first unit repair enable CRE1 is activated, that is, when the repair of the fault unit is indicated, the first multiplexer MUX1 to the third multiplexer MUX3 can output the third to fifth REP[3:5] of the repair data as the first fault unit address FCA1[1:3]. In addition, when the first REP[1] of the repair data is deactivated, the first multiplexer MUX1 to the third multiplexer MUX3 can output the first REP[1] of the repair data as the first fault unit address FCA1[1:3]. Similarly, when the second REP[2] of the repair data corresponding to the second unit repair enable CRE2 is activated, that is, when the repair of the fault unit is indicated, the fourth multiplexer MUX4 to the sixth multiplexer MUX6 can output the third to fifth REP[3:5] of the repair data as the second fault unit address FCA2[1:3]. In addition, when the second bit of the repair data REP[2] is deactivated, the fourth multiplexer MUX4 to the sixth multiplexer MUX6 can output the second bit of the repair data REP[2] as the second fault unit address FCA2[1:3].

[0055] refer to Figure 7C The multiplexing circuit 70c can generate the first unit repair enable CRE1 to the fourth unit repair enable CRE4 and the first fault unit address FCA1[1:3] to the fourth fault unit address FCA4[1:3] from the 10-bit repair data REP[1:10]. Figure 7C As shown, the multiplexing circuit 70c may include a first multiplexer MUX1 to a twelfth multiplexer MUX12.

[0056] When the first REP[1] of the repair data corresponding to the first unit repair enable CRE1 is activated, that is, when the repair of the fault unit is indicated, the first multiplexer MUX1 to the third multiplexer MUX3 can output the fifth to seventh REP[5:7] of the repair data as the first fault unit address FCA1[1:3]. In addition, when the first REP[1] of the repair data is deactivated, the first multiplexer MUX1 to the third multiplexer MUX3 can output the first REP[1] of the repair data as the first fault unit address FCA1[1:3]. Similarly, when the second REP[2] of the repair data corresponding to the second unit repair enable CRE2 is activated, that is, when the repair of the fault unit is indicated, the fourth multiplexer MUX4 to the sixth multiplexer MUX6 can output the eighth to tenth REP[8:10] of the repair data as the second fault unit address FCA2[1:3]. In addition, when the second bit of the repair data REP[2] is deactivated, the fourth multiplexer MUX4 to the sixth multiplexer MUX6 can output the second bit of the repair data REP[2] as the second fault unit address FCA2[1:3].

[0057] When the third bit of the repair data corresponding to the third unit repair enable CRE3 is activated, that is, when the repair of the fault unit is indicated, the seventh multiplexer MUX7 to the ninth multiplexer MUX9 can output the fifth to seventh bits of the repair data REP[5:7] as the third fault unit address FCA3[1:3]. In addition, when the third bit of the third repair data REP[3] is deactivated, the seventh multiplexer MUX7 to the ninth multiplexer MUX9 can output the third bit of the repair data REP[3] as the third fault unit address FCA3[1:3]. Similarly, when the fourth bit of the repair data corresponding to the fourth unit repair enable CRE4 is activated, that is, when the repair of the fault unit is indicated, the tenth multiplexer MUX10 to the twelfth multiplexer MUX12 can output the eighth to tenth bits of the repair data REP[8:10] as the fourth fault unit address FCA4[1:3]. In addition, when the fourth bit of the repair data REP[4] is deactivated, the tenth multiplexer MUX10 to the twelfth multiplexer MUX12 can output the fourth bit of the repair data REP[4] as the address of the fourth fault unit FCA4[1:3].

[0058] Figure 8 An example of system 80 is shown. For example, Figure 8A system 80 for testing integrated circuit 81 is shown. In some embodiments, system 80 may be included in the process of manufacturing integrated circuit 81. For example, integrated circuit 81 may be tested by system 80 after it has been manufactured using a semiconductor manufacturing process. As described below, defective resources included in integrated circuit 81 may be detected by system 80, and information for repairing defective resources may be generated. Figure 8 As shown, system 80 may include integrated circuit 81 and automated test equipment 82. (The remaining text is omitted.) Figure 8 Descriptions that overlap with those provided above with reference to the accompanying drawings.

[0059] refer to Figure 8 The automated test device 82 can be connected to and communicate with the integrated circuit 81. For example, the integrated circuit 81 may include at least one port for communicating with the automated test device 82, and the automated test device 82 may communicate with the integrated circuit 81 through at least one port according to a pre-shared protocol.

[0060] Integrated circuit 81 may include a built-in self-test circuit (BIST) and a built-in self-repair circuit (BISR). The BIST can test the hardware resources included in integrated circuit 81 and provide first information INF01, including the test results, to automated test equipment 82. For example, the BIST can write predefined data to a memory cell to test the memory cell and can read data from the memory cell. The first information INF01 may include the data read from the memory cell and the comparison result between the data written to the memory cell and the data read from the memory cell by the BIST.

[0061] The automated test equipment 82 can receive first information INF01 from the integrated circuit 81 and identify defective resources included in the integrated circuit 81 based on the first information INF01. The automated test equipment 82 can generate second information INF02 for repairing the detected defective resources based on the detected defective resources and provide the second information INF02 to the integrated circuit 81. For example, the automated test equipment 82 can generate second information INF02 including the address of the defective cell and / or the address of a redundant cell used to replace the defective cell.

[0062] The built-in self-healing circuit BISR can receive the second information INF02 from the automatic test equipment 82. (See above reference.) Figure 1 The built-in self-healing circuit BISR may include non-volatile memory, and the second information INF02 may be stored in the non-volatile memory. For example, the built-in self-healing circuit BISR may include an OTP memory such as a fuse, and the automatic test device 82 may blow the fuse to store the second information INF02.

[0063] In some embodiments, the built-in self-test circuit BIST may correspond to the functional blocks described above with reference to the accompanying drawings. For example, the built-in self-test circuit BIST may include scan triggers and function triggers. The built-in self-test circuit BIST can test hardware resources (e.g., memory cells) in normal mode and can output scan data to an external device (e.g., an automated test device 82) of the integrated circuit 81 in scan mode. As described above with reference to the accompanying drawings, scan triggers and function triggers may be included in a scan chain and can latch scan data in scan mode. In addition, in normal mode, scan triggers may latch repair data provided by the built-in self-repair circuit BISR, and function triggers may latch data (i.e., functional data) required to perform the designed function (i.e., self-test) of the built-in self-test circuit BIST. In some embodiments, the scan triggers included in the built-in self-test circuit BIST may be automatically inserted to test the automated test device 82. Examples of inserting scan triggers will be referred to subsequently. Figure 13 describe.

[0064] Figure 9 This is a flowchart illustrating an example of a built-in self-healing method. (Example:) Figure 9 As shown, the built-in self-healing method may include operations S11 to S17. In some embodiments, Figure 9 The method shown can be derived from Figure 1 The integrated circuit 10 performs this. Reference will be made below. Figure 1 describe Figure 9 .

[0065] refer to Figure 9 The mode can be identified in operation S11. For example, function block 11 can identify either a scanning mode or a normal mode based on a signal received externally from integrated circuit 10. Figure 9 As shown, when a scanning mode is detected, operations S12 to S14 can be performed, and when a normal mode is detected, operations S15 to S17 can be performed.

[0066] When a scan mode is detected, scan data can be latched by the scan trigger SF in operation S12, and by the function trigger FF in operation S13. As described above with reference to the accompanying drawings, in scan mode, the scan trigger SF and the function trigger FF can be included in the scan chain and can latch scan data. Operations S12 and S13 can be combined with... Figure 9 The different orders shown can be executed, and they can also be executed in parallel.

[0067] In operation S14, scan data can be output. For example, the scan data latched in operations S12 and S13 can be transmitted through the scan chain and output to the outside of integrated circuit 10. The scan data can be used to check the status of integrated circuit 10 or to debug integrated circuit 10.

[0068] When a normal mode is detected, the repair data REP can be latched by the scan trigger SF in operation S15, and the function data can be latched by the function trigger FF in operation S16. The scan trigger inserted to observe integrated circuit 10 can be deactivated in normal mode and instead reused to latch the repair data REP. Therefore, the cost of built-in self-repair can be reduced. Operations S15 and S16 can be used in conjunction with... Figure 9 The different sequences shown can be executed, and they can also be executed in parallel.

[0069] In operation S17, faulty resources can be repaired. For example, the repair data REP latched in operation S15 can be held by the scan trigger SF. Control circuit 14 can receive the repair data REP from the scan trigger SF and repair the faulty resources in the hardware resources by identifying the faulty and / or redundant resources based on the repair data REP. An example of operation S17 will be referred to later. Figure 10 and Figure 11 describe.

[0070] Figure 10 This is a flowchart illustrating an example of a built-in self-healing method. For example, Figure 10 The flowchart shows Figure 9 Example of operation S17. See the reference above. Figure 9 As mentioned above, it can be found in Figure 10 In operation S20, defective resources are repaired. For example... Figure 10 As shown, operation S20 may include operations S21 and S22. In some embodiments, operation S20 may be performed by... Figure 4 The integrated circuit 40 performs this. References will be made below. Figure 4 describe Figure 10 .

[0071] refer to Figure 10 Redundant cells can be identified in operation S21. For example, control circuit 44 can receive repair data REP and identify redundant cells included in memory cell array 41 from the repair data REP. In some embodiments, memory cell array 41 may include redundant columns, and control circuit 44 can identify at least one column of redundant columns based on repair data REP.

[0072] In operation S22, access to a defective cell can be switched to access to a redundant cell. For example, control circuit 44 can receive an address ADD for accessing memory cell array 41 and can identify access to a defective cell based on the address ADD. When access to a defective cell is identified, control circuit 44 can switch access to the defective cell to access to a redundant cell identified in operation S21. Therefore, the defective cell can be repaired by being replaced by a redundant cell.

[0073] Figure 11 This is a flowchart illustrating an example of a built-in self-healing method. For example, Figure 11 The flowchart shows Figure 9 Example of operation S17. See the reference above. Figure 9 As mentioned above, it can be found in Figure 11 Repair defective resources in operation S30. For example... Figure 11 As shown, operation S30 may include operations S31 and S32. In some embodiments, operation S30 may be performed by... Figure 6 The integrated circuit 60 performs this. References will be made below. Figure 6 describe Figure 11 .

[0074] refer to Figure 11 In operation S31, at least one output of the scan trigger can be selected. For example, multiplexing circuit 62 can select one of two signals based on a bit of the repair data REP provided by the scan trigger of function block 61, and provide the selected signal to control circuit 63. For this purpose, refer to the above. Figures 7A to 7C The multiplexing circuit 62 may include a multiplexer, and the multiplexer may output a signal based on a cell repair enable (a bit indicating whether a cell needs to be repaired).

[0075] In operation S32, faulty resources can be repaired based on the selected output. For example, the output selected by the multiplexing circuit 62 in operation S31 can be provided to the control circuit 63. The control circuit 63 can identify defective units and / or redundant units based on the signals provided by the multiplexing circuit 62, and repair the defective units.

[0076] Figure 12 This is a flowchart illustrating an example of a method for manufacturing an integrated circuit (IC). More specifically, Figure 12 The flowchart illustrates an example method for manufacturing an integrated circuit (IC) that includes cells. For example... Figure 12 As shown, the method for manufacturing an integrated circuit (IC) may include operations S41, S42, S43, and S44.

[0077] Cell library (or standard cell library) D12 may include information about standard cells, such as information about their function, characteristics, and layout. An integrated circuit IC may include multiple standard cells. A standard cell is a unit of layout included in an integrated circuit IC and can be designed to perform predefined functions. An integrated circuit IC may include various types of standard cells and can be arranged and placed along multiple rows. In some implementations, cell library D12 may include the standard cells referenced above. Figure 2 The described flip-flop 20 is defined as a standard cell. Design rule D14 may include requirements that the layout of the integrated circuit IC should follow. For example, design rule D14 may include requirements such as the spacing between patterns on the same layer, the minimum width of the pattern, and the routing direction of the wiring layer.

[0078] In operation S41, a logic synthesis operation can be performed to generate netlist data D13 from RTL data D11. For example, a semiconductor design tool (e.g., a logic synthesis tool) can generate netlist data D13, including a bitstream or netlist, by performing logic synthesis on RTL data D11 written in a hardware description language (HDL) (e.g., VHSIC Hardware Description Language (VHDL) and Verilog) while simultaneously performing logic synthesis on a reference cell library D12. Netlist data D13 may correspond to the layout and routing inputs, which will be described subsequently. In some implementations, refer to the following... Figure 13 As described above, the operation of adding a scan trigger can be performed in operation S41. Here, RTL data D11 can be referred to as input data, and the netlist data D13, which is separately defined as the scan trigger, can be referred to as output data.

[0079] In operation S42, cells can be placed and pins can be routed. For example, a semiconductor design tool (e.g., a P&R tool) can place cells used in netlist data D13 by referring to cell library D12 and design rule D14. For example, the semiconductor design tool can place cells corresponding to scan flip-flops and function flip-flops. The pins of the placed cells can be routed. For example, the semiconductor design tool can generate interconnects that electrically connect the output and input pins of the placed cells. Interconnects can include vias of the via layer and / or patterns of the routing layer. The semiconductor design tool can generate layout data D15 that defines the placed cells and the generated interconnects (i.e., the layout of the integrated circuit IC). Layout data D15 can have a format such as GDSII and can include geometric information about the cells and interconnects. The semiconductor design tool can refer to design rule D14 while routing the pins of the cells.

[0080] In operation S43, mask fabrication operations can be performed. For example, optical proximity correction (OPC) can be applied to the layout data D15 to correct distortions such as light refraction caused by the properties of light during the photolithography process. The pattern on the mask can be defined as a pattern formed on multiple layers based on the data from the applied OPC, and at least one mask (or photomask) can be fabricated to form the pattern for each of the multiple layers. In some embodiments, the layout of the integrated circuit IC can be restricted and modified in operation S43, and this restricted modification of the integrated circuit IC can be referred to as design polishing, a post-processing step for optimizing the structure of the integrated circuit IC.

[0081] In operation S44, processes for manufacturing an integrated circuit (IC) can be performed. For example, an IC can be manufactured by patterning multiple layers using at least one mask manufactured in operation S43. Front-end processes (FEOL) may include, for example, planarizing and cleaning the wafer, forming trenches, forming wells, forming gate electrodes, and forming source and drain electrodes. Individual devices such as transistors, capacitors, and resistors can be formed on the substrate via FEOL. Additionally, back-end processes (BEOL) may include, for example, silicided gate and source and drain regions, adding dielectrics, planarizing, forming vias, adding metal layers, forming vias, and forming passivation layers. Individual devices such as transistors, capacitors, and resistors can be connected to each other via BEOL. In some embodiments, a middle-end process (MOL) can be performed between FEOL and BEOL, and contacts can be formed on the individual devices. The IC can then be packaged into a semiconductor package and used as a component for various applications.

[0082] Figure 13 This is a flowchart illustrating an example of a built-in self-healing method. For example, Figure 13 The flowchart shows Figure 12 Example of operation S41. See the reference above. Figure 12 As described, input data defining the integrated circuit IC and output data for the built-in self-healing component can be generated in operation S50. For example... Figure 13 As shown, operation S50 may include operations S51 to S55. Referring below... Figure 12 describe Figure 13 .

[0083] refer to Figure 13 Input data defining hardware resources can be obtained in operation S51. For example, a semiconductor design tool can obtain RTL data D11 that defines the integrated circuit that performs the designed function. RTL data D11 can define the hardware resources included in the integrated circuit and the functional triggers included in the functional blocks of the integrated circuit.

[0084] In operation S52, scan triggers can be defined. For example, a semiconductor design tool can further define scan triggers for observing integrated circuits based on the input data obtained in operation S51. The semiconductor design tool can add the information defining the scan triggers to the input data, and as a result, the scan triggers can be added to the integrated circuit defined by the input data. As described above with reference to the accompanying drawings, scan triggers can be included in the scan chain along with functional triggers in scan mode, and unlike functional triggers that latch functional data in normal mode, scan triggers can latch repair data.

[0085] In operation S53, a repair circuit can be defined. For example, a semiconductor design tool can further define the repair circuit based on the scan trigger defined in operation S52. The semiconductor design tool can add the information defining the repair circuit to the input data, and thus the repair circuit can be added to the integrated circuit defined by the input data. As described above with reference to the accompanying drawings, the repair circuit can provide repair data to the scan trigger added in operation S52 in normal mode.

[0086] In operation S54, a control circuit can be defined. For example, a semiconductor design tool can further define the control circuit based on the scan trigger defined in operation S52. The semiconductor design tool can add the information defining the control circuit to the input data, and thus the control circuit can be added to the integrated circuit defined by the input data. As described above with reference to the accompanying drawings, the control circuit can receive repair data from the scan trigger added in operation S52 and repair hardware resources based on the repair data in normal mode.

[0087] During operation of S55, output data can be generated. For example, semiconductor design tools can generate data such as... Figure 12 The output data of netlist data D13 includes information that further defines the scan trigger in operation S52, the repair circuit in operation S53, and the control circuit in operation S54.

[0088] Figure 14 This is a block diagram illustrating an example of a System-on-Chip (SoC) 140. The SoC 140 is a semiconductor device that may include integrated circuits. As an integrated circuit that implements complex blocks such as intellectual property (IP) performing different functions on a single chip, the SoC 140 may include integrated circuits according to exemplary embodiments of this disclosure and provides built-in self-healing that allows for the repair of hardware resources at a reduced cost. Therefore, the SoC 140 can have high yield, reliability, and efficiency. Reference Figure 14The system-on-chip 140 may include a modem 142, a display controller 143, a memory 144, an external memory controller 145, a central processing unit (CPU) 146, a transaction unit 147, a power management integrated circuit (PMIC) 148, and a graphics processing unit (GPU) 149, and each functional block of the system-on-chip 140 may communicate with each other via a system bus 141.

[0089] The CPU 146, which controls the operation of the system-on-a-chip (SoC) 140 at the highest level, can also control the operation of other functional blocks 142 to 149. The modem 142 can demodulate signals received externally from the SoC 140 or modulate signals generated within the SoC 140. The external memory controller 145 can control the receiving and sending of data to external memory devices connected to the SoC 140. For example, programs and / or data stored in external memory devices can be sent to the CPU 146 or GPU 149 under the control of the external memory controller 145. The GPU 149 can execute program instructions related to graphics processing. The GPU 149 can receive graphics data through the external memory controller 145 and can send processed graphics data to the outside of the SoC 140 through the external memory controller 145. The transaction unit 147 can monitor data transactions for each functional block, and the PMIC 148 can control the power supplied to each functional block under the control of the transaction unit 147. The display controller 143 sends data generated within the system-on-chip 140 to a display (or display device) external to the system-on-chip 140. The memory 144 may include non-volatile memory such as electrically erasable programmable read-only memory (EEPROM) and flash memory, and may include volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM).

[0090] Figure 15 This is a block diagram illustrating an example of a computing system 150 including memory for storing programs. A built-in self-healing method (such as...) according to an example embodiment of this disclosure... Figure 12 and Figure 13 At least one of the operations shown can be performed by a computing system (or computer) 150.

[0091] The computing system 150 can be a fixed type of computing system, such as a desktop computer, workstation, and server, or a portable computing system, such as a laptop computer. Figure 15As shown, the computing system 150 may include a processor 151, input / output devices (I / O devices) 152, a network interface 153, random access memory 154, read-only memory 155, and storage device 156. The processor 151, input / output devices 152, network interface 153, RAM 154, ROM 155, and storage device 156 may be connected to a bus 157 and may communicate with each other via the bus 157.

[0092] Processor 151 may be referred to as a processing unit and may include at least one core for executing any instruction set, such as a microprocessor, application processor (AP), digital signal processor (DSP), and graphics processing unit (GPU), including Intel Architecture-32 (IA-32), 64-bit Extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc. For example, processor 151 may access memory, namely RAM 154 or ROM 155, via bus 157 and execute instructions stored in RAM 154 or ROM 155.

[0093] RAM 154 may store a program PGM or at least a portion thereof for a method according to an exemplary embodiment of the present disclosure, and the program PGM may allow processor 151 to perform actions such as Figure 12 and Figure 13 The method shown includes at least one of the operations. That is, the program PGM may include a plurality of instructions executable by the processor 151, and the instructions included in the program PGM may allow the processor 151 to perform at least one of the operations included in the flowchart described above.

[0094] Even if the power supply to the computing system 150 is cut off, the storage device 156 may not lose the stored data. For example, the storage device 156 may include a non-volatile storage device or a storage medium such as magnetic tape, optical disc, and magnetic disk. Additionally, the storage device 156 may be removable from the computing system 150. The storage device 156 may store a program PGM, and the program PGM, or at least a portion thereof, may be loaded from the storage device 156 into RAM 154 before the program PGM is executed by the processor 151. Alternatively, the storage device 156 may store a file written in a programming language, and a program PGM, or at least a portion thereof, generated from that file, for example via a compiler, may be loaded into RAM 154. Furthermore, as... Figure 15 As shown, storage device 156 can store database DB, and database DB can include information required for designing integrated circuits, such as data defining integrated circuits, Figure 12The unit library D12 and / or design rule D14.

[0095] Storage device 156 can store data to be processed by processor 151 or data processed by processor 151. That is, processor 151 can generate data by processing the data stored in storage device 156 according to program PGM, and can store the generated data in storage device 156. For example, storage device 156 can store... Figure 12 The RTL data D11, netlist data D13, and / or layout data D15.

[0096] Input / output device 152 may include input devices such as a keyboard and a pointing device, and may also include output devices such as a display device and a printer. For example, a user can use input / output device 152 to trigger the execution of program PGM by processor 151, inputting... Figure 12 The RTL data D11 and / or netlist data D13, or check Figure 12 The layout data is D15.

[0097] Network interface 153 can provide access to networks outside computing system 150. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of link.

[0098] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that can be claimed, but rather as descriptions of specific features of a particular embodiment of a particular invention. Some features described in the context of individual embodiments in this specification can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0099] As described above, exemplary embodiments have been disclosed in the accompanying drawings and specification. While exemplary embodiments have been described with reference to specific terminology, it should be understood that the terminology used herein is for the purpose of describing the technical spirit of this disclosure only and is not intended to limit the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments can be made without departing from the scope of this disclosure.

Claims

1. An integrated circuit, the integrated circuit including a plurality of hardware resources, the integrated circuit further including: At least one first trigger is configured to latch scan data in a first mode and latch repair data in a second mode, the scan data being output from the integrated circuit; as well as A control circuit configured to repair defective resources among the plurality of hardware resources in the second mode based on the repair data latched by the at least one first trigger.

2. The integrated circuit of claim 1, further comprising at least one second flip-flop, the at least one second flip-flop being configured to latch the scan data in the first mode and latch functional data in the second mode.

3. The integrated circuit according to claim 1, further comprising a memory cell array, the memory cell array comprising a plurality of cells, the plurality of hardware resources comprising the plurality of cells, and... in, The control circuit is further configured to identify at least one redundant unit among the plurality of units based on the repair data, and to switch access to at least one defective unit among the plurality of units to access to the at least one redundant unit.

4. The integrated circuit according to claim 3, wherein, The at least one redundant unit corresponds to at least one column in the storage cell array.

5. The integrated circuit according to claim 3, wherein, The repair data includes: The first data indicates the necessity of repair; and The second data indicates the address of the at least one defective unit.

6. The integrated circuit of claim 5, further comprising a multiplexing circuit configured to select a portion of the output of the at least one first flip-flop and provide the portion of the output to the control circuit based on the first data.

7. The integrated circuit of claim 1, further comprising a repair circuit including a non-volatile memory configured to store the repair data and to provide the repair data to the at least one first trigger in the second mode.

8. The integrated circuit of claim 1, further comprising a test circuit configured to test the plurality of hardware resources in the second mode.

9. A method executed by an integrated circuit, the integrated circuit including a plurality of hardware resources, the method comprising: In the first mode, scan data is latched by at least one first trigger, and the scan data is output from the integrated circuit; In the second mode, the repair data is latched and repaired using at least one first trigger. as well as In the second mode, the defective resources among the plurality of hardware resources are repaired based on the repair data latched in the at least one first trigger.

10. The method according to claim 9, further comprising: In the first mode, the scan data is latched by at least one second trigger; as well as In the second mode, functional data is latched by the at least one second trigger.

11. The method according to claim 9, wherein, The integrated circuit further includes a memory cell array, which comprises multiple cells, and the multiple hardware resources include the multiple cells. In the second mode, repairing the defective resource includes: Based on the repair data, at least one redundant unit among the plurality of units is identified; and Access to at least one defective unit among the plurality of units is switched to access to at least one redundant unit.

12. The method according to claim 11, wherein, The at least one redundant unit corresponds to at least one column in the storage cell array.

13. The method of claim 11, wherein, The repair data includes: The first data indicates the necessity of repair; and The second data indicates the address of the at least one defective unit.

14. The method of claim 13, wherein, The repair of the defective resources includes: Based on the first data, a portion of the output of the at least one first trigger is selected; and Repair the defective resource based on a portion of the selected output.

15. The method according to claim 9, further comprising: In the second mode, the repair data is read from non-volatile memory, wherein the non-volatile memory is included in the integrated circuit and configured to store the repair data; and The repair data is provided to the at least one first trigger.

16. The method of claim 9, further comprising testing the plurality of hardware resources in the second mode.

17. A method for providing a built-in self-healing integrated circuit, executed by at least one processor, the method comprising: Acquire input data, which defines multiple hardware resources included in the integrated circuit; as well as Output data is generated based on the input data, and the output data defines the integrated circuit. The generation of the output data includes: Add information defining at least one first trigger to the input data, the at least one first trigger being configured to latch scan data in a first mode and latch repair data in a second mode; Add information defining a repair circuit to the input data, the repair circuit being configured to provide the repair data to the at least one first flip-flop in the second mode; and Information defining a control circuit is added to the input data, the control circuit being configured to repair defective resources among the plurality of hardware resources based on the repair data latched by the at least one first trigger.

18. The method of claim 17, wherein, The input data defines at least one second trigger, which is configured to latch the scan data in the first mode and latch the function data in the second mode.

19. The method of claim 17, wherein, The input data definition includes a storage unit array of multiple units, and the multiple hardware resources include the multiple units, and The control circuit is further configured to identify at least one redundant unit among the plurality of units based on the repair data, and to switch access to at least one defective unit among the plurality of units to access to the at least one redundant unit.

20. The method according to claim 19, wherein, The at least one redundant unit corresponds to at least one column in the storage cell array.

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