Memory device and integrated circuit for detecting faults in signal paths and voltage paths

Abstract

A memory device and an integrated circuit are provided. The memory device includes a base chip and a core chip stacked on the base chip and connected through a voltage path. The base chip and the core chip drive the voltage path with an internal voltage after a TSV open short test is started, and detect a connection failure of the voltage path based on a logic level to which the voltage path is driven. The base chip cuts off a connection between the voltage path and a base drive circuit after a voltage monitoring operation is started. The core chip cuts off a connection between the voltage path and a core drive circuit after the voltage monitoring operation is started. The base chip detects a voltage level of a monitoring voltage generated during the voltage monitoring operation and used in the core chip through the voltage path.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Application No. 10-2025-0049810, filed on April 16, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a storage device for detecting faults in signal paths used for stacking multiple chips and in voltage paths used for voltage monitoring. Background Technology

[0004] With advancements in technologies for manufacturing memory devices, packaging techniques for implementing multiple core chips have achieved high integration and performance. In packaging technologies for implementing memory devices, various developments have occurred, ranging from two-dimensional structures where multiple core chips are laid flat on a printed circuit board (PCB) to three-dimensional structures where multiple core chips are vertically stacked. Memory devices with three-dimensional structures can be implemented by stacking multiple core chips interconnected via through-silicon vias (hereinafter referred to as "TSVs") (e.g., high-bandwidth memory HBM), or by stacking multiple core chips via wire bonding.

[0005] For higher integration and performance, methods are needed to detect connectivity faults in TSVs when multiple core chips are stacked. A representative method for detecting connectivity faults in TSVs can be performed by a TSV open / short circuit test as follows: turning on the PMOS transistor connected to the TSV of the core chip located at the top layer, turning on the NMOS transistor connected to the TSV of the base chip located at the bottom layer, and then detecting that the TSV is driven to a set logic level. Summary of the Invention

[0006] In one embodiment, a storage device may include a base chip and a core chip, the core chip being stacked on top of the base chip and connected via a voltage path. The base chip and core chip can drive the voltage path using internal voltages after a TSV open / short circuit test begins, and detect connection faults in the voltage path based on the logic level of the driven voltage path. The base chip can disconnect the voltage path from the base drive circuitry after a voltage monitoring operation begins. The core chip can disconnect the voltage path from the core drive circuitry after a voltage monitoring operation begins. The base chip can detect the voltage level of the monitoring voltage generated during the voltage monitoring operation and used in the core chip via the voltage path.

[0007] In one embodiment, a storage device may include a base chip and a core chip, the core chip being stacked on top of the base chip and connected via a first voltage path and a second voltage path. The base chip and core chip may utilize internal voltages to drive the first and second voltage paths after a TSV open / short circuit test begins, and detect connection faults in the first and second voltage paths based on the logic levels driven by the first and second voltage paths. The base chip may detect the voltage level of a monitoring voltage generated from either a power supply voltage received via the first voltage path or a high voltage received via the second voltage path after a voltage monitoring operation begins.

[0008] In one embodiment, a storage device may include a base chip and a core chip, with the core chip stacked on top of the base chip and connected via signal and voltage paths. The base chip and core chip can drive the signal and voltage paths after a TSV open / short circuit test begins, and detect connection faults in the signal and voltage paths based on the logic levels at which they are driven. The base chip can disconnect the voltage path from the base drive circuitry after a voltage monitoring operation begins. The core chip can disconnect the voltage path from the core drive circuitry after a voltage monitoring operation begins. The base chip can detect the voltage level of the high voltage used in the core chip via the voltage path after a voltage monitoring operation begins.

[0009] In one embodiment, an integrated circuit may include a semiconductor device that, after the start of a TSV open-circuit / short-circuit test, drives a first voltage path and a second voltage path using an internal voltage, controls the connection between the first voltage path and the second voltage path and a first base drive circuit and a second base drive circuit, detects connection faults of the first voltage path and the second voltage path based on the logic levels at which the first voltage path and the second voltage path are driven, and, after the start of a voltage monitoring operation, detects the voltage level of a monitoring voltage generated from either a power supply voltage received through the first voltage path or a high voltage received through the second voltage path. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the construction of a storage system according to an embodiment of the present disclosure.

[0011] Figure 2 This is a block diagram illustrating the construction of a storage device according to an embodiment of the present disclosure.

[0012] Figure 3 This is a block diagram illustrating the construction of a base chip according to an embodiment of the present disclosure.

[0013] Figure 4This is a block diagram illustrating the construction of a test control circuit according to an embodiment of the present disclosure.

[0014] Figure 5 This is a block diagram illustrating the construction of a basic test circuit according to an embodiment of the present disclosure.

[0015] Figure 6 This is a view illustrating the construction of a first fault signal generating circuit according to an embodiment of the present disclosure.

[0016] Figure 7 This is a view illustrating the construction of a third fault signal generating circuit according to an embodiment of the present disclosure.

[0017] Figure 8 This is a view illustrating the construction of a fourth fault signal generation circuit according to an embodiment of the present disclosure.

[0018] Figure 9 This is a block diagram illustrating the construction of a fourth core chip according to an embodiment of the present disclosure.

[0019] Figure 10 This is a block diagram illustrating the construction of a core test circuit according to an embodiment of the present disclosure.

[0020] Figure 11 This is a view illustrating the construction of a first path driving circuit according to an embodiment of the present disclosure.

[0021] Figure 12 This is a view illustrating the construction of a third path drive circuit according to an embodiment of the present disclosure.

[0022] Figure 13 This is a view illustrating the construction of a fourth path drive circuit according to an embodiment of the present disclosure.

[0023] Figure 14 This is a block diagram illustrating the construction of a voltage monitoring circuit according to an embodiment of the present disclosure.

[0024] Figure 15 This is a table used to describe the operation of detecting connection faults in voltage paths and monitoring voltage faults in storage devices according to embodiments of the present disclosure. Detailed Implementation

[0025] In the description of the following embodiments, terms such as "first" and "second" are used to distinguish individual components, but are not limited to any particular component. For example, a first component may be referred to as a second component, and vice versa.

[0026] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through another component in between. Conversely, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without any other component in between.

[0027] "Logic high" and "logic low" are used to describe the logic level of a signal. Signals with a "logic high" level are distinguished from signals with a "logic low" level. For example, when a signal with a first voltage corresponds to a signal with a "logic high" level, a signal with a second voltage can correspond to a signal with a "logic low" level. According to embodiments, a "logic high" level can be set to a voltage higher than a "logic low" level. According to embodiments, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, in some embodiments, a signal with a logic high level can be set to a logic low level, while in other embodiments, a signal with a logic low level can be set to a logic high level.

[0028] The present disclosure will be described in more detail below by way of examples. These examples are for illustrative purposes only, and the scope of the disclosure is not limited to the examples.

[0029] Figure 1 This is a block diagram illustrating the construction of a storage system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the storage system 1 may include a PCB 11, a substrate 13, an interposer 15, a storage device 17, and a processor 19.

[0030] PCB 11 connects several electronic components to form an electronic circuit (not shown). A copper layer, a solder mask layer, and a silkscreen layer can be formed on PCB 11. Circuit paths for transmitting signals or electricity can be formed in the copper layer. The solder mask layer prevents damage to the circuit and protects specific areas where components may be soldered. Furthermore, the silkscreen layer indicates the location or information of electronic components in the form of characters or symbols printed on the surface of PCB 11.

[0031] A substrate 13 is formed on the PCB 11, with bump pads (e.g., 111) between them, and the substrate 13 mechanically supports the interposer 15, the memory device 17, and the processor 19. The substrate 13 typically serves as an insulator, i.e., the physical basis for the PCB 11. Materials for the substrate 13 include FR4 (i.e., an insulator made of glass fiber and epoxy resin), ceramics (capable of withstanding high temperatures due to their thermal conductivity and typically used in high-frequency circuits or high-temperature environments), and polyimide (used as a base material for flexible PCBs due to its flexibility).

[0032] Intermediate layer 15 is formed on substrate 13 via bump pads and may include wires connecting electronic components (e.g., storage device 17 and processor 19) with mismatched form factors or pin arrangements. Intermediate layer 15 can convert signals in different interfaces.

[0033] Memory device 17 may be formed on interposer layer 15, with microbump pads (e.g., 113) between them. Under the control of processor 19, memory device 17 may store data applied by processor 19, or may output data stored in memory device 17 to processor 19. Memory device 17 may include base chip 120 and multiple core chips 130-1 to 130-L. Multiple core chips 130-1 to 130-L may be stacked on or on base chip 120, with microbump pads between them. Base chip 120 and multiple core chips 130-1 to 130-L may be vertically connected via TSVs. Base chip 120 may drive signal paths after the start of a TSV open / short circuit test. Base chip 120 may detect connection faults in signal paths based on the drive logic level of the signal paths after the start of a TSV open / short circuit test. Base chip 120 may drive voltage paths after the start of a TSV open / short circuit test. The base chip 120 can detect voltage path connection faults based on the drive logic level of the voltage path after the TSV open-circuit / short-circuit test begins. The base chip 120 can detect the power supply voltage ( Figure 3 VDD) and high voltage ( Figure 3 The voltage levels (VPP) in the base chip 120 are used in multiple core chips 130-1 to 130-L after the voltage monitoring operation begins. Signal paths and voltage paths can each be configured such that the TSV and microbump pads are connected along the path. The signal path can be configured such that input and output signals between the base chip 120 and the multiple core chips 130-1 to 130-L are transmitted along the path. The voltage path can be configured such that it is used by the base chip 120 to detect the voltages used in the multiple core chips 130-1 to 130-L.

[0034] The base chip 120 can be implemented using a common semiconductor device, controller, or integrated circuit that controls the operation of multiple core chips 130-1 to 130-L. Each of the multiple core chips 130-1 to 130-L can be implemented using a common semiconductor device, common memory device, or integrated circuit that stores and outputs the stored data.

[0035] Among the multiple core chips 130-1 to 130-L, the top-level core chip 130-L can drive the signal path after the TSV open-circuit / short-circuit test begins. Each of the multiple core chips 130-1 to 130-L can input and output data through each signal path. Each of the multiple core chips 130-1 to 130-L can store data and output the data stored in each core chip. Among the multiple core chips 130-1 to 130-L, the top-level core chip 130-L can drive the voltage path after the TSV open-circuit / short-circuit test begins. The multiple core chips 130-1 to 130-L can transmit the power supply voltage ( ) through the voltage path after the voltage monitoring operation begins. Figure 3 VDD) and high voltage ( Figure 3 The VPP in the chip is output to the base chip 120.

[0036] Each of the multiple core chips 130-1 to 130-L may include multiple independently operating channel regions. Each of the multiple channel regions may be assigned a channel that operates independently and can receive and transmit data. The number L of the multiple core chips 130-1 to 130-L may be 4, 8, 12, or 16. For example, when each of the core chips 130-1 to 130-12 includes 8 channels, each of the core chips 130-1 to 130-4, 130-5 to 130-8, and 130-9 to 130-12 may include 32 channel regions and may transmit and receive data from the processor 19 in units of memory rows including 32 channels.

[0037] In the signal transmission path of the base chip 120, the processor 19 can detect faulty signal transmission paths by means of wires formed in the interposer layer 15.

[0038] Figure 2 This is a block diagram illustrating the construction of a storage device 17 according to an embodiment of the present disclosure. Figure 2 As shown, the storage device 17 may include a base chip 120, a first core chip 130-1, a second core chip 130-2, a third core chip 130-3, and a fourth core chip 130-4.

[0039] The base chip 120 can be electrically connected to a first signal path, a second signal path, a first voltage path, and a second voltage path. The first signal path can be implemented by electrically connecting TSVs T11, T12, T13, T14, and T15 to microbump pads B11, B12, B13, and B14. The second signal path can be implemented by electrically connecting TSVs T21, T22, T23, T24, and T25 to microbump pads B21, B22, B23, and B24. The first voltage path can be implemented by electrically connecting TSVs T31, T32, T33, T34, and T35 to microbump pads B31, B32, B33, and B34. The second voltage path can be implemented by electrically connecting TSVs T41, T42, T43, T44, and T45 to microbump pads B41, B42, B43, and B44. The first and second signal paths can be implemented such that signals controlling the operation of the first core chip 130-1, the second core chip 130-2, the third core chip 130-3, and the fourth core chip 130-4 are input and output along these paths. The first and second voltage paths can be configured such that the power supply voltage used in the first core chip 130-1, the second core chip 130-2, the third core chip 130-3, and the fourth core chip 130-4 (…) Figure 3 VDD) and high voltage ( Figure 3 (VPP in the middle) along its output.

[0040] TSVs T11, T12, T13, T14, T15, T21, T22, T23, T24, T25, T31, T32, T33, T34, T35, T41, T42, T43, T44, and T45 can be implemented in a cylindrical form using conductive material, which connects the base chip 120, the first core chip 130-1, the second core chip 130-2, the third core chip 130-3, and the fourth core chip 130-4 to each other when vertically stacked. Microbump pads B11, B12, B13, B14, B21, B22, B23, B24, B31, B32, B33, B34, B41, B42, B43, and B44 can be implemented in a spherical form using conductive material for direct connection to the circuit board. The first signal path and the second signal path, as well as the first voltage path and the second voltage path, are each implemented to include five TSVs, but according to embodiments, they can be implemented to include various numbers of TSVs.

[0041] The base chip 120 may include TSV T11, T21, T31 and T41, a base test circuit (BASE TEST CT) 22, a fault detection circuit (FAIL DET CT) 23 and a voltage monitoring circuit (VM CT) 24.

[0042] TSV T11 can be electrically connected to microbump pad B11. TSV T21 can be electrically connected to microbump pad B21. TSV T31 can be electrically connected to microbump pad B31. TSV T41 can be electrically connected to microbump pad B41.

[0043] The basic test circuit 22 can drive TSVs T11, T21, T31, and T41 using either a PMOS transistor or an NMOS transistor after the TSV open-circuit / short-circuit test begins. The basic test circuit 22 can also utilize the internal voltage of the PMOS transistor after the upstream TSV open-circuit / short-circuit test begins. Figure 6 The VINT in the circuit drives TSVT11, T21, T31, and T41. The basic test circuit 22 can utilize the ground voltage (VINT in the circuit) after the start of the downstream TSV open / short circuit test during the TSV open / short circuit test. Figure 6 The VSS in the circuit drives TSVs T11, T21, T31, and T41. The basic test circuit 22 can generate a first fault detection signal to a fourth fault detection signal by detecting the logic level of the internal nodes connected to TSVs T11, T21, T31, and T41 after the TSV open-circuit and short-circuit tests have begun. Figure 3 (FD<1:4> in the text). The basic test circuit 22 can disconnect the TSV T31 of the first voltage path from the third basic drive circuit after the voltage monitoring operation begins. Figure 7 The connection between 223-2 in the diagram. The basic test circuit 22 can disconnect the TSV T41 of the second voltage path from the fourth basic drive circuit ( ) after the voltage monitoring operation begins. Figure 8 The connection between 224-2 in the middle.

[0044] Fault detection circuit 23 can detect faults based on the first fault detection signal to the fourth fault detection signal after the TSV open-circuit and short-circuit test begins. Figure 3 The FD<1:4> in the middle is used to detect connection faults in the first signal path and the second signal path, as well as the first voltage path and the second voltage path.

[0045] Voltage monitoring circuit 24 can detect the power supply voltage input through the first voltage path. Figure 3 The voltage level of VDD and the high voltage input through the second voltage path (in the second voltage path) Figure 3 The voltage level of VPP in the system.

[0046] The first core chip 130-1 can be electrically connected to microbump pads B11, B21, B31 and B41, and can be stacked on the base chip 120.

[0047] The first core chip 130-1 may include TSV T12, T22, T32 and T42.

[0048] TSV T12 can be electrically connected between microbump pads B11 and B12. TSV T22 can be electrically connected between microbump pads B21 and B22. TSV T32 can be electrically connected between microbump pads B31 and B32. TSV T42 can be electrically connected between microbump pads B41 and B42.

[0049] The second core chip 130-2 can be electrically connected to microbump pads B12, B22, B32 and B42, and can be stacked on the first core chip 130-1.

[0050] The second core chip 130-2 may include TSV T13, T23, T33 and T43.

[0051] TSV T13 can be electrically connected between microbump pads B12 and B13. TSV T23 can be electrically connected between microbump pads B22 and B23. TSV T33 can be electrically connected between microbump pads B32 and B33. TSV T43 can be electrically connected between microbump pads B42 and B43.

[0052] The third core chip 130-3 can be electrically connected to microbump pads B13, B23, B33 and B43, and can be stacked on the second core chip 130-2.

[0053] The third core chip 130-3 may include TSV T14, T24, T34 and T44.

[0054] TSV T14 can be electrically connected between microbump pads B13 and B14. TSV T24 can be electrically connected between microbump pads B23 and B24. TSV T34 can be electrically connected between microbump pads B33 and B34. TSV T44 can be electrically connected between microbump pads B43 and B44.

[0055] The fourth core chip 130-4 can be electrically connected to microbump pads B14, B24, B34 and B44, and can be stacked on the third core chip 130-3.

[0056] The fourth core chip 130-4 may include TSV T15, T25, T35 and T45 as well as the core test circuit (CORETEST CT) 51.

[0057] The core test circuit 51 can drive TSVs T15, T25, T35, and T45 using either a PMOS transistor or an NMOS transistor after the TSV open-circuit / short-circuit test begins. The core test circuit 51 can also utilize the internal voltage of the PMOS transistor after the downstream TSV open-circuit / short-circuit test begins. Figure 11 The VINT in the circuit drives TSVT15, T25, T35, and T45. The core test circuit 51 can utilize the ground voltage (VINT in the circuit) after the TSV open / short circuit test begins via an NMOS transistor. Figure 11 The VSS in the circuit drives TSV T15, T25, T35, and T45. The core test circuit 51 can disconnect TSV T35 of the first voltage path from the third core drive circuit after the voltage monitoring operation begins. Figure 12 The connection between 513-2 in the core test circuit 51 and the fourth core drive circuit (T45) can be disconnected after the voltage monitoring operation begins. Figure 13 The connection between 514-2 in the middle.

[0058] exist Figure 2 In this embodiment, a first core chip 130-1, a second core chip 130-2, a third core chip 130-3, and a fourth core chip 130-4 are vertically stacked on the base chip 120. However, according to the embodiment, various numbers of core chips, such as 8 and 16, can be stacked on the base chip 120.

[0059] Figure 2 The storage device 17 shown is implemented similarly to a high bandwidth memory (HBM) by vertically stacking a base chip 120, a first core chip 130-1, a second core chip 130-2, a third core chip 130-3, and a fourth core chip 130-4 interconnected via TSVs. However, this disclosure is not limited thereto, and according to embodiments, it can be implemented such that multiple core chips are stacked by wire bonding.

[0060] Figure 3 This is a block diagram illustrating the construction of a base chip 120 according to an embodiment of the present disclosure. The base chip 120 may include a test control circuit (TEST CTR CT) 21, a basic test circuit 22, a fault detection circuit 23, and a voltage monitoring circuit 24.

[0061] Based on the downlink scan enable signal DEN and the uplink scan enable signal UEN, the test control circuit 21 can generate the downlink scan signal DNS, the uplink scan signal UPS, the downlink latch signal DLAT, and the uplink latch signal ULAT. The downlink scan enable signal DEN can be configured to be enabled after the start of the downlink TSV open / short circuit test in the TSV open / short circuit test. The uplink scan enable signal UEN can be configured to be enabled after the start of the uplink TSV open / short circuit test in the TSV open / short circuit test. The test control circuit 21 can generate the downlink scan signal DNS, which is enabled when the downlink scan enable signal DEN is enabled. The test control circuit 21 can generate the downlink latch signal DLAT by delaying the downlink scan signal DNS. The test control circuit 21 can generate the uplink scan signal UPS, which is enabled when the uplink scan enable signal UEN is enabled. The test control circuit 21 can generate the uplink latch signal ULAT by delaying the uplink scan signal UPS.

[0062] Based on the downlink scan enable signal DEN and the uplink scan enable signal UEN, the test control circuit 21 can generate a scan enable signal SCE and an inverted scan enable signal SCEB. When either the downlink scan enable signal DEN or the uplink scan enable signal UEN is enabled, the test control circuit 21 can generate a scan enable signal SCE that is enabled at a high voltage level VPP. When both the downlink scan enable signal DEN and the uplink scan enable signal UEN are disabled, the test control circuit 21 can generate an inverted scan enable signal SCEB that is enabled at a high voltage level VPP.

[0063] The basic test circuit 22 can be electrically connected to TSVs T11, T21, T31, and T41. After the TSV open-circuit / short-circuit test begins, the basic test circuit 22 can drive TSVs T11, T21, T31, and T41 using either a PMOS transistor or an NMOS transistor. After the TSV open-circuit / short-circuit test begins, the basic test circuit 22 can also drive TSVs T11, T21, T31, and T41 using either a PMOS transistor or an NMOS transistor based on the downlink scan signal DNS and the uplink scan signal UPS. After the TSV open-circuit / short-circuit test begins, the basic test circuit 22 can latch the logic level of the internal nodes connected to TSVs T11, T21, T31, and T41 based on the downlink latch signal DLAT and the uplink latch signal ULAT. The basic test circuit 22 can generate the first to fourth fault detection signals FD<1:4> by detecting the latched logic levels of the internal nodes connected to TSV T11, T21, T31 and T41 after the TSV open and short circuit test begins.

[0064] The basic test circuit 22 can, after the voltage monitoring operation begins, output the power supply voltage VDD transmitted through the first voltage path TSV T31 as the first transmitted voltage TV1 based on the scan enable signal SCE and the inverted scan enable signal SCEB. The basic test circuit 22 can, after the voltage monitoring operation begins, output the high voltage VPP transmitted through the second voltage path TSV T41 as the second transmitted voltage TV2 based on the scan enable signal SCE and the inverted scan enable signal SCEB. The basic test circuit 22 can, after the voltage monitoring operation begins, disconnect the first voltage path TSV T31 from the third basic drive circuit (…). Figure 7 The connection between 223-2 in the diagram. The basic test circuit 22 can disconnect the TSV T41 of the second voltage path from the fourth basic drive circuit (based on the scan enable signal SCE and the inverted scan enable signal SCEB) after the voltage monitoring operation begins. Figure 8 The connection between 224-2 in the diagram. The power supply voltage VDD can be set to a voltage that has a higher voltage than the internal voltage ( ). Figure 6 The high voltage VPP can be set to a voltage level higher than the supply voltage VDD. Internal voltage (VINT) Figure 6 VINT in the first core chip 130-1 to the fourth core chip 130-4 is a voltage used within the first core chip 130-1 to the fourth core chip 130-4, and can be set to generate a voltage by reducing the voltage level of the power supply voltage VDD.

[0065] After the voltage monitoring operation begins, the TSV T31 of the first voltage path is disconnected from the third basic drive circuit via the basic test circuit 22. Figure 7 The operation of the connection between 223-2) is intended to: protect the third base drive circuit ( ) when a power supply voltage VDD with a high voltage level is output to the first voltage path. Figure 7 The components included in 223-2). After the voltage monitoring operation begins, the TSV T41 of the second voltage path is disconnected from the fourth basic drive circuit via the basic test circuit 22. Figure 8 The operation of the connection between 224-2) is intended to: protect the fourth base drive circuit ( ) when a high voltage VPP with a high voltage level is output to the second voltage path. Figure 8 The elements contained in 224-2).

[0066] The fault detection circuit 23 can detect connection faults in the first signal path and the second signal path, as well as the first voltage path and the second voltage path, based on the first fault detection signal to the fourth fault detection signal FD<1:4> after the TSV open-circuit and short-circuit test begins. The fault detection circuit 23 can also detect open-circuit faults—where the first signal path and the second signal path, as well as the first voltage path and the second voltage path, are disconnected—by detecting the logic levels of the first fault detection signal to the fourth fault detection signal FD<1:4> after the TSV open-circuit and short-circuit test begins. Conversely, the fault detection circuit 23 can detect short-circuit faults—where the first signal path and the second signal path, as well as the first voltage path and the second voltage path, are connected—by detecting the logic levels of the first fault detection signal to the fourth fault detection signal FD<1:4> after the TSV open-circuit and short-circuit test begins.

[0067] The voltage monitoring circuit 24 can receive a first transmitted voltage TV1 and a second transmitted voltage TV2 after the voltage monitoring operation begins. The voltage monitoring circuit 24 can generate a monitoring voltage VM from either the first transmitted voltage TV1 or the second transmitted voltage TV2 after the voltage monitoring operation begins. The voltage monitoring circuit 24 can detect the voltage level of the monitoring voltage VM after the voltage monitoring operation begins. The voltage monitoring circuit 24 can output the monitoring voltage VM to an external device, such as the processor 19, after the voltage monitoring operation begins.

[0068] Figure 4 This is a block diagram illustrating the construction of a test control circuit 21 according to an embodiment of the present disclosure. The test control circuit 21 may include a scan control circuit (SCAN CTR CT) 211, an enable signal generation circuit (EN GEN) 213, and a level shifting circuit (LV SFT) 215.

[0069] Based on the downlink scan enable signal DEN and the uplink scan enable signal UEN, the scan control circuit 211 can generate the downlink scan signal DNS, the uplink scan signal UPS, the downlink latch signal DLAT, and the uplink latch signal ULAT. When the downlink scan enable signal DEN is enabled, the scan control circuit 211 can generate the enabled downlink scan signal DNS. When the uplink scan enable signal UEN is enabled, the scan control circuit 211 can generate the enabled uplink scan signal UPS. The scan control circuit 211 can generate the downlink latch signal DLAT by delaying the downlink scan signal DNS. The scan control circuit 211 can generate the uplink latch signal ULAT by delaying the uplink scan signal UPS.

[0070] The enable signal generation circuit 213 can receive the internal voltage VINT and can generate an enable signal EN based on the downlink scan signal DNS and the uplink scan signal UPS. When either the downlink scan signal DNS or the uplink scan signal UPS is enabled, the enable signal generation circuit 213 can generate an enable signal EN driven to the voltage level of the internal voltage VINT.

[0071] Level shifting circuit 215 can receive a high voltage VPP and can generate scan enable signal SCE and inverted scan enable signal SCEB by shifting the logic level of enable signal EN. When enable signal EN is enabled, level shifting circuit 215 can generate scan enable signal SCE with a voltage level of high voltage VPP and inverted scan enable signal SCEB with a voltage level of ground voltage VSS. When enable signal EN is disabled, level shifting circuit 215 can generate inverted scan enable signal SCEB with a voltage level of high voltage VPP and scan enable signal SCE with a voltage level of ground voltage VSS. Level shifting circuit 215 can be implemented using a conventional level shifting circuit.

[0072] Figure 5 This is a block diagram illustrating the construction of a basic test circuit 22 according to an embodiment of the present disclosure. The basic test circuit 22 may include a first fault signal generation circuit (1... st FAIL GEN)221, Second Fault Signal Generating Circuit (2 nd FAIL GEN)222, Third Fault Signal Generating Circuit (3) rd FAIL GEN)223, Fourth Fault Signal Generation Circuit (4 th FAIL GEN)224 and fault detection signal generation circuit (FD GEN)225.

[0073] The first fault signal generation circuit 221 can be electrically connected to TSV T11 of the first signal path. The first fault signal generation circuit 221 can generate the first fault signal FAIL based on the downlink scan signal DNS, the uplink scan signal UPS, the downlink latch signal DLAT, and the uplink latch signal ULAT. <1> After the downlink TSV open / short circuit test begins, when the downlink scan signal DNS is enabled, the first fault signal generation circuit 221 can activate via an NMOS transistor ( Figure 6 The first fault signal generation circuit 221 (221-13) drives TSV T11. After the downlink TSV open-circuit / short-circuit test begins, when the downlink latch signal DLAT is enabled, the first fault signal generation circuit 221 can latch the internal node ( Figure 6 The logic level of ND221 in the internal node is connected to the NMOS transistor (ND221). Figure 6The TSV T11 is driven by 221-13 in the middle. After the uplink TSV open-circuit and short-circuit test starts, when the uplink scan signal UPS is enabled, the first fault signal generation circuit 221 can be activated by the PMOS transistor ( Figure 6 The first fault signal generation circuit 221 (221-12) drives TSVT11. After the uplink TSV open / short circuit test begins, when the uplink latch signal ULAT is enabled, the first fault signal generation circuit 221 can latch the internal node ( Figure 6 The logic level of ND221 in the internal node is connected to the PMOS transistor (ND221). Figure 6 The first fault signal generation circuit 221 can be based on the internal node connected to the TSV T11 (221-12). Figure 6 The logic level of ND221 in the code is used to generate the first fault signal FAIL. <1> .

[0074] The second fault signal generation circuit 222 can be electrically connected to TSV T21 of the second signal path. The second fault signal generation circuit 222 can generate the second fault signal FAIL based on the downlink scan signal DNS, the uplink scan signal UPS, the downlink latch signal DLAT, and the uplink latch signal ULAT. <2> After the downlink TSV open / short circuit test begins, when the downlink scan signal DNS is enabled, the second fault signal generation circuit 222 can drive TSV T21 via an NMOS transistor (not shown). After the downlink TSV open / short circuit test begins, when the downlink latch signal DLAT is enabled, the second fault signal generation circuit 222 can latch the logic level of an internal node (not shown) connected to TSV T21 driven by an NMOS transistor (not shown). After the uplink TSV open / short circuit test begins, when the uplink scan signal UPS is enabled, the second fault signal generation circuit 222 can drive TSV T21 via a PMOS transistor (not shown). After the uplink TSV open / short circuit test begins, when the uplink latch signal ULAT is enabled, the second fault signal generation circuit 222 can latch the logic level of an internal node (not shown) connected to TSV T21 driven by a PMOS transistor (not shown). The second fault signal generation circuit 222 can generate the second fault signal FAIL based on the logic level of the internal node (not shown) connected to TSV T21. <2> .

[0075] The third fault signal generation circuit 223 can be electrically connected to TSV T31 of the first voltage path. The third fault signal generation circuit 223 can generate the third fault signal FAIL based on the downlink scan signal DNS, the uplink scan signal UPS, the downlink latch signal DLAT, and the uplink latch signal ULAT. <3> After the downlink TSV open / short circuit test begins, when the downlink scan signal DNS is enabled, the third fault signal generation circuit 223 can activate via an NMOS transistor ( Figure 7 The third fault signal generation circuit 223 drives the TSV T31. After the downlink TSV open-circuit / short-circuit test begins, when the downlink latch signal DLAT is enabled, the third fault signal generation circuit 223 can latch the internal node ( Figure 7 The logic level of ND223 in the internal node is connected to the NMOS transistor (ND223). Figure 7 The TSV T31 is driven by 223-23 in the middle. After the uplink TSV open-circuit and short-circuit test begins, when the uplink scan signal UPS is enabled, the third fault signal generation circuit 223 can be activated by the PMOS transistor ( Figure 7 The third fault signal generation circuit 223 (223-22) drives TSVT31. After the uplink TSV open / short circuit test begins, when the uplink latch signal ULAT is enabled, the third fault signal generation circuit 223 can latch the internal node ( Figure 7 The logic level of ND223 in the internal node is connected to the PMOS transistor (ND223). Figure 7 The third fault signal generation circuit 223 can be based on the internal node connected to the TSV T31 (223-22). Figure 7 The logic level of ND223 in the code is used to generate the third fault signal FAIL. <3> The third fault signal generation circuit 223 can receive the power supply voltage VDD through TSV T31 of the first voltage path after the voltage monitoring operation begins. The third fault signal generation circuit 223 can output the power supply voltage VDD as the first transmission voltage TV1 after the voltage monitoring operation begins.

[0076] The fourth fault signal generation circuit 224 can be electrically connected to TSV T41 of the second voltage path. The fourth fault signal generation circuit 224 can generate the fourth fault signal FAIL based on the downlink scan signal DNS, the uplink scan signal UPS, the downlink latch signal DLAT, and the uplink latch signal ULAT. <4> After the downlink TSV open / short circuit test begins, when the downlink scan signal DNS is enabled, the fourth fault signal generation circuit 224 can activate via an NMOS transistor ( Figure 8The fourth fault signal generation circuit 224 (224-23) drives the TSV T41. After the downlink TSV open-circuit / short-circuit test begins, when the downlink latch signal DLAT is enabled, the fourth fault signal generation circuit 224 can latch the internal node ( Figure 8 The logic level of ND224 in the internal node is connected to the NMOS transistor (ND224). Figure 8 The TSV T41 is driven by 224-23 in the above. After the uplink TSV open-circuit and short-circuit test begins, when the uplink scan signal UPS is enabled, the fourth fault signal generation circuit 224 can be activated by the PMOS transistor ( Figure 8 The fourth fault signal generation circuit 224 (224-22) drives the TSVT41. After the uplink TSV open / short circuit test begins, when the uplink latch signal ULAT is enabled, the fourth fault signal generation circuit 224 can latch the internal node ( Figure 8 The logic level of ND224 in the internal node is connected to the PMOS transistor (ND224). Figure 8 The fourth fault signal generation circuit 224 can be based on the internal node connected to the TSV T41 (224-22). Figure 8 The logic level of ND224 in the code is used to generate the fourth fault signal FAIL. <4> The fourth fault signal generation circuit 224 can receive the high voltage VPP through TSV T41 of the second voltage path after the voltage monitoring operation begins. The fourth fault signal generation circuit 224 can also output the high voltage VPP as the second transmission voltage TV2 after the voltage monitoring operation begins.

[0077] The fault detection signal generation circuit 225 can generate the first fault detection signal to the fourth fault detection signal FD<1:4> based on the first fault signal to the fourth fault signal FAIL<1:4>. The fault detection signal generation circuit 225 can latch the first fault signal to the fourth fault signal FAIL<1:4>. The fault detection signal generation circuit 225 can output the latched first fault signal to the fourth fault signal FAIL<1:4> as the first fault detection signal to the fourth fault detection signal FD<1:4>.

[0078] Figure 6 This is a view illustrating the construction of a first fault signal generating circuit 221 according to an embodiment of the present disclosure. The first fault signal generating circuit 221 may include a first basic drive circuit 221-1, a first storage circuit 221-2, and a first input and output circuit 221-3.

[0079] The first basic drive circuit 221-1 may include an inverter 221-11, a PMOS transistor 221-12, and an NMOS transistor 221-13. The inverter 221-11 can output an uplink scan signal UPS by inverting the uplink scan signal UPS. The PMOS transistor 221-12 is connected between the internal voltage VINT and node ND221, and when the output signal of the inverter 221-11 is at a logic low level, it can generate the first basic data BD1 with a logic high level by driving node ND221 to the voltage level of the internal voltage VINT. The NMOS transistor 221-13 is connected between node ND221 and the ground voltage VSS, and when the downlink scan signal DNS is at a logic high level, it can generate the first basic data BD1 with a logic low level by driving node ND221 to the voltage level of the ground voltage VSS. The PMOS transistor 221-12 of the first basic drive circuit 221-1 can be configured to have a higher voltage level than the first core drive circuit (…). Figure 11 The NMOS transistor (511) in the middle Figure 11 (511-13) Greater driving force. Therefore, when no fault occurs in TSV T11, T12, T13, T14 and T15 in the first signal path, the first basic drive circuit 221-1 can drive TSV T11, T12, T13, T14 and T15 to the voltage level of the internal voltage VINT.

[0080] The first storage circuit 221-2 may include a first latch (1 st LATCH)221-21, Second Latch (2 nd LATCH)221-22 and AND gates 221-23.

[0081] When the power-on operation terminates, the first latch 221-21 can generate first latched data LD1 with a logic high level. When the downlink latch signal DLAT is enabled to a logic high level, the first latch 221-21 can latch the first basic data BD1. The first latch 221-21 can output the latched first basic data BD1 as the first latched data LD1. The power-on operation can be configured such that the internal voltage VINT rises based on the power supply voltage VDD and is generated to a preset voltage level before the first core chip 130-1 to the fourth core chip 130-4 begin their operation.

[0082] When the power-on operation terminates, the second latch 221-22 can generate second latched data LD2 with a logic high level. When the uplink latch signal ULAT is enabled to a logic high level, the second latch 221-22 can latch the first basic data BD1. The second latch 221-22 can output the latched first basic data BD1 as the second latched data LD2.

[0083] AND gates 221-23 can generate a first fault signal FAIL based on the logic level of the first latched data LD1 and the logic level of the second latched data LD2. <1> When the first latched data LD1 is at a logic high level and the second latched data LD2 is at a logic high level, AND gates 221-23 can generate a first fault signal FAIL with a logic high level. <1> When at least one of the first latched data LD1 and the second latched data LD2 is at a logic low level, AND gates 221-23 can generate a first fault signal FAIL with a logic low level. <1> .

[0084] The first input and output circuit 221-3 may include a transmitter (TX) 221-31 and a receiver (RX) 221-32.

[0085] Transmitter 221-31 can be driven by receiving an internal voltage VINT. Transmitter 221-31 can output a first signal SIG1, which is to be output from base chip 120 to the first core chip 130-1 through the fourth core chip 130-4, to TSVT11. The first signal SIG1 can be configured to include commands and data controlling the operation of the first core chip 130-1 through the fourth core chip 130-4.

[0086] Receiver 221-32 can be driven by receiving the internal voltage VINT. Receiver 221-32 can output the second signal SIG2 received from TSVT11 to the base chip 120. The second signal SIG2 can be configured to include data output from the first core chip 130-1 to the fourth core chip 130-4.

[0087] The first input and output circuit 221-3 can output signals from the base chip 120 to the first core chip 130-1 to the fourth core chip 130-4 via TSV T11. The first input and output circuit 221-3 can receive signals from the first core chip 130-1 to the fourth core chip 130-4 to the base chip 120 via TSV T11, and can output these signals to the base chip 120.

[0088] Figure 5The second fault signal generating circuit 222 shown is electrically connected to TSV T21 and generates the second fault signal FAIL. <2> and through with Figure 6 The circuit is implemented in the same way as the first fault signal generation circuit 221 shown, and performs the same operation as the first fault signal generation circuit 221. Therefore, its detailed description is omitted.

[0089] Figure 7 This is a view illustrating the construction of a third fault signal generating circuit 223 according to an embodiment of the present disclosure. The third fault signal generating circuit 223 may include a first switching circuit 223-1, a third basic drive circuit 223-2, and a third storage circuit 223-3.

[0090] The first switching circuit 223-1 may include transmission gates 223-11 and 223-12. Transmission gates 223-11 and 223-12 may be implemented using PMOS and NMOS transistors, which receive a high voltage VPP with a high voltage level through their gates without voltage drop. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverted scan enable signal SCEB is disabled to the ground voltage VSS level, transmission gate 223-11 can connect TSV T31 to the internal node ND223. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverted scan enable signal SCEB is enabled to the high voltage VPP level, transmission gate 223-11 can disconnect TSV T31 from the internal node ND223. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverting scan enable signal SCEB is enabled to the high voltage VPP level, the transmitter 223-12 can output the first transmission voltage TV1 by generating the first transmission voltage TV1 based on the power supply voltage VDD input from TSV T31. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverting scan enable signal SCEB is disabled to the ground voltage VSS level, the transmitter 223-12 may not output the first transmission voltage TV1 from the power supply voltage VDD input from TSV T31. When the scan enable signal SCE is enabled to the high voltage VPP level, the first switching circuit 223-1 can connect TSV T31 to the internal node ND223. When the inverting scan enable signal SCEB is enabled to the high voltage VPP level, the first switching circuit 223-1 can disconnect the connection between TSV T31 and the internal node ND223. When the inverting scan enable signal SCEB is enabled to a high voltage level VPP, the first switching circuit 223-1 can generate a first transmission voltage TV1 based on the power supply voltage VDD input from TSV T31 and output the first transmission voltage TV1.

[0091] The third basic drive circuit 223-2 may include an inverter 223-21, a PMOS transistor 223-22, and an NMOS transistor 223-23. The inverter 223-21 outputs the uplink scan signal UPS by inverting the uplink scan signal UPS. The PMOS transistor 223-22 is connected between the internal voltage VINT and node ND223, and when the output signal of the inverter 223-21 is at a logic low level, it can generate the third basic data BD3 with a logic high level by driving node ND223 to the voltage level of the internal voltage VINT. The NMOS transistor 223-23 is connected between node ND223 and the ground voltage VSS, and when the downlink scan signal DNS is at a logic high level, it can generate the third basic data BD3 with a logic low level by driving node ND223 to the voltage level of the ground voltage VSS. The PMOS transistor 223-22 of the third basic drive circuit 223-2 can be configured to have a higher voltage level than the third core drive circuit (…). Figure 12 The NMOS transistor (513) in the middle Figure 12 The third base drive circuit 223-2 can drive TSVs T31, T32, T33, T34, and T35 to the voltage level of the internal voltage VINT when no fault occurs in TSVs T31, T32, T33, T34, and T35 in the first voltage path. The third base drive circuit 223-2 can generate the third base data BD3 by driving the internal node ND223 of TSV T31 based on the downlink scan signal DNS and the uplink scan signal UPS via one of the PMOS transistors 223-22 and NMOS transistors 223-23.

[0092] The third storage circuit 223-3 may include a fifth latch (5 th LATCH)223-31, Sixth Latch (6 thLATCH 223-32 and AND gate 223-33. When the power-on operation terminates, the fifth latch 223-31 can generate the fifth latched data LD5 with a logic high level. When the downlink latch signal DLAT is enabled to a logic high level, the fifth latch 223-31 can latch the third basic data BD3. The fifth latch 223-31 can output the latched third basic data BD3 as the fifth latched data LD5. When the power-on operation terminates, the sixth latch 223-32 can generate the sixth latched data LD6 with a logic high level. When the uplink latch signal ULAT is enabled to a logic high level, the sixth latch 223-32 can latch the third basic data BD3. The sixth latch 223-32 can output the latched third basic data BD3 as the sixth latched data LD6. AND gates 223-33 can generate a third fault signal FAIL based on the logic level of the fifth latched data LD5 and the logic level of the sixth latched data LD6. <3> When the fifth latched data LD5 is at a logic high level and the sixth latched data LD6 is at a logic high level, AND gate 223-33 can generate a third fault signal FAIL with a logic high level. <3> When at least one of the fifth latched data LD5 and the sixth latched data LD6 is at a logic low level, AND gate 223-33 can generate a third fault signal FAIL with a logic low level. <3> The third storage circuit 223-3 can latch the third basic data BD3 based on the downlink latch signal DLAT and the uplink latch signal ULAT. The third storage circuit 223-3 can generate a third fault signal FAIL from the latched third basic data BD3. <3> .

[0093] Figure 8 This is a view illustrating the construction of a fourth fault signal generation circuit 224 according to an embodiment of the present disclosure. The fourth fault signal generation circuit 224 may include a second switching circuit 224-1, a fourth basic drive circuit 224-2, and a fourth storage circuit 224-3.

[0094] The second switching circuit 224-1 may include transmission gates 224-11 and 224-12. Transmission gates 224-11 and 224-12 can be implemented using PMOS and NMOS transistors, which receive a high voltage VPP with a high voltage level through their gates without voltage drop. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverted scan enable signal SCEB is disabled to the ground voltage VSS level, transmission gate 224-11 can connect TSV T41 to the internal node ND224. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverted scan enable signal SCEB is enabled to the high voltage VPP level, transmission gate 224-11 can disconnect TSV T41 from the internal node ND224. When the scan enable signal SCE is disabled to the voltage level of ground voltage VSS and the inverting scan enable signal SCEB is enabled to the voltage level of high voltage VPP, the transmitter 224-12 can output the second transmission voltage TV2 by generating the second transmission voltage TV2 based on the high voltage VPP input from TSV T41. When the scan enable signal SCE is enabled to the voltage level of high voltage VPP and the inverting scan enable signal SCEB is disabled to the voltage level of ground voltage VSS, the transmitter 224-12 may not output the second transmission voltage TV2 from the high voltage VPP input from TSV T41. When the scan enable signal SCE is enabled to the voltage level of high voltage VPP, the second switching circuit 224-1 can connect TSV T41 to the internal node ND224. When the inverting scan enable signal SCEB is enabled to the voltage level of high voltage VPP, the second switching circuit 224-1 can disconnect the connection between TSV T41 and the internal node ND224. When the inverting scan enable signal SCEB is enabled to a high voltage level VPP, the second switching circuit 224-1 can output the second transmission voltage TV2 by generating the second transmission voltage TV2 based on the high voltage VPP input from TSVT41.

[0095] The fourth basic driver circuit 224-2 may include an inverter 224-21, a PMOS transistor 224-22, and an NMOS transistor 224-23. Inverter 224-21 outputs the uplink scan signal UPS by inverting the uplink scan signal UPS. PMOS transistor 224-22 is connected between the internal voltage VINT and node ND224, and when the output signal of inverter 224-21 is at a logic low level, it can generate the fourth basic data BD4 with a logic high level by driving node ND224 to the voltage level of the internal voltage VINT. NMOS transistor 224-23 is connected between node ND224 and the ground voltage VSS, and when the downlink scan signal DNS is at a logic high level, it can generate the fourth basic data BD4 with a logic low level by driving node ND224 to the voltage level of the ground voltage VSS. The PMOS transistor 224-22 of the fourth basic driver circuit 224-2 can be configured to have a higher voltage level than the fourth core driver circuit (…). Figure 13 The NMOS transistor (514) in the middle Figure 13 The fourth base drive circuit 224-2 can drive TSVs T41, T42, T43, T44, and T45 to the voltage level of the internal voltage VINT when no fault occurs in TSVs T41, T42, T43, T44, and T45 in the fourth signal path. The fourth base drive circuit 224-2 can generate the fourth base data BD4 by driving the internal node ND224 of TSV T41 based on the downlink scan signal DNS and the uplink scan signal UPS via one of the PMOS transistors 224-32 and NMOS transistors 224-33.

[0096] The fourth storage circuit 224-3 may include a seventh latch (7 th LATCH)224-31, Eighth Latch (8 thLATCH 224-32 and AND gate 224-33. When the power-on operation terminates, the seventh latch 224-31 can generate the seventh latched data LD7 with a logic high level. When the downlink latch signal DLAT is enabled to a logic high level, the seventh latch 224-31 can latch the fourth basic data BD4. The seventh latch 224-31 can output the latched fourth basic data BD4 as the seventh latched data LD7. When the power-on operation terminates, the eighth latch 224-32 can generate the eighth latched data LD8 with a logic high level. When the uplink latch signal ULAT is enabled to a logic high level, the eighth latch 224-32 can latch the fourth basic data BD4. The eighth latch 224-32 can output the latched fourth basic data BD4 as the eighth latched data LD8. AND gate 224-33 can generate a fourth fault signal FAIL based on the logic level of the seventh latch data LD7 and the logic level of the eighth latch data LD8. <4> When the seventh latch data LD7 is at a logic high level and the eighth latch data LD8 is at a logic high level, AND gate 224-33 can generate a fourth fault signal FAIL with a logic high level. <4> When at least one of the seventh latched data LD7 and the eighth latched data LD8 is at a logic low level, AND gate 224-33 can generate a fourth fault signal FAIL with a logic low level. <4> The fourth storage circuit 224-3 can latch the fourth basic data BD4 based on the downlink latch signal DLAT and the uplink latch signal ULAT. The fourth storage circuit 224-3 can generate a fourth fault signal FAIL from the latched fourth basic data BD4. <4> .

[0097] Figure 9 This is a block diagram illustrating the construction of a fourth core chip 130-4 according to an embodiment of the present disclosure. The fourth core chip 130-4 may include TSVs T15, T25, T35, and T45, as well as a core test circuit 51.

[0098] The core test circuit 51 can receive the downlink scan signal DNS, uplink scan signal UPS, scan enable signal SCE, and inverted scan enable signal SCEB from the base chip 120. The downlink scan signal DNS, uplink scan signal UPS, scan enable signal SCE, and inverted scan enable signal SCEB can be input from the base chip 120 to the core test circuit 51 through TSVs separate from TSVs T11, T12, T13, T14, T15, T21, T22, T23, T24, T25, T31, T32, T33, T34, T35, T41, T42, T43, T44, and T45.

[0099] The core test circuit 51 can be electrically connected to TSVs T15, T25, T35, and T45. After the TSV open-circuit / short-circuit test begins, the core test circuit 51 can drive TSVs T15, T25, T35, and T45 using either a PMOS transistor or an NMOS transistor. After the TSV open-circuit / short-circuit test begins, the core test circuit 51 can drive TSVs T14, T24, T34, and T44 using either a PMOS transistor or an NMOS transistor based on the downlink scan signal DNS and the uplink scan signal UPS. After the downlink TSV open-circuit / short-circuit test begins, when the downlink scan signal DNS is enabled, the core test circuit 51 can utilize the internal voltage (…) of the PMOS transistor… Figure 11 The VINT signal in the NMOS transistor drives TSVs T15, T25, T35, and T45. After the uplink TSV open / short circuit test begins, when the uplink scan signal UPS is enabled, the core test circuit 51 can utilize the ground voltage (VINT) through the NMOS transistor. Figure 11 The VSS in the middle drives TSV T15, T25, T35 and T45.

[0100] After the voltage monitoring operation begins, the core test circuit 51 can output the power supply voltage VDD through TSV T31 of the first voltage path based on the scan enable signal SCE and the inverted scan enable signal SCEB. The core test circuit 51 can also output a high voltage VPP through TSV T41 of the second voltage path based on the scan enable signal SCE and the inverted scan enable signal SCEB. Finally, the core test circuit 51 can disconnect TSV T35 of the first voltage path from the third core drive circuit (…) based on the scan enable signal SCE and the inverted scan enable signal SCEB. Figure 12 The connection between 513-2 in the diagram. The core test circuit 51 can, after the voltage monitoring operation begins, disconnect the TSV T45 of the second voltage path from the fourth core drive circuit (based on the scan enable signal SCE and the inverted scan enable signal SCEB). Figure 13 The connection between 514-2 in the middle.

[0101] Figure 10 This is a block diagram illustrating the construction of a core test circuit 51 according to an embodiment of the present disclosure. The core test circuit 51 may include a first path drive circuit (1... st PATH DRV)511, Second Path Drive Circuit (2 nd PATH DRV)512, Third Path Drive Circuit (3 rd PATH DRV)513 and fourth path drive circuit (4 thPATH DRV)514.

[0102] The first path driving circuit 511 can be electrically connected to the TSV T15 of the first signal path. The first path driving circuit 511 can drive the TSV T15 based on the downlink scan signal DNS and the uplink scan signal UPS. When the downlink scan signal DNS is enabled, the first path driving circuit 511 can drive the TSV T15 through the PMOS transistor (…). Figure 11 The first path drive circuit 511 (511-12) drives TSV T15. When the uplink scan signal UPS is enabled, the first path drive circuit 511 can drive the TSV T15 through the NMOS transistor (511-12). Figure 11 (511-13) drives TSV T15.

[0103] The second path drive circuit 512 can be electrically connected to the TSV T25 of the second signal path. The second path drive circuit 512 can drive the TSV T25 based on the downlink scan signal DNS and the uplink scan signal UPS. When the downlink scan signal DNS is enabled, the second path drive circuit 512 can drive the TSV T25 through a PMOS transistor (not shown). When the uplink scan signal UPS is enabled, the second path drive circuit 512 can drive the TSV T25 through an NMOS transistor (not shown).

[0104] The third path drive circuit 513 can be electrically connected to the TSV T35 of the first voltage path. The third path drive circuit 513 can drive the TSV T35 based on the downlink scan signal DNS and the uplink scan signal UPS. When the downlink scan signal DNS is enabled, the third path drive circuit 513 can drive the TSV T35 through the PMOS transistor (…). Figure 12 The third path drive circuit 513 (513-22) drives the TSV T35. When the uplink scan signal UPS is enabled, the third path drive circuit 513 can drive the TSV T35 through the NMOS transistor ( Figure 12 The 513-23 in the middle drives the TSV T35.

[0105] The third path drive circuit 513 can output the power supply voltage VDD through TSV T35 based on the scan enable signal SCE and the inverted scan enable signal SCEB. The third path drive circuit 513 can also disconnect the TSV T35 from the third core drive circuit based on the scan enable signal SCE and the inverted scan enable signal SCEB. Figure 12 The connection between 513-2 in the middle.

[0106] The fourth path drive circuit 514 can be electrically connected to the TSV T45 of the second voltage path. The fourth path drive circuit 514 can drive the TSV T45 based on the downlink scan signal DNS and the uplink scan signal UPS. When the downlink scan signal DNS is enabled, the fourth path drive circuit 514 can drive the TSV T45 through the PMOS transistor (…). Figure 13 The fourth path drive circuit 514 (514-22) drives the TSV T45. When the uplink scan signal UPS is enabled, the fourth path drive circuit 514 can drive the TSV T45 through the NMOS transistor ( Figure 13 The 514-23) drive TSV T45.

[0107] The fourth path drive circuit 514 can output a high voltage VPP through TSV T45 based on the scan enable signal SCE and the inverted scan enable signal SCEB. The fourth path drive circuit 514 can also disconnect TSV T45 from the fourth core drive circuit based on the scan enable signal SCE and the inverted scan enable signal SCEB. Figure 13 The connection between 514-2 in the middle.

[0108] Figure 11 This is a view illustrating the construction of a first path driving circuit 511 according to an embodiment of the present disclosure. The first path driving circuit 511 may include a first core driving circuit 511-1 and a third input and output circuit 511-2.

[0109] The first core driving circuit 511-1 may include an inverter 511-11, a PMOS transistor 511-12, and an NMOS transistor 511-13. The inverter 511-11 outputs the downlink scan signal DNS by inverting the downlink scan signal DNS. The PMOS transistor 511-12 is connected between the internal voltage Vint and node ND511, and when the output signal of the inverter 511-11 is at a logic low level, it can generate the first core data CD1 with a logic high level by driving node ND511 to the voltage level of the internal voltage Vint. The NMOS transistor 511-13 is connected between node ND511 and the ground voltage VSS, and when the uplink scan signal UPS is at a logic high level, it can generate the first core data CD1 with a logic low level by driving node ND511 to the voltage level of the ground voltage VSS. The PMOS transistor 511-12 of the first core driving circuit 511-1 may be configured to have a higher voltage level than the NMOS transistor of the first fault signal generation circuit 221. Figure 6(221-13) Greater driving force. Therefore, when no fault occurs in TSV T11, T12, T13, T14 and T15 of the first signal path, the first core drive circuit 511-1 can drive TSV T11, T12, T13, T14 and T15 to the voltage level of the internal voltage VINT.

[0110] The third input and output circuit 511-2 may include a transmitter (TX) 511-21 and a receiver (RX) 511-22. The transmitter 511-21 can be driven by receiving an internal voltage VINT. The transmitter 511-21 can output a third signal SIG3, which is to be output from the fourth core chip 130-4 to the base chip 120, to the TSV T15. The third signal SIG3 can be configured to include data stored therein.

[0111] Receiver 511-22 can be driven by receiving the internal voltage VINT. Receiver 511-22 can output the fourth signal SIG4 received from TSVT15 to the fourth core chip 130-4. The fourth signal SIG4 can be configured to include commands and data controlling the operation of the first core chip 130-1 to the fourth core chip 130-4.

[0112] The third input and output circuit 511-2 can output the signal to be output from the fourth core chip 130-4 to the base chip 120 through TSV T15. The third input and output circuit 511-2 can receive the signal to be output from the base chip 120 to the fourth core chip 130-4 through TSV T15, and can also output the signal to the fourth core chip 130-4.

[0113] Figure 10 The second path drive circuit 512 shown is electrically connected to and drives the TSV T25, and through... Figure 11 The same circuitry as the first path drive circuit 511 shown is implemented and performs the same operation as the first path drive circuit 511. Therefore, its detailed description is omitted.

[0114] Figure 12 This is a view illustrating the construction of a third path driving circuit 513 according to an embodiment of the present disclosure. The third path driving circuit 513 may include a third switching circuit 513-1 and a third core driving circuit 513-2.

[0115] The third switching circuit 513-1 may include transmission gates 513-11 and 513-12. Transmission gates 513-11 and 513-12 can be implemented using PMOS and NMOS transistors, which receive a high voltage VPP with a high voltage level through their gates without voltage drop. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverted scan enable signal SCEB is disabled to the ground voltage VSS level, transmission gate 513-11 can connect TSV T35 to the internal node ND513. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverted scan enable signal SCEB is enabled to the high voltage VPP level, transmission gate 513-11 can disconnect TSV T35 from the internal node ND513. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverted scan enable signal SCEB is enabled to the high voltage VPP level, the transmitter 513-12 can output the power supply voltage VDD through TSV T35. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverted scan enable signal SCEB is disabled to the ground voltage VSS level, the transmitter 513-12 may not output the power supply voltage VDD to TSV T35. When the scan enable signal SCE is enabled to the high voltage VPP level, the third switch circuit 513-1 can connect TSV T35 to the internal node ND513. When the inverted scan enable signal SCEB is enabled to the high voltage VPP level, the third switch circuit 513-1 can disconnect the connection between TSV T35 and the internal node ND513. When the inverting scan enable signal SCEB is enabled to a high voltage level VPP, the third switching circuit 513-1 can output the power supply voltage VDD through TSV T35.

[0116] The third core driver circuit 513-2 may include an inverter 513-21, a PMOS transistor 513-22, and an NMOS transistor 513-23. The inverter 513-21 outputs the downlink scan signal DNS by inverting the downlink scan signal DNS. The PMOS transistor 513-22 is connected between the internal voltage Vint and node ND513, and when the output signal of the inverter 513-21 is at a logic low level, it can generate the third core data CD3 with a logic high level by driving node ND513 to the voltage level of the internal voltage Vint. The NMOS transistor 513-23 is connected between node ND513 and the ground voltage VSS, and when the uplink scan signal UPS is at a logic high level, it can generate the third core data CD3 with a logic low level by driving node ND513 to the voltage level of the ground voltage VSS. The PMOS transistor 513-22 of the third core driver circuit 513-2 can be configured to have a higher voltage level than the third basic driver circuit (…). Figure 7 NMOS transistor (223-2) Figure 7 The third core drive circuit 513-2 can drive TSVs T31, T32, T33, T34, and T35 to the internal voltage level VINT when no fault occurs in TSVs T31, T32, T33, T34, and T35 in the first voltage path. The third core drive circuit 513-2 can generate the third core data CD3 based on the downlink scan signal DNS and the uplink scan signal UPS by driving the internal node ND513 connected to TSV T35 via either PMOS transistor 513-22 or NMOS transistor 513-23.

[0117] Figure 13 This is a view illustrating the construction of a fourth path drive circuit 514 according to an embodiment of the present disclosure. The fourth path drive circuit 514 may include a fourth switching circuit 514-1 and a fourth core drive circuit 514-2.

[0118] The fourth switching circuit 514-1 may include transmission gates 514-11 and 514-12. Transmission gates 514-11 and 514-12 can be implemented using PMOS and NMOS transistors, which receive a high voltage VPP with a high voltage level through their gates without voltage drop. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverted scan enable signal SCEB is disabled to the ground voltage VSS level, transmission gate 514-11 can connect TSV T45 to the internal node ND514. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverted scan enable signal SCEB is enabled to the high voltage VPP level, transmission gate 514-11 can disconnect the connection between TSV T45 and the internal node ND514. When the scan enable signal SCE is disabled to the ground voltage VSS level and the inverted scan enable signal SCEB is enabled to the high voltage VPP level, the transmitter 514-12 can output the high voltage VPP through TSV T45. When the scan enable signal SCE is enabled to the high voltage VPP level and the inverted scan enable signal SCEB is disabled to the ground voltage VSS level, the transmitter 514-12 may not output the high voltage VPP to TSV T45. When the scan enable signal SCE is enabled to the high voltage VPP level, the fourth switch circuit 514-1 can connect TSV T45 to the internal node ND514. When the inverted scan enable signal SCEB is enabled to the high voltage VPP level, the fourth switch circuit 514-1 can disconnect the connection between TSV T45 and the internal node ND514. When the inverting scan enable signal SCEB is enabled to a high voltage level VPP, the fourth switching circuit 514-1 can output a high voltage VPP through TSVT45.

[0119] The fourth core driver circuit 514-2 may include an inverter 514-21, a PMOS transistor 514-22, and an NMOS transistor 514-23. Inverter 514-21 outputs the downlink scan signal DNS by inverting the downlink scan signal DNS. PMOS transistor 514-22 is connected between the internal voltage VINT and node ND514, and when the output signal of inverter 514-21 is at a logic low level, it can generate the fourth core data CD4 with a logic high level by driving node ND514 to the voltage level of the internal voltage VINT. NMOS transistor 514-23 is connected between node ND514 and the ground voltage VSS, and when the uplink scan signal UPS is at a logic high level, it can generate the fourth core data CD4 with a logic low level by driving node ND514 to the voltage level of the ground voltage VSS. The PMOS transistor 514-22 of the fourth core driver circuit 514-2 can be configured to have a higher voltage level than the fourth basic driver circuit (…). Figure 8 NMOS transistor (224-2) Figure 8 The fourth core drive circuit 514-2 can drive TSVs T41, T42, T43, T44, and T45 to the internal voltage level VINT when no fault occurs in TSVs T41, T42, T43, T44, and T45 in the second voltage path. The fourth core drive circuit 514-2 can generate the fourth core data CD4 by driving the internal node ND514 of TSV T45 via one of the PMOS transistors 514-22 and NMOS transistors 514-23 based on the downlink scan signal DNS and the uplink scan signal UPS.

[0120] Figure 14 This is a block diagram illustrating the construction of a voltage monitoring circuit 24 according to an embodiment of the present disclosure. The voltage monitoring circuit 24 may include a selection transmission circuit (MUX) 241 and pads 242.

[0121] The selection transmission circuit 241 can be driven by receiving a high voltage VPP. The selection transmission circuit 241 can be implemented using a multiplexer that receives the high voltage VPP without voltage loss. The selection transmission circuit 241 can generate a monitoring voltage VM based on a selection signal SEL according to either a first transmission voltage TV1 or a second transmission voltage TV2. When the selection signal SEL is at a logic low level, the selection transmission circuit 241 can output the first transmission voltage TV1 as the monitoring voltage VM. When the selection signal SEL is at a logic high level, the selection transmission circuit 241 can output the second transmission voltage TV2 as the monitoring voltage VM. The selection signal SEL can be configured such that it is generated at a logic low level to monitor the power supply voltage VDD after the voltage monitoring operation begins. The selection signal SEL can also be configured such that it is generated at a logic high level to monitor the high voltage VPP after the voltage monitoring operation begins.

[0122] Pad 242 can receive the monitoring voltage VM. Pad 242 can output the received monitoring voltage VM to an external device, such as processor 19. Pad 242 can be configured as a normal pad.

[0123] The voltage monitoring circuit 24 can detect the voltage level of the monitoring voltage VM generated based on the power supply voltage VDD input through the first voltage path. The voltage monitoring circuit 24 can also detect the voltage level of the monitoring voltage VM generated based on the high voltage VPP input through the second voltage path.

[0124] Figure 15 This is a table describing the operation of detecting connection faults in voltage paths and monitoring voltage faults in storage devices according to embodiments of this disclosure. Reference Figure 15 The operation of detecting connection faults in the voltage path and then detecting faults in the monitored voltage is described as an example below.

[0125] First, the procedure for detecting a connection fault in the voltage path is described below.

[0126] After the TSV open-circuit and short-circuit test begins, when no fault occurs in the first and second voltage paths (NORMAL), the third fault detection signal FD is generated at a logic high level H because the first and second voltage paths are driven to the voltage level of the internal voltage VINT. <3> and the fourth fault detection signal FD <4> When the third fault detection signal FD is generated with logic high level H. <3> and the fourth fault detection signal FD <4> At that time, the base chip 120 can detect that no fault has occurred in the first voltage path and the second voltage path.

[0127] After the TSV open-circuit and short-circuit test begins, when a fault occurs in the first voltage path and the second voltage path (FAULT IN VOLTAGE PATH, a fault occurs in the voltage path), because the first voltage path and the second voltage path are not driven to the internal voltage VINT level, a third fault detection signal FD is generated at a logic low level L. <3> and the fourth fault detection signal FD <4> When the third fault detection signal FD is generated with logic low level L. <3> and the fourth fault detection signal FD <4> At that time, the base chip 120 can detect faults occurring in the first voltage path and the second voltage path.

[0128] The operation of detecting connection faults in the first signal path and the second signal path is the same as the operation of detecting connection faults in the first voltage path and the second voltage path, therefore its detailed description is omitted.

[0129] The procedure for detecting faults in the monitored voltage is described below as an example.

[0130] After the monitoring operation begins, when the power supply voltage VDD used in the first core chip 130-1 to the fourth core chip 130-4 is normal, the monitoring voltage VM generated from the first voltage path is generated at the voltage level of the power supply voltage VDD. When the monitoring voltage VM is generated at the voltage level of the power supply voltage VDD, the base chip 120 can detect that the power supply voltage VDD used in the first core chip 130-1 to the fourth core chip 130-4 is not faulty.

[0131] After the monitoring operation begins, when the high voltage VPP used in the first core chip 130-1 to the fourth core chip 130-4 is normal, the monitoring voltage VM generated from the second voltage path is generated at the voltage level of the high voltage VPP. When the monitoring voltage VM is generated at the voltage level of the high voltage VPP, the base chip 120 can detect that the high voltage VPP used in the first core chip 130-1 to the fourth core chip 130-4 is not faulty.

[0132] After the monitoring operation begins, when a fault occurs in the power supply voltage VDD used in the first core chip 130-1 to the fourth core chip 130-4 (DEFECTIN MORNITIORING VOLTAGE), the monitoring voltage VM generated from the first voltage path is generated at the voltage level of the internal voltage VINT. When the monitoring voltage VM is generated at the voltage level of the internal voltage VINT, the base chip 120 can detect the fault in the power supply voltage VDD used in the first core chip 130-1 to the fourth core chip 130-4.

[0133] After the monitoring operation begins, when a fault occurs in the high voltage VPP used in the first core chip 130-1 to the fourth core chip 130-4 (DEFECTIN MORNITIORING VOLTAGE), the monitoring voltage VM generated from the second voltage path is generated at the voltage level of the internal voltage VINT. When the monitoring voltage VM is generated at the voltage level of the internal voltage VINT, the base chip 120 can detect the fault in the high voltage VPP used in the first core chip 130-1 to the fourth core chip 130-4.

[0134] As described above, the storage device 17 according to embodiments of this disclosure can detect connection faults in the signal path and voltage path by detecting the logic levels of internal nodes connected to the signal path and voltage path. The storage device 17 can protect components contained in the drive circuit by disconnecting the voltage path outputting a high voltage from the drive circuit driving that voltage path after the TSV open-circuit / short-circuit test begins. The storage device 17 can detect voltage path connection faults and monitoring voltage faults by detecting voltage path connection faults after the TSV open-circuit / short-circuit test begins and by monitoring the voltage level of the monitoring voltage output to the voltage path after the voltage monitoring operation begins.

[0135] Embodiments of this disclosure have been described so far. Those skilled in the art will understand that the invention can be practiced in modified forms without departing from its essential characteristics. Accordingly, the disclosed embodiments should be considered from a descriptive rather than a limiting perspective. The scope of this disclosure is described as claimed, but not as stated in the foregoing description, and all differences within their equivalents should be construed as being included in this disclosure.

Claims

1. A storage device, comprising: Basic chips; as well as The core chip, which is stacked on top of the base chip and connected via a voltage path, Specifically, after the TSV open / short circuit test begins, the base chip and the core chip use internal voltage to drive the voltage path, and detect connection faults in the voltage path based on the logic level driven by the voltage path. Specifically, the base chip disconnects the voltage path from the base drive circuit after the voltage monitoring operation begins. The core chip disconnects the voltage path from the core drive circuit after the voltage monitoring operation begins. The base chip detects the voltage level of the monitoring voltage generated during the voltage monitoring operation and used in the core chip via the voltage path.

2. The storage device as claimed in claim 1, in, The base chip drives the voltage path after the TSV open-circuit / short-circuit test begins by connecting either the first PMOS transistor or the first NMOS transistor to the voltage path. The core chip drives the voltage path after the TSV open-circuit and short-circuit test begins by connecting either the second PMOS transistor or the second NMOS transistor to the voltage path.

3. The storage device as claimed in claim 1, wherein, The monitoring voltage is set to a voltage level that is higher than the internal voltage.

4. The storage device as claimed in claim 1, wherein, The base chip includes: The test control circuit generates a downlink scan signal, an uplink scan signal, a downlink latch signal, an uplink latch signal, a scan enable signal, and an inverted scan enable signal based on the downlink enable signal and the uplink enable signal used to perform the TSV open-circuit and short-circuit test. The basic test circuit controls the connection between the voltage path and the basic drive circuit based on the scan enable signal and the inverted scan enable signal, drives the voltage path based on the downlink scan signal and the uplink scan signal, generates a fault detection signal based on the logic level of the voltage path, and outputs the transmission voltage transmitted through the voltage path. A fault detection circuit, which detects connection faults in the voltage path based on the fault detection signal; and A voltage monitoring circuit that generates the monitoring voltage from the transmitted voltage and detects the voltage level of the monitoring voltage.

5. The storage device as claimed in claim 4, wherein, The test control circuit includes: A scan control circuit generates the downlink scan signal and the uplink scan signal when the downlink enable signal and the uplink enable signal are enabled, and generates the downlink latch signal and the uplink latch signal by delaying the downlink scan signal and the uplink scan signal; An enable signal generating circuit that receives the internal voltage and generates an enable signal driven by the internal voltage when either the downlink scan signal or the uplink scan signal is enabled; and A level conversion circuit receives a high voltage and generates a scan enable signal and an inverted scan enable signal with voltage levels of the high voltage by converting the logic level of the enable signal.

6. The storage device as claimed in claim 4, wherein, The basic test circuit includes: A fault signal generation circuit controls the connection between the voltage path and the basic drive circuit based on the scan enable signal and the inverted scan enable signal; drives the voltage path through the basic drive circuit based on the downlink scan signal and the uplink scan signal; generates a fault signal based on the logic level of a first internal node connected to the voltage path when generating the downlink latch signal and the uplink latch signal; and outputs the transmission voltage transmitted through the voltage path. A fault detection signal generation circuit generates a fault detection signal by latching the fault signal.

7. The storage device as claimed in claim 4, wherein, The voltage monitoring circuit includes: The selection transmission circuit generates the monitoring voltage from the transmission voltage based on a selection signal; and The pads receive the monitoring voltage and output the monitoring voltage to a device external to the storage device.

8. The storage device of claim 6, wherein, The fault signal generation circuit includes: A first switching circuit connects the voltage path to the first internal node when the scan enable signal is enabled, disconnects the connection between the voltage path and the first internal node when the inverted scan enable signal is enabled, and generates the transmission voltage from the voltage path when the inverted scan enable signal is enabled. The basic driving circuit drives the basic data by driving the first internal node via one of a first PMOS transistor and a first NMOS transistor based on the downlink scan signal and the uplink scan signal; and A storage circuit that latches the basic data based on the downlink latch signal and the uplink latch signal, and generates the fault signal from the latched basic data.

9. The storage device as claimed in claim 1, wherein, The core chip includes a path driving circuit, which controls the connection between the voltage path and the core driving circuit based on a scan enable signal and an inverted scan enable signal, drives the voltage path through the core driving circuit based on a downlink scan signal and an uplink scan signal, and outputs a high voltage through the voltage path.

10. The storage device of claim 9, wherein, The path driving circuit includes: A second switching circuit connects the voltage path and the second internal node when the scan enable signal is enabled, disconnects the connection between the voltage path and the second internal node when the inverted scan enable signal is enabled, and outputs the high voltage to the voltage path when the inverted scan enable signal is enabled; and The core driving circuit drives the core data by driving the second internal node via either a second PMOS transistor or a second NMOS transistor based on the downlink scan signal and the uplink scan signal.

11. A storage device comprising: Basic chips; as well as The core chip is stacked on top of the base chip and connected via a first voltage path and a second voltage path. The base chip and the core chip, after the TSV open / short circuit test begins, use internal voltage to drive the first voltage path and the second voltage path, and detect connection faults in the first voltage path and the second voltage path based on the logic levels driven by the first voltage path and the second voltage path. The base chip detects the voltage level of a monitoring voltage generated from either the power supply voltage received through the first voltage path or the high voltage received through the second voltage path after the voltage monitoring operation begins.

12. The storage device as claimed in claim 11, in, The power supply voltage is set to a voltage level that is higher than the internal voltage. Wherein, the high voltage is a voltage having a voltage level higher than the power supply voltage, and The power supply voltage and the high voltage are each set to the voltage used within the core chip.

13. The storage device of claim 11, wherein, The base chip includes: The test control circuit generates a downlink scan signal, an uplink scan signal, a downlink latch signal, an uplink latch signal, a scan enable signal, and an inverted scan enable signal from the downlink enable signal and the uplink enable signal used to perform the TSV open-circuit and short-circuit test. The basic test circuit drives the first voltage path and the second voltage path based on the scan enable signal and the inverted scan enable signal, generates a first fault detection signal and a second fault detection signal based on the logic level of the first voltage path and the logic level of the second voltage path, and outputs a first transmission voltage generated from the power supply voltage through the first voltage path and a second transmission voltage generated from the high voltage through the second voltage path. A fault detection circuit, which detects the connection fault in the first voltage path and the second voltage path based on a first fault detection signal and a second fault detection signal; and A voltage monitoring circuit generates the monitoring voltage from either the first transmitted voltage or the second transmitted voltage, and detects the voltage level of the monitoring voltage.

14. The storage device of claim 13, wherein, The test control circuit includes: A scan control circuit generates the downlink scan signal and the uplink scan signal when the downlink enable signal and the uplink enable signal are enabled, and generates the downlink latch signal and the uplink latch signal by delaying the downlink scan signal and the uplink scan signal; An enable signal generating circuit that receives the internal voltage and generates an enable signal driven by the internal voltage when either the downlink scan signal or the uplink scan signal is enabled; and A level conversion circuit receives the high voltage and generates a scan enable signal and an inverted scan enable signal with the voltage level of the high voltage by converting the logic level of the enable signal.

15. The storage device of claim 13, wherein, The basic test circuit includes: The first fault signal generating circuit controls the connection between the first voltage path and the first basic drive circuit based on the scan enable signal and the inverted scan enable signal, drives the first voltage path through the first basic drive circuit based on the downlink scan signal and the uplink scan signal, generates a first fault signal based on the logic level of the first voltage path, and outputs the first transmission voltage transmitted through the first voltage path. A second fault signal generation circuit controls the connection between the second voltage path and the second basic drive circuit based on the scan enable signal and the inverted scan enable signal, drives the second voltage path through the second basic drive circuit based on the downlink scan signal and the uplink scan signal, generates a second fault signal based on the logic level of the second voltage path, and outputs the second transmission voltage transmitted through the second voltage path; and A fault detection signal generation circuit generates the first fault detection signal and the second fault detection signal by latching the first fault signal and the second fault signal.

16. The storage device of claim 15, wherein, The first fault signal generating circuit includes: A first switching circuit connects the first voltage path and the first internal node when the scan enable signal is enabled, disconnects the connection between the first voltage path and the first internal node when the inverted scan enable signal is enabled, and generates the first transmission voltage from the first voltage path when the inverted scan enable signal is enabled. The first basic driving circuit drives the first basic data by driving the first internal node via one of a first PMOS transistor and a first NMOS transistor based on the downlink scan signal and the uplink scan signal; and A first storage circuit latches the first basic data based on the downlink latch signal and the uplink latch signal, and generates the first fault signal from the latched first basic data.

17. The storage device of claim 15, wherein, The second fault signal generation circuit includes: The second switching circuit connects the second voltage path and the second internal node when the scan enable signal is enabled, disconnects the connection between the second voltage path and the second internal node when the inverted scan enable signal is enabled, and generates the second transmission voltage from the second voltage path when the inverted scan enable signal is enabled. The second basic driving circuit drives the second basic data by driving the second internal node via one of a second PMOS transistor and a second NMOS transistor based on the downlink scan signal and the uplink scan signal; and The second storage circuit latches the second basic data based on the downlink latch signal and the uplink latch signal, and generates the second fault signal from the latched second basic data.

18. The storage device of claim 13, wherein, The voltage monitoring circuit includes: A selection transmission circuit is used to generate the monitoring voltage from either the first transmission voltage or the second transmission voltage based on a selection signal; and The pads receive the monitoring voltage and output the monitoring voltage to a device external to the storage device.

19. The storage device of claim 11, wherein, The core chip includes a core test circuit. The core test circuit controls the connection between the first voltage path and the first core driving circuit based on the scan enable signal and the inverted scan enable signal, controls the connection between the second voltage path and the second core driving circuit based on the scan enable signal and the inverted scan enable signal, drives the first voltage path and the second voltage path based on the downlink scan signal and the uplink scan signal, outputs the power supply voltage to the first voltage path, and outputs the high voltage to the second voltage path.

20. The storage device of claim 19, wherein, The core test circuit includes: A first path driving circuit drives the first voltage path based on the downlink scan signal and the uplink scan signal, and outputs the power supply voltage to the first voltage path; and The second path driving circuit drives the second voltage path based on the downlink scan signal and the uplink scan signal, and outputs the high voltage to the second voltage path.

21. The storage device of claim 20, wherein, The first path driving circuit includes: A third switching circuit connects the first voltage path and the third internal node when the scan enable signal is enabled, disconnects the connection between the first voltage path and the third internal node when the inverted scan enable signal is enabled, and outputs the power supply voltage through the first voltage path when the inverted scan enable signal is enabled; and The first core driving circuit drives the first core data by driving the third internal node via one of the third PMOS transistor and the third NMOS transistor based on the downlink scan signal and the uplink scan signal.

22. The storage device of claim 20, wherein, The second path driving circuit includes: A fourth switching circuit connects the second voltage path and the fourth internal node when the scan enable signal is enabled, disconnects the connection between the second voltage path and the fourth internal node when the inverted scan enable signal is enabled, and outputs the high voltage through the second voltage path when the inverted scan enable signal is enabled; and The second core driving circuit drives the second core data by driving the fourth internal node via one of the fourth PMOS transistor and the fourth NMOS transistor based on the downlink scan signal and the uplink scan signal.

23. A storage device comprising: Basic chips; as well as The core chip, which is stacked on top of the base chip and connected via signal and voltage paths, Specifically, the base chip and the core chip drive the signal path and the voltage path after the TSV open / short circuit test begins, and detect connection faults in the signal path and the voltage path based on the logic levels driven by the signal path and the voltage path. Specifically, the base chip disconnects the voltage path from the base drive circuit after the voltage monitoring operation begins. The core chip disconnects the voltage path from the core drive circuit after the voltage monitoring operation begins. The base chip detects the voltage level of the high voltage used in the core chip via the voltage path after the voltage monitoring operation begins.

24. An integrated circuit, comprising: A semiconductor device that, after the start of a TSV open / short circuit test, drives a first voltage path and a second voltage path using internal voltages, controls the connection between the first voltage path and the second voltage path and a first base drive circuit and a second base drive circuit, detects connection faults of the first voltage path and the second voltage path based on the logic levels driven by the first voltage path and the second voltage path, and, after the start of a voltage monitoring operation, detects the voltage level of a monitoring voltage generated from either a power supply voltage received through the first voltage path or a high voltage received through the second voltage path.

25. The integrated circuit as claimed in claim 24, in, The power supply voltage is set to a voltage level that is higher than the internal voltage. Wherein, the high voltage is a voltage with a voltage level higher than the power supply voltage. Wherein, the internal voltage is the voltage used within the semiconductor device, and The power supply voltage and the high voltage are set to voltages used outside the semiconductor device.

26. The integrated circuit of claim 24, wherein, The semiconductor device includes: The test control circuit generates a downlink scan signal, an uplink scan signal, a downlink latch signal, an uplink latch signal, a scan enable signal, and an inverted scan enable signal based on the downlink enable signal and the uplink enable signal used to perform the TSV open-circuit and short-circuit test. The basic test circuit drives the first voltage path and the second voltage path based on the scan enable signal and the inverted scan enable signal, generates a first fault detection signal and a second fault detection signal based on the logic level of the first voltage path and the logic level of the second voltage path, and outputs a first transmission voltage generated from the power supply voltage through the first voltage path and a second transmission voltage generated from the high voltage through the second voltage path. A fault detection circuit, which detects the connection fault in the first voltage path and the second voltage path based on a first fault detection signal and a second fault detection signal; and A voltage monitoring circuit generates the monitoring voltage from either the first transmitted voltage or the second transmitted voltage, and detects the voltage level of the monitoring voltage.

27. The integrated circuit of claim 26, wherein, The test control circuit includes: A scan control circuit generates the downlink scan signal and the uplink scan signal when the downlink enable signal and the uplink enable signal are enabled, and generates the downlink latch signal and the uplink latch signal by delaying the downlink scan signal and the uplink scan signal; An enable signal generating circuit that receives the internal voltage and generates an enable signal driven by the internal voltage when either the downlink scan signal or the uplink scan signal is enabled; and A level conversion circuit receives the high voltage and generates a scan enable signal and an inverted scan enable signal with the voltage level of the high voltage by converting the logic level of the enable signal.

28. The integrated circuit of claim 26, wherein, The basic test circuit includes: The first fault signal generating circuit controls the connection between the first voltage path and the first basic drive circuit based on the scan enable signal and the inverted scan enable signal, drives the first voltage path through the first basic drive circuit based on the downlink scan signal and the uplink scan signal, generates a first fault signal based on the logic level of the first voltage path, and outputs the first transmission voltage transmitted through the first voltage path. A second fault signal generation circuit controls the connection between the second voltage path and the second basic drive circuit based on the scan enable signal and the inverted scan enable signal, drives the second voltage path through the second basic drive circuit based on the downlink scan signal and the uplink scan signal, generates a second fault signal based on the logic level of the second voltage path, and outputs the second transmission voltage transmitted through the second voltage path; and A fault detection signal generation circuit generates the first fault detection signal and the second fault detection signal by latching the first fault signal and the second fault signal.

29. The integrated circuit of claim 28, wherein, The first fault signal generating circuit includes: A first switching circuit connects the first voltage path and the first internal node when the scan enable signal is enabled, disconnects the connection between the first voltage path and the first internal node when the inverted scan enable signal is enabled, and generates the first transmission voltage from the first voltage path when the inverted scan enable signal is enabled. The first basic driving circuit drives the first basic data by driving the first internal node via one of a first PMOS transistor and a first NMOS transistor based on the downlink scan signal and the uplink scan signal; and A first storage circuit latches the first basic data based on the downlink latch signal and the uplink latch signal, and generates the first fault signal from the latched first basic data.

30. The integrated circuit of claim 28, wherein, The second fault signal generation circuit includes: The second switching circuit connects the second voltage path and the second internal node when the scan enable signal is enabled, disconnects the connection between the second voltage path and the second internal node when the inverted scan enable signal is enabled, and generates the second transmission voltage from the second voltage path when the inverted scan enable signal is enabled. The second basic driving circuit drives the second basic data by driving the second internal node via one of a second PMOS transistor and a second NMOS transistor based on the downlink scan signal and the uplink scan signal; and The second storage circuit latches the second basic data based on the downlink latch signal and the uplink latch signal, and generates the second fault signal from the latched second basic data.

31. The integrated circuit of claim 26, wherein, The voltage monitoring circuit includes: A selection transmission circuit is used to generate the monitoring voltage from either the first transmission voltage or the second transmission voltage based on a selection signal; and The pad receives the monitoring voltage and outputs the monitoring voltage to a device external to the semiconductor device.

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