A test circuit

Abstract

The present disclosure provides a test circuit. The test circuit comprises m transmission circuits and a controller. The m transmission circuits are connected in series and configured to sequentially shift n-bit initial test data in series; wherein one transmission circuit stores at least one corresponding bit of initial test data; m and n are both greater than 1. The controller is connected with the m transmission circuits respectively and configured to generate control signals and output corresponding control signals to the m transmission circuits to control the output of the initial test data stored in the m transmission circuits; wherein the initial test data is used to test the read / write function in built-in self-test. The present disclosure can flexibly configure multiple groups of independent test data by independently storing initial test data in each transmission circuit, effectively improving the richness and diversity of topology test data; and the controller can issue global synchronous control signals under a unified timing reference to control the data output of each transmission circuit.

Description

Technical Field

[0001] This disclosure relates to the field of test circuit design, and more particularly to a test circuit. Background Technology

[0002] With the continuous improvement of memory chip performance, Memory Built-in Self-Test (MBIST) has become the mainstream self-test technology for memory chips. Existing architectures mostly adopt a centralized topology test data generation scheme, in which test data is uniformly generated by the internal data module of MBIST and then distributed to each data transmission channel. In order to match the rate difference between the internal low-frequency logic and the external high-speed input / output (I / O) interface, the existing architecture adopts a 1 / 4 rate division strategy, that is, each transmission circuit requires 4 parallel internal data lines, and the internal low-speed parallel data is converted into high-speed serial data output through a 4:1 parallel-to-serial converter located near the transmission channel.

[0003] However, the centralized generation of test data leads to a shortage of wiring and logic resources in the central area of ​​the chip, which restricts the scale of the test data generation logic. This results in a lack of diversity in the generated test data, making it difficult to meet the needs of test scenarios that require multiple sets of independent test data, such as error correction code (ECC) verification and device current (IDD) testing. Summary of the Invention

[0004] This disclosure provides a test circuit that can flexibly configure multiple sets of independent test data by independently storing initial test data in each transmission circuit, effectively improving the richness and diversity of topology test data; and controls the data output of each transmission circuit by issuing a global synchronization control signal with a unified timing reference through a controller.

[0005] The technical solution of this disclosure embodiment is implemented as follows: This disclosure provides a test circuit comprising: m transmission circuits and a controller; the m transmission circuits are connected in series and configured to sequentially shift and register n bits of initial test data; wherein each transmission circuit registers at least one bit of the initial test data; m and n are both greater than 1; the controller is connected to each of the m transmission circuits and configured to generate control signals and output corresponding control signals to each of the m transmission circuits to control the output of the initial test data registered in the m transmission circuits; wherein the initial test data is used to test the read / write function in the built-in self-test.

[0006] In some embodiments of this disclosure, the m transmission circuits are arranged as i columns of transmission circuits; wherein, a column of transmission circuits includes j transmission circuits arranged at intervals along a first direction and connected in series; i and j are both less than m and greater than 1; the i columns of transmission circuits are arranged at intervals along a second direction; wherein, the first direction and the second direction are perpendicular.

[0007] In some embodiments of this disclosure, the controller and the transmission circuit are connected via transmission signal lines; the transmission signal lines are configured to transmit the control signal to the transmission circuit; at least a portion of the transmission signal lines have a bypass portion that increases the wiring length; and the difference in wiring length between any two transmission signal lines is less than a preset threshold.

[0008] In some embodiments of this disclosure, the test circuit further includes: a plurality of transmission circuit groups; wherein, the transmission circuit group includes: at least two of the transmission circuits in two adjacent columns of the transmission circuits; the transmission signal line includes: a common signal line group and at least two independent signal lines; the input end of the common signal line group is connected to the output end of the controller, and the output end of the common signal line group is connected to one end of the independent signal line; wherein, the output end of the common signal line group is located at the center of the transmission circuit group; the other end of the independent signal line is connected to the transmission circuit.

[0009] In some embodiments of this disclosure, adjacent columns of transmission circuits are staggered along the first direction.

[0010] In some embodiments of this disclosure, at least one of the m transmission circuits serves as a redundant circuit for replacing a faulty transmission circuit; the redundant circuit is located between two of the transmission circuits and is connected to both of the transmission circuits respectively.

[0011] In some embodiments of this disclosure, the transmission circuit includes: a register circuit and a selection circuit; the register circuit is configured to sequentially shift and register multiple bits of the initial test data in serial order; the input terminal of the selection circuit is connected to the output terminal of the register circuit; wherein, the selection circuit is configured to select multiple bits from the initial test data registered in the register circuit and output parallel first test data.

[0012] In some embodiments of this disclosure, the register circuit includes: a plurality of registers connected in series; wherein the clock input terminals of the plurality of registers are connected to the same clock signal; and the output terminals of the plurality of registers are connected one-to-one with the input ports of the selection circuit.

[0013] In some embodiments of this disclosure, the selection circuit includes: four multiplexers; the four multiplexers are configured to synchronously output four-bit parallel first test data according to the control signal.

[0014] In some embodiments of this disclosure, the transmission circuit further includes: a first conversion circuit; the input of the first conversion circuit is connected to the output of the selection circuit; the first conversion circuit is configured to convert the parallel first test data into serial second test data, such that the data transmission rate inside the transmission circuit matches the transmission rate of the output interface.

[0015] In some embodiments of this disclosure, the test circuit further includes: a second conversion circuit; the input of the second conversion circuit is connected to the output of the first conversion circuit, and the output of the second conversion circuit is connected to the input of the storage array; the second conversion circuit is configured to convert the serial second test data into parallel third test data, such that the output third test data matches the parallel access mode of the storage array.

[0016] In some embodiments of this disclosure, the transmission circuit further includes: an XOR gate; the first input of the XOR gate is connected to the output of the selection circuit to receive the first test data; the second input of the XOR gate is connected to a read buffer to receive read data; wherein the read buffer is used to buffer the read data read by the storage array; the output of the XOR gate indicates whether the first test data written to the storage array and the read data are consistent.

[0017] The embodiments disclosed herein have the following beneficial effects: By storing multiple independent initial test data in each transmission circuit, this disclosure allows for flexible configuration of multiple sets of independent test data, effectively improving the richness and diversity of topology test data; and by issuing global synchronization control signals with a unified timing reference through a controller, it controls the data output of each transmission circuit to ensure the coordination and consistency of the overall test timing. Under the same chip layout area, high-bandwidth memory can achieve completely independent output of multiple sets of test data, accurately adapting to the high-speed test vector usage requirements of various functional modules of the memory, meeting the needs of full-scenario automated testing of the chip, and stably supporting stringent dynamic current test items such as IDD7 (interleaved read current of the entire memory bank), fully adapting to the mass production testing and reliability verification requirements of high-end high-bandwidth memory. Furthermore, it accurately meets the verification requirements of various error combination injections of ECC logic, effectively improving overall test coverage and fault detection accuracy. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the centralized test data distribution architecture in some embodiments; Figure 2 This is a schematic diagram showing the connection between the controller and various transmission circuits in the test circuit provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of the structure of multiple transmission circuits configured in series in the test circuit provided in the embodiments of this disclosure; Figure 4 This is a schematic diagram of the register circuit in the test circuit provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the structure for generating pointer signals in the test circuit provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the transmission structure of the multiplexer in the test circuit provided in the embodiments of this disclosure; Figure 7 A waveform diagram showing the conversion of initial test data into serial data in the test circuit provided in the embodiments of this disclosure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this disclosure. The following embodiments are used to illustrate the embodiments of this disclosure, but are not intended to limit the scope of the embodiments of this disclosure.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] In the following description, the terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0022] In this document, when a layer / component is referred to as being "above" another layer / component, the layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Furthermore, in one orientation, a layer / component is "above" another layer / component; when the orientation is reversed, the layer / component may be "below" the other layer / component.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this disclosure belong. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0024] In some embodiments, Figure 1 This is a schematic diagram of the centralized test data distribution architecture for the control module, referencing... Figure 1 As shown, the Built-in Self-Test (MBIST) scheme in high-speed memory employs a centralized topology data generation architecture. Test data is uniformly generated by the control module and distributed to each data transmission channel via a global bus. Specifically, the control module internally contains four byte data generation modules (MDB0, MDB1, MDB2, and MDB3), each connected to eight transmission circuits (e.g., DQ0-DQ7). To match the internal low-frequency and external high-speed interfaces, a 1 / 4 rate division is used. Each transmission circuit is configured with four parallel internal lines, and the output is after a 4:1 parallel-to-serial conversion near the transmission circuit. When the test length is 8, test data 0-3 and test data 4-7 are transmitted in two cycles. Under this architecture, the eight test data streams are generated from the same source, differing only in transmission timing. The data are highly correlated but lack independence, making it difficult to meet the needs of test scenarios requiring multiple sets of independent test data, such as error correction code (ECC) verification and device current (IDD) testing. Furthermore, the large differences in transmission timing between near and far end transmission channels make it difficult to converge timing in the back-end design, which is not conducive to the design and mass production application of high-speed memory chips.

[0025] Based on this, the present disclosure provides a test circuit. Figure 2 This is a schematic diagram of the controller connected to each transmission circuit (DQ0-DQ31) via transmission signal line 20. Figure 3 This is a schematic diagram of a serially configured structure for m transmission circuits. For example, m is 32, meaning there are a total of 32 transmission circuits (DQ0-DQ31). (Refer to...) Figure 2 and Figure 3As shown, the test circuit includes m transmission circuits (DQ0-DQ31) and a controller 10. The m transmission circuits (DQ0-DQ31), connected end-to-end in series, are configured to sequentially shift and register n bits of initial test data; each transmission circuit registers at least one bit of the corresponding initial test data; both m and n are greater than 1. The controller 10, connected to each of the m transmission circuits (DQ0-DQ31), is configured to generate control signals and output corresponding control signals to each of the m transmission circuits (DQ0-DQ31) to control the output of the initial test data registered in the m transmission circuits (DQ0-DQ31); the initial test data is used to test the read / write function in the built-in self-test.

[0026] It should be noted that, referring to Figure 2 and Figure 3 As shown, the initial test data pre-stored in m transmission circuits (DQ0-DQ31) is serially configured using the IEEE 1500 embedded kernel test standard. This standard is equipped with a unified serial test access interface and a standard scan path, enabling batch distribution and data writing to each transmission circuit (DQ0-DQ31) in serial transmission form. The configuration process is well-organized and uniform, possessing excellent universal adaptability and efficiently completing the pre-configuration of multi-channel test data. By connecting all transmission circuits (DQ0-DQ31) sequentially end-to-end according to their location, the serial configuration of multiple transmission circuits (DQ0-DQ31) is achieved, thereby significantly reducing the configuration time of the initial test data.

[0027] Understandably, referring to Figure 2 and Figure 3 As shown, by storing multiple independent initial test data in each transmission circuit (DQ0-DQ31), multiple sets of independent test data can be flexibly configured, effectively improving the richness and diversity of topology test data. Furthermore, the controller 10 issues global synchronization control signals based on a unified timing reference to control the data output of each transmission circuit (DQ0-DQ31), ensuring the coordination and consistency of the overall test timing. Under the same chip layout area, high-bandwidth memory can achieve completely independent output of multiple sets of test data, accurately adapting to the high-speed test vector requirements of various functional modules of the memory, meeting the needs of automated testing across all chip scenarios, and stably supporting stringent dynamic current tests such as IDD7 (interleaved read current across the entire memory bank), fully adapting to the mass production testing and reliability verification requirements of high-end, high-bandwidth memory. Simultaneously, it accurately meets the verification requirements for various error combination injections of ECC logic, effectively improving overall test coverage and fault detection accuracy.

[0028] In some embodiments of this disclosure, reference is made to Figure 2 and Figure 3As shown, m transmission circuits (DQ0-DQ31) are arranged in i columns; wherein, each column of transmission circuits includes j transmission circuits arranged at intervals along the first direction X and connected in series; i and j are both less than m and greater than 1; the i columns of transmission circuits are arranged at intervals along the second direction Y; wherein, the first direction X and the second direction Y are perpendicular.

[0029] It should be noted that, referring to Figure 2 and Figure 3 As shown, j transmission circuits in one column are arranged at intervals along the first direction X, and i transmission circuits are arranged at intervals along the second direction Y. This increases the layout spacing between adjacent transmission circuits (such as DQ0, DQ1), reserving sufficient wiring channels and layout space, avoiding wiring congestion and interference caused by dense component placement, and facilitating flexible signal line routing.

[0030] In some embodiments of this disclosure, reference is made to Figure 2 As shown, the controller 10 and the transmission circuit (DQ0-DQ31) are connected by a transmission signal line 20; the transmission signal line 20 is configured to transmit control signals to the transmission circuit (DQ0-DQ31); at least a portion of the transmission signal line 20 has a bypass portion that increases the wiring length; the difference in wiring length between any two transmission signal lines 20 is less than a preset threshold.

[0031] It should be noted that, referring to Figure 2 As shown, the controller 10 and the transmission circuits (DQ0-DQ31) are connected via transmission signal lines 20, and the difference in wiring length between any two transmission signal lines 20 is less than a preset threshold. In other words, all transmission signal lines 20 are designed with equal-length wiring, ensuring that the wiring length remains essentially consistent. This fundamentally eliminates the path deviation in signal transmission time between different transmission circuit (DQ0-DQ31) channels, allowing the global control signal and sampling clock to arrive at all transmission circuits (DQ0-DQ31) simultaneously, significantly reducing the difficulty of timing convergence. Simultaneously, the control signal is universal across the transmission circuit (DQ0-DQ31) channels and can be uniformly distributed through a tree-like wiring structure, synchronously delivered to each transmission circuit (DQ0-DQ31) via the tree network, providing a precise and unified time reference for the independent configuration and generation of test data for each channel. Through the coordinated use of equal-length wiring and tree-like distribution, both global timing consistency and the independence of data generation for each channel are ensured, resulting in efficient and reliable timing convergence. Furthermore, when the temperature rises or the voltage drops, the delay of all transmission circuit (DQ0-DQ31) channels increases or decreases synchronously, thereby avoiding timing collapse under extreme operating conditions caused by process-voltage-temperature (PVT) fluctuations and improving yield stability during mass production.

[0032] In some embodiments of this disclosure, reference is made to Figure 2 As shown, the test circuit also includes: multiple transmission circuit groups; wherein, the transmission circuit group includes: at least two transmission circuits (such as DQ0, DQ1) in two adjacent transmission circuit columns; the transmission signal line 20 includes: a common signal line group 21 and at least two independent signal lines 22; the input end of the common signal line group 21 is connected to the output end of the controller 10, and the output end of the common signal line group 21 is connected to one end of the independent signal line 22; wherein, the output end of the common signal line group 21 is located at the center of the transmission circuit group; the other end of the independent signal line 22 is connected to the transmission circuit (such as DQ0).

[0033] It should be noted that, referring to Figure 2 As shown, the transmission signal line 20 is divided into a common signal line group 21 and at least two independent signal lines 22. The input terminal of the common signal line group 21 is connected to the output terminal of the controller 10, and the two ends of the independent signal lines 22 are connected to the output terminal of the common signal line group 21 and the input terminal of the transmission circuit (such as DQ0), respectively. In this way, at least two transmission circuits (such as DQ0 and DQ1) can share the same common signal line group 21 to receive control signals. There is no need to lay out dedicated control lines for each transmission circuit (DQ0-DQ31), which effectively reduces the overall number of signal lines in the transmission circuit group, significantly reduces the layout area and wiring channel resources occupied by metal traces, simplifies the internal wiring architecture, alleviates the wiring congestion problem under high-density layout, and improves the chip layout space utilization. In addition, the output of the common signal line group is located at the center of the transmission circuit group, which further shortens the overall wiring length and unifies the routing distance of each branch. This not only reduces the consumption of wiring materials and wiring costs, but also reduces the signal transmission delay deviation. While simplifying wiring resources, it makes the transmission delay of each control signal more consistent, which is more conducive to the rapid convergence of the overall circuit timing.

[0034] It should also be noted that, Figure 2 and Figure 3The document also illustrates several standard control and data signals known in the art. These are non-essential technical features in this embodiment and include, but are not limited to, data parity check signals (DPAR0), write data strobe differential pairs (WDQS0_t / WDQS0_c), read data strobe differential pairs (RDQS0_t / RDQS0_c), data error indication signals (DERR0), scan enable signals (SEV0 / SEV1), and data bus inversion signals (DBI3). The timing and functions of these signals are well-known to those skilled in the art and will not be elaborated upon here. The standard control and data signals are only located in their corresponding positions and are not connected to the multiple serially connected transmission circuits (DQ0-DQ31). These standard control and data signals are physically independent of the multiple serially connected transmission circuits (DQ0-DQ31), and there is no direct electrical connection between them. The standard signals are only deployed in their corresponding functional areas or interface locations, and their function is to provide auxiliary control or data verification functions for the chip, without participating in the test data path of the transmission circuits. Figure 2 and Figure 3 The relative positions of the standard control signals and data signals, and the multiple transmission circuits (DQ0-DQ31) shown are for illustrative purposes only and do not constitute any limitation on their physical connection. When multiple transmission circuits (DQ0-DQ31) are arranged in the serial direction, if there are already standard control signals and data signals (such as DPAR0, WDQS0_t / c, RDQS0_t / c, DERR0, SEV0 / SEV1, DBI3, etc.) on their routing paths, the transmission circuits can be routed around these standard signals to avoid the wiring area occupied by them, thereby maintaining the physical continuity of the serial connection link.

[0035] Furthermore, the physical arrangement of the two adjacent columns of transmission circuits in the chip layout adopts a staggered and interleaved layout (see details). Figure 1 This is to reduce crosstalk between adjacent signal lines. It needs to be clarified that... Figure 2 The signal arrangement and positional relationships shown are only schematic representations and do not strictly reflect the physical spacing, line width, and relative orientation in the actual layout. Their purpose is to clearly show the connection relationship between the circuits in this embodiment, rather than limiting the actual physical layout.

[0036] In some embodiments of this disclosure, reference is made to Figure 2 As shown, adjacent columns of transmission circuits are staggered along the first direction X. This increases the physical spacing between adjacent leads, effectively avoiding the risk of short circuits.

[0037] In some embodiments of this disclosure, reference is made to Figure 2 and Figure 3As shown, at least one of the m transmission circuits is used as a redundant circuit (such as RD0) to replace the faulty transmission circuit; the redundant circuit (such as RD0) is located between two transmission circuits (such as DQ3, DQ5) and is connected to the two transmission circuits (such as DQ3, DQ5) respectively.

[0038] It should be noted that, referring to Figure 2 and Figure 3 As shown, redundant circuits (such as RD0) are arranged between two adjacent transmission circuits (such as DQ3 and DQ5) and electrically connected to each of them. This allows for rapid replacement of the faulty transmission circuit in the event of a malfunction, line fault, or test failure in any of the transmission circuits, enabling the transmission of test data and self-test functions to be completed. Furthermore, path replacement can be achieved without significant modifications to the overall cabling architecture, effectively ensuring the continuity and stability of the MBIST system and preventing interruptions to the overall testing process due to a single transmission circuit failure.

[0039] In some embodiments of this disclosure, reference is made to Figures 4 to 6 As shown, the transmission circuit (DQ0-DQ31) includes: a register circuit and a selection circuit; the register circuit is configured to sequentially shift and register multiple bits of serial initial test data; the input of the selection circuit is connected to the output of the register circuit; wherein, the selection circuit is configured to select multiple bits from the initial test data registered in the register circuit and output the first test data in parallel.

[0040] It should be noted that, referring to Figures 4 to 6 As shown, the register circuit is used to receive multiple bits of initial test data from the serial input, and sequentially shifts and registers the serial data bit by bit according to timing logic to achieve temporary storage of the serial test data. The input terminal of the selection circuit is connected to the data output terminal of the register circuit. According to the actual test configuration requirements, it can select a specified number of bits of data signal from the multiple sets of initial test data that have been buffered inside the register circuit for integration and output. Finally, the selected data is converted into parallel first test data and sent out.

[0041] In some embodiments of this disclosure, reference is made to Figure 4 As shown, the register circuit includes: multiple registers FF1 connected in series; wherein the clock input terminals of the multiple registers FF1 are connected to the same clock signal; and the output terminals of the multiple registers FF1 are connected one by one to the input ports of the selection circuit.

[0042] It should be noted that, referring to Figure 4 As shown, the register circuit consists of multiple registers FF1 connected in series. All registers FF1 share the same clock signal to achieve synchronous timing control. The output of each register FF1 is connected to the respective input port of the selection circuit.

[0043] Reference Figure 3 and Figure 4 As shown, multiple transmission circuits are configured serially, and each transmission circuit has multiple registers FF1, which are used to pre-store initial test data. Configuration is written serially starting from the transmission circuit (DQ1) via the IEEE 1500 embedded core test standard interface. This configuration method shifts the generation of initial test data to outside the chip, avoiding the occupation of internal chip space and generating diverse test data through external logic.

[0044] In some embodiments of this disclosure, reference is made to Figure 6 As shown, the selection circuit includes: four multiplexers (MUX0-MUX3); the four multiplexers (MUX0-MUX3) are configured to synchronously output four-bit parallel first test data according to the control signal.

[0045] It should be noted that, referring to Figure 6 As shown, the controller 10 can generate two phase pointer signals, 0° and 180°, which are synchronously transmitted to each transmission circuit (DQ0-DQ31) through a tree-like wiring structure. The transmission circuits (DQ0-DQ31) rely on multiplexers (MUX0-MUX3) to receive the phase pointer signals, accurately selecting and outputting different types of test data. Taking a scenario with sixteen sets of test data output as an example, configuring four four-input multiplexers (MUX0-MUX3) is sufficient to complete the data sorting and output. The test data filtered by the multiplexers (MUX0-MUX3) is then sent to the first conversion circuit P2S at the back end for parallel-to-serial conversion.

[0046] In some embodiments of this disclosure, reference is made to Figure 6 As shown, the transmission circuit (DQ0-DQ31) further includes: an XOR gate (XOR0-XOR3); the first input of the XOR gate (XOR0-XOR3) is connected to the output of the selection circuit to receive the first test data; the second input of the XOR gate (XOR0-XOR3) is connected to the read buffer FIFO to receive the read data; wherein, the read buffer FIFO is used to buffer the read data read from the memory array; the output result of the XOR gate (XOR0-XOR3) indicates whether the first test data written to the memory array and the read data are consistent.

[0047] It should be noted that, referring to Figure 6As shown, the first input of the XOR gate (XOR0-XOR3) is connected to the first test data output by the selection circuit, and the second input is connected to the read buffer FIFO to obtain the read data read from and buffered by the storage array. The read buffer FIFO is used to temporarily store the data read back from the storage array. By using the XOR gate (XOR0-XOR3) to logically compare the written data and the read data, the output level of the XOR gate (XOR0-XOR3) can be used to intuitively determine whether the test data written to the storage array is consistent with the actual read data, quickly completing the data read and write verification and efficiently detecting whether the read and write functions of the storage array are normal.

[0048] It should also be noted that, referring to Figure 5 As shown, Figure 5 A circuit diagram for generating the pointer signal is shown. Specifically, the circuit includes two sets of circular shift register chains, whose clock outputs correspond to the phase pointer signal (dwdqs_ptr). <0> dwdqs_ptr <2> The phase pointer signal is used to provide phase selection for the common clock path, ensuring that the two register chains complete synchronous triggering and state latching within the optimal data window. Each cyclic shift register chain is formed by four registers FF2 connected in series, with the data input of the first register FF2 connected to the data output of the fourth register FF2 to implement the cyclic shift function. After cyclic shifting and mapping by internal decoding logic, the four registers FF2 generate a two-bit control pointer signal (S01<1:0> or S23<1:0>). Figure 5 The control pointer signals (S01<1:0>, S23<1:0>) output in the middle are used as Figure 6 The control signals of the multiplexers (MUX0-MUX3) are used to control multiple registers FF1 to select the specified test data to the input ports of the multiplexers (MUX0-MUX3).

[0049] Reference Figure 6 As shown, Figure 6Four multiplexers (MUX0-MUX3) are shown. The outputs of the four multiplexers (MUX0-MUX3) are connected to the inputs of the first conversion circuit P2S (i.e., the parallel-to-serial circuit). Furthermore, the outputs of the four multiplexers (MUX0-MUX3) are also connected to the inputs of the XOR gates (XOR0-XOR3), and the inputs of the XOR gates (XOR0-XOR3) are also connected to the read buffer FIFO. After receiving the test data from the register circuit, the four multiplexers (MUX0-MUX3) input 4 bits of parallel test data to the first conversion circuit P2S. The XOR gates (XOR0-XOR3) are used to compare the actual read data of the read buffer FIFO with the expected read data (i.e., the input test data) to determine whether the read and write functions of the memory array are normal. The read operation of the read buffer FIFO and the input operation of the multiplexers (MUX0-MUX3) are controlled and synchronized by the same read clock signal to ensure that the actual read data output by the read buffer FIFO and the expected read data output by the multiplexers (MUX0-MUX3) are in a one-to-one correspondence in timing.

[0050] Table 1. Correspondence between Multiplexer Output Signals and Control Pointer Signals

[0051] For example, in combination Figures 4 to 6 As shown, n can be 4, meaning the register circuit has a total of 16 registers FF1, and the inputs of the four multiplexers (MUX0-MUX3) are connected to the outputs of the 16 registers FF1 respectively; where, <0> , <1> , <2> ... <e> 、 <f>These correspond to the signals output from registers FF1, respectively. S01<1:0> is used to select the input ports of the first multiplexer (MUX0) and the second multiplexer (MUX1), and S23<1:0> is used to select the input ports of the third multiplexer (MUX2) and the fourth multiplexer (MUX3). S01<1:0> and S23<1:0> include four control pointer codes: 00, 01, 10, and 11, respectively. The specific control relationships are shown in Table 1. For example, when S01<1:0>=00, the first multiplexer (MUX0) selects its first input terminal and outputs a signal. <0> The second multiplexer (MUX1) selects the first input and outputs a signal. <1> When S01<1:0>=01, the first multiplexer (MUX0) selects the second input and outputs a signal. <c>The second multiplexer (MUX1) selects the second input and outputs a signal. <d>It should be noted that, Figure 5 This description uses only two control pointer signals (S01<1:0>, S23<1:0>) as an example to select the input ports of four multiplexers (MUX0-MUX3), but this disclosure does not limit the number of control pointer signals. In other embodiments, four control pointer signals (e.g., S01<1:0>, S23<1:0>, S45<1:0>, S67<1:0>) can also be generated, with each control pointer signal corresponding to control the port selection of one multiplexer.

[0052] In some embodiments of this disclosure, Figure 7 The waveform generated for the second test data. (Refer to...) Figure 6 and Figure 7 As shown, the transmission circuit (DQ0-DQ31) further includes: a first conversion circuit P2S; the input of the first conversion circuit P2S is connected to the output of the selection circuit; the first conversion circuit P2S is configured to convert the parallel first test data into the serial second test data, so that the data transmission rate inside the transmission circuit (DQ0-DQ31) matches the transmission rate of the output interface.

[0053] It should be noted that, referring to Figure 6 and Figure 7 As shown, the transmission circuit (DQ0-DQ31) also includes a first conversion circuit P2S, whose input is connected to the output of the selection circuit. The first conversion circuit P2S converts the parallel-output first test data into serial second test data, achieving parallel-to-serial format conversion. This ensures precise matching between the internal data transmission rate and the external output interface transmission rate, guaranteeing stable and smooth transmission of test data.

[0054] It should also be noted that, Figure 7 This diagram illustrates the structure for converting initial test data into serial data. Multiple phase pointer signals (dwdqs_ptr) are shown. <0> dwdqs_ptr <2> The first converter circuit P2S provides a phase reference for the test clock to determine the phase reference for data sampling. Multiple control pointers (S01<1:0>, S023<1:0>) are coupled to the selection control terminals of the corresponding multiplexers (MUX0-MUX3) to select the connection path between the gating register FF1 and the corresponding input port. Multiple biphase first test data (datatopo04_2phase, datatopo15_2phase, datatopo26_2phase, datatopo37_2phase) are applied as parallel input signals to the parallel data input terminal of the first conversion circuit P2S. Under the control of multiple sampling clocks (PlsER, PlsEF, PlsOR, PlsOF), the first conversion circuit P2S converts the parallel input first test data into serial second test data and outputs it through a data bump (DQ_bump).

[0055] In some embodiments of this disclosure, reference is made to Figure 6 As shown, the test circuit also includes: a second conversion circuit S2P; the input terminal of the second conversion circuit S2P is connected to the output terminal of the first conversion circuit P2S, and the output terminal of the second conversion circuit S2P is connected to the input terminal of the memory array; the second conversion circuit S2P is configured to convert the serial second test data into parallel third test data, so that the output third test data matches the parallel access mode of the memory array.

[0056] It should be noted that, referring to Figure 6 As shown, the second conversion circuit S2P can convert the serial second test data back into parallel third test data, so that the output data format is compatible with the parallel access mode of the storage array and meets the timing and interface requirements of normal read and write tests of the storage array.

[0057] It should also be noted that, referring to Figure 6 As shown, the first test data is the parallel test data output by the selection circuit. It is then converted into serial second test data by the first conversion circuit P2S to complete rate adaptation, and finally restored to parallel third test data by the second conversion circuit S2P. The first and third test data have completely identical data content, undergoing only parallel-to-serial and serial-to-parallel format conversion and timing rate adjustment. The data itself is unmodified and without loss. The final output third test data is equivalent to the initial first test data and can directly adapt to the parallel access requirements of the storage array.

[0058] It should be understood that in the various embodiments of this disclosure, the sequence numbers of the processes described above do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the embodiments of this disclosure are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0059] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0060] The above are merely specific implementations of the embodiments of this disclosure, but the protection scope of the embodiments of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this disclosure should be included within the protection scope of the embodiments of this disclosure.< / d> < / c> < / f> < / e>

Claims

1. A test circuit, characterized in that, The test circuit includes: m transmission circuits and a controller; The m transmission circuits are connected in series, and are configured to sequentially shift and register n bits of initial test data; wherein each transmission circuit registers at least one bit of the initial test data; and both m and n are greater than 1. The controller is connected to each of the m transmission circuits and is configured to generate control signals and output corresponding control signals to each of the m transmission circuits to control the output of the initial test data stored in the m transmission circuits; wherein the initial test data is used to test the read / write function in the built-in self-test.

2. The test circuit according to claim 1, characterized in that, The m transmission circuits are arranged in i columns; wherein, each column of the transmission circuits includes j transmission circuits arranged at intervals along a first direction and connected in series; i and j are both less than m and greater than 1; The i-column transmission circuit columns are arranged at intervals along the second direction; wherein the first direction and the second direction are perpendicular.

3. The test circuit according to claim 2, characterized in that, The controller and the transmission circuit are connected via a transmission signal line; The transmission signal line is configured to transmit the control signal to the transmission circuit; At least a portion of the transmission signal line has a bypass portion that increases the wiring length; The difference in wiring length between any two of the transmission signal lines is less than a preset threshold.

4. The test circuit according to claim 3, characterized in that, The test circuit further includes: multiple transmission circuit groups; wherein, each transmission circuit group includes at least two transmission circuits in two adjacent columns of transmission circuits; The transmission signal lines include: a common signal line group and at least two independent signal lines; The input terminal of the common signal line group is connected to the output terminal of the controller, and the output terminal of the common signal line group is connected to one end of the independent signal line; wherein, the output terminal of the common signal line group is located at the center of the transmission circuit group; The other end of the independent signal line is connected to the transmission circuit.

5. The test circuit according to claim 2, characterized in that, The adjacent columns of transmission circuits are staggered along the first direction.

6. The test circuit according to claim 2, characterized in that, At least one of the m transmission circuits is used as a redundant circuit to replace the faulty transmission circuit. The redundant circuit is located between the two transmission circuits and is connected to both transmission circuits respectively.

7. The test circuit according to claim 1, characterized in that, The transmission circuit includes: a register circuit and a selection circuit; The register circuit is configured to sequentially shift and register multiple bits of the initial test data in serial order; The input terminal of the selection circuit is connected to the output terminal of the register circuit; wherein, the selection circuit is configured to select multiple bits from the initial test data stored in the register circuit and output parallel first test data.

8. The test circuit according to claim 7, characterized in that, The register circuit includes: multiple registers connected in series; wherein the clock input terminals of the multiple registers are connected to the same clock signal; The output terminals of the multiple registers are connected one-to-one with the input ports of the selection circuit.

9. The test circuit according to claim 7, characterized in that, The selection circuit includes: four multiplexers; The four multiplexers are configured to synchronously output four-bit parallel first test data according to the control signal.

10. The test circuit according to claim 7, characterized in that, The transmission circuit further includes: a first conversion circuit; The input terminal of the first conversion circuit is connected to the output terminal of the selection circuit; The first conversion circuit is configured to convert the parallel first test data into serial second test data, such that the data transmission rate inside the transmission circuit matches the transmission rate of the output interface.

11. The test circuit according to claim 10, characterized in that, The test circuit also includes: a second conversion circuit; The input terminal of the second conversion circuit is connected to the output terminal of the first conversion circuit, and the output terminal of the second conversion circuit is connected to the input terminal of the storage array; The second conversion circuit is configured to convert the serial second test data into parallel third test data, such that the output third test data matches the parallel access mode of the storage array.

12. The test circuit according to claim 11, characterized in that, The transmission circuit further includes: an XOR gate; The first input of the XOR gate is connected to the output of the selection circuit to receive the first test data; the second input of the XOR gate is connected to the read buffer to receive read data; wherein, the read buffer is used to buffer the read data read by the storage array; The output of the XOR gate indicates whether the first test data written to the storage array and the read data are consistent.

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