Non-volatile memory and programming method, reading method, and device thereof

Abstract

The present disclosure provides a non-volatile memory and a programming method, a reading method and a device thereof, and belongs to the technical field of non-volatile memories. The method comprises: in response to a programming instruction sent by a system end, performing error correction processing on to-be-programmed data in the programming instruction to obtain a first error correction code, performing parity check coding on the to-be-programmed data and the first error correction code to obtain first forward error correction information; programming the to-be-programmed data, the first error correction code and the first forward error correction information to a target data block; after programming is completed, reading data in the target data block; performing error correction processing on the read programmed data and the first error correction code to obtain corrected data and a second error correction code, performing parity check coding on the corrected data and the second error correction code to obtain a second forward error correction code; and determining a programming result according to the first forward error correction information and the read second forward error correction code and sending the programming result to the system end, thereby improving data reliability and system security.

Description

Technical Field

[0001] This disclosure relates to the field of data storage technology, and in particular to a memory bit line control method, a memory bit line control device, and a memory. Background Technology

[0002] Non-volatile memory has become an important way to preserve data because the stored data will not be lost when power is off.

[0003] In related technologies, non-volatile memory typically employs Error Correcting Code (ECC) to correct and detect errors in read data. When ECC corrects an error, it generates a corresponding error correction flag, which is then sent to the system to promptly notify the system that an error correction operation has been performed on the non-volatile memory. However, if ECC performs a false correction or fails to correct an error, the system may misjudge the situation as a safe state, leading to a security risk. Summary of the Invention

[0004] This disclosure provides a non-volatile memory and its programming method, reading method, and apparatus, which at least to some extent overcomes the problem in related technologies where non-volatile memory causes system misjudgment and poses security risks when ECC generates false corrections or fails to correct errors.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a method for programming a non-volatile memory is provided, comprising: responding to a programming instruction sent from a system terminal, performing error correction processing on data to be programmed in the programming instruction to obtain a first error correction code; performing parity check encoding on the data to be programmed and the first error correction code to obtain first forward error correction information, the first forward error correction information including at least one first forward error correction code; programming the data to be programmed, the first error correction code, and the first forward error correction information into a target data block, the target data block being a data block in the non-volatile memory corresponding to a target storage address in the programming instruction; responding to the end of programming, reading the programmed data, the first error correction code, and the first forward error correction information from the target data block; performing error correction processing on the programmed data and the first error correction code to obtain erroneously corrected data and a second error correction code; performing parity check encoding on the erroneously corrected data and the second error correction code to obtain a second forward error correction code; determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code; and sending the programming result of the data to be programmed to the system terminal.

[0007] In one embodiment of this disclosure, the step of performing parity-check encoding on the data to be programmed and the first error correction code to obtain first forward error correction information includes: performing an XOR operation on each bit of the data to be programmed and the first error correction code to obtain an XOR result; configuring the at least one bit of the first forward error correction code to be 1 in response to the XOR result being 1 and the parity check mode being even, or the XOR result being 0 and the parity check mode being odd; and configuring the at least one bit of the first forward error correction code to be 0 in response to the XOR result being 1 and the parity check mode being odd, or the XOR result being 0 and the parity check mode being even.

[0008] In one embodiment of this disclosure, programming the data to be programmed, the first error correction code, and the first forward error correction information into a target data block includes: programming the data to be programmed, the first error correction code, and the first forward error correction information into the target data block in a preset order, wherein the preset order includes any of the following: the order of the data to be programmed, the first error correction code, and the first forward error correction information; the order of the data to be programmed, the first forward error correction information, and the first error correction code; or a cross-mixing method of the data to be programmed, the first forward error correction information, and the first error correction code.

[0009] In one embodiment of this disclosure, the first forward error correction information includes a 1-bit first forward error correction code; wherein, determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code includes: determining that the programming result of the data to be programmed is successful if the values ​​of the first forward error correction code and the second forward error correction code are the same; and determining that the programming result of the data to be programmed is unsuccessful if the first forward error correction code and the second forward error correction code are different.

[0010] In one embodiment of this disclosure, the first forward error correction code includes two bits of a first forward error correction code; wherein, determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code includes: in response to the two bits of the first forward error correction code having the same value, and the first forward error correction code and the second forward error correction code having the same value, determining that the programming result of the data to be programmed is successful; in response to the two bits of the first forward error correction code having different values, or the two bits of the first forward error correction code having the same value and the first forward error correction code and the second forward error correction code having different values, determining that the programming result of the data to be programmed is unsuccessful.

[0011] In one embodiment of this disclosure, the first forward error correction code includes a 3-bit first forward error correction code; wherein, determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code includes: in response to the fact that the 3 bits of the first forward error correction code have the same value and the first forward error correction code and the second forward error correction code have the same value, or the 2 bits of the first forward error correction code in the first forward error correction information have the same value and the 2 bits of the first forward error correction code have the same value and the second forward error correction code has the same value, determining that the programming result of the data to be programmed is successful; in response to the fact that the 3 bits of the first forward error correction code have the same value and the first forward error correction code and the second forward error correction code have different values, or the 2 bits of the first forward error correction code in the first forward error correction information have the same value and the 2 bits of the first forward error correction code have the same value and the second forward error correction code has different values, determining that the programming result of the data to be programmed is unsuccessful.

[0012] In one embodiment of this disclosure, sending the programming result of the data to be programmed to the system includes: generating a first alarm flag bit in response to the programming result of the data to be programmed being a programming failure, wherein the first alarm flag bit indicates that the programming of the data to be programmed has failed; outputting the first alarm flag bit to the input / output pin of the non-volatile memory, or writing the first alarm flag bit to a functional safety register so that the system reads the first alarm flag bit.

[0013] According to another aspect of this disclosure, a method for reading non-volatile memory is provided, comprising: responding to a read instruction sent by a system terminal, reading data, error correction codes, and forward error correction information from a target data block to obtain corresponding data to be verified, a third error correction code, and second forward error correction information, wherein the target data block is a data block in the non-volatile memory corresponding to the target storage address of the read instruction, and the second forward error correction information includes at least one bit of a third forward error correction code; performing error correction processing on the data to be verified and the third error correction code to obtain erroneously corrected data and a fourth error correction code; performing parity check encoding on the erroneously corrected data and the fourth error correction code to obtain a fourth forward error correction code; determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code; and sending the reading result of the data to be verified to the system terminal.

[0014] In one embodiment of this disclosure, the second forward error correction information includes a 1-bit third forward error correction code; wherein, determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: determining that the reading result of the data to be verified is successful if the value of the third forward error correction code is the same as the value of the fourth forward error correction code; and determining that the reading result of the data to be verified is unsuccessful if the third forward error correction code and the fourth forward error correction code are different.

[0015] In one embodiment of this disclosure, the second forward error correction information includes a 2-bit third forward error correction code; wherein, determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: in response to the two bits of the third forward error correction code having the same value, and the third forward error correction code and the fourth forward error correction code having the same value, determining that the reading result of the data to be verified is a successful reading; in response to the two bits of the third forward error correction code having different values, or the two bits of the third forward error correction code having the same value and the third forward error correction code and the fourth forward error correction code having different values, determining that the reading result of the data to be verified is a failed reading.

[0016] In one embodiment of this disclosure, the second forward error correction information includes a 3-bit third forward error correction code; wherein, determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: in response to the three bits of the third forward error correction code having the same value, and the third forward error correction code having the same value as the fourth forward error correction code, determining that the reading result of the data to be verified is successful; in response to the three bits of the third forward error correction code having the same value, and the third forward error correction code having a different value than the fourth forward error correction code. If the reading result of the data to be verified is determined to be a reading failure, or if the values ​​of the two bits of the third forward error correction code in the second forward error correction information are the same, and the values ​​of the two bits of the third forward error correction code are the same as the values ​​of the fourth forward error correction code, the reading result of the data to be verified is determined to be a reading success; if the values ​​of the two bits of the third forward error correction code in the second forward error correction information are the same, and the values ​​of the two bits of the third forward error correction code are different from the values ​​of the fourth forward error correction code, the reading result of the data to be verified is determined to be a reading failure.

[0017] In one embodiment of this disclosure, sending the reading result of the data to be verified to the system includes: generating a second alarm flag bit in response to the reading result of the data to be verified being a reading failure, wherein the second alarm flag bit indicates that the data to be verified has been read without success; outputting the second alarm flag bit to the input / output pin of the non-volatile memory, or writing the second alarm flag bit to a functional safety register, so that the system reads the second alarm flag bit.

[0018] In one embodiment of this disclosure, after performing error correction processing on the data to be verified and the third error correction code to obtain the error-corrected data and the fourth error correction code, the method further includes: generating a single-bit error detection flag and a double-bit error detection flag; sending the single-bit error detection flag and the double-bit error detection flag to an input / output pin or writing them to a functional safety register so that the system reads the single-bit error detection flag and the double-bit error detection flag.

[0019] According to another aspect of this disclosure, a programming apparatus for a non-volatile memory is also provided, comprising: a first error correction module, configured to, in response to a programming instruction sent from a system, perform error correction processing on data to be programmed in the programming instruction to obtain a first error correction code, and perform parity check encoding on the data to be programmed and the first error correction code to obtain first forward error correction information, the first forward error correction information including at least one bit of the first forward error correction code; and a data programming module, configured to program the data to be programmed, the first error correction code, and the first forward error correction information into a target data block, the target data block being a data block in the non-volatile memory corresponding to the target data in the programming instruction. The system comprises: a data block corresponding to a specified storage address; a first reading module, configured to read the programmed data, the first error correction code, and the first forward error correction information from the target data block in response to the end of programming; a first error correction module, further configured to perform error correction processing on the programmed data and the first error correction code to obtain erroneously corrected data and a second error correction code, and to perform parity check encoding on the erroneously corrected data and the second error correction code to obtain a second forward error correction code; and a first determining module, configured to determine the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code, and to send the programming result of the data to be programmed to the system.

[0020] According to another aspect of this disclosure, a reading device for a non-volatile memory is also provided, comprising: a second reading module, configured to, in response to a read command sent by a system terminal, read data, an error correction code, and forward error correction information from a target data block to obtain corresponding data to be verified, a third error correction code, and second forward error correction information, wherein the target data block is a data block in the non-volatile memory corresponding to the target storage address of the read command, and the second forward error correction information includes at least one bit of a third forward error correction code; a second error correction module, configured to perform error correction processing on the data to be verified and the third error correction code to obtain error-corrected data and a fourth error correction code, and perform parity check encoding on the error-corrected data and the fourth error correction code to obtain a fourth forward error correction code; and a second determining module, configured to, based on the second forward error correction information and the fourth forward error correction code, determine the reading result of the data to be verified, and send the reading result of the data to be verified to the system terminal.

[0021] According to another aspect of this disclosure, a non-volatile memory is also provided, comprising one or more data blocks, wherein each data block includes two or more pages, and further comprising: a programming device for the non-volatile memory, the programming device being configured to perform the above-described programming method for the non-volatile memory; or a reading device for the non-volatile memory, the reading device being configured to perform the above-described reading method for the non-volatile memory.

[0022] In the embodiments of this disclosure, in response to a programming instruction sent by the system, error correction processing is performed on the data to be programmed in the programming instruction to obtain a first error correction code; parity check encoding is performed on the data to be programmed and the first error correction code to obtain first forward error correction information, the first forward error correction information including at least one first forward error correction code; the data to be programmed, the first error correction code, and the first forward error correction information are programmed into a target data block, the target data block being a data block in non-volatile memory corresponding to the target storage address in the programming instruction; in response to the end of programming, the programmed data, the first error correction code, and the first forward error correction information in the target data block are read; error correction processing is performed on the programmed data and the first error correction code to obtain erroneously corrected data and a second error correction code; parity check encoding is performed on the erroneously corrected data and the second error correction code to obtain a second forward error correction code; based on the first forward error correction information and the second forward error correction code, the programming result of the data to be programmed is determined, and the programming result of the data to be programmed is sent to the system. This disclosure ensures the integrity and correctness of programming data. Through a two-level error correction and detection mechanism, it improves data reliability, reduces the impact of data transmission errors, further enhances the system's fault tolerance, and makes the system more secure and reliable.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 A flowchart illustrating a programming method for a non-volatile memory provided in an embodiment of this disclosure is shown.

[0026] Figure 2 The flowchart of a first forward error correction information encoding method provided in an embodiment of this disclosure is shown.

[0027] Figure 3 A flowchart illustrating another method for programming a non-volatile memory provided in an embodiment of this disclosure is shown.

[0028] Figure 4 This diagram illustrates a programming method flowchart for another non-volatile memory provided in an embodiment of the present disclosure.

[0029] Figure 5 A flowchart illustrating another method for programming a non-volatile memory provided in an embodiment of this disclosure is shown.

[0030] Figure 6 A flowchart illustrating another method for programming a non-volatile memory provided in an embodiment of this disclosure is shown.

[0031] Figure 7 This diagram illustrates a programming method for a non-volatile memory in case of programming failure, as provided in an embodiment of this disclosure.

[0032] Figure 8 This diagram illustrates a flowchart of a method for reading a non-volatile memory according to an embodiment of the present disclosure.

[0033] Figure 9 This diagram illustrates a flowchart of another method for reading a non-volatile memory provided in an embodiment of this disclosure.

[0034] Figure 10 This diagram illustrates a flowchart of another method for reading a non-volatile memory provided in an embodiment of this disclosure.

[0035] Figure 11 This diagram illustrates the structure of a programming apparatus for a non-volatile memory according to an embodiment of the present disclosure.

[0036] Figure 12 This diagram illustrates the structure of a non-volatile memory reading device provided in an embodiment of the present disclosure.

[0037] Figure 13 This diagram illustrates the structure of a non-volatile memory provided in an embodiment of the present disclosure.

[0038] Figure 14 This diagram illustrates a storage structure of a data block according to an embodiment of the present disclosure.

[0039] Figure 15 This diagram illustrates another data block storage structure provided in an embodiment of the present disclosure.

[0040] Figure 16 This diagram illustrates another data block storage structure provided in an embodiment of the present disclosure.

[0041] Figure 17 A schematic diagram of the overall structure of the non-volatile memory provided in an embodiment of this disclosure is shown.

[0042] Figure 18 A flowchart illustrating an example of a programming method for a non-volatile memory provided in an embodiment of this disclosure is shown.

[0043] Figure 19 A flowchart illustrating an example of a method for reading a non-volatile memory provided in an embodiment of this disclosure is shown. Detailed Implementation

[0044] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0045] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0046] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0047] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0048] It should be noted that the terms “one” and “multiple” used in this disclosure are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as “one or more”, where “multiple” means two or more.

[0049] Memory is a storage component used to store programs and various data information. Based on its usage type, memory can be divided into Read Only Memory (ROM) and Random Access Memory (RAM). ROM can include Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), and Flash memory. Flash memory includes NOR flash memory and NAND flash memory.

[0050] NAND flash memory is a type of non-volatile flash memory that allows data to be stored even after power is turned off. This characteristic makes NAND flash memory a popular choice for built-in storage in external devices, mobile portable devices, and consumer electronics products.

[0051] NAND flash memory types include Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), and Quadruple-Level Cell (QLC). Different types of flash memory differ in their structural characteristics, cell bit width, and endurance. Endurance is determined by the number of program / erase (P / E) cycles a flash memory cell can complete before it begins to wear out. An erase operation and / or a programming operation writing to a memory cell constitutes one P / E cycle. The higher the nominal P / E cycle value, the more times the memory chip can be erased and rewritten, i.e., the higher its endurance.

[0052] Each cell of SLC NAND flash memory stores one bit of information, either 0 or 1, offering fast data writing and retrieval, optimal performance, high durability, and providing up to 100,000 P / E cycles.

[0053] Non-volatile memory comprises multiple memory cells arranged in an array. Each row of memory cells is controlled by a word line (WL), and each column of memory cells is controlled by a bit line (BL). Multiple memory cells connected to word lines are called a page, and multiple memory cells connected to bit lines are called a string. When data needs to be read from the memory cell corresponding to the p-th row and q-th column, a first reference voltage Vcgrv needs to be applied to the p-th word line (or the selected word line or the word line containing the data to be read). To ensure data reading accuracy, a second reference voltage Vread needs to be applied to the memory cells corresponding to the non-selected word lines (word lines other than the p-th row) to keep the memory cells corresponding to the non-selected word lines in a conducting state. This avoids interference caused by the memory cells of the non-selected word lines reading the selected memory cells in applications with few writes and many reads.

[0054] In related technologies, to ensure the correctness and security of data transmission, non-volatile memory typically employs Error Correcting Code (ECC) to correct and detect errors in read data. When ECC corrects an error, it generates a corresponding error correction flag, which is provided to the system to promptly notify the system that an error correction operation has been performed on the non-volatile memory. However, if ECC results in a false correction or fails to correct an error, the system may mistakenly determine it as a safe state, leading to misjudgment and posing a security risk.

[0055] To address at least some of the aforementioned problems, this disclosure provides a programming method for non-volatile memory. In response to a programming instruction sent from the system, the method performs error correction processing on the data to be programmed in the programming instruction to obtain a first error correction code; parity check encoding is performed on the data to be programmed and the first error correction code to obtain first forward error correction information, the first forward error correction information including at least one bit of the first forward error correction code; the method programs the data to be programmed, the first error correction code, and the first forward error correction information into a target data block, the target data block being a data block in the non-volatile memory corresponding to the target storage address in the programming instruction; in response to the end of programming, the programming data in the target data block is read. The system comprises: post-programmed data, the first error correction code, and the first forward error correction information; error correction processing of the post-programmed data and the first error correction code to obtain erroneously corrected data and a second error correction code; parity check encoding of the erroneously corrected data and the second error correction code to obtain a second forward error correction code; determination of the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code; and sending the programming result of the data to be programmed to the system. This disclosure ensures the integrity and correctness of the programming data, improves data reliability through a two-level error correction and detection mechanism, reduces the impact of data transmission errors, further enhances the fault tolerance of the system, and makes the system more secure and reliable.

[0056] It should be noted that, without conflict, the embodiments of the present invention and the technical features thereof can be combined with each other.

[0057] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0058] This disclosure provides a method for programming and reading non-volatile memory, which can be executed by any system with computing power. For example, the programming method for non-volatile memory in this disclosure can be executed by a programming device for non-volatile memory, and the reading method for non-volatile memory can be executed by a reading device for non-volatile memory. The programming device or the reading device for non-volatile memory can be located in the controller of the non-volatile memory, and can be a Programmable Logic Controller (PLC) or a microcontroller, as long as it can perform the corresponding functions.

[0059] Figure 1 A flowchart illustrating a programming method for a non-volatile memory according to an embodiment of this disclosure is shown. Figure 1 As shown, the programming method for non-volatile memory in this embodiment of the present disclosure mainly includes the following steps:

[0060] S102. In response to the programming instruction sent by the system, the data to be programmed in the programming instruction is subjected to error correction processing to obtain a first error correction code. The data to be programmed and the first error correction code are subjected to parity check encoding to obtain first forward error correction information. The first forward error correction information includes at least one first forward error correction code.

[0061] In one embodiment, the system side can be a microcontroller or a processor.

[0062] Programming instructions are instruction information sent by the system. Programming instructions include the data to be programmed and the target memory address. The data to be programmed is the data of the target data block corresponding to the target memory address in the non-volatile memory. The target memory address is used to determine the address of the target data block used to store the data to be programmed in the non-volatile memory.

[0063] In one embodiment, after receiving the programming instructions, the non-volatile memory can store the data to be programmed and the target memory address into an internal cache. The internal cache is a temporary memory within the non-volatile memory, thereby improving system performance and response speed. The internal cache can be either Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0064] In one embodiment, after the non-volatile memory receives the data to be programmed, it can send the data to the ECC engine module. The ECC engine module processes the data to be programmed using a preset ECC encoding algorithm to generate a corresponding first error correction code.

[0065] The data to be programmed and the first error correction code are sent to the parity check engine module for encoding to generate the first forward error correction information. The parity check engine module performs an XOR operation on each bit of the data to be programmed and the first error correction code to obtain the XOR result. Based on the XOR result, the first forward error correction code is obtained. According to the parity check method and the number of first forward error correction codes, the first forward error correction information is encoded.

[0066] The number of first forward error correction codes in the first forward error correction information can be determined according to actual needs. The first forward error correction information includes 1 bit to 3 bits of first forward error correction codes. When the first forward error correction information includes multiple first forward error correction codes, the values ​​of the multiple first forward error correction codes are the same. For example, when the first forward error correction code is 1 and the number of first forward error correction codes is 2, the first forward error correction information is 11; when the first forward error correction code is 1 and the number of first forward error correction codes is 3, the first forward error correction information is 111.

[0067] Parity checking methods can include odd parity or even parity. Odd parity is used to detect whether the data to be programmed and the first error correction code contain an odd number of 1s, while even parity is used to detect whether the data to be programmed and the first error check code contain an even number of 1s.

[0068] S104. Program the data to be programmed, the first error correction code, and the first forward error correction information to the target data block. The target data block is a data block in non-volatile memory that corresponds to the target storage address in the programming instruction.

[0069] After obtaining the data to be programmed, the first error correction code, and the first forward error correction information, the programming state machine is started to program the data to be programmed, the first error correction code, and the first forward error correction information into the target data block of the non-volatile memory.

[0070] During the programming process, the non-volatile memory uses a programming verification voltage to verify the target data block, checking whether the threshold voltage of the storage cells in the target data block meets the requirements. If the verification passes, it indicates that the data to be programmed, the first error correction code, and the first forward error correction information are consistent with the data stored in the target data block, and the entire programming process ends. If the verification fails, it indicates that the data to be programmed, the first error correction code, and the first forward error correction information are inconsistent with the data stored in the target data block, and the programming voltage is used to program the storage cells of the target data block. After programming is completed, the verification count is incremented by 1, and it is determined whether the verification count has reached the maximum verification count set at the factory. If so, the entire programming operation ends; otherwise, the programming verification state is entered, and the programming operation is repeated until the programming verification passes, ending the entire programming process.

[0071] S106. In response to the end of programming, read the programmed data, the first error correction code, and the first forward error correction information from the target data block.

[0072] The data after programming is the data stored in the target data block after the programming operation.

[0073] After programming is completed, the programmed data, the first error correction code, and the first forward error correction information in the target data block are reread and sent to the functional safety diagnostic module for functional safety diagnostics of the programming operation.

[0074] S108. Perform error correction processing on the programmed data and the first error correction code to obtain the error-corrected data and the second error correction code. Perform parity check encoding on the error-corrected data and the second error correction code to obtain the second forward error correction code.

[0075] The functional safety diagnostic module performs ECC error correction on the programmed data and the first error correction code to obtain the error-corrected data and the second error correction code. It then performs parity check processing on the error-corrected data and the second error correction code to obtain the second forward error correction code.

[0076] It should be noted that if ECC error correction is required for the programmed data and the first error correction code, the corrected data will be different from the programmed data, and / or the first error correction code and the second error correction code will be different; if ECC error correction is not required for the programmed data and the first error correction code, the corrected data will be the same as the programmed data, and the first error correction code and the second error correction code will be the same.

[0077] In one embodiment, the second forward error correction code is used to characterize whether the number of 0s or 1s in the corrected data and the second error correction code is odd or even. The generation method of the second forward error correction code is similar to that of the first forward error correction code, and will not be described again here.

[0078] S110. Based on the first forward error correction information and the second forward error correction code, determine the programming result of the data to be programmed, and send the programming result of the data to be programmed to the system.

[0079] In one embodiment, the programming result is determined based on the number and value of the first forward error correction code and the second forward error correction code. When the first forward error correction information includes one first forward error correction code, the first forward error correction code read from the target data block and the second forward error correction code generated after error correction are compared. If they match, the programming result is determined to be successful; if they do not match, the programming result is determined to be unsuccessful.

[0080] When the first forward error correction information includes two or more first forward error correction codes, it is necessary to determine the consistency of the two or more first forward error correction codes, and then determine the programming result based on the judgment result and the second forward error correction code.

[0081] In one embodiment, the programming result of the data to be programmed can be distinguished by a flag bit. For example, when the programming result is successful, the flag bit is 0, and when the programming result is unsuccessful, the flag bit is 1.

[0082] After the programming operation verification is completed, the flag bit can be output to the input / output (I / O) pin of the non-volatile memory. The I / O pin of the non-volatile memory can be used for device addressing, address space expansion, and hardware configuration. Multiple chips of the same type can be connected on the same bus. The address space can be expanded by setting the I / O pin. By outputting the flag bit information to the I / O pin, the server can read the value of the flag bit and determine the programming result based on the value of the flag bit.

[0083] After the programming operation verification is completed, the flag bit can also be written to the functional safety register. The functional safety register is composed of flip-flops with storage functions. One flip-flop can store 1 bit of binary code. For a functional safety register that stores n bits of binary code, n flip-flops are required. When the functional safety register is updated, the server can read the flag bit in the functional safety register to determine the programming result in a timely manner.

[0084] In one embodiment, in response to a programming failure in the data to be programmed, an alarm flag is generated. By outputting the alarm flag to the I / O pin of the non-volatile memory or writing it to the functional safety register, the server can be promptly notified of the programming failure and take appropriate action, thereby effectively improving the security and reliability of the system and greatly reducing the system's processing time.

[0085] In the embodiments of this disclosure, in response to a programming instruction sent by the system, error correction processing is performed on the data to be programmed in the programming instruction to obtain a first error correction code; parity check encoding is performed on the data to be programmed and the first error correction code to obtain first forward error correction information, the first forward error correction information including at least one first forward error correction code; the data to be programmed, the first error correction code, and the first forward error correction information are programmed into a target data block, the target data block being a data block in non-volatile memory corresponding to the target storage address in the programming instruction; in response to the end of programming, the programmed data, the first error correction code, and the first forward error correction information in the target data block are read; error correction processing is performed on the programmed data and the first error correction code to obtain erroneously corrected data and a second error correction code; parity check encoding is performed on the erroneously corrected data and the second error correction code to obtain a second forward error correction code; based on the first forward error correction information and the second forward error correction code, the programming result of the data to be programmed is determined, and the programming result of the data to be programmed is sent to the system. This disclosure ensures the integrity and correctness of programming data. Through a two-level error correction and detection mechanism, it improves data reliability, reduces the impact of data transmission errors, further enhances the system's fault tolerance, and makes the system more secure and reliable.

[0086] Figure 2 This diagram illustrates a flowchart of a first forward error correction information encoding method provided in an embodiment of this disclosure. Figure 2 As shown, in one embodiment, S102 above performs parity check encoding on the data to be programmed and the first error correction code to obtain first forward error correction information, including:

[0087] S2022. Perform an XOR operation on the data to be programmed and each bit of the first error correction code to obtain the XOR result.

[0088] S2024. In response to an XOR result of 1 and parity check mode of even parity, or an XOR result of 0 and parity check mode of odd parity, configure at least one bit of the first forward error correction code to be 1.

[0089] S2026. In response to an XOR result of 1 and parity check mode of odd parity, or an XOR result of 0 and parity check mode of even parity, configure at least one bit of the first forward error correction code to be 0.

[0090] In S2022, the XOR gate can be used to perform an XOR operation on each bit of the data to be programmed and the first error correction code to obtain the XOR result. The XOR result can be 0 or 1. An XOR result of 0 indicates that there are an even number of 1s in the data to be programmed and the first error correction code, and an XOR result of 1 indicates that there are an odd number of 1s in the data to be programmed and the first error correction code.

[0091] In S2024 and S2026, different values ​​can be configured for the first error correction code of each bit in the first forward error correction information according to the value of the XOR result and the different parity check methods.

[0092] For example, when the XOR result is 0 and the parity is even, or when the XOR result is 1 and the parity is odd, the first forward error correction code is configured to be 0. Correspondingly, the first forward error correction information can be configured to be 0 (1 bit), 00 (2 bits), or 000 (3 bits).

[0093] When the XOR result is 1 and the parity is even, or the XOR result is 0 and the parity is odd, the first forward error correction code is configured as 1, and the corresponding first forward error correction information is configured as 1 (1 bit), 11 (2 bits), or 111 (3 bits).

[0094] In this embodiment of the disclosure, by configuring different numbers of bits in the first forward error correction information to form single-mode redundancy check bits, double-mode redundancy check bits, or triple-mode redundancy check bits, the correctness of the check bits is effectively improved, the data reliability is enhanced, the impact of data transmission errors is reduced, the system has stronger fault tolerance, and the system is more secure and reliable.

[0095] Figure 3 A flowchart illustrating another method for programming a non-volatile memory provided in an embodiment of this disclosure is shown. Figure 1 Based on the embodiment, S104 is further refined into S1042, thereby limiting the order of programming operations. In one embodiment, such as Figure 3 As shown, the above-mentioned S104 programm the data to be programmed, the first error correction code, and the first forward error correction information into the target data block, including:

[0096] S1042. Program the data to be programmed, the first error correction code, and the first forward error correction information to the target data block according to a preset order, wherein the preset order includes any of the following: the order of the data to be programmed, the first error correction code, and the first forward error correction information; the order of the data to be programmed, the first forward error correction information, and the first error correction code; or a mixed method of the data to be programmed, the first forward error correction information, and the first error correction code.

[0097] In one embodiment, the data arrangement order of the Main data to be programmed, the first error correction code (ECC code), and the first forward error correction information (PEC bit) in the target data block can be referenced. Figure 14 , Figure 15 As shown, you can also refer to... Figure 16 A mixed arrangement of the three.

[0098] In addition, the first error correction code (ECC code) and the first forward error correction information (PEC bit) can be stored in a dedicated storage area, which is not specifically limited in this disclosure.

[0099] like Figure 17 As shown, based on Figure 14 The data storage method allows for the setting of N data blocks arranged in an array in non-volatile memory, where N is a positive integer.

[0100] In this embodiment of the disclosure, the data to be programmed, the first error correction code, and the first forward error correction information are programmed into the target data block in a preset order, which enables the data and the corresponding verification information to be stored in the target data block, facilitating data management.

[0101] Figure 4 This diagram illustrates a flowchart of a programming method for another non-volatile memory provided in an embodiment of this disclosure. Figure 1 Based on the embodiment, S110 is further refined into S1102 to limit the case where the first forward error correction information includes one bit of the first forward error correction code. For example... Figure 4 As shown, in one embodiment, the first forward error correction information includes a 1-bit first forward error correction code. The above-described S110 determines the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code, including:

[0102] S1102. In response to the first forward error correction code being the same as the second forward error correction code, the programming result of the data to be programmed is determined to be successful; in response to the first forward error correction code being different from the second forward error correction code, the programming result of the data to be programmed is determined to be unsuccessful.

[0103] In S1102, the value of the first forward error correction code read from the target data block is compared with the value of the second forward error correction code generated by the error-corrected data and the second error correction code. Based on the comparison result, the programming result is determined. If the two are the same, the programming is considered successful; if the two are different, the programming is considered to have failed.

[0104] It should be noted that the data to be programmed may differ from the data read after programming. Therefore, the value of the first forward error correction code may be different before and after reading. This disclosure can effectively improve the validity and reliability of data during the programming process.

[0105] Figure 5 A flowchart illustrating another method for programming a non-volatile memory provided in an embodiment of this disclosure is shown. Figure 1 Based on the embodiment, S110 is further refined into S1104 to limit the case where the first forward error correction information includes two bits of the first forward error correction code. For example... Figure 5 As shown, in one embodiment, the first forward error correction information includes a 2-bit first forward error correction code. The above-described S110 determines the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code, including:

[0106] S1104. In response to the fact that the two first forward error correction codes have the same value and the first forward error correction code and the second forward error correction code have the same value, the programming result of the data to be programmed is determined to be successful; in response to the fact that the two first forward error correction codes have different values, or the two first forward error correction codes have the same value and the first forward error correction code and the second forward error correction code have different values, the programming result of the data to be programmed is determined to be unsuccessful.

[0107] In S1104, when the first forward error correction information includes two first forward error correction codes, the consistency of the two first forward error correction codes is first checked. If they are consistent, the consistency of the first forward error correction code and the second forward error correction code is checked. If they are consistent, the programming is considered successful; if they are inconsistent, the programming is considered to have failed. If the two first forward error correction codes are inconsistent, the programming is considered to have failed.

[0108] For example, when the first forward error correction information is 11, if the second forward error correction code is 1, the programming is successful; if the second forward error correction code is 0, the programming fails. When the first forward error correction information is 00, if the second forward error correction code is 1, the programming fails; if the second forward error correction code is 0, the programming is successful. When the first forward error correction information is 01 or 10, the programming fails.

[0109] In this embodiment of the disclosure, the correctness of the check bit can be further ensured by using a 2-bit first forward error correction code, thereby effectively improving the reliability of data transmission.

[0110] Figure 6 A flowchart illustrating another method for programming a non-volatile memory provided in an embodiment of this disclosure is shown. Figure 1 Based on the embodiment, S110 is further refined into S1106 to limit the case where the first forward error correction information includes a 3-bit first forward error correction code. For example... Figure 6 As shown, in one embodiment, the first forward error correction information includes a 3-bit first forward error correction code; the above-described S110 determines the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code, including:

[0111] S1106. In response to the fact that the values ​​of the three first forward error correction codes are the same and the values ​​of the first forward error correction codes and the second forward error correction codes are the same, or the values ​​of the two first forward error correction codes in the first forward error correction information are the same and the values ​​of the two first forward error correction codes and the second forward error correction codes are the same, the programming result of the data to be programmed is determined to be successful.

[0112] If the values ​​of the three first forward error correction codes are the same and the values ​​of the first forward error correction codes and the second forward error correction codes are different, or if the values ​​of the two first forward error correction codes in the first forward error correction information are the same and the values ​​of the two first forward error correction codes and the second forward error correction codes are different, the programming result of the data to be programmed is determined to be a programming failure.

[0113] In S1106, when the first forward error correction information includes a 3-bit first forward error correction code, the consistency of the 3-bit first forward error correction code is compared. If the 3-bit first forward error correction code is consistent, the value of the first forward error correction code is compared with the second forward error correction code. If the two are consistent, the programming is determined to be successful; if the two are inconsistent, the programming is determined to be unsuccessful. If the 3-bit first forward error correction code is inconsistent, the same value of the 2-bit first forward error correction code is determined, and then the same value of the 2-bit first forward error correction code is compared with the second forward error correction code. If the two are consistent, the programming is successful; if the two are inconsistent, the programming is unsuccessful.

[0114] For example, when the first forward error correction information is 111, if the second forward error correction code is 1, the programming is successful; if the second forward error correction code is 0, the programming fails. When the first forward error correction information is 000, if the second forward error correction code is 1, the programming fails; if the second forward error correction code is 0, the programming is successful.

[0115] When the 2-bit first forward error correction code in the first forward error correction information is 1 (e.g., 011, 101, or 110), if the second forward error correction code is 1, the programming is successful; if the second forward error correction code is 0, the programming fails. When the 2-bit first forward error correction code in the first forward error correction information is 0 (e.g., 001, 100, or 010), if the second forward error correction code is 1, the programming fails; if the second forward error correction code is 0, the programming is successful.

[0116] In this embodiment of the disclosure, the correctness of the check bit can be further ensured by using a 3-bit first forward error correction code, thereby effectively improving the reliability of data transmission.

[0117] Figure 7 This diagram illustrates a programming method for non-volatile memory in case of programming failure, as provided in an embodiment of this disclosure. Figure 7 As shown, in one embodiment, sending the programming result of the data to be programmed to the system in S110 above includes:

[0118] S702. In response to the programming result of the data to be programmed being programming failure, a first alarm flag is generated, wherein the first alarm flag indicates that the programming of the data to be programmed has failed.

[0119] S704. Output the first alarm flag bit to the input / output pin of the non-volatile memory, or write the first alarm flag bit to the functional safety register so that the system can read the first alarm flag bit.

[0120] In S702, the first alarm flag can be a binary data bit. For example, when programming fails, a first alarm flag with a value of 1 is generated to indicate that the programming operation has failed.

[0121] In the S704, after the first alarm flag is output to the IO pin, the system reads the first alarm flag and performs corresponding processing based on the value of the first alarm flag, such as resending the programming command.

[0122] The first alarm flag can also be written to the functional safety register. After the system detects the update of the functional safety register status, it reads the first alarm flag and then performs corresponding processing, such as resending the programming instructions.

[0123] It should be noted that when the programming result of the data to be programmed is successful, there is no need to send a message to the system, thus effectively saving system resources.

[0124] In this embodiment of the disclosure, when programming fails, a first alarm flag is generated and output to the IO pin or stored in the functional safety register. On the one hand, this allows the system to read the first alarm flag in a timely manner and perform corresponding processing, thereby improving the effectiveness of data storage.

[0125] Figure 8 This diagram illustrates a flowchart of a method for reading a non-volatile memory according to an embodiment of this disclosure. Figure 8 As shown, in one embodiment, the method for reading the non-volatile memory disclosed herein mainly includes the following steps:

[0126] S802, in response to a read command sent by the system, read the data, error correction code and forward error correction information from the target data block to obtain the corresponding data to be verified, the third error correction code and the second forward error correction information, wherein the target data block is a data block in non-volatile memory corresponding to the target storage address of the read command, and the second forward error correction information includes at least one third forward error correction code.

[0127] In one embodiment, a read instruction is an instruction message sent by the system to read data from a target data block in non-volatile memory. The read instruction includes a target memory address, which is used to record the address of the data block in non-volatile memory where the data to be read is stored.

[0128] The data to be verified is the data read from the target data block corresponding to the target storage address.

[0129] The third error correction code is the error correction code read from the target data block corresponding to the target storage address. Usually, the third error correction code is consistent with the first error correction code read from the target data block in the programming method embodiment. In some cases, such as changes in the usage environment of non-volatile memory (low temperature environment or high temperature environment), the reading results of the two error correction codes may be inconsistent. Therefore, in order to distinguish between the programming process and the reading process, different names are used for definition.

[0130] The second forward error correction information is the forward error correction information read from the target database corresponding to the target storage address. The number of bits of the third forward error correction code in the second forward error correction information can be determined during the programming process. The second forward error correction information may include 1 bit to 3 bits of the third forward error correction code. In order to distinguish between the programming process and the reading process, different names are used for definition.

[0131] S804. Perform error correction processing on the data to be checked and the third error correction code to obtain the error-corrected data and the fourth error correction code. Perform parity check encoding on the error-corrected data and the fourth error correction code to obtain the fourth forward error correction code.

[0132] After reading the data to be verified, the data to be verified and the third error correction code can be sent to the ECC decoding module. The ECC decoding module decodes and corrects the data to be verified and the third error correction code to obtain the corrected data and the fourth error correction code. At the same time, the corrected data can be sent to the IO pin of the non-volatile memory for the system to sample the data.

[0133] The error-corrected data and the fourth error correction code obtained by the ECC decoding module are sent to the parity check engine decoding module. The parity check engine decoding module performs parity check encoding on the error-corrected data and the fourth error correction code to generate the fourth forward error correction code, which is used to compare with the second forward error correction information stored in the target data block to determine the consistency of the read operation.

[0134] S806. Based on the second forward error correction information and the fourth forward error correction code, determine the reading result of the data to be verified, and send the reading result of the data to be verified to the system.

[0135] The result of reading the data to be verified can include whether the reading was successful or failed.

[0136] In one embodiment, the reading result of the data to be verified can be distinguished by a flag bit. For example, when the reading result is successful, the flag bit is 0, and when the reading result is unsuccessful, the flag bit is 1.

[0137] After the read operation verification is completed, the flag bit can be output to the IO pin of the non-volatile memory so that the server can read the value of the flag bit and determine the read result based on the value of the flag bit.

[0138] After the read operation verification is complete, the flag bit can also be written to the functional safety register. When the functional safety register is updated, the server can read the flag bit in the functional safety register to determine the read result in a timely manner.

[0139] In one embodiment, in response to a read failure, an alarm flag is generated. By outputting the alarm flag to the I / O pin of the non-volatile memory or writing it to the functional safety register, the server is promptly notified of the read failure and can then take appropriate action, effectively improving the security and reliability of the system and greatly reducing system latency.

[0140] In this embodiment, in response to a read command sent by the system, data, error correction codes, and forward error correction information in the target data block are read to obtain corresponding data to be verified, a third error correction code, and second forward error correction information. The target data block is a data block in non-volatile memory corresponding to the target storage address of the read command. The second forward error correction information includes at least one third forward error correction code. Error correction processing is performed on the data to be verified and the third error correction code to obtain corrected data and a fourth error correction code. Parity check encoding is performed on the corrected data and the fourth error correction code to obtain a fourth forward error correction code. Based on the second forward error correction information and the fourth forward error correction code, the reading result of the data to be verified is determined, and the reading result is sent to the system. This disclosure ensures the integrity and correctness of the programming data. Through a two-level error correction and detection mechanism, it improves data reliability, reduces the impact of data transmission errors, further enhances the system's fault tolerance, and makes the system more secure and reliable.

[0141] In one embodiment, the second forward error correction information includes a 1-bit third forward error correction code; wherein, in S806 above, determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: in response to the value of the third forward error correction code being the same as the value of the fourth forward error correction code, determining that the reading result of the data to be verified is successful; in response to the third forward error correction code being different from the fourth forward error correction code, determining that the reading result of the data to be verified is unsuccessful.

[0142] It should be noted that when the second forward error correction information includes one third forward error correction code, the implementation method of determining the reading result by the third forward error correction code and the fourth forward error correction code is similar to the implementation method of determining the programming result by the first forward error correction code and the second forward error correction code when the first forward error correction information includes one first forward error correction code in the aforementioned embodiment, and will not be repeated here.

[0143] In this embodiment of the disclosure, by comparing the read third forward error correction code with the fourth forward error correction code generated after error correction, the reading result can be quickly determined, thereby effectively improving the effectiveness and reliability of data in the reading process.

[0144] In one embodiment, the second forward error correction information includes a 2-bit third forward error correction code; wherein, in S806 above, determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: in response to the two-bit third forward error correction code having the same value, and the third forward error correction code and the fourth forward error correction code having the same value, determining that the reading result of the data to be verified is successful; in response to the two-bit third forward error correction code having different values, or the two-bit third forward error correction code having the same value and the third forward error correction code and the fourth forward error correction code having different values, determining that the reading result of the data to be verified is unsuccessful.

[0145] It should be noted that when the second forward error correction information includes two third forward error correction codes, the implementation method of determining the reading result by the third and fourth forward error correction codes is similar to the implementation method of determining the programming result by the first and second forward error correction codes when the first forward error correction information includes two first forward error correction codes in the aforementioned embodiment, and will not be repeated here.

[0146] In this embodiment of the disclosure, by judging the consistency of the read 2-bit third forward error correction code, the correctness of the calibration bit can be further ensured, thereby effectively improving the validity and reliability of the data during the reading process and ensuring the accuracy of data reading.

[0147] In one embodiment, the second forward error correction information includes a 3-bit third forward error correction code; wherein, in S806 above, determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: in response to the three-bit third forward error correction code having the same value, and the third forward error correction code having the same value as the fourth forward error correction code, determining that the reading result of the data to be verified is successful; in response to the three-bit third forward error correction code having the same value, and the third forward error correction code having the same value as the fourth forward error correction code, determining that the reading result of the data to be verified is successful; If the values ​​are different, the reading result of the data to be verified is determined to be a reading failure; or if the two-bit third forward error correction code in the second forward error correction information has the same value, and the two-bit third forward error correction code has the same value as the fourth forward error correction code, the reading result of the data to be verified is determined to be a reading success; if the two-bit third forward error correction code in the second forward error correction information has the same value, and the two-bit third forward error correction code has the same value as the fourth forward error correction code, the reading result of the data to be verified is determined to be a reading failure.

[0148] It should be noted that when the second forward error correction information includes a 3-bit third forward error correction code, the implementation method of determining the reading result by the third forward error correction code and the fourth forward error correction code is similar to the implementation method of determining the programming result by the first forward error correction code and the second forward error correction code when the first forward error correction information includes a 3-bit first forward error correction code in the aforementioned embodiment, and will not be repeated here.

[0149] In this embodiment, the correctness of the check bit can be further ensured by using a 3-bit third forward error correction code, thereby effectively improving the reliability of data transmission and ensuring the accuracy of data reading.

[0150] Figure 9 This diagram illustrates a flowchart of another method for reading non-volatile memory provided in an embodiment of this disclosure. Figure 8 Based on the embodiment, S806 is further refined into S902 and S904 to limit the circumstances under which an alarm is triggered due to a read failure. For example... Figure 9As shown, in one embodiment, sending the read result of the data to be verified to the system in S806 above includes:

[0151] S902. In response to the reading result of the data to be verified being a reading failure, a second alarm flag is generated, wherein the second alarm flag indicates that the data to be verified has failed to be read.

[0152] S904. Output the second alarm flag bit to the input / output pin of the non-volatile memory, or write the second alarm flag bit to the functional safety register so that the system can read the second alarm flag bit.

[0153] In S902, the second alarm flag can be a binary data bit. For example, when a read operation fails, a second alarm flag with a value of 1 is generated to indicate that the read operation failed.

[0154] In the S904, after the second alarm flag is output to the IO pin, the system reads the second alarm flag and performs corresponding processing based on the value of the second alarm flag, such as resending the read command.

[0155] The second alarm flag can also be written to the functional safety register. After the system detects the update of the functional safety register status, it reads the second alarm flag and then performs corresponding processing, such as resending the read command.

[0156] It should be noted that when the programming result of the data to be verified is successful, there is no need to send information to the system, thus effectively saving system resources.

[0157] In this embodiment of the disclosure, when a read fails, a second alarm flag is generated and output to the IO pin or stored in the functional safety register, so that the system can read the second alarm flag in a timely manner and perform corresponding processing, thereby improving the effectiveness of data storage.

[0158] Figure 10 This diagram illustrates a flowchart of another method for reading a non-volatile memory provided in an embodiment of this disclosure. Figure 10 As shown, in one embodiment, after performing error correction processing on the data to be verified and the third error correction code in S804 to obtain the error-corrected data and the fourth error correction code, the non-volatile memory reading method of this embodiment further includes:

[0159] S1002, Generate single-bit error detection flag and double-bit error detection flag;

[0160] S1004. Send the single-bit error detection flag and the double-bit error detection flag to the input / output pin, or write them to the functional safety register, so that the system can read the single-bit error detection flag and the double-bit error detection flag.

[0161] In one embodiment, if the ECC decoding module performs error correction and error detection on the data to be checked and the third error correction code, then a corresponding single-bit error detection flag (Single Error Correction, SEC) and a double-bit error detection flag (DED) will be generated. The single-bit error detection flag is used to detect and correct errors of a single bit, and the double-bit error detection flag is used to detect errors of two bits.

[0162] The SEC and DED can be output to the IO pin or written to the functional safety register. The system can read the read operation failure information and perform subsequent safety processing, thereby improving the system's security.

[0163] Based on the same inventive concept, this disclosure also provides a programming device for non-volatile memory and a reading device for non-volatile memory, as shown in the following embodiments. Since the principle by which this device embodiment solves the problem is similar to that of the above method embodiment, the implementation of this device embodiment can refer to the implementation of the above method embodiment, and repeated details will not be described again.

[0164] Figure 11 This diagram illustrates the structure of a programming apparatus for a non-volatile memory according to an embodiment of the present disclosure. Figure 11 As shown, the programming device for the non-volatile memory in this embodiment includes a first error correction module 1110, a data programming module 1120, a first reading module 1130, and a first determination module 1140.

[0165] The first error correction module 1110 is used to respond to the programming instructions sent by the system, perform error correction processing on the data to be programmed in the programming instructions to obtain a first error correction code, perform parity check encoding on the data to be programmed and the first error correction code to obtain first forward error correction information, and the first forward error correction information includes at least one first forward error correction code.

[0166] The data programming module 1120 is used to program the data to be programmed, the first error correction code and the first forward error correction information into the target data block, where the target data block is a data block in non-volatile memory that corresponds to the target storage address in the programming instruction;

[0167] The first reading module 1130 is used to read the programmed data, the first error correction code and the first forward error correction information from the target data block in response to the end of programming.

[0168] The first error correction module 1110 is also used to perform error correction processing on the programmed data and the first error correction code to obtain the error-corrected data and the second error correction code, and to perform parity check encoding on the error-corrected data and the second error correction code to obtain the second forward error correction code.

[0169] The first determining module 1140 is used to determine the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code, and send the programming result of the data to be programmed to the system.

[0170] In one embodiment, the first error correction module 1110 is configured to perform an XOR operation on the data to be programmed and each bit of the first error correction code to obtain an XOR result; in response to the XOR result being 1 and the parity check mode being even parity, or the XOR result being 0 and the parity check mode being odd parity, configure at least one bit of the first forward error correction code to be 1; in response to the XOR result being 1 and the parity check mode being odd parity, or the XOR result being 0 and the parity check mode being even parity, configure at least one bit of the first forward error correction code to be 0.

[0171] In one embodiment, the data programming module 1120 is used to program the data to be programmed, the first error correction code, and the first forward error correction information into a target data block in a preset order, wherein the preset order includes any of the following: the order of the data to be programmed, the first error correction code, and the first forward error correction information; the order of the data to be programmed, the first forward error correction information, and the first error correction code; or a cross-mixing method of the data to be programmed, the first forward error correction information, and the first error correction code.

[0172] In one embodiment, the first forward error correction information includes a 1-bit first forward error correction code; the first determining module 1140 is configured to determine that the programming result of the data to be programmed is successful if the value of the first forward error correction code is the same as the value of the second forward error correction code; and to determine that the programming result of the data to be programmed is unsuccessful if the first forward error correction code is different from the second forward error correction code.

[0173] In one embodiment, the first forward error correction code includes a 2-bit first forward error correction code; the first determining module 1140 is configured to determine that the programming result of the data to be programmed is successful if the values ​​of the 2-bit first forward error correction code are the same and the values ​​of the first forward error correction code and the second forward error correction code are the same; and to determine that the programming result of the data to be programmed is unsuccessful if the values ​​of the 2-bit first forward error correction code are different, or if the values ​​of the 2-bit first forward error correction code are the same and the values ​​of the first forward error correction code and the second forward error correction code are different.

[0174] In one embodiment, the first forward error correction code includes a 3-bit first forward error correction code; the first determining module 1140 is configured to determine that the programming result of the data to be programmed is successful if the 3-bit first forward error correction code has the same value and the first forward error correction code has the same value as the second forward error correction code, or if the 2-bit first forward error correction code in the first forward error correction information has the same value and the 2-bit first forward error correction code has the same value as the second forward error correction code; and to determine that the programming result of the data to be programmed is unsuccessful if the 3-bit first forward error correction code has the same value and the first forward error correction code has the same value as the second forward error correction code, or if the 2-bit first forward error correction code in the first forward error correction information has the same value and the 2-bit first forward error correction code has the same value and the 2-bit first forward error correction code has the same value as the second forward error correction code.

[0175] In one embodiment, the first determining module 1140 is configured to generate a first alarm flag bit in response to the programming result of the data to be programmed being programming failure, wherein the first alarm flag bit indicates that the programming of the data to be programmed has failed; output the first alarm flag bit to the input / output pin of the non-volatile memory, or write the first alarm flag bit to the functional safety register so that the system reads the first alarm flag bit.

[0176] In this embodiment, in response to a programming instruction sent by the system, error correction processing is performed on the data to be programmed in the programming instruction to obtain a first error correction code. Parity check encoding is performed on the data to be programmed and the first error correction code to obtain first forward error correction information, which includes at least one bit of the first forward error correction code. The data to be programmed, the first error correction code, and the first forward error correction information are programmed into a target data block, which is a data block in non-volatile memory corresponding to the target storage address in the programming instruction. In response to the end of programming, the programmed data, the first error correction code, and the first forward error correction information in the target data block are read. Error correction processing is performed on the programmed data and the first error correction code to obtain erroneously corrected data and a second error correction code. Parity check encoding is performed on the erroneously corrected data and the second error correction code to obtain a second forward error correction code. Based on the first forward error correction information and the second forward error correction code, the programming result of the data to be programmed is determined, and the programming result of the data to be programmed is sent to the system. This disclosure ensures the integrity and correctness of programming data. Through a two-level error correction and detection mechanism, it improves data reliability, reduces the impact of data transmission errors, further enhances the system's fault tolerance, and makes the system more secure and reliable.

[0177] Figure 12 This diagram illustrates the structure of a read device for a non-volatile memory according to an embodiment of the present disclosure. Figure 12 As shown, the non-volatile memory reading device in this embodiment includes a second reading module 1210, a second error correction module 1220, and a second determination module 1230.

[0178] The second reading module 1210 is used to respond to the read command sent by the system to read the data, error correction code and forward error correction information in the target data block, and obtain the corresponding data to be verified, the third error correction code and the second forward error correction information. The target data block is a data block in non-volatile memory corresponding to the target storage address of the read command, and the second forward error correction information includes at least one third forward error correction code.

[0179] The second error correction module 1220 is used to perform error correction processing on the data to be checked and the third error correction code to obtain the error-corrected data and the fourth error correction code, and to perform parity check encoding on the error-corrected data and the fourth error correction code to obtain the fourth forward error correction code.

[0180] The second determining module 1230 is used to determine the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code, and send the reading result of the data to be verified to the system.

[0181] In one embodiment, the second forward error correction information includes a 1-bit third forward error correction code; the second determining module 1230 is further configured to determine that the reading result of the data to be verified is successful if the value of the third forward error correction code is the same as the value of the fourth forward error correction code; and to determine that the reading result of the data to be verified is unsuccessful if the third forward error correction code is different from the fourth forward error correction code.

[0182] In one embodiment, the second forward error correction information includes a 2-bit third forward error correction code; the second determining module 1230 is further configured to determine that the reading result of the data to be verified is successful if the values ​​of the 2-bit third forward error correction code are the same and the values ​​of the third forward error correction code and the fourth forward error correction code are the same; and to determine that the reading result of the data to be verified is unsuccessful if the values ​​of the 2-bit third forward error correction code are different, or if the values ​​of the 2-bit third forward error correction code are the same and the values ​​of the third forward error correction code and the fourth forward error correction code are different.

[0183] In one embodiment, the second forward error correction information includes a 3-bit third forward error correction code; the second determining module 1230 is further configured to determine that the reading result of the data to be verified is successful if the values ​​of the 3-bit third forward error correction code are the same and the values ​​of the third forward error correction code and the fourth forward error correction code are the same; to determine that the reading result of the data to be verified is unsuccessful if the values ​​of the 3-bit third forward error correction code are the same and the values ​​of the third forward error correction code and the fourth forward error correction code are different; or to determine that the reading result of the data to be verified is successful if the values ​​of the 2-bit third forward error correction code in the second forward error correction information are the same and the values ​​of the 2-bit third forward error correction code and the fourth forward error correction code are the same; and to determine that the reading result of the data to be verified is unsuccessful if the values ​​of the 2-bit third forward error correction code in the second forward error correction information are the same and the values ​​of the 2-bit third forward error correction code and the fourth forward error correction code are different.

[0184] In one embodiment, the second determining module 1230 is further configured to generate a second alarm flag bit in response to the reading result of the data to be verified being a reading failure, wherein the second alarm flag bit indicates that the data to be verified has been read without success; output the second alarm flag bit to the input / output pin of the non-volatile memory, or write the second alarm flag bit to the functional safety register so that the system reads the second alarm flag bit.

[0185] In one embodiment, the device is further configured to generate a single-bit error detection flag and a double-bit error detection flag after performing error correction processing on the data to be verified and the third error correction code to obtain the error-corrected data and the fourth error correction code; and send the single-bit error detection flag and the double-bit error detection flag to the input / output pin or write them to the functional safety register so that the system can read the single-bit error detection flag and the double-bit error detection flag.

[0186] In this embodiment, in response to a read command sent by the system, data, error correction codes, and forward error correction information in the target data block are read to obtain corresponding data to be verified, a third error correction code, and second forward error correction information. The target data block is a data block in non-volatile memory corresponding to the target storage address of the read command. The second forward error correction information includes at least one third forward error correction code. Error correction processing is performed on the data to be verified and the third error correction code to obtain corrected data and a fourth error correction code. Parity check encoding is performed on the corrected data and the fourth error correction code to obtain a fourth forward error correction code. Based on the second forward error correction information and the fourth forward error correction code, the reading result of the data to be verified is determined, and the reading result is sent to the system. This disclosure ensures the integrity and correctness of the programming data. Through a two-level error correction and detection mechanism, it improves data reliability, reduces the impact of data transmission errors, further enhances the system's fault tolerance, and makes the system more secure and reliable.

[0187] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0188] Figure 13 This diagram illustrates the structure of a non-volatile memory 1300 provided in an embodiment of the present disclosure. Figure 13 As shown, the non-volatile memory 1300 in this embodiment of the present disclosure may include one or more data blocks 1310, wherein each data block 1310 includes two or more pages. Figure 13 In the non-volatile memory 1300, there are data blocks 1 to n, where n is a positive integer and n≥1. Each data block 1310 includes multiple pages.

[0189] In one embodiment, the non-volatile memory 1300 further includes a non-volatile memory programming device 1100, wherein the non-volatile memory programming device 1100 is configured to perform the non-volatile memory programming method provided in the above embodiments, and similarities will not be repeated.

[0190] In one embodiment, the non-volatile memory 1300 further includes a non-volatile memory reading device 1200, wherein the non-volatile memory reading device 1200 is configured to perform the non-volatile memory reading method provided in the above embodiment, and similarities will not be repeated.

[0191] To deepen the understanding of the programming and reading methods of the non-volatile memory disclosed herein, the following will be combined with... Figure 18 and Figure 19 Please provide a detailed explanation.

[0192] like Figure 18 As shown in the embodiments of this disclosure, a programming method for a non-volatile memory mainly includes the following steps:

[0193] S1801: Receive programming instructions sent by the system, which carry the data to be programmed. Send the main data to the ECC engine encoding module to generate ECC code.

[0194] S1802. Send the data to be encoded and the ECC code to the parity check engine module for encoding to generate PEC bits;

[0195] S1803. Program the data to be encoded, the ECC code, and the PEC bit into the target data block of the non-volatile memory;

[0196] S1804. After programming, read the Main data, ECC code, and PEC bit.

[0197] S1805. The read Main data, ECC code, and PEC bit are sent to the functional safety diagnostic module for functional safety diagnostics. If the diagnostics pass, the programming state machine ends; if the diagnostics fail, the first alarm flag is generated.

[0198] S1806. Perform functional safety management by outputting the first alarm flag to the IO pin or writing it into the functional safety register.

[0199] like Figure 19 As shown in the embodiments of this disclosure, a method for reading non-volatile memory mainly includes the following steps:

[0200] S1901: Receive a read command sent by the system, the read command includes the target storage address; read the target data, ECC code and PEC bit from the target data block corresponding to the target storage address in the non-volatile memory, obtain PEC0 and send it to the functional safety diagnostic module;

[0201] S1902: Send the target data and ECC code to the ECC engine decoding module for error correction and error detection to obtain the corrected data and ECC code1. The corrected data is then output to the chip's IO pin.

[0202] S1903. The error-corrected data and ECC code1 are sent to the parity check engine decoding module to generate PEC1, and then sent to the functional safety diagnostic module.

[0203] S1904 The functional safety diagnostic module compares PEC0 and PEC1. If they are different, a second alarm flag is generated.

[0204] S1905. Perform functional safety management by outputting the second alarm flag to the IO pin or writing it into the functional safety register.

[0205] It should be noted that in S1902, if the ECC engine decoding module performs error correction and error detection on the target data and ECC code, that is, if there is a reading error in the target data and ECC code, SEC and DED are generated, and the SEC and DED are managed for functional safety.

[0206] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0207] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware.

[0208] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope of this disclosure is indicated by the appended claims.

Claims

1. A programming method for non-volatile memory, characterized in that, include: In response to a programming instruction sent by the system, the data to be programmed in the programming instruction is subjected to error correction processing to obtain a first error correction code. The data to be programmed and the first error correction code are subjected to parity check encoding to obtain first forward error correction information. The first forward error correction information includes at least one first forward error correction code. The data to be programmed, the first error correction code, and the first forward error correction information are programmed into a target data block, wherein the target data block is a data block in the non-volatile memory corresponding to the target storage address in the programming instructions; In response to the end of programming, the programmed data, the first error correction code, and the first forward error correction information in the target data block are read. The programmed data and the first error correction code are subjected to error correction processing to obtain the error-corrected data and the second error correction code. The error-corrected data and the second error correction code are subjected to parity check encoding to obtain the second forward error correction code. Based on the first forward error correction information and the second forward error correction code, the programming result of the data to be programmed is determined, and the programming result of the data to be programmed is sent to the system.

2. The method according to claim 1, characterized in that, The step of performing parity-check encoding on the data to be programmed and the first error correction code to obtain the first forward error correction information includes: Perform an XOR operation on the data to be programmed and each bit of the first error correction code to obtain the XOR result; In response to the XOR result being 1 and the parity check mode being even parity, or the XOR result being 0 and the parity check mode being odd parity, the at least one bit of the first forward error correction code is configured to be 1; In response to the XOR result being 1 and the parity check mode being odd, or the XOR result being 0 and the parity check mode being even, the first forward error correction code of at least one bit is configured to be 0.

3. The method according to claim 1, characterized in that, The step of programming the data to be programmed, the first error correction code, and the first forward error correction information into the target data block includes: The data to be programmed, the first error correction code, and the first forward error correction information are programmed into the target data block according to a preset order, wherein the preset order includes any of the following: In the order of the data to be programmed, the first error correction code, and the first forward error correction information; In the order of the data to be programmed, the first forward error correction information, and the first error correction code; The programming data, the first forward error correction information, and the first error correction code are mixed in a cross-mixing manner.

4. The method according to claim 1, characterized in that, The first forward error correction information includes a 1-bit first forward error correction code; The step of determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code includes: If the values ​​of the first forward error correction code and the second forward error correction code are the same, the programming result of the data to be programmed is determined to be successful. In response to the difference between the first forward error correction code and the second forward error correction code, the programming result of the data to be programmed is determined to be a programming failure.

5. The method according to claim 1, characterized in that, The first forward error correction code includes 2 bits of the first forward error correction code; The step of determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code includes: In response to the fact that the two bits of the first forward error correction code have the same value, and the first forward error correction code and the second forward error correction code have the same value, the programming result of the data to be programmed is determined to be successful. In response to the two bits of the first forward error correction code having different values, or the two bits of the first forward error correction code having the same value and the first forward error correction code and the second forward error correction code having different values, the programming result of the data to be programmed is determined to be a programming failure.

6. The method according to claim 1, characterized in that, The first forward error correction code includes a 3-bit first forward error correction code; The step of determining the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code includes: In response to the fact that the values ​​of the three first forward error correction codes are the same and the values ​​of the first forward error correction codes and the second forward error correction codes are the same, or the values ​​of the two first forward error correction codes in the first forward error correction information are the same and the values ​​of the two first forward error correction codes are the same, the programming result of the data to be programmed is determined to be successful. In response to the fact that the three bits of the first forward error correction code have the same value and the first forward error correction code and the second forward error correction code have different values, or the two bits of the first forward error correction code in the first forward error correction information have the same value and the two bits of the first forward error correction code have different values ​​from the second forward error correction code, the programming result of the data to be programmed is determined to be a programming failure.

7. The method according to any one of claims 1-6, characterized in that, Sending the programming result of the data to be programmed to the system includes: In response to the programming result of the data to be programmed being programming failure, a first alarm flag is generated, wherein the first alarm flag indicates that the programming of the data to be programmed has failed; The first alarm flag can be output to the input / output pin of the non-volatile memory, or the first alarm flag can be written to the functional safety register so that the system can read the first alarm flag.

8. A method for reading a non-volatile memory, characterized in that, include: In response to a read command sent by the system, the data, error correction code, and forward error correction information in the target data block are read to obtain the corresponding data to be verified, the third error correction code, and the second forward error correction information. The target data block is the data block in the non-volatile memory corresponding to the target storage address of the read command, and the second forward error correction information includes at least one third forward error correction code. The data to be verified and the third error correction code are subjected to error correction processing to obtain the error-corrected data and the fourth error correction code. The error-corrected data and the fourth error correction code are subjected to parity check encoding to obtain the fourth forward error correction code. Based on the second forward error correction information and the fourth forward error correction code, the reading result of the data to be verified is determined, and the reading result of the data to be verified is sent to the system.

9. The method according to claim 8, characterized in that, The second forward error correction information includes one third forward error correction code; The step of determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: If the values ​​of the third forward error correction code and the fourth forward error correction code are the same, the reading result of the data to be verified is determined to be successful. In response to the difference between the third forward error correction code and the fourth forward error correction code, the reading result of the data to be verified is determined to be a reading failure.

10. The method according to claim 8, characterized in that, The second forward error correction information includes a 2-bit third forward error correction code; The step of determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: In response to the fact that the values ​​of the two bits of the third forward error correction code are the same, and the values ​​of the third forward error correction code and the fourth forward error correction code are the same, it is determined that the reading result of the data to be verified is successful. In response to the two bits of the third forward error correction code having different values, or the two bits of the third forward error correction code having the same value and the third forward error correction code and the fourth forward error correction code having different values, the reading result of the data to be verified is determined to be a reading failure.

11. The method according to claim 8, characterized in that, The second forward error correction information includes a 3-bit third forward error correction code; The step of determining the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code includes: In response to the fact that the values ​​of the three bits of the third forward error correction code are the same, and the values ​​of the third forward error correction code and the fourth forward error correction code are the same, it is determined that the reading result of the data to be verified is successful. If the values ​​of the three bits of the third forward error correction code are the same, and the values ​​of the third forward error correction code and the fourth forward error correction code are different, the reading result of the data to be verified is determined to be a reading failure; or In response to the fact that the two bits of the third forward error correction code in the second forward error correction information have the same value, and the two bits of the third forward error correction code have the same value as the fourth forward error correction code, the reading result of the data to be verified is determined to be a successful reading. If the two bits of the third forward error correction code in the second forward error correction information have the same value, and the two bits of the third forward error correction code have a different value from the fourth forward error correction code, the reading result of the data to be verified is determined to be a reading failure.

12. The method according to any one of claims 8-11, characterized in that, Sending the read result of the data to be verified to the system includes: In response to the failure to read the data to be verified, a second alarm flag is generated, wherein the second alarm flag indicates that the data to be verified has failed to be read; The second alarm flag can be output to the input / output pin of the non-volatile memory, or written to the functional safety register so that the system can read the second alarm flag.

13. The method according to claim 8, characterized in that, After performing error correction processing on the data to be verified and the third error correction code to obtain the error-corrected data and the fourth error correction code, the method further includes: Generate single-bit error detection flags and double-bit error detection flags; The single-bit error detection flag and the double-bit error detection flag are sent to the input / output pin or written to the functional safety register so that the system can read the single-bit error detection flag and the double-bit error detection flag.

14. A programming device for a non-volatile memory, characterized in that, include: The first error correction module is used to respond to the programming instructions sent by the system, perform error correction processing on the data to be programmed in the programming instructions to obtain a first error correction code, and perform parity check encoding on the data to be programmed and the first error correction code to obtain first forward error correction information, wherein the first forward error correction information includes at least one first forward error correction code. The data programming module is used to program the data to be programmed, the first error correction code, and the first forward error correction information into a target data block, wherein the target data block is a data block in the non-volatile memory corresponding to the target storage address in the programming instructions; The first reading module is used to read the programmed data, the first error correction code, and the first forward error correction information from the target data block in response to the end of programming. The first error correction module is further configured to perform error correction processing on the programmed data and the first error correction code to obtain the error-corrected data and the second error correction code, and to perform parity check encoding on the error-corrected data and the second error correction code to obtain the second forward error correction code. The first determining module is used to determine the programming result of the data to be programmed based on the first forward error correction information and the second forward error correction code, and send the programming result of the data to be programmed to the system terminal.

15. A read device for a non-volatile memory, characterized in that, include: The second reading module is used to respond to a read command sent by the system to read data, error correction code and forward error correction information from the target data block, and obtain the corresponding data to be verified, third error correction code and second forward error correction information. The target data block is the data block in the non-volatile memory corresponding to the target storage address of the read command, and the second forward error correction information includes at least one third forward error correction code. The second error correction module is used to perform error correction processing on the data to be verified and the third error correction code to obtain the error-corrected data and the fourth error correction code, and to perform parity check encoding on the error-corrected data and the fourth error correction code to obtain the fourth forward error correction code. The second determining module is used to determine the reading result of the data to be verified based on the second forward error correction information and the fourth forward error correction code, and send the reading result of the data to be verified to the system terminal.

16. A non-volatile memory, characterized in that, It includes one or more data blocks, wherein each data block includes two or more pages, and also includes: A programming device for non-volatile memory, the programming device for non-volatile memory being configured to perform the programming method for the non-volatile memory according to any one of claims 1 to 7; or A read device for a non-volatile memory, the read device being configured to perform the read method for a non-volatile memory as described in any one of claims 8 to 13.

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