Memory operation method, memory and electronic device

Abstract

The present disclosure provides a memory operation method, a memory and an electronic device, and relates to the technical field of semiconductors. The memory operation method comprises: in response to a first self-check instruction, performing self-checking on a first error correction code engine and a second error correction code engine to obtain a first self-check result; in the case where the first self-check result is a first result, performing error correction processing on original data and a first error correction code by the first error correction code engine to obtain first output data, a second error correction code and a first flag; performing error correction processing on the first output data and the second error correction code by the second error correction code engine to obtain a second flag; and in the case where the first flag and the second flag both satisfy a first preset condition, outputting the first output data. The present disclosure can discover problems in data transmission in a timely manner, ensure the functional safety of the memory, and also improve the reliability of the memory operation. In addition, the original data is subjected to twice error correction processing, thereby further improving the accuracy of the data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory operation method, a memory, and an electronic device. Background Technology

[0002] To ensure the correctness and reliability of non-volatile memory such as flash memory during data transmission, Error-Correcting Code (ECC) technology is employed as an important functional safety mechanism. The main function of the ECC engine is to detect and correct potential errors in real time during data transmission. Through this mechanism, when data is corrupted during transmission, the ECC engine can automatically recover the original data, or issue an error warning to the system if recovery is impossible. This effectively prevents potential problems caused by data errors, ensuring that the system maintains high reliability and security when processing data from non-volatile memory.

[0003] However, when the ECC engine itself malfunctions, errors during data transmission may not be correctly corrected, or even result in false error corrections or false alarms. This malfunction could prevent the system from detecting problems in data transmission in a timely manner, thus triggering serious functional safety issues.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a memory operation method, a memory, and an electronic device, which can detect whether the ECC engine has malfunctioned to a certain extent in a timely manner, thereby promptly identifying problems in data transmission, ensuring the functional safety of the memory, and improving the reliability of memory operation.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0007] According to one aspect of this disclosure, a memory operation method is provided. The memory includes a first error correction code engine and a second error correction code engine. The memory operation method includes: responding to a first self-test instruction, performing a self-test on the first error correction code engine and the second error correction code engine to obtain a first self-test result; if the first self-test result is a first result, the first error correction code engine acquires original data stored in the memory and a first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain first output data, a second error correction code corresponding to the first output data, and a first flag bit; the second error correction code engine performs error correction processing on the first output data and the second error correction code to obtain a second flag bit; if both the first flag bit and the second flag bit satisfy a first preset condition, outputting the first output data from the memory interface of the memory; wherein, the first result indicates that both the first error correction code engine and the second error correction code engine are working normally.

[0008] In some embodiments, the step of performing a self-test on the first error correction code engine and the second error correction code engine in response to a first self-test instruction to obtain a first self-test result includes: in response to the first self-test instruction, generating random data and a third error correction code corresponding to the random data, and performing error injection processing on the random data to obtain erroneous data; the first error correction code engine performing error correction processing on the third error correction code and the erroneous data to obtain a first flag bit; the second error correction code engine performing error correction processing on the third error correction code and the erroneous data to obtain a second flag bit; and verifying the first flag bit and the second flag bit to obtain the first self-test result.

[0009] In some embodiments, the method further includes: when the first self-test result is the second result, shutting down the first error correction code engine, the second error correction code engine acquiring the original data stored in the memory and the first error correction code corresponding to the original data, and performing error correction processing on the original data and the first error correction code to obtain second output data and a second flag bit; when the second flag bit satisfies a second preset condition, outputting the second output data from the memory interface of the memory; wherein the second result is that the second error correction code engine is working normally and the first error correction code engine has failed.

[0010] In some embodiments, the method further includes: when the first error correction code engine is shut down, in response to a second self-test instruction, performing a self-test on the second error correction code engine to obtain a second self-test result; when the second self-test result is a third result, generating an alarm signal and shutting down the second error correction code engine, wherein the third result is that both the first error correction code engine and the second error correction code engine have failed.

[0011] In some embodiments, the method further includes: when the first self-test result is a fourth result, shutting down the second error correction code engine, wherein the first error correction code engine obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain third output data and a first flag bit; when the first flag bit satisfies a third preset condition, outputting the third output data from the memory interface of the memory; wherein the fourth result is that the first error correction code engine is working normally and the second error correction code engine has failed.

[0012] In some embodiments, the method further includes: when the second error correction code engine is turned off, in response to a third self-test instruction, performing a self-test on the first error correction code engine to obtain a third self-test result; when the third self-test result is a third result, generating an alarm signal and turning off the first error correction code engine, wherein the third result is that both the first error correction code engine and the second error correction code engine have failed.

[0013] In some embodiments, the method further includes: if the first self-test result is a third result, shutting down the first error correction code engine and the second error correction code engine, generating an alarm signal, wherein the third result is that both the first error correction code engine and the second error correction code engine have failed.

[0014] In some embodiments, the memory further includes a functional safety register; the memory interface and / or the functional safety register are used to receive the alarm signal, which indicates that both the first error correction code engine and the second error correction code engine have failed.

[0015] In some embodiments, the first flag bit includes a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit includes a second single-bit repair flag bit and a second double-bit detection flag bit; both the first single-bit repair flag bit and the second single-bit repair flag bit are used to indicate the detection and repair of a single bit error in the original data; both the first double-bit detection flag bit and the second double-bit detection flag bit are used to indicate whether a two-bit error is detected in the original data or the first output data.

[0016] According to another aspect of this disclosure, a memory is also provided, comprising: a first error correction code engine, configured to, when a first self-test result is a first result, acquire raw data stored in the memory and a first error correction code corresponding to the raw data, and perform error correction processing on the raw data and the first error correction code to obtain first output data, a second error correction code corresponding to the first output data, and a first flag bit; a second error correction code engine, configured to, when the first self-test result is a first result, perform error correction processing on the first output data and the second error correction code to obtain a second flag bit; and a functional safety diagnostic module, configured to verify whether the first flag bit and the second flag bit meet a first preset condition, so that when both the first flag bit and the second flag bit meet the first preset condition, the first output data is output from the memory interface of the memory; wherein, the first self-test result is obtained by performing a self-test on the first error correction code engine and the second error correction code engine in response to a first self-test instruction.

[0017] In some embodiments, the memory further includes: a self-test data fault injection module, configured to, in response to the first self-test instruction, generate random data and a third error correction code corresponding to the random data, and perform error injection processing on the random data to obtain erroneous data; wherein, the first error correction code engine is further configured to perform error correction processing on the third error correction code and the erroneous data to obtain a first flag bit; the second error correction code engine is further configured to perform error correction processing on the third error correction code and the erroneous data to obtain a second flag bit; and the functional safety diagnostic module is configured to verify the first flag bit and the second flag bit to obtain a first self-test result.

[0018] In some embodiments, the memory further includes a functional safety register; the functional safety register is used for one of the following: disabling the first error correction code engine when the first self-test result is a second result; disabling the second error correction code engine when the first self-test result is a fourth result; and disabling both the first and second error correction code engines when the first self-test result is a third result; wherein the second result is that the second error correction code engine is working normally and the first error correction code engine has failed; the third result is that both the first and second error correction code engines have failed; and the fourth result is that the first error correction code engine is working normally and the second error correction code engine has failed.

[0019] In some embodiments, the first error correction code engine is further configured to, when the first self-test result is a fourth result, acquire the original data stored in the memory and the first error correction code corresponding to the original data, and perform error correction processing on the original data and the first error correction code to obtain third output data and a first flag bit; the functional safety diagnostic module is further configured to verify the first flag bit so that, when the first flag bit meets a third preset condition, the third output data is output from the memory interface of the memory; or, the second error correction code engine is further configured to, when the first self-test result is a second result, acquire the original data stored in the memory and the first error correction code corresponding to the original data, and perform error correction processing on the original data and the first error correction code to obtain second output data and a second flag bit; the functional safety diagnostic module is further configured to verify the second flag bit so that, when the second flag bit meets a second preset condition, the second output data is output from the memory interface of the memory.

[0020] According to another aspect of this disclosure, an electronic device is also provided, the electronic device comprising: the memory described in any one of the foregoing claims.

[0021] In the embodiments of this disclosure, the memory responds to a first self-test instruction to perform self-tests on the first error correction code engine and the second error correction code engine, obtaining a first self-test result. If the first self-test result is the first result, the first error correction code engine acquires the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain first output data, a second error correction code corresponding to the first output data, and a first flag bit. The second error correction code engine performs error correction processing on the first output data and the second error correction code to obtain a second flag bit. If both the first flag bit and the second flag bit satisfy a first preset condition, the first output data is output from the memory interface of the memory. The first result indicates that both the first and second error correction code engines are working normally. This disclosure, by performing self-tests on the first and second error correction code engines, ensures that both engines operate in a fault-free state, can promptly detect problems in data transmission, ensures the functional safety of the memory, and improves the reliability of the memory operation. In addition, the first error correction code engine and the second error correction code engine work in sequence, that is, the original data is processed twice for error correction. When both the first flag bit and the second flag bit meet the first preset condition, the first output data is output from the memory interface of the memory. The two error correction processes can further improve the accuracy of the first output data.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] Figure 1 This diagram illustrates a flowchart of a memory operation method according to an embodiment of the present disclosure;

[0025] Figure 2 A flowchart of a memory operation method according to another embodiment of this disclosure is shown;

[0026] Figure 3 A flowchart of a memory operation method is shown in another embodiment of this disclosure;

[0027] Figure 4 A flowchart of a memory operation method in yet another embodiment of this disclosure is shown;

[0028] Figure 5 A flowchart of a memory operation method in yet another embodiment of this disclosure is shown;

[0029] Figure 6 This diagram shows a structural block diagram of a memory according to an embodiment of the present disclosure;

[0030] Figure 7 A block diagram of the memory structure is shown in another embodiment of this disclosure;

[0031] Figure 8 This diagram shows a structural block diagram of a memory according to another embodiment of the present disclosure;

[0032] Figure 9 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0033] Figure 10 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0034] Figure 11 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0035] Figure 12 This diagram illustrates the switching of operating modes in an embodiment of the present disclosure.

[0036] Figure 13 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0037] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0039] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0040] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0041] It should be noted that the terms “one” and “multiple” used in this disclosure are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as “one or more”, where “multiple” means two or more.

[0042] Memory is a storage component used to store programs and various data information. Based on its usage type, memory can be divided into Read Only Memory (ROM) and Random Access Memory (RAM). ROM can include Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), and Flash memory. Flash memory includes NOR flash memory and NAND flash memory.

[0043] In related technologies, ECC engines are typically used as functional safety mechanisms to ensure the correctness of memory during data transmission. ECC engines can correct and detect errors that occur during data transmission, thereby ensuring that the original data can be recovered or that error warnings are issued to the system in the event of data corruption, thus improving the reliability and security of the system.

[0044] However, when the ECC engine malfunctions, it may cause data transmission to fail to correct errors correctly or result in false errors and false alarms, leading to functional safety issues. Specifically, if errors are not corrected in time or false alarms are generated, the system may mistakenly believe that data transmission is normal, causing subsequent operations to rely on corrupted data and affecting the overall functionality of the system. Therefore, the reliability of the ECC engine is crucial; a malfunction can lead to serious functional failures, affecting the security and stability of the entire system.

[0045] To address the aforementioned problems, this disclosure provides a memory operation method applicable to the memory field. For example, the memory operation method of this disclosure can be applied to non-volatile memory, and also to other types of memory; this disclosure does not limit its application in this regard. The memory operation method includes: responding to a first self-test instruction, performing a self-test on a first error correction code engine 61 and a second error correction code engine 62 to obtain a first self-test result; if the first self-test result is the first result, the first error correction code engine 61 acquires the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain first output data, a second error correction code corresponding to the first output data, and a first flag bit; the second error correction code engine 62 performs error correction processing on the first output data and the second error correction code to obtain a second flag bit; if both the first flag bit and the second flag bit satisfy a first preset condition, outputting the first output data from the memory interface 63 of the memory; wherein, the first result is that both the first error correction code engine 61 and the second error correction code engine 62 are working normally. This disclosure ensures that the first error correction engine 61 and the second error correction engine 62 operate in a fault-free state by performing self-tests on them. This allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving its operational reliability. Furthermore, the first and second error correction engines 61 and 62 operate serially, meaning that the original data undergoes two error correction processes. Only when both the first and second flag bits meet the first preset condition is the first output data output from the memory interface 63. These two error correction processes further improve the accuracy of the first output data.

[0046] This disclosure provides a memory operation method, which can be executed by any electronic device with computing capabilities. For example, an electronic device with computing capabilities can be a memory. The following description uses a memory as an example.

[0047] Figure 1 This diagram illustrates a flowchart of a memory operation method according to an embodiment of the present disclosure. The memory of the present disclosure includes a first error correction engine 61 and a second error correction engine 62, as shown below. Figure 1 As shown, the memory operation method provided in this embodiment may include the following S102 and S1041.

[0048] S102, in response to the first self-test instruction, performs a self-test on the first error correction code engine 61 and the second error correction code engine 62, and obtains the first self-test result.

[0049] In this embodiment of the disclosure, the first self-test instruction is an instruction used to instruct the first error correction code engine 61 and the second error correction code engine 62 to perform a self-test.

[0050] For example, the system sends a first self-test instruction to the memory. After receiving the first self-test instruction, the memory generates self-test data (such as random data and error correction data as described below). The first error correction code engine 61 and the second error correction code engine 62 are self-tested using the self-test data, which can ensure that the first error correction code engine 61 and the second error correction code engine 62 perform error correction processing on the data (such as the original data) under normal working conditions.

[0051] It should be noted that the system side can be a microcontroller or a processor. The ECC (Error-Correcting Code Engine) is used to perform error detection and correction functions, especially in data storage and transmission. The ECC engine is usually used in conjunction with Error Correction Code (ECC) to ensure that the system can effectively detect and repair errors that may occur during data transmission or storage.

[0052] S1041, if the first self-test result is the first result, the first error correction engine 61 obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain the first output data, the second error correction code corresponding to the first output data, and the first flag bit; the second error correction engine 62 performs error correction processing on the first output data and the second error correction code to obtain the second flag bit; if both the first flag bit and the second flag bit satisfy the first preset condition, the first output data is output from the memory interface 63 of the memory; wherein, the first result is that both the first error correction engine 61 and the second error correction engine 62 are working normally.

[0053] In this embodiment of the disclosure, the first error correction code is used to detect and correct errors that occur during the original data transmission or storage process, and the second error correction code is used to detect and correct errors that occur during the first output data transmission or storage process.

[0054] In this embodiment of the disclosure, the original data can be data stored on a memory array. Before storage, a first error correction code (the correct error correction code) is calculated using an encoding algorithm, and the first error correction code is also stored on the memory array. The first error correction engine 61 can obtain the original data and the first error correction code from the memory array, and perform error correction processing on the original data according to the first error correction code. Similarly, a second error correction code can be calculated based on the first output data.

[0055] The specific methods for obtaining the first and second error correction codes are not limited in the embodiments of this disclosure. For example, the original data can be encoded using an encoding algorithm (such as Hamming code) to obtain the first error correction code. As another example, the first output data can be encoded using an encoding algorithm (such as low-density parity-checking code, Reed-Solomon code, etc.) to obtain the second error correction code. It should be noted that if the original data is error-free, the first output data is the same as the original data; similarly, the second error correction code is the same as the first error correction code.

[0056] In this embodiment of the disclosure, the first error correction code can be an ECC, and the second error correction code can also be an ECC. ECC adds redundant information to the data so that when an error occurs during data transmission or storage, the first error correction engine 61 and the second error correction engine 62 can detect and correct the error.

[0057] In this embodiment, the first flag bit is used to indicate whether a single-bit error has occurred in the original data and to correct it, and whether a two-bit error has been detected in the original data. The second flag bit is used to indicate whether a single-bit error has occurred in the first output data and to correct it, and whether a two-bit error has been detected in the first output data. It should be noted that if two or more bit errors exist, it indicates that the memory is in an unsafe state and an alarm needs to be triggered.

[0058] In one embodiment, both the first and second flag bits are represented by two-bit values. For example, a first flag bit of "00" indicates that the original data is correct. Specifically, a "0" in the first bit indicates that the original data has no errors, and a "0" in the second bit indicates that there are no errors of two or more bits in the original data. As another example, a first flag bit of "10" indicates that a 1-bit error occurred in the original data, and the first error correction engine 61 has successfully corrected the error; there are no errors of two or more bits in the original data. Here, a "1" in the first bit indicates that a 1-bit error existed in the original data, and the first error correction engine 61 has successfully corrected the error. A "0" in the second bit indicates that there are no errors of two or more bits in the original data.

[0059] Similarly, the second flag bit functions similarly to the first flag bit. For example, a second flag bit of "00" indicates that the first output data is correct. Specifically, a "0" in the first bit indicates that the first output data has no error, and a "0" in the second bit indicates that there are no errors of two or more bits in the first output data. As another example, a second flag bit of "10" indicates that a 1-bit error occurred in the first output data, and the second error correction engine 62 has successfully corrected the error. Here, a "1" in the first bit indicates that a 1-bit error existed in the first output data, and the second error correction engine 62 has successfully corrected the error. A "0" in the second bit indicates that there are no errors of two or more bits in the first output data.

[0060] In this embodiment, the first preset condition is used to determine the accuracy of the first output data. If both the first flag bit and the second flag bit satisfy the first preset condition, it indicates that the first output data is correct, and the first output data is output from the memory interface 63 of the memory. For example, the first preset condition is that the flag bit is "10" or "00". If the first flag bit is "10" or "00" and the second flag bit is "10" or "00", it indicates that both the first flag bit and the second flag bit satisfy the first preset condition. Otherwise, the first preset condition is not satisfied.

[0061] This disclosure uses a first flag bit and a second flag bit to determine whether the first output data has an error, enabling rapid and accurate identification of data error states. Furthermore, through feedback from the error correction engine, it can effectively detect and correct errors in single bits, avoiding complex error handling processes. This disclosure improves the reliability and accuracy of data transmission while reducing reliance on external detection and error correction methods, thus enhancing system stability.

[0062] In another embodiment, the first flag bit may include a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit may include a second single-bit repair flag bit and a second double-bit detection flag bit; both the first single-bit repair flag bit and the second single-bit repair flag bit are used to indicate the detection and repair of a single-bit error in the original data; both the first double-bit detection flag bit and the second double-bit detection flag bit are used to indicate whether a two-bit error is detected in the original data or the first output data. That is, the first double-bit detection flag bit is used to indicate whether a two-bit error is detected in the original data, and the second double-bit detection flag bit is used to indicate whether a two-bit error is detected in the first output data.

[0063] For example, the first single-bit correction flag can be a single-bit error correction (SEC) flag, denoted by SEC1. The first double-bit detection flag can be a double-bit error detection (DEC) flag, denoted by DEC1. Similarly, the second single-bit correction flag can be a single-bit error correction flag, denoted by SEC2. The second double-bit detection flag can be a double-bit error detection flag, denoted by DEC2.

[0064] When SEC1,DED1 = 2'b00 and SEC2,DED2 = 2'b00, the system is safe, indicating that the original data in the storage array has not been corrupted and the memory interface 63 can output data correctly (first output data).

[0065] When SEC1,DED1 = 2'b10 and SEC2,DED2 = 2'b00, the system is safe, indicating that a 1-bit error has occurred in the original data in the storage array. The first error correction engine 61 performs 1-bit error correction, and the memory interface 63 can output data correctly.

[0066] It should be noted that other conditions of the first and second flag bits indicate that the data (raw data or first output data) has an error greater than 1 bit, or that the ECC engine has malfunctioned. At this time, the system is in an unsafe state and will generate an alarm signal. The alarm signal will be output to the memory interface 63 or sent to the functional safety register 66 (a register in the memory of this disclosure). The system can obtain the alarm signal by sampling the alarm memory interface 63 or reading the functional safety register 66.

[0067] For example, the memory may also include a functional safety register 66; the memory interface 63 and / or the functional safety register 66 are used to receive the alarm signal, which indicates that both the first error correction engine 61 and the second error correction engine 62 have failed.

[0068] It should be noted that the alarm signal generated by the failure of both the first error correction code engine 61 and the second error correction code engine 62 is different from the alarm signal generated by the data having an error greater than 1 bit. The cause of the failure can be distinguished based on the different alarm signals.

[0069] This disclosure uses a first single-bit repair flag, a first double-bit detection flag, a second single-bit repair flag, and a second double-bit detection flag to determine whether the first output data has an error. This allows for rapid and accurate identification of data errors. Furthermore, through feedback from the error correction engine, it effectively detects and corrects errors in single bits, avoiding complex error handling processes. This disclosure improves the reliability and accuracy of data transmission while reducing reliance on external detection and error correction methods, thus enhancing system stability.

[0070] In this embodiment of the disclosure, memory interface 63 is an interface for the memory to output data. The specific type of interface 63 is not limited in this disclosure. For example, memory interface 63 can be an input / output pin (IO pin) of the memory.

[0071] This embodiment of the disclosure performs self-tests on the first error correction engine 61 and the second error correction engine 62, thereby ensuring that the first error correction engine 61 and the second error correction engine 62 operate in a fault-free state. This allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving the reliability of the memory operation. Furthermore, the first error correction engine 61 and the second error correction engine 62 operate serially, meaning that the original data undergoes two error correction processes. Only when both the first flag bit and the second flag bit meet the first preset condition is the first output data output from the memory interface 63. These two error correction processes further improve the accuracy of the first output data.

[0072] The following is an explanation of how to implement self-checks for the first error correction engine 61 and the second error correction engine 62.

[0073] In an exemplary embodiment, such as Figure 2 As shown, in the memory operation method provided in this disclosure, in response to the first self-test instruction, the first error correction code engine 61 and the second error correction code engine 62 are self-tested, and the first self-test result can include the following S1021 to S1024.

[0074] S1021, in response to the first self-test instruction, generates random data and the third error correction code corresponding to the random data, and performs error injection processing on the random data to obtain error data.

[0075] In this embodiment of the disclosure, the first self-test instruction is an instruction to perform a self-test on the first error correction code engine 61 and the second error correction code engine 62. The random data can be a random vector.

[0076] The system issues a first self-test command based on the detection requirements. For example, the system issues a first self-test command to the memory at regular intervals. For instance, the system issues a first self-test command to the memory every 5 minutes. As another example, when the system samples an alarm signal at memory interface 63 or reads an alarm signal from functional safety register 66, it will immediately issue a first self-test command until both the first error correction code engine 61 and the second error correction code engine 62 fail.

[0077] In this embodiment of the disclosure, there are no limitations on how to perform error injection processing on random data, as long as the processing can cause errors in the random data. For example, errors can be generated in the random data according to the number of error-generating bits and the position of the error-generating bit sent by the first self-test instruction. For example, if the random data is [1 0 0 0], error injection processing on the random data can result in error data [0 0 0 0].

[0078] The method for obtaining the third error correction code based on random data is the same as the method for obtaining the first error correction code based on the original data, and will not be described again here.

[0079] S1022, the first error correction engine 61 performs error correction processing on the third error correction code and the error data to obtain the first flag bit.

[0080] S1023, the second error correction engine 62 performs error correction processing on the third error correction code and the error data to obtain the second flag bit.

[0081] It should be noted that the error correction processing in S1022 and S1023 is similar to the error correction processing in S204, and will not be described again here.

[0082] S1024, verify the first flag bit and the second flag bit to obtain the first self-test result.

[0083] In this embodiment of the disclosure, the first self-test result belongs to one of the first result, the second result, the third result, and the fourth result. The first result is that both the first error correction code engine 61 and the second error correction code engine 62 are working normally; the second result is that the second error correction code engine 62 is working normally, but the first error correction code engine 61 malfunctions; the third result is that both the first error correction code engine 61 and the second error correction code engine 62 malfunction; and the fourth result is that the first error correction code engine 61 is working normally, but the second error correction code engine 62 malfunctions.

[0084] This embodiment of the disclosure performs self-tests on the first error correction engine 61 and the second error correction engine 62, thereby ensuring that the first error correction engine 61 and the second error correction engine 62 operate in a fault-free state. This can promptly detect problems in data transmission, ensure the functional safety of the memory, and improve the reliability of the memory operation.

[0085] The following three exemplary embodiments illustrate the case where the first self-test result is the second result, the third result, and the fourth result, respectively.

[0086] In one exemplary embodiment, such as Figure 3 As shown, after S102, the memory operation method provided in this disclosure may further include S1042.

[0087] S1042, if the first self-test result is the second result, the first error correction engine 61 is turned off, the second error correction engine 62 obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain the second output data and the second flag bit; if the second flag bit satisfies the second preset condition, the second output data is output from the memory interface 63 of the memory; wherein, the second result is that the second error correction engine 62 is working normally and the first error correction engine 61 has failed.

[0088] In this embodiment, due to a malfunction of the first error correction engine 61, in order to improve the accuracy of the second output data, the first error correction engine 61 is shut down, and the second error correction engine 62 performs error correction processing on the original data based on the first error correction code. That is, when the first error correction engine 61 malfunctions, it is short-circuited, and the second error correction engine 62 enters the data output path.

[0089] In this embodiment, the second flag bit includes a second single-bit repair flag bit (SEC2) and a second double-bit detection flag bit (DED2). The second preset condition is a condition used to determine the accuracy of the second output data. If the second flag bit meets the second preset condition, it indicates that the second output data is correct, and the second output data is output from the memory interface 63 of the memory.

[0090] For example, when SEC2,DED2 = 2'b00, the system is safe, that is, the second flag bit meets the second preset condition, indicating that the original data in the storage array has not been erroneous, and the memory interface 63 can correctly output data (second output data);

[0091] When SEC2,DED2 = 2'b10, the system is safe. That is, the second flag bit meets the second preset condition, indicating that a 1-bit error has occurred in the original data in the storage array. The second error correction engine 62 performs 1-bit error correction, and the memory interface 63 can output data correctly.

[0092] It should be noted that other conditions of the second flag bit indicate that the data has an error greater than 1 bit, or that the second error correction code engine 62 has malfunctioned. At this time, the system is in an unsafe state and will generate an alarm signal, which will be output to the memory interface 63 or stored in the functional safety register 66. The system can obtain the alarm signal by sampling the memory interface 63 or reading the functional safety register 66.

[0093] In this embodiment of the present disclosure, when the first error correction engine 61 fails, the state in which the first error correction engine 61 and the second error correction engine 62 work simultaneously is switched to the state in which the second error correction engine 62 works alone, thereby ensuring the accuracy of the output data and improving the reliability and security of the system.

[0094] In one embodiment, the memory operation method provided in this disclosure may further include: when the first error correction code engine 61 is turned off, in response to a second self-test instruction, performing a self-test on the second error correction code engine 62 to obtain a second self-test result; when the second self-test result is a third result, generating an alarm signal and turning off the second error correction code engine 62, wherein the third result is that both the first error correction code engine 61 and the second error correction code engine 62 have failed.

[0095] In this embodiment, the second self-test instruction is an instruction to perform a self-test on the second error correction code engine 62. With the first error correction code engine 61 disabled, the system issues the second self-test instruction according to detection requirements. For example, the system issues the second self-test instruction to the memory at regular intervals. For instance, the system issues the second self-test instruction to the memory every minute. As another example, when the system samples an alarm signal at the memory interface 63 or reads an alarm signal from the functional safety register 66, it immediately issues a second self-test instruction until both the first and second error correction code engines 61 and 62 fail. It should be noted that only the second error correction code engine 62 is active when the second self-test instruction is issued. Therefore, the interval between issuing the second self-test instruction is shorter than the interval between issuing the first self-test instruction. Shortening the time interval for sending self-test instructions allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving the reliability of memory operation.

[0096] The method for performing a self-test on the second error correction engine 62 in this embodiment is similar to that in S102, and will not be repeated here.

[0097] In the event of a failure in the first error correction engine 61, the second error correction engine 62 is self-tested. This allows for timely detection of faults in the second error correction engine 62, thereby identifying problems in data transmission, ensuring the functional safety of the memory, and improving the reliability of the memory operation.

[0098] In another exemplary embodiment, such as Figure 4 As shown, after S102, the memory operation method provided in this disclosure may further include S1043.

[0099] S1043, if the first self-test result is the third result, shut down the first error correction code engine 61 and the second error correction code engine 62, generate an alarm signal, and the third result is that both the first error correction code engine 61 and the second error correction code engine 62 have failed.

[0100] In one embodiment, the first self-test result determines the status of the first error correction code engine 61 and the second error correction code engine 62 using a first flag bit and a second flag bit. The first flag bit may include a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit may include a second single-bit repair flag bit and a second double-bit detection flag bit; both the first single-bit repair flag bit and the second single-bit repair flag bit are used to indicate the detection and repair of a single bit error in the original data; both the first double-bit detection flag bit and the second double-bit detection flag bit are used to indicate whether a two-bit error is detected in the original data or the first output data.

[0101] For example, the first single-bit repair flag can be used for single-bit error repair, denoted by SEC1. The first double-bit detection flag can be used for double-bit error detection, denoted by DEC1. Similarly, the second single-bit repair flag can be used for single-bit error repair, denoted by SEC2. The second double-bit detection flag can be used for double-bit error detection, denoted by DEC2.

[0102] It should be noted that when SEC1,DED1 = 2'b00 or SEC1,DED1 = 2'b10, it indicates that the first error correction engine 61 is not malfunctioning; otherwise, it indicates that the first error correction engine 61 has malfunctioned. When SEC2,DED2 = 2'b00 or SEC2,DED2 = 2'b10, it indicates that the second error correction engine 62 is not malfunctioning; otherwise, it indicates that the second error correction engine 62 has malfunctioned.

[0103] In one embodiment, if both the first error correction engine 61 and the second error correction engine 62 fail, the functional safety register 66 will issue an alarm, both engines will be shut down, and the data in the storage array will be directly output without being processed by the first error correction engine 61 and the second error correction engine 62.

[0104] This embodiment of the disclosure improves the reliability of the output data by performing self-checks on the first error correction engine 61 and the second error correction engine 62, which can promptly detect their faults and quickly shut down the corresponding engines, while triggering alarm processing.

[0105] In yet another exemplary embodiment, such as Figure 5 As shown, after S102, the memory operation method provided in this disclosure may further include S1044.

[0106] S1044, if the first self-test result is the fourth result, the second error correction engine 62 is turned off, the first error correction engine 61 obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain the third output data and the first flag bit; if the first flag bit meets the third preset condition, the third output data is output from the memory interface 63 of the memory; wherein, the fourth result is that the first error correction engine 61 is working normally and the second error correction engine 62 has failed.

[0107] In this embodiment, due to a malfunction of the second error correction engine 62, in order to improve the accuracy of the third output data, the second error correction engine 62 is shut down, and the first error correction engine 61 performs error correction processing on the original data based on the first error correction code. That is, when the second error correction engine 62 malfunctions, it is short-circuited, and the first error correction engine 61 enters the data output path.

[0108] In this embodiment of the disclosure, the first flag bit is the first single-bit repair flag bit (SEC1) and the first double-bit detection flag bit (DED1). The third preset condition is a condition used to determine the accuracy of the third output data. If the first flag bit meets the third preset condition, it indicates that the third output data is correct, and the third output data is output from the memory interface 63 of the memory.

[0109] In one embodiment, a fault is detected in the second error correction engine 62 during self-testing, and the fault information is sent to the functional safety register 66. The second error correction engine 62 is turned off, and the original data in the storage array and the first error correction code are processed by the first error correction engine 61. The resulting third output data is then output to the memory interface 63 of the memory (e.g., a chip I / O pin).

[0110] When SEC1,DED1 = 2'b00, the system is safe. That is, the first flag bit meets the third preset condition, indicating that the original data in the storage array has not been erroneous and the memory interface 63 can output data correctly.

[0111] When SEC1,DED1=2'b10, the system is safe. That is, the first flag bit meets the third preset condition, indicating that a 1-bit error has occurred in the original data in the storage array. The first error correction engine 61 performs 1-bit error correction, and the memory interface 63 can output data correctly.

[0112] It should be noted that other conditions of the first flag bit indicate that the data has an error greater than 1 bit, or that the first error correction code engine 61 has malfunctioned. At this time, the system is in an unsafe state and will generate an alarm signal, which will be output to the memory interface 63 or sent to the functional safety register 66. The system can obtain the alarm signal by sampling the memory interface 63 or reading the safety management register.

[0113] In this embodiment of the present disclosure, when the second error correction engine 62 fails, the state in which the first error correction engine 61 and the second error correction engine 62 work simultaneously is switched to the state in which the first error correction engine 61 works alone, thereby ensuring the accuracy of the output data and improving the reliability and security of the system.

[0114] In one embodiment, the memory operation method provided in this disclosure may further include: when the second error correction code engine 62 is turned off, in response to a third self-test instruction, performing a self-test on the first error correction code engine 61 to obtain a third self-test result; when the third self-test result is a third result, generating an alarm signal and turning off the first error correction code engine 61, wherein the third result is that both the first error correction code engine 61 and the second error correction code engine 62 have failed.

[0115] In this embodiment, the third self-test instruction is an instruction to perform a self-test on the first error correction code engine 61. With the second error correction code engine 62 disabled, the system issues a third self-test instruction according to detection requirements. For example, the system issues a third self-test instruction to the memory at regular intervals. For instance, the system issues a third self-test instruction to the memory every minute. As another example, when the system samples an alarm signal at the memory interface 63 or reads an alarm signal from the functional safety register 66, it immediately issues a third self-test instruction until the first error correction code engine 61 also fails. It should be noted that only the first error correction code engine 61 is working when the third self-test instruction is issued. Therefore, the interval between issuing the third self-test instruction is shorter than the interval between issuing the first self-test instruction. Shortening the time interval for sending self-test instructions allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving the reliability of memory operation.

[0116] The method for performing a self-test on the first error correction code engine 61 in this embodiment is similar to that in S102, and will not be repeated here.

[0117] In the event of a failure of the second error correction engine 62, the first error correction engine 61 is self-tested, which can promptly detect the failure of the first error correction engine 61, thereby promptly identifying problems in data transmission, ensuring the functional safety of the memory, and improving the reliability of the memory operation.

[0118] Based on the same inventive concept, this disclosure also provides a memory, as described in the following embodiments. Since the principle by which this memory embodiment solves the problem is similar to that of the above-described method embodiments, the implementation of this memory embodiment can refer to the implementation of the above-described method embodiments, and repeated details will not be elaborated further.

[0119] Figure 6 This diagram illustrates a structural block diagram of a memory according to an embodiment of the present disclosure, as follows: Figure 6 As shown, a memory provided in this disclosure may include a first error correction code engine 61, a second error correction code engine 62, a memory interface 63, and a functional safety diagnostic module 64.

[0120] In one embodiment, the first error correction engine 61 can be used to obtain the original data stored in the memory and the first error correction code corresponding to the original data when the first self-test result is the first result, and perform error correction processing on the original data and the first error correction code to obtain the first output data, the second error correction code corresponding to the first output data, and the first flag bit; the second error correction engine 62 can be used to perform error correction processing on the first output data and the second error correction code when the first self-test result is the first result to obtain the second flag bit; the functional safety diagnostic module 64 can be used to verify whether the first flag bit and the second flag bit meet the first preset condition, so that when both the first flag bit and the second flag bit meet the first preset condition, the first output data is output from the memory interface 63 of the memory; wherein, the first self-test result is obtained by performing a self-test on the first error correction engine 61 and the second error correction engine 62 in response to the first self-test instruction.

[0121] In one embodiment, the first error correction code engine 61 can also be used to obtain the original data stored in the memory and the first error correction code corresponding to the original data when the first self-test result is the fourth result, and perform error correction processing on the original data and the first error correction code to obtain the third output data and the first flag bit; the functional safety diagnostic module 64 is also used to verify the first flag bit so that when the first flag bit meets the third preset condition, the third output data is output from the memory interface 63 of the memory.

[0122] In one embodiment, the second error correction code engine 62 can also be used to obtain the original data stored in the memory and the first error correction code corresponding to the original data when the first self-test result is the second result, and perform error correction processing on the original data and the first error correction code to obtain the second output data and the second flag bit; the functional safety diagnostic module 64 can also be used to verify the second flag bit so that when the second flag bit meets the second preset condition, the second output data is output from the memory interface 63 of the memory.

[0123] The memory disclosed in this embodiment performs self-tests on the first error correction engine 61 and the second error correction engine 62, thereby ensuring that the first error correction engine 61 and the second error correction engine 62 operate in a fault-free state. This allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving the reliability of the memory operation.

[0124] Furthermore, the first error correction engine 61 and the second error correction engine 62 can work in sequence. That is, the original data is processed twice for error correction. When both the first flag bit and the second flag bit meet the first preset condition, the first output data is output from the memory interface 63 of the memory. The two error correction processes can further improve the accuracy of the first output data.

[0125] Furthermore, when one of the first error correction code engine 61 and the second error correction code engine 62 fails, the other can still function normally. In other words, path replacement can be achieved, ensuring data security and significantly improving the reliability and security of the system.

[0126] In one embodiment, such as Figure 7 As shown, dashed lines represent unused paths, and solid lines represent used paths. The memory may also include a self-test data fault injection module 65. This module 65 can respond to a first self-test command by generating random data and a corresponding third error correction code, and performing error injection processing on the random data to obtain erroneous data. It should be noted that the self-test data fault injection module 65 may include a random generator to generate random data. Alternatively, multiple pre-set selectable data can be stored in the self-test data fault injection module 65. After receiving the first self-test command, it randomly selects one data point from the selectable data as the random data. This embodiment does not specifically limit how the random data is generated.

[0127] The first error correction code engine 61 can also be used to perform error correction processing on the third error correction code and the error data to obtain the first flag bit; the second error correction code engine 62 can also be used to perform error correction processing on the third error correction code and the error data to obtain the second flag bit; the functional safety diagnostic module 64 can be used to verify the first flag bit and the second flag bit to obtain the first self-test result.

[0128] In one embodiment, the memory further includes a functional safety register 66; the functional safety register 66 is used to: disable the first error correction engine 61 if the first self-test result is a second result; disable the second error correction engine 62 if the first self-test result is a fourth result; disable both the first error correction engine 61 and the second error correction engine 62 if the first self-test result is a third result; wherein the second result is that the second error correction engine 62 is working normally and the first error correction engine 61 has failed; the third result is that both the first error correction engine 61 and the second error correction engine 62 have failed; and the fourth result is that the first error correction engine 61 is working normally and the second error correction engine 62 has failed.

[0129] In this embodiment of the disclosure, by sending the first self-test result to the functional safety register 66, the functional safety register 66 can shut down the first error correction engine 61 and / or the second error correction engine 62 that has malfunctioned, depending on the status of the first error correction engine 61 and the second error correction engine 62.

[0130] In this embodiment, the first flag bit may include a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit may include a second single-bit repair flag bit and a second double-bit detection flag bit; both the first single-bit repair flag bit and the second single-bit repair flag bit are used to indicate the detection and repair of a single bit error in the original data; both the first double-bit detection flag bit and the second double-bit detection flag bit are used to indicate whether a two-bit error is detected in the original data or the first output data. That is, the first double-bit detection flag bit is used to indicate whether a two-bit error is detected in the original data, and the second double-bit detection flag bit is used to indicate whether a two-bit error is detected in the first output data. The first flag bit and the second flag bit can be used to determine the fault status of the first error correction engine 61 and the second error correction engine 62.

[0131] The memory in this disclosure uses a first flag bit and a second flag bit to determine whether an error has occurred in the first output data. This enables rapid and accurate identification of data error states. Furthermore, through feedback from the error correction engine, it can effectively detect and correct errors in single bits, avoiding complex error handling processes. This disclosure improves the reliability and accuracy of data transmission while reducing reliance on external detection and error correction methods, thus enhancing system stability.

[0132] The memory disclosed herein uses four operating modes, which are described below through four exemplary embodiments. This disclosure also enables switching between the four operating modes.

[0133] In one exemplary embodiment, such as Figure 8 As shown, solid lines represent the currently used data paths, while dashed lines represent paths that exist but are not currently in use. No faults were found in the first error correction engine 61 and the second error correction engine 62 during the previous self-test. In other words, the state where both the first error correction engine 61 and the second error correction engine 62 are functioning normally is defined as Mode 1.

[0134] The raw data in the storage array and the first error correction code are corrected by the first error correction engine 61 to obtain the first output data, the second error correction code, SEC1, and DEC1. The first output data is output to the memory interface 63, and simultaneously sent to the second error correction engine 62. The corrected second error correction code is also sent to the second error correction engine 62. The generated SEC1 (correction 1 flag) and DEC1 (detection 2 flag) are sent to the functional safety diagnostic module 64. The second error correction engine 62 performs secondary ECC error correction on the second error correction code and the first output data, and sends the generated SEC2 and DEC2 to the functional safety diagnostic module 64. The functional safety diagnostic module 64 diagnoses the values ​​of the four flag signals SEC1, DEC1, SEC2, and DEC2.

[0135] When SEC1,DED1 = 2'b00 and SEC2,DED2 = 2'b00, the first preset condition is met, indicating that the system is safe and that no errors have occurred in the original data in the storage array, and the memory interface 63 can output data correctly.

[0136] When SEC1,DED1 = 2'b10 and SEC2,DED2 = 2'b00, the first preset condition is met, the system is safe, indicating that a 1-bit error has occurred in the original data in the storage array, the first error correction engine 61 has performed 1-bit error correction, and the memory interface 63 can output data correctly.

[0137] When SEC1, DED1, SEC2, and DED2 are values ​​other than those mentioned above (2'b10 and 2'b00), it indicates that the first preset condition is not met. If the first preset condition is not met, it indicates that the original data has an error greater than 1 bit, or that the ECC engine has malfunctioned. At this time, the system is in an unsafe state and will generate an alarm signal. The alarm signal will be output to the memory interface 63 (not shown in the figure) or sent to the functional safety register 66. The system can perform the judgment by sampling the memory interface 63 or reading the functional safety register 66.

[0138] In another exemplary embodiment, such as Figure 9 As shown, solid lines represent currently used data paths, while dashed lines represent paths that exist but are not currently in use. The state of self-testing the first error correction engine 61 and the second error correction engine 62 is defined as mode two (self-test mode). When the system needs to perform a test, it sends a self-test command (such as the first self-test command), and the memory enters mode two.

[0139] After the system sends a self-test command, the self-test data fault injection module 65 generates random data and a corresponding third error correction code. The random data can be a data vector, with its length consistent with the granularity of the built-in ECC engine algorithm (e.g., the first error correction engine 61 and the second error correction engine 62). Errors are generated in the vector according to the number of error-generating bits and the location specified in the self-test command, resulting in erroneous data. The first and second error correction engines 61 and 62 perform error correction and detection on the erroneous data, generating ECC status bits SEC1, DED1, SEC2, and DED2. The functional safety diagnostic module 64 verifies the ECC status bits generated by these two engines. When the generated ECC status bit differs from the expected value, it indicates that the engine's error correction or detection behavior cannot be correctly reported. In this case, the system is in an unsafe state, generating an alarm signal that is output to the memory interface 63 or sent to the functional safety register 66. The system can then determine the status by sampling the memory interface 63 or reading the functional safety register 66.

[0140] If both ECC engines are functioning normally (i.e., the first result), the memory continues to operate in mode one. It should be noted that the system can perform self-tests on the ECC engines as needed. For example, the system can perform periodic self-tests, such as entering self-test mode every 5 minutes. Another example is entering self-test mode when a testing requirement arises by sending a self-test command.

[0141] If one of the two ECC engines fails, the memory will short-circuit the failed ECC engine, and memory interface 63 will switch to the other working ECC engine. See Mode 3 and Mode 4 for specific operating modes.

[0142] If both ECC engines fail, Function Safety Register 66 will trigger an alarm, both ECC engines will be shut down, and data on the storage array will be output directly without undergoing error correction processing by the ECC engines.

[0143] In yet another exemplary embodiment, such as Figure 10 As shown, solid lines represent the currently used data paths, while dashed lines represent paths that exist but are not currently in use. The state where the first error correction engine 61 malfunctions and the second error correction engine 62 operates normally is defined as mode three.

[0144] During self-testing, a fault was found in the first error correction engine 61. The first error correction engine 61 was short-circuited, and the second error correction engine 62 entered the data output path.

[0145] The functional safety diagnostic module 64 detects a fault in the first error correction code engine 61 and sends the fault information to the functional safety register 66. The first error correction code engine 61 shuts down. The original data and the first error correction code in the storage array are processed by the second error correction code engine 62, and then the second output data, SEC2, and DEC2 are output. The second output data is then output to the memory interface 63. It should be noted that when the original data is error-free, the second output data is the same as the original data. SEC2 and DEC2 are sent to the functional safety diagnostic module 64. The functional safety diagnostic module 64 diagnoses the values ​​of the SEC2,DED2 flag signals. The second preset condition is SEC2,DED2 = 2'b00 or SEC2,DED2 = 2'b10.

[0146] When SEC2,DED2=2'b00, the second preset condition is met, the system is safe, indicating that the original data in the storage array has not been corrupted, and the memory interface 63 can output data correctly;

[0147] When SEC2,DED2=2'b10, the second preset condition is met, the system is safe, indicating that a 1-bit error has occurred in the original data in the storage array, the second error correction engine 62 has performed 1-bit error correction, and the memory interface 63 can output data correctly.

[0148] When SEC2 and DEC2 are values ​​other than those mentioned above (2'b00 and 2'b10), it indicates that the second preset condition is not met. If the second preset condition is not met, it means that the original data has an error greater than 1 bit, or the second error correction code engine 62 has malfunctioned. At this time, the system is in an unsafe state and will generate an alarm signal. The alarm signal will be output to the memory interface 63 (not shown in the figure) or sent to the functional safety register 66. The system can perform a judgment by sampling the memory interface 63 or reading the functional safety register 66.

[0149] It should be noted that a self-check of the second error correction engine 62 is also required in mode 3 to facilitate the timely detection of faults in the second error correction engine 62.

[0150] In yet another exemplary embodiment, such as Figure 11 As shown, solid lines represent the currently used data paths, while dashed lines represent paths that exist but are not currently in use. The state where the second error correction engine 62 malfunctions and the first error correction engine 61 operates normally is defined as mode four.

[0151] During self-testing, a fault was found in the second error correction engine 62. The second error correction engine 62 was short-circuited, and it was no longer used for real-time dual protection.

[0152] The functional safety diagnostic module 64 detects a fault in the second error correction code engine 62 and sends the fault information to the functional safety register 66. The second error correction code engine 62 shuts down. The original data and the first error correction code in the storage array are processed by the first error correction code engine 61, and then the third output data, SEC1, and DEC1 are output. The third output data is then output to the memory interface 63. When the original data is error-free, the third output data is the same as the original data. SEC1 and DEC1 are sent to the functional safety diagnostic module 64. The functional safety diagnostic module 64 diagnoses the values ​​of the SEC1,DED1 flag signals. The third preset condition is SEC1,DED1 = 2'b00 or SEC1,DED1 = 2'b10.

[0153] When SEC1,DED1=2'b00, the third preset condition is met, the system is safe, indicating that the original data in the storage array has not been corrupted, and the memory interface 63 can output data correctly;

[0154] When SEC1,DED1=2'b10, the third preset condition is met, the system is safe, indicating that a 1-bit error has occurred in the original data in the storage array, the first error correction engine 61 performs 1-bit error correction, and the memory interface 63 can output data correctly.

[0155] When SEC1 and DED1 are values ​​other than those mentioned above (2'b00 and 2'b10), it indicates that the third preset condition is not met. If the third preset condition is not met, it means that the original data has an error greater than 1 bit, or the first error correction engine 61 has malfunctioned. At this time, the system is in an unsafe state and will generate an alarm signal. The alarm signal will be output to the memory interface 63 (not shown in the figure) or sent to the functional safety register 66. The system can perform a judgment by sampling the memory interface 63 or reading the functional safety register 66.

[0156] It should be noted that a self-check of the first error correction engine 61 is also required in mode four, so as to facilitate the timely detection of faults in the first error correction engine 61.

[0157] In summary, Mode 1, Mode 3, and Mode 4 are all normal working modes, while Mode 2 is a self-test mode entered when a self-test command is sent when there is a testing requirement.

[0158] like Figure 12 As shown, a dual-engine failure indicates that both the first error correction engine 61 and the second error correction engine 62 have failed. Engine 1 failure indicates a failure in the first error correction engine 61, and Engine 2 failure indicates a failure in the second error correction engine 62. Similarly, a dual-engine normal operation indicates that both the first error correction engine 61 and the second error correction engine 62 are functioning normally. Engine 1 normal operation indicates that the first error correction engine 61 is functioning normally, and Engine 2 normal operation indicates that the second error correction engine 62 is functioning normally.

[0159] Depend on Figure 12 It can be seen that Mode 1 and Mode 2 can work together. When Mode 1 and Mode 2 work together, if a dual-engine failure is detected, it means that the dual engines have failed. The raw data is directly output from memory interface 63 and an alarm warning is issued.

[0160] When Mode 1 and Mode 2 are working together, if a fault is detected in Engine 1, the system will switch from "Mode 1 and Mode 2 working together" to "Mode 3 and Mode 2 working together". When Mode 3 and Mode 2 are working together, if a fault is detected in Engine 2, it indicates that both engines have failed. The raw data will be output directly from memory interface 63 and an alarm warning will be issued.

[0161] When Mode 1 and Mode 2 are working together, if a fault is detected in Engine 2, the system will switch from "Mode 1 and Mode 2 working together" to "Mode 4 and Mode 2 working together". When Mode 4 and Mode 2 are working together, if a fault is detected in Engine 1, it indicates that both engines have failed. The raw data will be output directly from memory interface 63, and an alarm warning will be issued.

[0162] It should be noted that the memory integrates two ECC engines. When the system needs to detect faults, it directly sends commands to inject faults into the two ECC engines, detects the correctness of the ECC engine functions, prevents ECC engine failures from becoming latent faults, and greatly improves the reliability of the system.

[0163] Therefore, the memory disclosed herein is a functional safety mechanism with a two-level ECC engine, fault injection, and path replacement. This ensures that when any level of ECC engine fails, the system can quickly receive feedback and the faulty ECC engine can be short-circuited, while the memory continues to function normally, thus improving system reliability. In other words, the fault injection self-test for the first error correction engine 61 and the second error correction engine 62, as well as the fault injection self-test after path replacement, proposed in this disclosure can detect faults in each ECC engine. When one ECC engine fails, it is short-circuited, while the other normal ECC engine and the fault self-test still ensure data security, thereby significantly improving system reliability and security.

[0164] In addition, this disclosure also provides an electronic device. Figure 13 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure is shown. For example... Figure 13 As shown, the electronic device 1300 includes a memory. The memory can perform the above-described methods; the memory is described in the relevant sections of the embodiments of this disclosure and will not be repeated here. The memory can be combined with... Figures 6-11 The above embodiments illustrate any type of memory.

[0165] For example, electronic device 1300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, stylus, true wireless earbuds, car infotainment screen, car, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, and tablets. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0166] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. This disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions after understanding the spirit of this disclosure. Furthermore, for the sake of brevity, detailed descriptions of known technologies are omitted here.

[0167] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0168] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory operation method, characterized in that, The memory includes a first error correction code engine and a second error correction code engine, and the memory operation method includes: In response to the first self-test command, a self-test is performed on the first error correction code engine and the second error correction code engine to obtain the first self-test result; If the first self-test result is the first result, the first error correction code engine obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain first output data, a second error correction code corresponding to the first output data, and a first flag bit; the second error correction code engine performs error correction processing on the first output data and the second error correction code to obtain a second flag bit; if both the first flag bit and the second flag bit satisfy the first preset condition, the first output data is output from the memory interface of the memory. The first result indicates that both the first error correction code engine and the second error correction code engine are working normally.

2. The memory operation method according to claim 1, characterized in that, The step of responding to the first self-test instruction by performing a self-test on the first error correction code engine and the second error correction code engine to obtain a first self-test result includes: In response to the first self-test command, random data and a third error correction code corresponding to the random data are generated, and error injection processing is performed on the random data to obtain error data; The first error correction engine performs error correction processing on the third error correction code and the error data to obtain a first flag bit; The second error correction engine performs error correction processing on the third error correction code and the error data to obtain the second flag bit; The first flag bit and the second flag bit are verified to obtain the first self-test result.

3. The memory operation method according to claim 1, characterized in that, The method further includes: If the first self-test result is the second result, the first error correction code engine is turned off, the second error correction code engine obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain the second output data and the second flag bit; if the second flag bit satisfies the second preset condition, the second output data is output from the memory interface of the memory. The second result indicates that the second error correction engine is working normally, while the first error correction engine has malfunctioned.

4. The memory operation method according to claim 3, characterized in that, The method further includes: When the first error correction code engine is turned off, in response to the second self-test command, the second error correction code engine is self-tested to obtain the second self-test result. If the second self-test result is the third result, an alarm signal is generated and the second error correction code engine is shut down. The third result is that both the first error correction code engine and the second error correction code engine have failed.

5. The memory operation method according to claim 1, characterized in that, The method further includes: If the first self-test result is the fourth result, the second error correction code engine is turned off. The first error correction code engine obtains the original data stored in the memory and the first error correction code corresponding to the original data, and performs error correction processing on the original data and the first error correction code to obtain the third output data and the first flag bit. If the first flag bit satisfies the third preset condition, the third output data is output from the memory interface of the memory. The fourth result is that the first error correction engine is working normally, while the second error correction engine malfunctions.

6. The memory operation method according to claim 5, characterized in that, The method further includes: When the second error correction code engine is turned off, in response to the third self-test command, the first error correction code engine is self-tested to obtain the third self-test result. If the third self-test result is the third result, an alarm signal is generated and the first error correction code engine is shut down. The third result indicates that both the first error correction code engine and the second error correction code engine have failed.

7. The memory operation method according to claim 1, characterized in that, The method further includes: If the first self-test result is the third result, the first error correction code engine and the second error correction code engine are shut down, and an alarm signal is generated. The third result is that both the first error correction code engine and the second error correction code engine have failed.

8. The memory operation method according to any one of claims 4, 6 and 7, characterized in that, The memory also includes a functional safety register; The memory interface and / or the functional safety register are used to receive the alarm signal, which indicates that both the first error correction code engine and the second error correction code engine have failed.

9. The memory operation method according to any one of claims 1 to 7, characterized in that, The first flag bit includes a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit includes a second single-bit repair flag bit and a second double-bit detection flag bit. Both the first single-bit repair flag and the second single-bit repair flag are used to indicate the detection and repair of a single bit error in the original data; Both the first double-bit detection flag and the second double-bit detection flag are used to indicate whether a two-bit error is detected in the original data or the first output data.

10. A memory, characterized in that, include: The first error correction code engine is used to obtain the original data stored in the memory and the first error correction code corresponding to the original data when the first self-test result is the first result, and to perform error correction processing on the original data and the first error correction code to obtain the first output data, the second error correction code corresponding to the first output data and the first flag bit. The second error correction code engine is used to perform error correction processing on the first output data and the second error correction code when the first self-test result is the first result, to obtain the second flag bit; The functional safety diagnostic module is used to verify whether the first flag bit and the second flag bit meet the first preset condition, so that when both the first flag bit and the second flag bit meet the first preset condition, the first output data is output from the memory interface of the memory. The first self-test result is obtained by performing a self-test on the first error correction code engine and the second error correction code engine in response to the first self-test instruction.

11. The memory according to claim 10, characterized in that, The memory also includes: The self-test data fault injection module is used to respond to the first self-test command, generate random data and a third error correction code corresponding to the random data, and perform error injection processing on the random data to obtain error data. The first error correction code engine is further used to perform error correction processing on the third error correction code and the error data to obtain a first flag bit; The second error correction engine is also used to perform error correction processing on the third error correction code and the error data to obtain a second flag bit; The functional safety diagnostic module is used to verify the first flag bit and the second flag bit to obtain a first self-test result.

12. The memory according to claim 10, characterized in that, The memory also includes a functional safety register; the functional safety register is used for one of the following: If the first self-test result is the second result, then the first error correction code engine is turned off; If the first self-test result is the fourth result, the second error correction code engine is turned off; If the first self-test result is the third result, shut down the first error correction code engine and the second error correction code engine. The second result is that the second error correction engine is working normally, while the first error correction engine is malfunctioning. The third result is that both the first error correction code engine and the second error correction code engine malfunction; the fourth result is that the first error correction code engine is working normally, while the second error correction code engine malfunctions.

13. The memory according to claim 10, characterized in that, The first error correction code engine is further configured to, when the first self-test result is the fourth result, acquire the original data stored in the memory and the first error correction code corresponding to the original data, and perform error correction processing on the original data and the first error correction code to obtain the third output data and the first flag bit; the functional safety diagnostic module is further configured to verify the first flag bit so that when the first flag bit meets the third preset condition, the third output data is output from the memory interface of the memory. or, The second error correction code engine is further configured to, when the first self-test result is the second result, obtain the original data stored in the memory and the first error correction code corresponding to the original data, and perform error correction processing on the original data and the first error correction code to obtain the second output data and the second flag bit; the functional safety diagnostic module is further configured to verify the second flag bit so that when the second flag bit meets the second preset condition, the second output data is output from the memory interface of the memory.

14. An electronic device, characterized in that, include: The memory as described in any one of claims 10 to 13.

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