Memory operation method, memory and electronic device

Abstract

The disclosure provides a memory operation method, a memory and an electronic device, and relates to the technical field of semiconductors. Original data and an error correction code are obtained, the error correction code is used for error correction of the original data; the original data is subjected to error correction processing based on the error correction code, first data is obtained, and the first data comprises first output data; the first data is subjected to delay processing, first check data is obtained; the original data and the error correction code are subjected to delay processing, second data is obtained, and the second data comprises delay data and a delay error correction code; the delay data is subjected to error correction processing based on the delay error correction code, second check data is obtained; and the first check data and the second check data are subjected to checking, indication data is obtained, and the indication data is used for indicating whether the first output data is correct. The disclosure can discover errors in memory output data in time, thereby generating an error alarm in time, and ensuring the safety of system work.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory operation method, a memory, and an electronic device. Background Technology

[0002] To ensure the correctness and reliability of data transmission in non-volatile memory such as flash memory, Error-Correcting Code (ECC) technology is employed as an important functional safety mechanism. The main function of the ECC engine is to detect and correct potential errors in real time during data transmission. Through this mechanism, when data is corrupted during transmission, the ECC engine can automatically recover the original data. This effectively prevents potential problems caused by data errors, ensuring that the system maintains high reliability and security when processing data from non-volatile memory.

[0003] However, when the ECC engine itself malfunctions, corrupted data during transmission cannot be correctly corrected, and may even result in false corrections. Simultaneously, the error alarm mechanism may fail to trigger in a timely manner, thus creating system security vulnerabilities.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a memory operation method, a memory, and an electronic device, which can at least to a certain extent detect errors in the memory output data in a timely manner and ensure the security of system operation.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a memory operation method is provided, comprising: acquiring raw data and an error correction code, the error correction code being used to correct errors in the raw data; performing error correction processing on the raw data based on the error correction code to obtain first data, the first data including first output data; performing delay processing on the first data to obtain first verification data; performing delay processing on the raw data and the error correction code to obtain second data, the second data including delayed data and a delayed error correction code; performing error correction processing on the delayed data based on the delayed error correction code to obtain second verification data; and verifying the first verification data and the second verification data to obtain indication data, the indication data being used to indicate whether the first output data is correct.

[0008] According to another aspect of this disclosure, a memory is also provided, comprising: a first error correction code engine, configured to acquire raw data and an error correction code, the error correction code being used to correct errors in the raw data; performing error correction processing on the raw data based on the error correction code to obtain first data, the first data including first output data; a first delay module, configured to perform delay processing on the first data to obtain first verification data; a second delay module, configured to perform delay processing on the raw data and the error correction code to obtain second data, the second data including delayed data and a delayed error correction code; a second error correction code engine, configured to perform error correction processing on the delayed data based on the delayed error correction code to obtain second verification data; and a verification module, configured to verify the first verification data and the second verification data to obtain indication data, the indication data being used to indicate whether the first output data is correct.

[0009] According to another aspect of this disclosure, an electronic device is also provided, the electronic device comprising: the memory described in any one of the preceding claims.

[0010] In the embodiments of this disclosure, original data and an error correction code are obtained, the error correction code being used to correct errors in the original data; based on the error correction code, the original data is subjected to error correction processing to obtain first data, the first data including first output data; the first data is subjected to delay processing to obtain first verification data; the original data and the error correction code are subjected to delay processing to obtain second data, the second data including delayed data and a delayed error correction code; based on the delayed error correction code, the delayed data is subjected to error correction processing to obtain second verification data; the first verification data and the second verification data are verified to obtain indication data, the indication data being used to indicate whether the first output data is correct. This disclosure performs error correction processing on the original data and the delayed original data (delayed data) in parallel, and verifies the first verification data and the second verification data obtained after error correction processing to obtain indication data. Through the indication data, errors in the memory output data (such as the first output data) can be detected in a timely manner, thereby generating error alarms in a timely manner and ensuring the security of system operation.

[0011] Furthermore, delaying the processing of the original data and error correction codes, as well as delaying the processing of the first data, ensures the consistency of the first and second verification data during verification, enabling effective comparison and verification of the data. Moreover, by comparing the data on the two paths (the first and second verification data), the system can respond immediately upon detecting a difference, thereby preventing erroneous data from entering subsequent processing flows.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0014] Figure 1 This diagram illustrates a flowchart of a memory operation method according to an embodiment of the present disclosure;

[0015] Figure 2 A flowchart of a memory operation method according to another embodiment of this disclosure is shown;

[0016] Figure 3 This diagram shows a structural block diagram of a memory according to an embodiment of the present disclosure;

[0017] Figure 4 A block diagram of the memory structure is shown in another embodiment of this disclosure;

[0018] Figure 5 This diagram shows a structural block diagram of a memory according to another embodiment of the present disclosure;

[0019] Figure 6 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0020] Figure 7 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0021] Figure 8 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0022] Figure 9 This diagram shows a structural block diagram of a memory according to yet another embodiment of the present disclosure;

[0023] Figure 10 This diagram illustrates the switching of operating modes in an embodiment of the present disclosure.

[0024] Figure 11 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0027] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0028] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0029] It should be noted that the terms “one” and “multiple” used in this disclosure are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as “one or more”, where “multiple” means two or more.

[0030] Memory is a storage component used to store programs and various data information. Based on its usage type, memory can be divided into Read Only Memory (ROM) and Random Access Memory (RAM). ROM can include Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), and Flash memory. Flash memory includes NOR flash memory and NAND flash memory.

[0031] In related technologies, ECC engines are typically used as functional safety mechanisms to ensure the correctness of memory during data transmission. ECC engines can correct and detect errors that occur during data transmission, thereby ensuring that the original data can be recovered or that error warnings are issued to the system in the event of data corruption, thus improving the reliability and security of the system.

[0032] However, when the ECC engine itself malfunctions, corrupted data during transmission cannot be correctly corrected, and may even be incorrectly corrected. Simultaneously, the error alarm mechanism may fail to trigger in a timely manner, leading to system security vulnerabilities. Specifically, if error correction is not timely or false alarms are generated, the system may mistakenly believe that data transmission is normal, causing subsequent operations to rely on corrupted data and affecting the overall system functionality. Therefore, the reliability of the ECC engine is crucial; a malfunction can lead to serious system failures, impacting the security and stability of the entire system.

[0033] To address the aforementioned problems, this disclosure provides a memory operation method applicable to the field of memory. For example, the memory operation method of this disclosure can be applied to non-volatile memory, and also to other types of memory; this disclosure does not limit its application in this regard. The memory operation method includes: acquiring original data and an error correction code, the error correction code being used to correct errors in the original data; performing error correction processing on the original data based on the error correction code to obtain first data, the first data including first output data; performing delay processing on the first data to obtain first verification data; performing delay processing on the original data and the error correction code to obtain second data, the second data including delayed data and a delayed error correction code; performing error correction processing on the delayed data based on the delayed error correction code to obtain second verification data; and verifying the first verification data and the second verification data to obtain indication data, the indication data being used to indicate whether the first output data is correct. This disclosure performs error correction processing on the original data and delayed data in parallel, and verifies the first and second verification data obtained after error correction processing to obtain indication data. The indication data allows for timely detection of errors in the first output data, thereby generating timely error alarms and ensuring the security of system operation. Furthermore, delaying the processing of the original data and error correction codes, as well as delaying the processing of the first data, ensures the consistency of the first and second checksums during verification, enabling effective comparison and verification of the data. Moreover, by comparing the first and second checksums, the system can respond immediately upon detecting a difference, thereby preventing erroneous data from entering subsequent processing flows.

[0034] This disclosure provides a memory operation method, which can be executed by any electronic device with computing capabilities. For example, an electronic device with computing capabilities can be a memory. The following description uses a memory as an example.

[0035] Figure 1 A flowchart of a memory operation method according to an embodiment of this disclosure is shown, as follows: Figure 1 As shown, the memory operation method provided in this embodiment may include the following steps S101 to S106.

[0036] S101, Obtain the raw data and error correction code. The error correction code is used to correct errors in the raw data.

[0037] In this embodiment of the disclosure, the error correction code is used to correct errors in the original data. That is, the error correction code is used to detect and correct errors that occur during the transmission or storage of the original data.

[0038] In this embodiment of the disclosure, the original data can be data stored on the memory array. Before storage, the original data is used to calculate the error correction code (i.e. the correct error correction code) through an encoding algorithm, and the error correction code is also stored on the memory array.

[0039] The present disclosure does not limit the specific method for obtaining the error correction code. For example, the error correction code can be obtained by encoding the original data using an encoding algorithm (such as Hamming code, low-density parity-check code, Reed-Solomon code, etc.).

[0040] S102, based on the error correction code, perform error correction processing on the original data to obtain the first data, which includes the first output data.

[0041] In this embodiment of the disclosure, the error correction code can be an ECC (Error Correction Code). ECC adds redundant information to the data, enabling the error correction engine to detect and correct errors that occur during data transmission or storage. For example, the error correction engine can obtain the original data and the error correction code from the storage array, and perform error correction processing on the original data based on the error correction code.

[0042] It should be noted that, assuming no errors occur in the original data, the first output data will be the same as the original data.

[0043] In this embodiment, the first output data is the output data of the memory, and the first output data is output through the memory interface. It should be noted that the memory interface is the interface through which the memory outputs data; however, this disclosure does not limit the specific type of memory interface. For example, the memory interface can be an input / output pin (IO pin) of the memory.

[0044] In this embodiment of the disclosure, the first data may include a first flag bit and / or first output data.

[0045] S103, perform delay processing on the first data to obtain the first verification data.

[0046] In this embodiment, delaying the first data enables delayed locking, thereby ensuring data consistency, improving fault tolerance, and ensuring timely detection and correction of errors, thus greatly enhancing the system's reliability and security. This embodiment does not limit how the first data is delayed; for example, it can be delayed using a delayed lockstep circuit to obtain first verification data. Another example is using a buffer to delay the first data to obtain first verification data.

[0047] S104, the original data and error correction code are delayed to obtain second data, which includes delayed data and delayed error correction code.

[0048] In this embodiment of the disclosure, the delay processing of the original data and error correction code is also to achieve delayed lockstep, thereby ensuring that the first verification data and the second verification data are verified synchronously, which improves the verification speed and the verification accuracy.

[0049] It should be noted that the delay processing method in S104 has been described in S103, and will not be repeated here.

[0050] Delayed data is the data obtained after delaying the original data, and delayed error correction code is the data obtained after delaying the error correction code.

[0051] S105, based on the delay error correction code, performs error correction processing on the delayed data to obtain the second verification data.

[0052] This disclosure does not limit the methods for error correction processing of delayed data. For example, the ECC engine performs error correction processing on delayed data based on delay error correction codes.

[0053] S106, verify the first verification data and the second verification data to obtain indication data, which is used to indicate whether the first output data is correct.

[0054] In this embodiment, the time for delaying the first data is the same as the time for delaying the original data and error correction code; that is, the number of delay cycles is the same for both. For example, the number of delay cycles can be any number between 0 and 100. Other examples include delay cycles of 0, 1, 2, 3, 4, 5, 6, 8, and 10. It should be noted that the specific value of the number of cycles can be determined based on the specific application scenario and practical experience, according to the logic of memory data processing. This allows for time-varying flexibility, ensuring the reliability and accuracy of memory operation.

[0055] In this embodiment of the disclosure, the delayed lockstep technique is used to ensure that the first verification data and the second verification data can be verified synchronously one by one, thereby improving the speed and accuracy of the verification.

[0056] The specific type of indication data is not limited in this embodiment. For example, indication data is obtained by comparing first verification data with second verification data. If the comparison result shows that the first verification data and the second verification data are the same, the indication data is 1, where "1" indicates that the first output data is correct, and the first output data is output from the memory interface of the memory. Conversely, if the comparison result shows that the first verification data and the second verification data are different, the indication data is 0, where "0" indicates that the first output data is incorrect. When the first output data is incorrect, the memory issues an alarm, thereby improving the system's safety. For example, in a vehicle-to-everything (V2X) scenario, if the raw data is incorrect, the system reads an alarm signal from the functional safety register and / or alarm pin of the memory to issue an alarm. The driver can promptly detect the data error and take appropriate action, thereby improving driving safety. For example, in an autonomous driving system, the raw data (real-time data) provided by the vehicle speed sensor is used to control the vehicle's speed. If an error occurs during the storage of the raw data, an alarm signal is generated. The system reads the relevant alarm signal from the functional safety register in the memory to remind the driver that the vehicle speed data is incorrect. Once the driver notices the problem, they can manually adjust the vehicle speed or switch to a safe mode to ensure safe driving and avoid potential accidents.

[0057] This embodiment of the disclosure performs error correction processing on the original data and the delayed original data (delayed data) in parallel, and verifies the first and second verification data obtained after the error correction processing to obtain indication data. The indication data can promptly detect errors in the memory output data (such as the first output data), thereby generating error alarms in a timely manner and ensuring the safety of the system operation.

[0058] Furthermore, delaying the processing of the original data and error correction codes, as well as delaying the processing of the first data, ensures the consistency of the first and second verification data during verification, enabling effective comparison and verification of the data. Moreover, by comparing the data on the two paths (the first and second verification data), the system can respond immediately upon detecting a difference, thereby preventing erroneous data from entering subsequent processing flows.

[0059] The following three exemplary embodiments illustrate how to determine the indication data.

[0060] In an exemplary embodiment, the first data may further include a first flag bit, and the second verification data may include a second flag bit. In this embodiment, the first flag bit is used to indicate whether a single-bit error has occurred in the original data and to correct it, and whether a two-bit error has been detected in the original data. The second flag bit is used to indicate whether a single-bit error has occurred in the delayed data and to correct it, and whether a two-bit error has been detected in the delayed data. It should be noted that if two or more bit errors exist, it indicates that the memory is in an unsafe state and an alarm needs to be triggered.

[0061] In the memory operation method provided in this disclosure, S103 may include: delaying the first flag bit to obtain first check data; the first check data includes the delayed first flag bit. The method used for delaying the flag bit has been explained in S103 and will not be repeated here.

[0062] In the memory operation method provided in this disclosure, S106 may include: verifying the delayed first flag bit and the second flag bit to obtain indication data; wherein, in order to ensure timing consistency, the time for delaying the first flag bit is equal to the time for delaying the original data and the error correction code.

[0063] The specific representation of the first and second flag bits is not limited in this disclosure. For example, both the first and second flag bits are represented by two-bit values. For instance, if both the first and second flag bits are 00, then the first and second flag bits are the same, indicating that the ECC engine has not malfunctioned and the exponential data indicates that the first output data is correct.

[0064] In one embodiment, both the first and second flag bits are represented by two-bit values. For example, a first flag bit of "00" indicates that the original data is correct. Specifically, a "0" in the first bit indicates that the original data has no errors, and a "0" in the second bit indicates that there are no errors of two or more bits in the original data. As another example, a first flag bit of "10" indicates that a 1-bit error occurred in the original data, and the ECC engine (such as the first error correction engine) has successfully corrected the error, meaning there are no errors of two or more bits in the original data. Here, a "1" in the first bit indicates that a 1-bit error existed in the original data, and the ECC engine (such as the first error correction engine) has successfully corrected the error. A "0" in the second bit indicates that there are no errors of two or more bits in the original data.

[0065] Similarly, the second flag bit functions similarly to the first flag bit. For example, a second flag bit of "00" indicates that the delayed data is correct. Specifically, a "0" in the first bit indicates that the delayed data has no errors, and a "0" in the second bit indicates that there are no errors of two or more bits in the delayed data. As another example, a second flag bit of "10" indicates that a 1-bit error occurred in the delayed data, and the ECC engine (such as the second error correction engine) has successfully corrected the error. A "1" in the first bit indicates that a 1-bit error existed in the delayed data, and the ECC engine (such as the second error correction engine) has successfully corrected the error. A "0" in the second bit indicates that there are no errors of two or more bits in the delayed data.

[0066] It should be noted that the ECC engine is usually used in conjunction with Error Correction Code (ECC) to ensure that the system can effectively detect and repair errors that may occur during data transmission or storage.

[0067] This embodiment of the disclosure obtains indication data by verifying the delayed first and second flag bits. The indication data is then used to determine if the first output data contains errors. If the first output data is incorrect, a rapid alarm can be triggered, thereby improving system security. Because the first and second flag bits have relatively few bits, the verification speed can be further improved.

[0068] In another embodiment, the first flag bit may include a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit may include a second single-bit repair flag bit and a second double-bit detection flag bit; both the first single-bit repair flag bit and the second single-bit repair flag bit are used to indicate the detection and repair of a single-bit error in the original data; both the first double-bit detection flag bit and the second double-bit detection flag bit are used to indicate whether a two-bit error is detected in the delayed data. That is, the first double-bit detection flag bit is used to indicate whether a two-bit error is detected in the original data, and the second double-bit detection flag bit is used to indicate whether a two-bit error is detected in the delayed data.

[0069] For example, the first single-bit correction flag can be a single-bit error correction (SEC) flag, denoted by SEC1. The first double-bit detection flag can be a double-bit error detection (DEC) flag, denoted by DEC1. Similarly, the second single-bit correction flag can be a single-bit error correction flag, denoted by SEC2. The second double-bit detection flag can be a double-bit error detection flag, denoted by DEC2.

[0070] When SEC1,DED1 = 2'b00 and SEC2,DED2 = 2'b00, the first flag bit and the second flag bit are the same, indicating that the original data in the storage array has not been corrupted. At this time, the system is safe and the first output data output by the memory interface is correct.

[0071] When SEC1,DED1 = 2'b11 and SEC2,DED2 = 2'b00, the first flag bit and the second flag bit are different, indicating that the original data in the storage array has been corrupted. At this time, the system is not safe and an alarm signal is generated.

[0072] It should be noted that alarm signals can be output to the memory interface, alarm pin, or sent to the functional safety register (a register in the memory disclosed herein). The system can obtain alarm signals by sampling the alarm memory interface, alarm pin, or reading the functional safety register. The system can be a microcontroller or a processor. The ECC engine (Error-Correcting Code Engine) is used to perform error detection and correction functions, especially in data storage and transmission.

[0073] For example, the memory may also include a functional safety register. An alarm signal is generated if the indication data indicates an error in the first output data. The memory interface and / or the functional safety register are used to receive the alarm signal, which indicates an error in the first output data.

[0074] The embodiments disclosed herein use a first single-bit repair flag, a first double-bit detection flag, a second single-bit repair flag, and a second double-bit detection flag to determine whether the first output data has an error, thereby quickly and accurately identifying the error state of the data.

[0075] In another exemplary embodiment, the second verification data may include second output data; the second output data is data after error correction processing of the delayed data, and if the delayed data is correct, the second output data is equal to the original data.

[0076] The memory operation method provided in this disclosure, which delays the processing of the first data to obtain the first verification data, may include: delaying the processing of the first output data to obtain the first verification data, wherein the first verification data includes the delayed first output data.

[0077] The memory operation method provided in this disclosure, which verifies the first verification data and the second verification data to obtain the indication data, may include: verifying the delayed first output data and the second output data to obtain the indication data; wherein the time for delaying the first output data is equal to the time for delaying the original data and the error correction code.

[0078] In this embodiment of the disclosure, when the first output data and the second output data are the same, the indicator data indicates that the first output data is correct. When the first output data and the second output data are different, the indicator data indicates that the first output data is incorrect and an alarm is triggered.

[0079] This embodiment of the disclosure determines whether the first output data is correct by comparing the first output data and the second output data, thereby ensuring the accuracy of the memory data output. An alarm can be triggered promptly when an error exists in the first output data output by the memory.

[0080] In yet another exemplary embodiment, the first data may further include a first flag bit, and the second verification data may include a second flag bit and second output data. The specifics of the first flag bit, the second flag bit, and the second output data have been described in the above embodiments and will not be repeated here.

[0081] In the memory operation method provided in this disclosure, S103 may include: delaying the first output data and the first flag bit to obtain first verification data, wherein the first verification data includes the delayed first output data and the delayed first flag bit. The method used for delaying the data has been explained in S103 and will not be repeated here.

[0082] In the memory operation method provided in this disclosure, S106 may include: verifying the delayed first output data and the second output data to obtain a first verification result; verifying the delayed first flag bit and the second flag bit to obtain a second verification result; and obtaining indication data based on the first verification result and the second verification result; wherein the time for delaying the first output data and the first flag bit is equal to the time for delaying the original data and the error correction code.

[0083] When the first verification result shows that the first output data and the second output data are the same, and the second verification result shows that the first flag bit and the second flag bit are the same, the indication data is that the first output data is correct. In other words, the ECC engine used for correction processing has not malfunctioned. Otherwise, it indicates that the first output data is incorrect.

[0084] The embodiments of this disclosure, by verifying the first output data and the second output data, as well as verifying the first flag bit and the second flag bit, can more accurately determine whether there is an error in the first output data, thereby improving the accuracy of the verification.

[0085] To improve the efficiency of the system in acquiring memory output data, the present disclosure provides the following exemplary embodiments.

[0086] In an exemplary embodiment, before verifying the first verification data and the second verification data to obtain the indication data, the memory operation method provided in this disclosure may further include: outputting delayed first output data and second output data, both of which are used for internal operations of the memory.

[0087] This embodiment of the disclosure adds two additional outputs to one output, providing three outputs for the internal computation of the memory or system, while ensuring that errors in the output data (such as the first output data and the second output data) can be detected in a timely manner. This reduces latency, optimizes resource utilization, and significantly improves the computational efficiency, processing power, and flexibility of the memory or system, thus meeting the requirements of high performance and strong real-time performance.

[0088] To ensure that the ECC engine corrects the raw data without failure, the present disclosure provides the following exemplary embodiments.

[0089] In an exemplary embodiment, the memory includes a first error correction code engine and a second error correction code engine; such as Figure 2 As shown, the memory operation method provided in this disclosure may further include S201 to S204.

[0090] S201, in response to the first self-test instruction, generates random data and an error correction check code, performs error injection processing on the random data to obtain erroneous data, and uses the error correction check code to correct the erroneous data.

[0091] The first self-test instruction is used to instruct the first error correction engine and the second error correction engine to perform a self-test.

[0092] For example, the system sends a first self-test instruction to the memory. After receiving the first self-test instruction, the memory generates self-test data (such as random data and error correction check codes). The first error correction code engine and the second error correction code engine are self-tested by the self-test data, which can ensure that the first error correction code engine and the second error correction code engine perform error correction processing on the data (such as the original data) under normal working conditions.

[0093] It should be noted that the system can be an integrated circuit with computing capabilities, such as a microcontroller or processor. The ECC (Error-Correcting Code Engine) is used to perform error detection and correction functions, especially in data storage and transmission. The ECC engine is usually used in conjunction with Error Correction Code (ECC) to ensure that the system can effectively detect and repair errors that may occur during data transmission or storage.

[0094] The system issues a first self-test command based on the detection requirements. For example, the system issues a first self-test command to the memory at regular intervals. For instance, the system issues a first self-test command to the memory every 5 minutes. Furthermore, when the system samples an alarm signal at the memory interface, reads an alarm signal from the functional safety register, or samples an alarm signal from the alarm pin, it immediately issues a first self-test command until both the first and second error correction code engines fail.

[0095] In this embodiment of the disclosure, there are no limitations on how to perform error injection processing on random data; any processing that can cause errors in the random data is acceptable. For example, the first self-test instruction carries the number of error-causing bits and the location of the error, and the random data is erroneously injected based on the number of error-causing bits and the location of the error. For example, if the random data is [0 00 0], error injection processing on the random data yields the erroneous data [0 0 0 1].

[0096] The error correction check code is a type of ECC. The method for obtaining the error correction check code based on random data is the same as the method for obtaining the error correction code based on the original data, and will not be described in detail here.

[0097] S202, the first error correction code engine performs error correction processing on the erroneous data based on the error correction check code to obtain the first flag bit.

[0098] S203, the second error correction code engine performs error correction processing on the erroneous data based on the error correction check code to obtain the second flag bit.

[0099] It should be noted that the error correction processing in S202 and S203 is similar to the error correction processing in S102, and will not be described again here.

[0100] S204, verify the first flag bit and the second flag bit to obtain the first self-test result.

[0101] In one embodiment, the first flag bit may include a first single-bit repair flag bit and a first double-bit detection flag bit; the second flag bit may include a second single-bit repair flag bit and a second double-bit detection flag bit. The first single-bit repair flag bit can be for single-bit error repair, denoted by SEC1. The first double-bit detection flag bit can be for double-bit error detection, denoted by DEC1. Similarly, the second single-bit repair flag bit can be for single-bit error repair, denoted by SEC2. The second double-bit detection flag bit can be for double-bit error detection, denoted by DEC2.

[0102] When SEC1,DED1 = 2'b10, it indicates that a 1-bit error has occurred in the erroneous data in the storage array, and the first error correction engine can work normally.

[0103] When SEC2,DED2 = 2'b10, it indicates that a 1-bit error has occurred in the erroneous data in the storage array, and the second error correction engine can work normally.

[0104] It should be noted that other values ​​for the first and second flags indicate that the erroneous data has an error greater than 1 bit, or that the ECC engine has malfunctioned.

[0105] In this embodiment of the disclosure, there are four types of self-test results: the first result, the second result, the third result, and the fourth result. The first result is that both the first and second error correction code engines are working normally; the second result is that the second error correction code engine is working normally, but the first error correction code engine is malfunctioning; the third result is that both the first and second error correction code engines are malfunctioning; and the fourth result is that the first error correction code engine is working normally, but the second error correction code engine is malfunctioning.

[0106] For example, if the first self-test result is a first result, first output data is output from the memory interface of the memory, wherein the first result indicates that both the first error correction engine and the second error correction engine are working normally. If both the first error correction engine and the second error correction engine are working normally, and the indication data indicates that the first output data is output correctly, then the first output data is output from the memory interface of the memory.

[0107] For example, if the first self-test result is the second result, the first error correction code engine is shut down, and the second output data is output from the memory interface of the memory; in response to the second self-test instruction, the second error correction code engine is self-tested to obtain the second self-test result; wherein, the second result is that the first error correction code engine has failed, and the second error correction code engine is working normally.

[0108] In this embodiment, when the first error correction engine fails, the second error correction engine can operate normally. The second output data output by the second error correction engine is the original data after error correction, and the second output data is output from the memory interface of the memory. In this embodiment, the first and second error correction engines operate in parallel. When the first error correction engine fails, the second error correction engine can operate normally, thereby improving the reliability of the memory operation.

[0109] In this embodiment, the second self-test instruction is an instruction to perform a self-test on the second error correction code engine. With the first error correction code engine disabled, the system issues the second self-test instruction according to detection requirements. For example, the system issues the second self-test instruction to the memory at regular intervals. For instance, the system issues the second self-test instruction to the memory every minute. As another example, when the system samples an alarm signal at the memory interface, or at the alarm interface, or reads an alarm signal from the functional safety register, it immediately issues a second self-test instruction until the second error correction code engine also fails. It should be noted that only the second error correction code engine is working when the second self-test instruction is issued. Therefore, the interval between issuing the second self-test instruction is shorter than the interval between issuing the first self-test instruction. Shortening the time interval for sending self-test instructions allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving the reliability of memory operation.

[0110] Regarding how the second error correction code engine performs a self-test in this embodiment, the method is similar to the method for performing a self-test on the second error correction code engine in S204. Specifically, it is determined whether the second error correction code engine has malfunctioned based on the second flag bit, so it will not be described in detail again here.

[0111] In the event of a failure in the first error correction engine, the embodiments disclosed herein perform a self-test on the second error correction engine, which can promptly detect the failure of the second error correction engine, thereby promptly identifying problems in data transmission, ensuring the functional safety of the memory, and improving the reliability of the memory operation.

[0112] For example, if the first self-test result is the third result, the first error correction engine and the second error correction engine are shut down, and the raw data is output from the memory interface of the memory. The third result indicates that both the first error correction engine and the second error correction engine have failed.

[0113] For example, when SEC1,DED1 = 2'b01 or SEC1,DED1 = 2'b11, it indicates that the first error correction engine has malfunctioned. When SEC2,DED2 = 2'b01 or SEC2,DED2 = 2'b11, it indicates that the second error correction engine has malfunctioned.

[0114] For example, if the first self-test result is the fourth result, the second error correction code engine is shut down, and the first output data is output from the memory interface of the memory. In response to the third self-test instruction, the first error correction code engine is self-tested to obtain the third self-test result, wherein the fourth result is that the first error correction code engine is working normally and the second error correction code engine has failed.

[0115] The third self-test instruction is used to perform a self-test on the first error correction engine. With the second error correction engine disabled, the system issues the third self-test instruction based on testing requirements. For example, the system issues the third self-test instruction to the memory at regular intervals, such as every minute. Furthermore, when the system samples an alarm signal at the memory interface, on an alarm pin, or reads an alarm signal from the functional safety register, it immediately issues the third self-test instruction until the first error correction engine also fails. It should be noted that only the first error correction engine is active when the third self-test instruction is issued. Therefore, the interval between issuing the third self-test instruction is shorter than the interval between issuing the first self-test instruction. Shortening the time interval for sending self-test instructions allows for timely detection of problems in data transmission, ensuring the functional safety of the memory and improving its reliability.

[0116] Regarding how the first error correction code engine performs a self-test in this embodiment, the method is similar to the method for performing a self-test on the first error correction code engine in S204. Specifically, it is determined whether the first error correction code engine has malfunctioned based on the third flag bit, so it will not be described in detail again here.

[0117] It should be noted that the alarm signal generated by the failure of both the first and second error correction code engines is different from the alarm signal generated by the data having an error greater than 1 bit. The cause of the failure can be distinguished based on the different alarm signals.

[0118] In the event of a failure of the second error correction engine, the embodiments of this disclosure perform a self-test on the first error correction engine, which can promptly detect the failure of the first error correction engine, thereby promptly identifying problems in data transmission, ensuring the functional safety of the memory, and improving the reliability of the memory operation.

[0119] This embodiment of the present disclosure uses a first flag bit to determine whether the first error correction code engine is faulty, and uses a second flag bit to determine whether the second error correction code engine is faulty. This enables timely detection of the fault status of the first and second error correction code engines, ensuring the output of correct data. At the same time, it can reduce the dependence on external detection and error correction methods and enhance the stability of the system.

[0120] Based on the same inventive concept, this disclosure also provides a memory, as described in the following embodiments. Since the principle by which this memory embodiment solves the problem is similar to that of the above-described method embodiments, the implementation of this memory embodiment can refer to the implementation of the above-described method embodiments, and repeated details will not be elaborated further.

[0121] Figure 3 This diagram illustrates a structural block diagram of a memory according to an embodiment of the present disclosure, as follows: Figure 3 As shown, a memory provided in this disclosure may include a first error correction code engine 31, a first delay module 32, a second delay module 33, a second error correction code engine 34, and a verification module 35.

[0122] The first error correction engine 31 can be used to acquire raw data and error correction codes, with the error correction codes used to correct errors in the raw data. Based on the error correction codes, the raw data is processed to obtain first data, which includes first output data. It should be noted that the first output data can be output through the memory interface of the memory.

[0123] The first delay module 32 can be used to delay the first data to obtain the first verification data. It should be noted that the first verification data can be the delayed first output data and / or the first flag bit.

[0124] The second delay module 33 can be used to delay the original data and the error correction code to obtain second data, which includes delayed data and delayed error correction code; wherein, the delayed data is the delayed original data and the delayed error correction code is the delayed error correction code.

[0125] The second error correction engine 34 can be used to perform error correction processing on delayed data based on delayed error correction codes to obtain second check data. It should be noted that the second check data and the first check data have the same data type and the same number of bits.

[0126] The verification module 35 can be used to verify the first verification data and the second verification data to obtain indication data, which is used to indicate whether the first output data is correct. The verification module 35 can determine whether the first verification data and the second verification data are the same. This embodiment of the disclosure does not specifically limit the type of circuit that the verification module 35 is. Any circuit capable of implementing the comparison function is acceptable. For example, the verification module 35 can be a comparator.

[0127] In this embodiment of the disclosure, the specific circuits of the first delay module 32 and the second delay module 33 are not limited. For example, the first delay module 32 and the second delay module 33 can be lockstep circuits. As another example, the first delay module 32 and the second delay module 33 can be buffers.

[0128] In related technologies, only one error correction code engine is designed in the memory. After reading the original data and error correction code from the memory such as non-volatile memory, the data undergoes error correction and detection processing by the first error correction code engine 31. The processed data (first output data) is then output to the memory interface of the non-volatile memory through the data output channel. This disclosure, based on this, adds a first delay module 32, a second delay module 33, a second error correction code engine 34, and a verification module 35 to diagnose the security of the first error correction code engine 31.

[0129] It should be noted that the number of delay cycles for the first delay module 32 and the second delay module 33 can be configured by the system. The memory interface is the interface through which the memory outputs data; this disclosure does not limit the specific type of memory interface. For example, the memory interface can be an input / output pin (IO pin) of the memory.

[0130] The memory disclosed in this embodiment performs error correction processing on the original data and the delayed original data (delayed data) in parallel, and verifies the first and second verification data obtained after the error correction processing to obtain indication data. Through the indication data, errors in the memory output data (such as the first output data) can be detected in a timely manner, thereby generating error alarms in a timely manner and ensuring the safety of system operation.

[0131] Furthermore, delaying the processing of the original data and error correction codes, as well as delaying the processing of the first data, ensures the consistency of the first and second verification data during verification, enabling effective comparison and verification of the data. Moreover, by comparing the data on the two paths (the first and second verification data), the system can respond immediately upon detecting a difference, thereby preventing erroneous data from entering subsequent processing flows.

[0132] In one embodiment, such as Figure 4 As shown, the first data may further include a first flag bit, and the second verification data may include a second flag bit; the first delay module 32 may also be used to delay the first flag bit to obtain the first verification data; the first verification data includes the delayed first flag bit; the verification module 35 may also be used to verify the delayed first flag bit and the second flag bit to obtain indication data; wherein, the time for delaying the first flag bit is equal to the time for delaying the original data and the error correction code.

[0133] The memory disclosed in this embodiment obtains indication data by verifying the delayed first and second flag bits. The indication data is used to determine whether the first output data contains errors. If the first output data is incorrect, a rapid alarm can be triggered to improve system security. Because the first and second flag bits have relatively few bits, the verification speed can be further improved.

[0134] In one embodiment, such as Figure 5 As shown, the second verification data may include the second output data; the first delay module 32 may also be used to delay the first output data to obtain the first verification data, which includes the delayed first output data; the verification module 35 may also be used to verify the delayed first output data and the second output data to obtain the indication data; wherein, the time for delaying the first output data is equal to the time for delaying the original data and the error correction code.

[0135] The memory disclosed in this embodiment determines whether the first output data is correct by comparing the first output data and the second output data, thereby ensuring the accuracy of the memory data output.

[0136] In one embodiment, such as Figure 6 As shown, the first data may further include a first flag bit, and the second verification data may include a second flag bit and a second output data; the first delay module 32 may also be used to delay the first output data and the first flag bit to obtain the first verification data, which includes the delayed first output data and the delayed first flag bit; the verification module 35 may also be used to verify the delayed first output data and the second output data to obtain a first verification result; verify the delayed first flag bit and the second flag bit to obtain a second verification result; and obtain indication data based on the first verification result and the second verification result.

[0137] The time for delaying the first output data and the first flag is equal to the time for delaying the original data and the error correction code.

[0138] The embodiments of this disclosure, by verifying the first output data and the second output data, as well as verifying the first flag bit and the second flag bit, can more accurately determine whether there is an error in the first output data, thereby improving the accuracy of the verification.

[0139] In one embodiment, such as Figure 7 As shown, the first delay module 32 can also be used to output the delayed first output data; the second error correction code engine can also be used to output the second output data, and the delayed first output data and the second output data are both used for internal calculations in the memory.

[0140] This embodiment of the disclosure adds two additional outputs to one output, providing three outputs for the internal computation of the memory or system, while ensuring that errors in the output data (such as the first output data and the second output data) can be detected in a timely manner. This reduces latency, optimizes resource utilization, and significantly improves the computational efficiency, processing power, and flexibility of the memory or system, thus meeting the requirements of high performance and strong real-time performance.

[0141] It should be noted that when the first output data is correct, the delayed first and second output data output by the other two output branches are also correct. By outputting correct data (such as the original data after error correction) through the three branches simultaneously, the internal calculation accuracy can be improved, and the calculation speed can be increased.

[0142] In one embodiment, such as Figure 8As shown, dashed lines represent unused paths, and solid lines represent used paths. The memory may also include a self-test data fault injection module 36. The self-test data fault injection module 36 can be used to generate random data and error correction check codes in response to a first self-test command, and perform error injection processing on the random data to obtain erroneous data. The error correction check codes are used to correct the erroneous data. The first error correction code engine 31 can also be used to perform error correction processing on the erroneous data based on the error correction check codes to obtain a first flag bit. The second error correction code engine 34 can also be used to perform error correction processing on the erroneous data based on the error correction check codes to obtain a second flag bit. The verification module 35 can also be used to verify the first flag bit and the second flag bit to obtain a first self-test result.

[0143] It should be noted that the self-test data fault injection module 36 may include a random generator to generate random data. Alternatively, multiple pre-set data to be selected can be stored in the self-test data fault injection module 36. Upon receiving a self-test command (such as a first self-test command), the module randomly selects one data point from the data to be selected as the random data. This disclosure does not specifically limit how the random data is generated.

[0144] In one embodiment, such as Figure 9 As shown, dashed lines represent unused paths, and solid lines represent used paths. The memory may also include a functional safety register 37 and a memory interface 38.

[0145] If the first self-test result is the first result, the first output data is output from the memory interface 38 of the memory, wherein the first result is that the first error correction code engine 31 and the second error correction code engine 34 are working normally.

[0146] If the first self-test result is the second result, the functional safety register 37 is used to shut down the first error correction code engine 31 and output the second output data from the memory interface 38 of the memory; in response to the second self-test instruction, the second error correction code engine 34 is self-tested to obtain the second self-test result; wherein, the second result is that the first error correction code engine 31 has failed and the second error correction code engine 34 is working normally.

[0147] If the first self-test result is the third result, the functional safety register 37 is used to shut down the first error correction code engine 31 and the second error correction code engine 34, and output the raw data from the memory interface 38 of the memory. The third result indicates that both the first error correction code engine 31 and the second error correction code engine 34 have failed.

[0148] If the first self-test result is the fourth result, the functional safety register 37 is used to shut down the second error correction code engine 34 and output the first output data from the memory interface 38 of the memory; in response to the third self-test instruction, the first error correction code engine 31 is self-tested to obtain the third self-test result, wherein the fourth result is that the first error correction code engine 31 is working normally and the second error correction code engine 34 has failed.

[0149] The memory disclosed herein has four operating modes. Mode 1 is when both the first error correction engine 31 and the second error correction engine 34 are operating normally. Mode 2 is a self-test mode, which has three modes: self-testing of both the first and second error correction engines 31, self-testing of the first error correction engine 31, and self-testing of the second error correction engine 34. Mode 3 is when the first error correction engine 31 is off, and the second error correction engine 34 is operating normally. Mode 4 is when the second error correction engine 34 is off, and the first error correction engine 34 is operating normally. It should be noted that Modes 1, 3, and 4 are normal operating modes, while Mode 2 is a self-test mode entered when a self-test command is sent when there is a testing requirement.

[0150] like Figure 10 As shown, a dual-engine failure indicates that both the first error correction engine 31 and the second error correction engine 34 have failed. Engine 1 failure indicates a failure in the first error correction engine 31, and Engine 2 failure indicates a failure in the second error correction engine 34. Similarly, a dual-engine normal operation indicates that both the first error correction engine 31 and the second error correction engine 34 are functioning normally. Engine 1 normal operation indicates that the first error correction engine 31 is functioning normally, and Engine 2 normal operation indicates that the second error correction engine 34 is functioning normally.

[0151] Depend on Figure 10 It can be seen that Mode 1 and Mode 2 can work together. When Mode 1 and Mode 2 work together, if a dual-engine failure is detected, it means that the dual engines have failed. The raw data is directly output from memory interface 38 and an alarm warning is issued.

[0152] When Mode 1 and Mode 2 are working together, if a fault is detected in Engine 1, the system will switch from "Mode 1 and Mode 2 working together" to "Mode 3 and Mode 2 working together". When Mode 3 and Mode 2 are working together, if a fault is detected in Engine 2, it indicates that both engines have failed. The raw data will be output directly from memory interface 38, and an alarm warning will be issued.

[0153] When Mode 1 and Mode 2 are working together, if a fault is detected in Engine 2, the system will switch from "Mode 1 and Mode 2 working together" to "Mode 4 and Mode 2 working together". When Mode 4 and Mode 2 are working together, if a fault is detected in Engine 1, it indicates that both engines have failed. The raw data will be output directly from memory interface 38, and an alarm warning will be issued.

[0154] It should be noted that the memory integrates two ECC engines. When the system needs to detect faults, it directly sends commands to inject faults into the two ECC engines, detects the correctness of the ECC engine functions, prevents ECC engine failures from becoming latent faults, and greatly improves the reliability of the system.

[0155] In one embodiment, the memory also includes an alarm pin (not shown in the figure), which is a newly added dedicated alarm pin that can quickly feed back an alarm signal (such as the signal on the alarm flag bit) to the alarm pin when the ECC engine malfunctions. The verification module 35 can also be used to generate an alarm signal when the indication data indicates that the first output data has an error; the functional safety register 37 and / or the alarm pin are used to receive the alarm signal and trigger an alarm.

[0156] For example, such as Figure 9 As shown, the original data and error correction codes in the memory pass through the second delay module 33, and then through the second error correction code engine 34 to perform error correction processing on the original data before being sent to the verification module 35. The first error correction code engine 31 uses error correction codes to perform error correction processing on the original data, and then passes through the first delay module 32, and after delay processing, it is sent to the verification module 35.

[0157] The verification module 35 compares the first verification data output by the first delay module 32 and the second verification data output by the second error correction engine 34. If the comparison results are equal, it indicates that the first error correction engine 31 is secure. If the comparison results are unequal, it indicates that there may be a potential risk in the ECC engine of the system, and an alarm signal will be generated. The alarm signal will be output to the dedicated alarm pin (alarm pin, in...). Figure 9 (Not shown in the image) or output to Functional Safety Register 37 so that the system can read the flag bit.

[0158] This disclosure designs a two-level security mechanism for the first error correction code engine 31, namely, a first delay module 32, a second delay module 33, a second error correction code engine 34, a verification module 35, and an alarm pin or functional safety register 37.

[0159] The secondary security mechanism of this embodiment ensures that when the primary security measure (first error correction engine 31) fails, the secondary security mechanism can quickly detect that the primary security measure has failed. This can significantly improve the reliability and security of the system.

[0160] In addition, this disclosure also provides an electronic device. Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure is shown. For example... Figure 11As shown, the electronic device 1100 includes a memory. The memory can perform the methods described above; details regarding the memory can be found in the relevant descriptions of the embodiments of this disclosure above, and will not be repeated here.

[0161] Among them, the memory can be a combination Figures 3-9 The above embodiments illustrate any type of memory.

[0162] For example, electronic device 1100 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, stylus, true wireless earbuds, car center console screen, car, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, and tablets. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0163] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. This disclosure is not limited to the specific steps and structures described above and shown in the figures. Those skilled in the art can make various changes, modifications, and additions after understanding the spirit of this disclosure. Furthermore, for the sake of brevity, detailed descriptions of known technologies are omitted here.

[0164] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0165] In addition, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0166] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory operation method, characterized in that, include: Obtain the original data and error correction codes, wherein the error correction codes are used to correct errors in the original data; Based on the error correction code, the original data is subjected to error correction processing to obtain first data, the first data including first output data; The first data is delayed to obtain the first verification data; The original data and the error correction code are delayed to obtain second data, which includes delayed data and delayed error correction code. Based on the delay error correction code, the delay data is processed to obtain the second verification data; The first verification data and the second verification data are verified to obtain indication data, which is used to indicate whether the first output data is correct.

2. The memory operation method according to claim 1, characterized in that, The first data also includes a first flag bit, and the second verification data includes a second flag bit; The step of delaying the first data to obtain the first verification data includes: The first flag bit is delayed to obtain the first verification data, which includes the delayed first flag bit. The step of verifying the first verification data and the second verification data to obtain indication data includes: The delayed first and second flag bits are verified to obtain the indication data; The time for delaying the processing of the first flag bit is equal to the time for delaying the processing of the original data and the error correction code.

3. The memory operation method according to claim 1, characterized in that, The second verification data includes the second output data; The step of delaying the first data to obtain the first verification data includes: The first output data is delayed to obtain the first verification data, which includes the delayed first output data. The step of verifying the first verification data and the second verification data to obtain indication data includes: The delayed first output data and the second output data are verified to obtain the indication data; The time for delaying the first output data is equal to the time for delaying the original data and the error correction code.

4. The memory operation method according to claim 1, characterized in that, The first data also includes a first flag bit, and the second verification data includes a second flag bit and second output data; The step of delaying the first data to obtain the first verification data includes: The first output data and the first flag bit are delayed to obtain the first verification data, which includes the delayed first output data and the delayed first flag bit. The step of verifying the first verification data and the second verification data to obtain indication data includes: The delayed first output data and the second output data are verified to obtain a first verification result; The delayed first and second flag bits are verified to obtain a second verification result; Based on the first verification result and the second verification result, the indication data is obtained; The time for delaying the first output data and the first flag bit is equal to the time for delaying the original data and the error correction code.

5. The memory operation method according to claim 3 or 4, characterized in that, Before verifying the first verification data and the second verification data to obtain the indication data, the method further includes: The delayed first output data and the delayed second output data are output, and both the delayed first output data and the delayed second output data are used for internal operations in the memory.

6. The memory operation method according to claim 1, characterized in that, The memory includes a first error correction code engine and a second error correction code engine; The method further includes: In response to the first self-test command, random data and error correction check codes are generated, and error injection processing is performed on the random data to obtain error data. The error correction check codes are used to correct the error data. The first error correction code engine performs error correction processing on the erroneous data based on the error correction check code to obtain the first flag bit; The second error correction code engine performs error correction processing on the erroneous data based on the error correction check code to obtain the second flag bit; The first flag bit and the second flag bit are verified to obtain the first self-test result.

7. The memory operation method according to claim 6, characterized in that, If the first self-test result is the first result, the first output data is output from the memory interface of the memory, wherein the first result indicates that both the first error correction code engine and the second error correction code engine are working normally; or, If the first self-test result is the second result, the first error correction code engine is shut down, and second output data is output from the memory interface of the memory; in response to the second self-test instruction, the second error correction code engine is self-tested to obtain a second self-test result; wherein, the second result indicates that the first error correction code engine has failed, and the second error correction code engine is working normally; or, If the first self-test result is the third result, then the first error correction code engine and the second error correction code engine are shut down, and the original data is output from the memory interface of the memory. The third result indicates that both the first and second error correction code engines have failed; or... If the first self-test result is the fourth result, the second error correction code engine is shut down, and the first output data is output from the memory interface of the memory; in response to the third self-test instruction, the first error correction code engine is self-tested to obtain the third self-test result, wherein the fourth result is that the first error correction code engine is working normally and the second error correction code engine has failed.

8. The memory operation method according to claim 1, characterized in that, An alarm signal is generated if the indicated data indicates that the first output data contains an error.

9. A memory, characterized in that, include: The first error correction code engine is used to obtain the original data and error correction codes, wherein the error correction codes are used to correct errors in the original data; Based on the error correction code, the original data is subjected to error correction processing to obtain first data, the first data including first output data; The first delay module is used to delay the first data to obtain the first verification data; The second delay module is used to delay the original data and the error correction code to obtain second data, the second data including delayed data and delayed error correction code; The second error correction code engine is used to perform error correction processing on the delayed data based on the delayed error correction code to obtain the second verification data; The verification module is used to verify the first verification data and the second verification data to obtain indication data, which is used to indicate whether the first output data is correct.

10. The memory according to claim 9, characterized in that, The first data also includes a first flag bit, and the second verification data includes a second flag bit; The first delay module is further configured to delay the first flag bit to obtain first verification data; the first verification data includes the delayed first flag bit. The verification module is also used to verify the delayed first flag bit and the second flag bit to obtain the indication data; The time for delaying the processing of the first flag bit is equal to the time for delaying the processing of the original data and the error correction code.

11. The memory according to claim 9, characterized in that, The second verification data includes the second output data; The first delay module is further configured to delay the first output data to obtain the first verification data, wherein the first verification data includes the delayed first output data; The verification module is also used to verify the delayed first output data and the second output data to obtain the indication data; The time for delaying the first output data is equal to the time for delaying the original data and the error correction code.

12. The memory according to claim 9, characterized in that, The first data also includes a first flag bit, and the second verification data includes a second flag bit and second output data; The first delay module is further configured to delay the first output data and the first flag bit to obtain the first verification data, wherein the first verification data includes the delayed first output data and the delayed first flag bit. The verification module is also used to verify the delayed first output data and the second output data to obtain a first verification result; The delayed first and second flag bits are verified to obtain a second verification result; Based on the first verification result and the second verification result, the indication data is obtained; The time for delaying the first output data and the first flag bit is equal to the time for delaying the original data and the error correction code.

13. The memory according to claim 11, characterized in that, The first delay module is also used to output the delayed first output data; the second error correction engine is also used to output the second output data, and the delayed first output data and the second output data are both used for internal operations of the memory.

14. The memory according to claim 11, characterized in that, The memory also includes a self-test data fault injection module; The self-test data fault injection module is used to respond to the first self-test command, generate random data and error correction check codes, and perform error injection processing on the random data to obtain error data. The error correction check codes are used to correct the error data. The first error correction code engine is further configured to perform error correction processing on the erroneous data based on the error correction check code to obtain a first flag bit; The second error correction code engine is also used to perform error correction processing on the erroneous data based on the error correction check code to obtain a second flag bit; The verification module is also used to verify the first flag bit and the second flag bit to obtain a first self-test result.

15. The memory according to claim 14, characterized in that, The memory also includes a functional safety register; If the first self-test result is the first result, the first output data is output from the memory interface of the memory, wherein the first result indicates that both the first error correction code engine and the second error correction code engine are working normally; or, If the first self-test result is the second result, the functional safety register is used to disable the first error correction code engine and output second output data from the memory interface of the memory; in response to the second self-test instruction, a self-test is performed on the second error correction code engine to obtain a second self-test result; wherein, the second result indicates that the first error correction code engine has failed and the second error correction code engine is working normally; or, If the first self-test result is the third result, the functional safety register is used to disable the first error correction code engine and the second error correction code engine, and output the original data from the memory interface of the memory, wherein the third result is that both the first error correction code engine and the second error correction code engine have failed; or, If the first self-test result is the fourth result, the functional safety register is used to shut down the second error correction code engine and output the first output data from the memory interface of the memory; in response to the third self-test instruction, the first error correction code engine is self-tested to obtain the third self-test result, wherein the fourth result is that the first error correction code engine is working normally and the second error correction code engine has failed.

16. The memory according to claim 15, characterized in that, The memory also includes an alarm pin; The verification module is also used to generate an alarm signal when the indication data indicates that there is an error in the first output data; The functional safety register and / or alarm pin are used to receive the alarm signal and trigger an alarm.

17. An electronic device, characterized in that, include: The memory as described in any one of claims 9 to 16.

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