Flash control layer data correction process test method, test device and computer program product

Abstract

Embodiments of the present application disclose a flash control layer data error correction process test method, test equipment and computer program product. The method comprises: performing at least one error correction process according to a preset error correction verification logic; and checking whether record information related to a read retry voltage table position in a flash control layer is consistent with expected record information corresponding to the preset error correction verification logic during execution of the error correction process. The present application can significantly improve the read performance stability and data reliability of an SSD under complex working conditions.

Description

Technical Field

[0001] This application relates to the field of storage device testing technology, and in particular to a flash memory control layer data error correction process testing method, testing equipment, and computer program product. Background Technology

[0002] In the data error correction process of the Flash Control Layer (FCL), existing testing methods only focus on whether the error correction function exists, that is, only verifying whether the error correction process is triggered and whether the error correction is ultimately successful. However, the internal execution logic of the error correction process directly determines the read performance and reliability of the SSD. If there are defects in the internal logic of the error correction process in the firmware, even if the error correction is ultimately successful, it may lead to an unnecessary increase in the number of read retries, increased power consumption, decreased performance, and even the risk of data loss under certain boundary conditions. Summary of the Invention

[0003] This application provides a flash memory control layer data error correction process testing method, testing equipment, and computer program product to significantly improve the read performance stability and data reliability of SSDs under complex operating conditions.

[0004] In a first aspect, embodiments of this application provide a method for testing the data error correction process of a flash memory control layer, the method comprising: Based on the preset error correction and verification logic, execute the error correction process at least once; During the error correction process, it is verified whether the recorded information related to the read retest voltage meter setting inside the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic.

[0005] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: After each successful error correction, check whether the specified retest voltmeter setting is located at the first expected position of the preset first retest voltmeter. If yes, output a test success message; otherwise, output a test failure message.

[0006] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic further includes: After each successful error correction, check whether the previously specified retest voltmeter setting is located at the second expected position of the preset first retest voltmeter.

[0007] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: After each successful error correction, check whether all specified retest voltmeter ranges are located at the corresponding expected positions of the preset first retest voltmeter.

[0008] In at least one specific implementation, the expected positions are arranged in order from nearest to farthest from the start of the current error correction process, and / or, the first read retest voltmeter is a fast read retest voltmeter range table, and / or, the error correction verification logic is set to the most recent success priority logic.

[0009] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: Verify that the default reading voltmeter value has been updated to the same voltmeter range used in multiple successful error corrections.

[0010] The process of performing at least one error correction includes: Specify the Xth read retest voltmeter as the required range for successful error correction, and continuously cycle Y times to ensure successful error correction at the Xth range, where X and Y are both integers, and Y is greater than or equal to the preset update threshold. The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic includes: Check if the default reading of the voltmeter has been updated to level X.

[0011] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic includes: Verify whether the voltmeter ranges were traversed in the preset order and hardware decoding was performed until successful, and whether software decoding was performed once after all ranges failed to be hardware decoded.

[0012] In at least one specific implementation, prior to executing the error correction process at least once, the following is included: The bits in the physical page of the superblock to be tested are flipped to inject real physical error information, thereby triggering the data error correction process.

[0013] In at least one specific implementation, the real physical injection error information includes: flipping only the bits of the user data segment while keeping the error correction code verification information of the flash page unchanged.

[0014] In at least one specific implementation, the real physical injection error information includes: independently preparing test data and injecting error bits for the low, middle and high pages of the multi-layer storage cell flash memory chip, respectively.

[0015] Secondly, embodiments of this application provide a test device including a processor and a memory, the memory being coupled to the processor, the memory being used to store computer program code, the computer program code including computer instructions, and when the processor reads the computer instructions from the memory, causing the processor to execute the steps in the flash memory control layer data error correction process test method as described in the first aspect.

[0016] Thirdly, embodiments of this application provide a computer program product, the computer program product comprising: computer program code, which, when run on a computer, causes the computer to execute the steps in the flash memory control layer data error correction process test method as described in the first aspect.

[0017] The beneficial effects of this application are: This application embodiment actively captures the recorded information related to the read retest voltage meter setting within the flash memory control layer during the error correction process, and compares it item by item with the expected recorded information corresponding to the preset logic. This extends the testing granularity to the management behavior level within the firmware, thereby enabling the early detection of logical defects that may lead to performance degradation or failure under boundary conditions even if the error correction function exists during the firmware development stage. This ensures that the internal management logic of the flash memory control layer error correction function fully meets the design expectations, significantly improving the read performance stability and data reliability of the SSD under complex operating conditions. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the data error correction process test method for the flash memory control layer according to an embodiment of this application.

[0020] Figure 2 This is a flowchart illustrating the flash memory control layer data error correction process test method according to the first embodiment of this application.

[0021] Figure 3This is a flowchart illustrating the flash memory control layer data error correction process test method according to the second embodiment of this application.

[0022] Figure 4 This is a schematic flowchart of the flash memory control layer data error correction process test method according to the third embodiment of this application.

[0023] Figure 5 This is a schematic diagram of the structure of the test equipment according to an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0026] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0027] In the firmware architecture of a solid-state drive (SSD), the Flash Control Layer (FCL) is responsible for direct command interaction, data transfer, and error correction with the NAND flash memory chips. When the FCL performs a read operation, if an uncorrectable hardware decoding error occurs at the default read reference voltage, a read retry process must be initiated. This involves rereading data by traversing multiple levels (i.e., different read reference voltage offset values) in the Read Retry Table (RRT) until error correction is successful or the traversal is complete. To improve read retry efficiency, the FCL also maintains a FastSearch Table and a Default Read Table. These tables record the order of recently successfully used RRT levels (updated according to the "most recent success priority" principle) and the statistically optimal default starting level (updated according to the "frequency priority" principle), respectively. The correctness of these error correction and verification logics directly affects the SSD's read performance and data reliability.

[0028] Currently, testing methods for FCL error correction primarily focus on verifying whether the error correction process is triggered and whether the error correction is ultimately successful. For example, this involves injecting error bits into the flash memory and then checking if data can be successfully read. These methods only focus on the final result of the error correction function and cannot verify whether the internal error correction verification logic of the FCL (e.g., whether the RRT range traversal order is correct, whether the fast search table is updated according to the "most recent success first" rule, and whether the default voltage meter read is set according to the "frequency first" rule) is correctly implemented. Furthermore, existing tests often embed the test logic into the firmware business code, resulting in high coupling between the test code and the business code. Test cases are difficult to add or modify flexibly, and they cannot be executed independently and automatically without the involvement of the FTL (Flash Translation Layer).

[0029] In view of this, this application provides a flash memory control layer data error correction process testing method, aiming to ensure that the firmware can not only successfully correct errors, but also correctly execute the error correction process, thereby significantly improving the read performance stability and data reliability of SSDs under complex operating conditions. Please refer to... Figure 1 The flash memory control layer data error correction process test method of this application embodiment includes: In step S100, at least one error correction process is executed according to the preset error correction verification logic; In step S200, during the error correction process, it is verified whether the recorded information related to the read retest voltage meter range inside the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic.

[0030] Unlike existing technologies that only verify whether the error correction process is triggered and whether the error correction is ultimately successful, without considering the internal records of the FCL related to the RRT range (such as the order of the fast search table, the default voltmeter reading, and the traversal order), this embodiment is the first to propose verifying whether these internal records conform to the preset error correction verification logic during the execution of the error correction process, achieving a leap from "functional verification" to "logic verification." The test framework predefines the error correction verification logic (e.g., "after each successful error correction, the successful range is moved to the first position of the fast search table"), and then triggers the error correction process through software simulation of error injection or real physical error injection. During the process execution, the fast search table, the default voltmeter reading, or the log recording the traversal order inside the FCL are read and compared with the expected record information corresponding to the preset logic, and the comparison result is output.

[0031] Please refer to Figure 2 In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: In step S201, after each successful error correction, it is checked whether the specified read retest voltage meter setting is located at the preset first expected position of the first read retest voltage meter. If yes, output a test success message; otherwise, output a test failure message.

[0032] This application embodiment realizes the detection of errors in the firmware's first read retry voltmeter update algorithm, such as failure to move the gear position successfully or moving to the wrong position.

[0033] Specifically, the error correction process can be simulated by software. The first time the Nth level is specified successfully, the quick search table is read and [N] is confirmed. The second time the Mth level is specified successfully, the quick search table is read and [M, N] is confirmed. If [M, N] is correct, a success message is output; otherwise, a failure message is output and the error is recorded.

[0034] Please continue to refer to this. Figure 2 In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic further includes: In step S202, after each successful error correction, it is checked whether the previously specified retest voltmeter setting is located at the preset second expected position of the first retest voltmeter.

[0035] In this embodiment of the application, for example, after the second successful test (the Mth gear), it is checked not only that the Mth gear is in the first position, but also that the Nth gear is in the second position. If the second position is not the Nth gear, the test is deemed to have failed. This ensures that the error correction process not only moves the most recent gear to the first position, but also correctly maintains the relative order of other gears, effectively avoiding the first reading retest voltmeter being out of order or lost.

[0036] Please continue to refer to this. Figure 2 In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic further includes: In step S203, after each successful error correction, it is checked whether all the specified retest voltage meter ranges are located at the corresponding expected positions of the preset first retest voltage meter.

[0037] In this embodiment, for example, error correction is performed sequentially in four steps (N-level → M-level → N-level → K-level). After each successful step, the contents of the fast search table are checked to ensure they are completely consistent with the expected order (e.g., [N] → [M, N] → [N, M] → [K, N]). If any discrepancy occurs, the test is deemed a failure. This comprehensively verifies the correctness of the dynamic update logic of the first-read retry voltmeter throughout the entire test process, including multiple successes and repeated levels. It can also uncover more complex defects, such as eviction errors when the buffer capacity overflows and failure to promote repeated levels.

[0038] In some possible implementations, the expected positions are arranged in ascending order from the beginning of the current error correction process. The first retest voltmeter is a fast retest voltmeter range table, and the error correction verification logic is set to prioritize the most recent success. "Arranged in ascending order" means that the most recently successfully used range is in the first position, the last successfully used range is in the second position, and the expected positions are arranged in ascending order of success time, from most recent to most recent, as first, second, and so on. The test framework sets the expected values ​​according to this rule.

[0039] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: Verify that the default reading voltmeter value has been updated to the same voltmeter range used in multiple successful error corrections.

[0040] This embodiment proposes a method to verify whether the default reading voltmeter is updated to the same range that has been successfully updated multiple times according to the "frequency priority" rule. Verifying whether the FCL sets the range with the highest statistical success rate as the default reading voltage to optimize the starting point for subsequent read retry can detect errors in the default reading voltmeter update threshold, statistical logic, or update timing.

[0041] For details, please refer to Figure 3 In at least one possible implementation, the execution of the error correction process at least once specifically includes: In step S111, the Xth read retest voltmeter is designated as the required range for successful error correction, and the error correction is successfully completed in the Xth range by Y consecutive cycles, where Y is greater than or equal to the preset update threshold. The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: In step S212, it is checked whether the contents of the default reading voltmeter have been updated to the Xth level.

[0042] In this embodiment, specific operating parameters (number of cycles Y and threshold) are defined to make the test steps quantifiable. This ensures that the default reading voltmeter update must accumulate a sufficient number of successful cycles before it can be triggered, avoiding premature or delayed updates and improving the repeatability and automation of the test.

[0043] For example, if the error correction process specifies the retest voltmeter setting as the 3rd setting and the update threshold is set to 5, then after 5 consecutive successful attempts at setting 3, the default voltmeter reading is performed. If the value is 3, the process passes. However, if the value is updated to 3 after the 4th attempt, it may trigger a premature update defect.

[0044] In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: Verify whether the voltmeter ranges were traversed in the preset order and hardware decoding was performed until successful, and whether software decoding was performed once after all ranges failed to be hardware decoded.

[0045] Specifically, stubs can be installed in the FCL firmware or logs can be recorded through the debug interface for each RRT gear switch, and the results can be compared to see if the execution is performed in ascending or descending order of the index.

[0046] For details, please refer to Figure 4 In at least one specific implementation, before executing the error correction process at least once, the method further includes: In step S121, bits are flipped in the physical page of the superblock to be tested to inject real physical error information, thereby triggering the data error correction process; In at least one specific implementation, the step of verifying whether the recorded information related to the read retest voltage meter setting within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: In step S222, it is checked whether the hard decoding was performed by traversing the retest voltmeter ranges in the preset order until the hard decoding was successful, and whether a soft decoding was performed after all ranges failed to be hard decoded.

[0047] Using real physical error injection (bit flipping) instead of software simulation makes it closer to actual hardware failures. At the same time, by verifying two sub-steps (first traversing RRT hardware decoding in sequence, and then switching to software decoding after failure), the complete path of the basic error correction process is verified to be correct. By using real physical error injection to make hardware decoding inevitably fail, it ensures that the firmware can correctly execute the entire process of first traversing the voltmeter range in the preset order and then performing software decoding when encountering real data corruption.

[0048] In at least one possible implementation, the real physical injection error information specifically includes: While keeping the error correction code verification information of the flash page unchanged, only the bits of its user data segment are flipped.

[0049] In existing technologies, physical errors often affect both data and ECC simultaneously, or occur naturally due to wear and tear. In this embodiment, the ECC is calculated and stored before writing data. Then, a specific command from the flash controller (such as reading back the original data) is used to retrieve the undecoded data buffer, toggles specified bits within it, and then the original write command is used to write back to the same physical page without recalculating the ECC. This constructs a test scenario that can both force the error correction process and precisely control the fault location, making the test repeatable and controllable, and preventing the ECC's own error correction capabilities from accidentally masking firmware logic errors.

[0050] In at least one possible implementation, the real physical injection error information specifically includes: independently preparing test data and injecting error bits for the low, middle and high pages of the multi-layer storage cell flash memory chip, respectively.

[0051] This application embodiment utilizes the physical characteristics of different bit error rates in low, middle, and high pages of TLC / QLC flash memory to independently inject errors for each type of page, ensuring that the FCL error correction process can respond correctly to all page types, avoiding error correction defects caused by differences in page types, thereby improving the comprehensiveness and depth of testing, and enabling the discovery of specific defects that are only triggered on high pages and not on low pages.

[0052] The following examples, Example 1, Example 2, and Example 3, describe in detail the test method for the data error correction process of the flash memory control layer in this application.

[0053] Example 1: Logic Verification of Hardware Decoding and Software Decoding This example starts the test by actually injecting error information into the physical location of the flash memory. The specific test procedure is as follows: 1. Error message injection process Taking a 4-plane, three-level cell (TLC) NAND flash memory as an example: First, modify the size of the master's buffer to one-quarter of the page size, allocate three pages for a total of forty-eight buffers, and prepare random data in the buffers.

[0054] Enable the randomization function and low-density parity-check (LDPC) encoding function of the main flash controller, and write the prepared data in the buffer into the NAND cache through the cachedata in command.

[0055] Then, enable the randomization function of the main flash controller and disable the LDPC decoding function. Use the cache data out command to read the raw data in the NAND cache back into the buffer.

[0056] The above two steps are executed three times. The pages selected for the three buffered data input / output operations are located in the NAND string as low page, mid page, and up page, respectively.

[0057] N error bits are precisely injected into the data segments of the original data in the forty-eight buffers.

[0058] 2. Testing Process Obtain the head super physical block (SPB) from the test block list as the super block to be tested. After erasing the super block to be tested, write the data in the buffer into the super block to be tested using the raw write method.

[0059] Select the low, middle, and high pages of the superblock to be tested, respectively. Enable the randomization function and LDPC encoding function of the main flash controller. Read a 4KB data, a complete physical page, and a multi-plane physical page, respectively, to trigger the FCL error correction process. Check for any logical anomalies within the FCL error correction process by analyzing the printed information during the FCL error correction process.

[0060] This example constructs a fault scenario where hard decoding inevitably fails by injecting real physical errors (bit flips), thereby forcibly triggering the complete Read Retry Voltage Table (RRT) traversal of the hard decoding → software decoding process. Unlike existing black-box tests that only determine "whether error correction was successful," this example can accurately verify the execution logic of the following two key steps: whether the read traversal is performed in a preset order (e.g., increasing RRT level index), and whether the system automatically switches to software decoding after a read traversal fails. The technical effect is to ensure that the basic error correction path of the Flash Controller Layer (FCL) meets design expectations, avoiding unnecessary read retry delays or increased power consumption due to incorrect process order (e.g., disordered read traversal order, some levels not being traversed, skipping traversal and directly entering software decoding), thus ensuring the read performance of the SSD under normal operating conditions.

[0061] Example 2: Quick Search Logic Verification This example implements error message injection using software. The specific process is as follows: Obtain the head super physical block from the test block list as the super block to be tested, initialize the Fast Search Table (FST) used by the super block (i.e., the fast read retest voltmeter range table), and prepare the test data.

[0062] Specify the Nth range in the Read Retry Table (RRT) as the position where hard decoding can successfully correct errors.

[0063] A physical page of the superblock under test is read, triggering a soft injection error message process and initiating hard decoding and error correction. When the Nth level of RRT is executed, the data is successfully recovered. The index of the record in the first level of the fast search table is checked to ensure it equals the index of the Nth level RRT, and that the index of the record in the second level is the default value.

[0064] The Mth RRT file is designated as the position where hardware decoding can successfully correct errors (M≠N).

[0065] Read a physical page of the superblock under test, triggering a soft injection error message process and entering hard decoding and error correction. Check if the RRT level index used during the first error correction is level N. When the M-level RRT is executed, the data is successfully corrected. Check if the index of the record in the first level of the fast search table is equal to the M-level RRT index, and if the index of the record in the second level is equal to the N-level RRT index.

[0066] The Nth RRT level is then designated as the position where hardware decoding can successfully correct errors.

[0067] Read a physical page of the superblock under test, triggering a soft injection error message process and entering hard decoding and error correction. Check if the RRT level index used during the first error correction is level M. When executing level N RRT, the data is successfully corrected. Check if the index of the record in the first level of the fast search table is equal to the level N RRT index, and if the index of the record in the second level is equal to the level M RRT index.

[0068] The Kth RRT is designated as the position where hardware decoding can successfully correct errors (K is a new RRT that has not been recorded in the fast search table).

[0069] Read a physical page of the superblock under test, triggering a soft injection error message process and entering hard decoding and error correction. Check if the RRT level index used during the first error correction is level N. When the Kth level RRT is executed, the data is successfully corrected. Check if the index of the record in the first level of the fast search table is equal to the Kth level RRT index, and if the index of the record in the second level is equal to the Nth level RRT index.

[0070] This example simulates error injection using software, precisely controlling the RRT (Recent Success Rate) level (N→M→N→K) for each successful error correction, and verifying the order changes of the level indexes in the Fast Search Table (FST). Compared to existing technologies that do not involve the internal structure of the FST at all, this example verifies for the first time the correct implementation of the "recent success priority" caching strategy: after each successful error correction, the level used this time must be moved to the head of the table, the original levels are moved backward in reverse order of success time, and the last level that exceeds the capacity is evicted. Its technical effect is that it can discover defects in the firmware's FST update algorithm (such as unsuccessful level movement, incorrect movement positions, and incorrect eviction logic), thereby ensuring that the FST truly plays its role in accelerating subsequent read retries, effectively reducing the average number of read retries and read latency.

[0071] Example 3: Default Read Logic Verification This example implements error message injection using software. The specific process is as follows: Obtain the head super physical block from the test block list as the super block to be tested, initialize the default read table (DRT) used by the super block, and prepare the test data.

[0072] The Xth range in the retest voltage meter is designated as the position where hardware decoding can successfully correct errors.

[0073] The test superblock is read Y times in a loop.

[0074] Check if the default reading of the voltmeter is equal to the reading of the Xth RRT.

[0075] This example simulates error injection using software, specifying the same RRT level (level X) as the only successful level multiple times (Y times), and verifies whether the default read voltage meter (DRT) sets this level as the new default read voltage after reaching the update threshold. This example verifies the correctness of the "frequency priority" statistical strategy: the firmware should set the level with the highest success rate as the default starting retry voltage based on the statistical results of historical successes, ensuring that the default read voltage meter can dynamically adapt to changes in the physical characteristics of flash memory (such as wear and temperature drift), maximizing the hit rate of the first retry, further reducing the number of read retries, and improving the read performance and data access stability of the SSD under complex operating conditions.

[0076] By implementing the above three examples, this application systematically covers the three core logics of the flash memory control layer data error correction process test: basic path control logic (RRT traversal of hardware decoding → software decoding), cache table update logic (fast search table prioritizing the most recently successful result), and adaptive statistical logic (default read voltage meter frequency priority). Through the above verification, logical defects that may still lead to performance degradation or boundary failures even if error correction is ultimately successful can be detected in advance. This ensures that the SSD error correction module guarantees data reliability while its internal management strategy fully meets design expectations, significantly improving the read performance stability and data access efficiency of the SSD under complex operating conditions such as long-term use, temperature changes, and accelerated wear.

[0077] Please refer to Figure 5 This application also provides a testing device, including a processor 100 and a memory 200, wherein the memory 200 is coupled to the processor 100 and is used to store computer program code, the computer program code including computer instructions, wherein when the processor 100 reads the computer instructions from the memory 200, the processor 100 performs the steps of the method in any possible implementation of any of the foregoing embodiments.

[0078] This application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method in any of the possible implementations of the foregoing embodiments.

[0079] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0080] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A test method for data error correction process in flash memory control layer, characterized in that, The method includes: Based on the preset error correction and verification logic, execute the error correction process at least once; During the error correction process, it is verified whether the recorded information related to the read retest voltage meter setting inside the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic.

2. The test method for flash memory control layer data error correction process according to claim 1, characterized in that, The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: After each successful error correction, check whether the specified retest voltmeter setting is located at the first expected position of the preset first retest voltmeter. If yes, output a test success message; otherwise, output a test failure message.

3. The flash memory control layer data error correction process test method according to claim 2, characterized in that, The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic also includes: After each successful error correction, check whether the previously specified retest voltmeter setting is located at the second expected position of the preset first retest voltmeter.

4. The test method for data error correction process of flash memory control layer according to claim 3, characterized in that, The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: After each successful error correction, check whether all specified retest voltmeter ranges are located at the corresponding expected positions of the preset first retest voltmeter.

5. The flash memory control layer data error correction process test method according to claim 4, characterized in that, The expected positions are arranged in order from nearest to farthest from the start of this error correction process, and / or, the first read retest voltmeter is a fast read retest voltmeter range table, and / or, the error correction verification logic is set to the most recent success priority logic.

6. The flash memory control layer data error correction process test method according to claim 1, characterized in that, The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic specifically includes: Verify that the default reading voltmeter value has been updated to the same voltmeter range used in multiple successful error corrections.

7. The flash memory control layer data error correction process test method according to claim 6, characterized in that, The process of performing at least one error correction includes: Specify the Xth read retest voltmeter as the required range for successful error correction, and continuously cycle Y times to ensure successful error correction at the Xth range, where X and Y are both integers, and Y is greater than or equal to the preset update threshold. The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic includes: Check if the default reading of the voltmeter has been updated to level X.

8. The flash memory control layer data error correction process test method according to claim 1, characterized in that, The step of verifying whether the recorded information related to the read retest voltage meter range within the flash memory control layer is consistent with the expected recorded information corresponding to the preset error correction verification logic includes: Verify whether the voltmeter ranges were traversed in the preset order and hardware decoding was performed until successful, and whether software decoding was performed once after all hardware decoding failed.

9. The test method for data error correction process of flash memory control layer according to claim 8, characterized in that, Before performing at least one error correction process, including: The data error correction process is triggered by injecting real physical error information by flipping bits in the physical pages of the superblock under test.

10. The flash memory control layer data error correction process test method according to claim 9, characterized in that, The real physical injection error information includes: flipping only the bits of the user data segment while keeping the error correction code verification information of the flash page unchanged.

11. The flash memory control layer data error correction process test method according to claim 9 or 10, characterized in that, The real physical injection error information includes: preparing test data and injecting error bits independently for the low, middle and high pages of the flash memory chips in the multi-layer storage unit.

12. A testing device, characterized in that, It includes a processor and a memory coupled to the processor. The memory is used to store computer program code, which includes computer instructions. When the processor reads the computer instructions from the memory, the processor performs the steps in the flash memory control layer data error correction process test method as described in any one of claims 1-11.

13. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the steps in the flash memory control layer data error correction process test method as described in any one of claims 1-11.

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