Voltage detection circuit, semiconductor storage device, and control method thereof

Abstract

The present application provides a voltage detection circuit, a semiconductor storage device and a control method thereof. The voltage detection circuit is arranged in the semiconductor storage device. The voltage detection circuit comprises a control unit. The control unit is used to detect a starting voltage level of the semiconductor storage device based on a specific correction result in the semiconductor storage device.

Description

Technical Field

[0001] This invention relates to a voltage detection circuit, a semiconductor memory device, and a control method for the semiconductor memory device. Background Technology

[0002] Existing semiconductor memory devices (e.g., Dynamic Random Access Memory (DRAM)) read initial setting information from a non-volatile memory device provided in the semiconductor memory device when an external power source is connected to the semiconductor memory device. The non-volatile memory device stores initial setting information used to set the operating conditions of the semiconductor memory device (e.g., the operating voltage in the semiconductor memory device) (e.g., Patent Document 1: Japanese Patent Application Publication No. 2001-176290).

[0003] The semiconductor memory device is equipped with a voltage detection circuit to detect the voltage of the external power supply. When the detected voltage reaches the start-up voltage level, the voltage detection circuit activates a trigger signal (high level) to start the start-up operation of the semiconductor memory device (e.g., reading the initial setting information stored in the non-volatile memory device).

[0004] Due to variations in manufacturing conditions or operating environment, the effective start-up voltage level for the trigger signal may deviate from the expected level (i.e., a deviation in the start-up voltage level of the semiconductor memory device). For example, if the trigger signal is effective when the external power supply voltage is below the expected level, there is a risk that the initial setting information cannot be correctly read from the non-volatile memory device. In this case, because the initial setting operation based on the initial setting information cannot be properly performed, there is a possibility of malfunction or failure of the semiconductor memory device. Summary of the Invention

[0005] The present invention provides a voltage detection circuit, a semiconductor memory device, and a control method for the semiconductor memory device, which can suppress deviations in the startup voltage level of the semiconductor memory device caused by deviations in manufacturing conditions or the influence of the usage environment.

[0006] The present invention provides a voltage detection circuit disposed in a semiconductor memory device. The voltage detection circuit includes a control unit for detecting the startup voltage level of the semiconductor memory device based on a specific calibration result in the semiconductor memory device.

[0007] The present invention also provides a semiconductor storage device, which includes the voltage detection circuit of the above invention.

[0008] The present invention also provides a control method for a semiconductor memory device, comprising the steps of: enabling a control unit disposed in a voltage detection circuit of the semiconductor memory device to detect the startup voltage level of the semiconductor memory device based on a specific calibration result in the semiconductor memory device.

[0009] According to the voltage detection circuit, semiconductor memory device, and control method of the semiconductor memory device of the present invention, deviations in the start-up voltage level of the semiconductor memory device caused by manufacturing deviations or changes in usage conditions can be suppressed. Attached Figure Description

[0010] Figure 1 This diagram shows a block illustration of a semiconductor memory device according to an embodiment of the present invention.

[0011] Figure 2 A circuit diagram of an embodiment of the program code selection unit is shown.

[0012] Figure 3 A circuit diagram of an embodiment of the detection unit is shown.

[0013] Figure 4 In the diagram, (a) and (b) show the time progression of the power supply voltage, voltage level detection signal, and the voltage of each node in the detection unit.

[0014] Figure 5 In the diagram, (a) and (b) show the time progression of the power supply voltage, voltage level detection signal, and the voltage of each node in the detection unit.

[0015] Figure 6 A timing diagram showing the time-lapse of voltages for various signals within a semiconductor memory device.

[0016] Figure 7 A timing diagram showing the time-lapse of voltages for various signals within a semiconductor memory device.

[0017] Figure 8 Circuit diagrams showing other embodiments of the detection unit.

[0018] Symbol explanation:

[0019] 1: Semiconductor memory devices;

[0020] 10: Voltage detection circuit;

[0021] 20: Oscillator;

[0022] 30: Correction circuit;

[0023] 40: Boost circuit;

[0024] 50: OTP Control Unit;

[0025] 60: OTP memory;

[0026] 100: Control unit;

[0027] 110: Selection Department;

[0028] 120: Testing Department;

[0029] 121: Pull up the correction section;

[0030] 122: Pull down the calibration section;

[0031] adj_pu[4:0],adj_puv[4:0]: Pull-up calibration code; adj_pd[4:0],adj_pdv[4:0]: Pull-down calibration code; INV1-INV12: Inverter circuit;

[0032] MN0-MN15: NMOS transistors (NMOSFETs); MP0-MP15: PMOS transistors (PMOSFETs); R1-R12: Resistors;

[0033] clk_osc: Clock signal;

[0034] onvdd: trigger signal;

[0035] en_cal,en_pump,en_otp: signal;

[0036] VDD: Voltage;

[0037] cal_busy: signal;

[0038] votp: voltage;

[0039] / reset: signal;

[0040] por_cal: signal;

[0041] n11, n12, n13, n14, n15: Nodes;

[0042] MP(i+6): PMOS transistor (first transistor);

[0043] MPi: PMOS transistor (second transistor);

[0044] i: an integer greater than 0 and less than 4;

[0045] MP(j+6): PMOS transistor;

[0046] j: an integer greater than 0 and less than 5;

[0047] MN(k+6): NMOS transistor (third transistor);

[0048] MNk: NMOS transistor (fourth transistor);

[0049] k: an integer greater than 0 and less than 4;

[0050] R(MN0-MN4): On-resistance of MN0-MN4;

[0051] R(MP0-MP4): On-resistance of MP0-MP4;

[0052] t1-t3, t11-t14, t21-t24, t31-t34: time;

[0053] otp_clk: Clock signal;

[0054] otp_cmd: Command signal;

[0055] otp_adr: Address signal;

[0056] otp_di: Input data signal;

[0057] otp_do: Outputs data signals;

[0058] 111, 113: NAND circuit;

[0059] 112, 114: NOR circuit;

[0060] 115, 116: D flip-flop circuit;

[0061] onpower: signal. Detailed Implementation

[0062] Reference Figure 1 In this embodiment, the semiconductor memory device 1 is, for example, a DRAM such as a Double-Data-Rate4 Synchronous Dynamic Random Access Memory (DDR4 SDRAM). The semiconductor memory device 1 includes a voltage detection circuit 10, an oscillator 20, a correction circuit 30, a boost circuit 40, a One-Time Programmable (OTP) control unit 100, and an OTP memory 60. The voltage detection circuit 10 includes the control unit 100. Furthermore, for the sake of simplicity, other existing configurations of the semiconductor memory device 1 (e.g., memory cell array, power supply circuit, instruction decoder, clock generator, etc.) are not shown here.

[0063] The voltage detection circuit 10 detects the voltage VDD of the external power supply. When the voltage VDD of the external power supply reaches a specific start-up voltage level, the voltage detection circuit asserts the trigger signal onvdd to start the startup operation of the semiconductor memory device 1. The voltage detection circuit 10 outputs the signal onpower, which instructs the OTP control unit 50 to access the OTP memory 60, to the OTP control unit 50.

[0064] Oscillator 20 generates a specific clock signal clk_osc. Oscillator 20 receives the signal en_cal output from correction circuit 30, the signal en_pump output from boost circuit 40, and the signal en_otp output from OTP control unit 50. When oscillator 20 is activated by any one of these signals en_cal, en_pump, and en_otp, it generates the clock signal clk_osc and outputs it to voltage detection circuit 10, correction circuit 30, boost circuit 40, and OTP control unit 50.

[0065] The correction circuit 30 performs ZQ correction operation. When a valid signal por_cal (described later) is input from the voltage detection circuit 10, the correction circuit 30 outputs a valid signal en_cal to the oscillator 20, and performs ZQ correction operation (including pull-up correction and pull-down correction) according to the clock signal clk_osc output from the oscillator 20.

[0066] In this embodiment, during the execution of the ZQ correction operation, the correction circuit 30 effectively represents the execution status of the ZQ correction operation with a signal cal_busy and outputs it to the voltage detection circuit 10. When the ZQ correction operation is completed, the correction circuit 30 outputs pull-up correction code adj_pu[4:0] to display the pull-up correction result and pull-down correction code adj_pd[4:0] to display the pull-down correction result to the voltage detection circuit 10.

[0067] The boost circuit 40 boosts the power supply voltage to generate voltage Votp. For example, when a valid trigger signal onvdd is input from the voltage detection circuit 10, the boost circuit 40 outputs a valid signal en_pump to the oscillator 20, and boosts the power supply voltage (external power supply voltage VDD) according to the clock signal clk_osc output from the oscillator 20, and outputs the boosted voltage as voltage Votp (at this time, Votp > VDD) to the voltage detection circuit 10 and the OTP memory 60. The boost circuit 40 can be constructed using a charge pump circuit.

[0068] In a typical boost circuit 40, the maximum boost rate of the power supply voltage is set to a specific value (e.g., 3, i.e., 3 times the power supply voltage). Therefore, when the trigger signal onvdd is active while the power supply voltage (external power supply voltage VDD) is at a low level, even if the power supply voltage in the boost circuit 40 is boosted to the maximum boost rate, the boosted voltage votp does not reach the voltage level required to read information stored in the OTP memory 60. Therefore, it is necessary to control the timing so that the trigger signal onvdd is active at the appropriate time point when the power supply voltage reaches the appropriate level.

[0069] The OTP control unit 50 reads and writes information to the OTP memory 60. For example, when a valid signal "onpower" is input from the voltage detection circuit 10, the OTP control unit 50 outputs a valid signal "en_otp" to the oscillator 20, and performs reading and writing of information to the OTP memory 60 based on the clock signal "clk_osc" output from the oscillator 20. Here, reading and writing of information to the OTP memory 60 can be performed by sending a clock signal "otp_clk", an instruction signal "otp_cmd", an address signal "otp_adr", and an input data signal "otp_di" to the OTP memory 60 from the OTP control unit 50, and sending an output data signal "otp_do" from the OTP memory 60 to the OTP control unit 50. The input data signal "otp_di" can be input to the OTP control unit 50 from outside the semiconductor memory device 1 via an instruction decoder (not shown), and the output data signal "otp_do" can be output from the OTP control unit 50 to outside the semiconductor memory device 1 via an instruction decoder (not shown).

[0070] The OTP memory 60 stores initial setting information for setting the operating conditions of the semiconductor memory device 1 (e.g., the operating voltage within the semiconductor memory device 1). The OTP memory 60 is activated by the boosted voltage votp in the boost circuit 40. Furthermore, the OTP memory 60 can be constructed using a one-time programmable read-only memory (OTPROM) such as a fuse read-only memory (ROM), or a non-volatile memory such as a laser fuse or other non-volatile memory.

[0071] Next, the configuration of the control unit 100 of the voltage detection circuit 10 will be described. In this embodiment, the control unit 100 detects the startup voltage level of the semiconductor memory device 1 based on a specific calibration result (ZQ calibration in this embodiment) in the semiconductor memory device 1.

[0072] The control unit 100 can detect the startup voltage level of the semiconductor memory device 1 by adjusting the impedance of a circuit (the detection unit 120, described later in this embodiment) containing at least one element based on the ZQ correction result. In this way, the startup voltage level of the semiconductor memory device 1 can be easily detected based on the impedance of the circuit adjusted according to the ZQ correction result.

[0073] The aforementioned circuit can also be housed within the control unit 100. This allows for easy detection of the startup voltage level of the semiconductor memory device 1 within the control unit 100.

[0074] The control unit 100 can detect the startup voltage level of the semiconductor memory device 1 by adjusting the impedance of the circuit using any value within the range of the correction program code that displays the ZQ correction result as the initial value. In this way, the impedance of the circuit can be adjusted while the circuit impedance is initially set based on the initial value.

[0075] When the voltage VDD of the external power supply reaches a specific value (e.g., a voltage level for specific corrections such as ZQ correction), the control unit 100 can detect the startup voltage level of the semiconductor memory device 1 based on a specific correction result in the semiconductor memory device 1. In this way, the startup voltage level of the semiconductor memory device 1 can be detected by performing specific corrections.

[0076] In this embodiment, the control unit 100 includes a display screen. Figure 2 Selection section 110 and display Figure 3 The detection unit 120. The selection unit 110 selects either the initial value of a preset calibration program code or the value of a calibration program code of the ZQ calibration result displayed in the calibration circuit 30. Based on the value of the calibration program code selected by the selection unit 110, the detection unit 120 detects the startup voltage level of the semiconductor memory device 1 (i.e., the level of the power supply voltage at which the trigger signal onvdd is effective).

[0077] Reference Figure 2 The following describes an example of the configuration of the selection unit 110 in this embodiment. The selection unit 110 includes three inverter circuits INV1, INV2, and INV3 constituting the delay unit, two NAND circuits 111 and 113, two NOR circuits 112 and 114, and two D flip-flop circuits 115 and 116. Furthermore, the example described is the case where the delay unit is composed of three inverter circuits INV1, INV2, and INV3, but different numbers of inverter circuits can also be used to construct the delay unit, or other circuits or components different from inverter circuits can be used to construct the delay unit.

[0078] A trigger signal, onvdd, is input to the first input terminal of the NAND circuit 111, and a signal, / reset, is input to the second input terminal of the NAND circuit 111. Three inverter circuits, INV1, INV2, and INV3, are connected in series, and the output signal of the NAND circuit 111 is input to the input terminal of the inverter circuit INV1. Furthermore, in this embodiment, the delay time in the delay section (inverter circuits INV1, INV2, and INV3) is designed to be longer than the ZQ correction period. The output signal of the NAND circuit 111 is input to the first input terminal of the NOR circuit 112, and the output signal of the inverter circuit INV3 is input to the second input terminal of the NOR circuit 112.

[0079] The clock signal clk_osc is input to the first input terminal of the NAND circuit 113, and the output signal por_cal of the NOR circuit 112 is input to the second input terminal of the NAND circuit 113.

[0080] The signal cal_busy is input to the first input terminal of the NOR circuit 114, and the output signal of the NAND circuit 113 is input to the second input terminal of the NOR circuit 114.

[0081] The pull-up calibration code adj_pu[4:0] is input to the D terminal of the D flip-flop circuit 115, the signal / reset is input to the reset terminal of the D flip-flop circuit 115, and the output signal of the NOR circuit 114 is input to the clock terminal of the D flip-flop circuit 115. The pull-down calibration code adj_pd[4:0] is input to the D terminal of the D flip-flop circuit 116, the signal / reset is input to the reset terminal of the D flip-flop circuit 116, and the output signal of the NOR circuit 114 is input to the clock terminal of the D flip-flop circuit 116.

[0082] In the selection unit 110 configured as described above, when the signal / reset is invalid (low level), the initial value of the pull-up correction code adj_puv[4:0] (here, 16) is set in the D flip-flop circuit 115, and the initial value of the pull-down correction code adj_pdv[4:0] (here, 16) is set in the D flip-flop circuit 116. Furthermore, in this embodiment, the case with an initial value of 16 is used as an example for explanation, but the initial value may also be set to other values ​​besides 16. The signal / reset may be a signal input by an external command when an external power supply is applied to the semiconductor memory device 1. The trigger signal onvdd input to the selection unit 110 may be the trigger signal onvdd output from the detection unit 120, or the trigger signal onvdd output from another voltage detection circuit (not shown) different from the detection unit 120.

[0083] After the two D flip-flop circuits 115 and 116 are set with initial values, the selection unit 110 outputs the pull-up correction program code adj_puv[4:0] and the pull-down correction program code adj_pdv[4:0] to the detection unit 120. Thereby, as described later, the detection unit 120 performs the detection process of the startup voltage of the semiconductor memory device 1. During this detection process, when the trigger signal onvdd is active, and consequently, when the signal / reset is active and the signal por_cal is active, the calibration in the control unit 100 (hereinafter referred to as POR (Power On Reset) calibration) begins.

[0084] When POR correction begins, oscillator 20 is activated, and the clock signal clk_osc is toggled. Correction circuit 30 performs ZQ correction. During ZQ correction, the signal cal_busy is enabled to prevent the values ​​held in the two D flip-flop circuits 115 and 116 from being updated. When ZQ correction is complete, the signal cal_busy is disabled. The toggling output of the clock signal clk_osc sets the value of the pull-up correction code adj_pu[4:0] output from correction circuit 30 to the D flip-flop circuit 115, and the toggling output of the clock signal clk_osc sets the value of the pull-down correction code adj_pd[4:0] output from correction circuit 30 to the D flip-flop circuit 116. This updates the values ​​held in the two D flip-flop circuits 115 and 116.

[0085] When the transmission of the pull-up correction code adj_pu[4:0] and pull-down correction code adj_pd[4:0] from the correction circuit 30 to the selection unit 110 is completed, the valid information of the trigger signal onvdd propagated through the delay unit (here, the inverter circuits INV1, INV2, and INV3) is output from the inverter circuit INV3, invalidating the signal por_cal. Therefore, even if the clock signal clk_osc is toggled, or the pull-up correction code adj_pu[4:0] or pull-down correction code adj_pd[4:0] in the correction circuit 30 is updated, the two D flip-flop circuits 115 and 116 can maintain their set values ​​without being updated.

[0086] Next, refer to Figure 3 The following describes an example of the configuration of the detection unit 120 in this embodiment. The detection unit 120 includes multiple resistors R1 to R6, multiple inverter circuits INV5 to INV12, multiple PMOS transistors (PMOSFETs) MP0 to MP14, and multiple NMOS transistors (NMOSFETs) MN0 to MN15. The detection unit 120 detects the startup voltage of the semiconductor memory device 1 by adjusting the impedance based on the ZQ correction result in the correction circuit 30. Here, the detection unit 120 is an example of the "circuit" of the present invention.

[0087] The detection unit 120 includes: an up-correction unit 121 for performing POR correction based on the ZQ correction result in the correction circuit 30; and a down-correction unit 122 for performing POR correction based on the ZQ correction result in the correction circuit 30.

[0088] Five resistors, R1 to R5, are connected in series between the high power supply voltage (VDD) and the low power supply voltage (ground voltage).

[0089] The pull-up correction unit 121 includes multiple PMOS transistors MP0 to MP11 and multiple inverter circuits INV5 to INV9. The gate terminals (control terminals) of each of the PMOS transistors MPi (i is an integer between 0 and 4) and MP(i+6) are connected to the output terminal of the inverter circuit INV(i+5), and the gate terminals of each of the PMOS transistors MP5 and MP11 are connected to a low power supply voltage. The pull-up correction program code adj_puv[i] is input to the inverter circuit INV(i+5). Furthermore, the source terminal of the PMOS transistor MP(j+6) (j is an integer between 0 and 5) is connected to node n11 between resistors R1 and R2, and the drain terminal of the PMOS transistor MP(j+6) is connected to the source terminal of the PMOS transistor MPj (i.e., the channels of PMOS transistors MPj and MP(j+6) are connected in series). Furthermore, the drain terminal of the PMOS transistor MPj is connected to node n12 between resistor R3 and resistor R4.

[0090] The 1-bit signal corresponding to the pull-up correction code adj_puv[4:0] (the logic inversion signal of the pull-up correction code adj_puv[i]) representing the ZQ correction result is input to the respective gate terminals of PMOS transistor MPi and PMOS transistor MP(i+6). Here, each of PMOS transistor MPi and PMOS transistor MP(i+6) is an example of the "first transistor element" of the present invention. PMOS transistor MP(i+6) is an example of the "first transistor" of the present invention, and PMOS transistor MPi is an example of the "second transistor" of the present invention.

[0091] The pull-down correction unit 122 includes multiple NMOS transistors MN0 to MN10. The gate terminals (control terminals) of each NMOS transistor MNk (where k is an integer between 0 and 4) are connected to node n12, and the pull-down correction program code adj_pdv[k] is input to the gate terminals of each NMOS transistor MN(k+6). The drain terminal of NMOS transistor MNk is connected to the drain terminal of NMOS transistor MN5, and the source terminal of NMOS transistor MNk is connected to the drain terminal of NMOS transistor MN(k+6) (i.e., the channels of NMOS transistors MNk and MN(k+6) are connected in series). Furthermore, the source terminal of NMOS transistor MN(k+6) is connected to a low-voltage power supply.

[0092] The 1-bit signal (pull-down correction code adj_pdv[4:0]) corresponding to the pull-down correction code adj_pdv[4:0] representing the ZQ correction result is input to each gate terminal of the NMOS transistor MN(k+6). Here, NMOS transistors MNk and MN(k+6) are examples of the "second transistor element" of this invention. NMOS transistor MN(k+6) is an example of the "third transistor" of this invention, and NMOS transistor MNk is an example of the "fourth transistor" of this invention.

[0093] The source terminal of PMOS transistor MP12 is connected to a high-voltage power supply, and the drain terminal of PMOS transistor MP12 is connected to the drain terminal of NMOS transistor MN5. The gate terminal of PMOS transistor MP12 is connected to the gate terminal of PMOS transistor MP13. The source terminal of PMOS transistor MP13 is connected to a high-voltage power supply, and the drain terminal of PMOS transistor MP13 is connected to the drain terminal of NMOS transistor MN12. The gate terminal of PMOS transistor MP13 is connected to the drain terminal of PMOS transistor MP13 (diode connection).

[0094] The gate terminal of NMOS transistor MN5 is connected to node n12, and the source terminal of NMOS transistor MN5 is connected to the drain terminal of NMOS transistor MN11. The gate terminal of NMOS transistor MN11 is connected to a high-voltage power supply, and the source terminal of NMOS transistor MN11 is connected to a low-voltage power supply.

[0095] The gate terminal of NMOS transistor MN12 is connected to node n13 between resistor R6 and the drain terminal of NMOS transistor MN14. The source terminal of NMOS transistor MN12 is connected to the drain terminal of NMOS transistor MN13. The gate terminal of NMOS transistor MN13 is connected to a high-voltage power supply, and the source terminal of NMOS transistor MN13 is connected to a low-voltage power supply.

[0096] Three inverter circuits, INV10 to INV12, are connected in series. The input terminal of inverter circuit INV10 is connected to node n14 between the drain terminal of PMOS transistor MP12 and the drain terminal of NMOS transistor MN5. Inverter circuit INV12 outputs a trigger signal onvdd.

[0097] Node n15 between inverter circuits INV11 and INV12 is connected to the gate terminal of PMOS transistor MP14. The source terminal of PMOS transistor MP14 is connected to a high-voltage power supply, and the drain terminal of PMOS transistor MP14 is connected to node n11.

[0098] One end of resistor R6 is connected to node n12, and the other end of resistor R6 is connected to the drain terminal of NMOS transistor MN14. The gate terminal of NMOS transistor MN14 is connected to node n12, and the source terminal of NMOS transistor MN14 is connected to the drain terminal of NMOS transistor MN15. The gate terminal of NMOS transistor MN15 is connected to a high-voltage power supply, and the source terminal of NMOS transistor MN15 is connected to a low-voltage power supply.

[0099] In the detection unit 120 configured as described above, a trigger signal onvdd is generated by comparing the voltage at node n12 with the voltage at node n13. For example, when the voltage VDD of the external power supply becomes sufficiently high, the NMOS transistor MN14 becomes on, and the voltage at node n13 drops. The potential at node n14 changes from a high level to a low level, thereby making the trigger signal onvdd a high level. The signal at node n15 (the logic inversion signal of the trigger signal onvdd) is fed back to node n11 for hysteresis control. Through hysteresis control, the voltage at which the trigger signal onvdd is invalid is set to be lower than the voltage at which the trigger signal onvdd is valid. For example, near the voltage at which the trigger signal onvdd is valid, the voltage VDD is affected by voltage fluctuations due to noise or current consumption in the circuit, thus suppressing frequent switching of the trigger signal onvdd.

[0100] The detection unit 120 optimizes the startup voltage (VDD when the trigger signal onvdd is active) of the semiconductor memory device 1 by adjusting the impedance of the pull-up correction unit 121 and the pull-down correction unit 122 based on the ZQ correction result (i.e., the values ​​of the pull-up correction code adj_puv[4:0] and the pull-down correction code adj_pdv[4:0]).

[0101] Reference Figure 4This is an example illustrating the relationship between the startup voltage level of semiconductor memory device 1 and the resistances of each MOS transistor in pull-up correction section 121 and pull-down correction section 122. First, as... Figure 4 As shown in (a), the smaller the on-resistance (R(MN0~MN4)) of the NMOS transistors MN0, MN1, MN2, MN3, and MN4 in the pull-down correction section 122, the lower the voltage at node n14. This means that the startup voltage level of the semiconductor memory device 1 will decrease. Figure 4 As shown in (b), the smaller the on-resistance (R(MP0~MP4)) of the PMOS transistors MP0, MP1, MP2, MP3, and MP4 in the pull-up correction section 121, the closer the voltage at node n12 is to voltage VDD. As a result, the voltage VDD required for node n14 to become a low level will decrease. This means that the startup voltage level of the semiconductor memory device 1 will decrease.

[0102] Reference Figure 5 This is an example illustrating the relationship between the startup voltage level of semiconductor memory device 1 and the values ​​of the pull-up correction code adj_puv[4:0] and the pull-down correction code adj_pdv[4:0]. First, as... Figure 5 As shown in (a), the smaller the value of the pull-down correction code adj_pdv[4:0], the larger the on-resistance (R(MN0~MN4)) of the NMOS transistors MN0, MN1, MN2, MN3, and MN4 in the pull-down correction section 122, and therefore the voltage at node n14 will rise. This means that by reducing the value of the pull-down correction code adj_pdv[4:0], the startup voltage level of the semiconductor memory device 1 will increase. Figure 5 As shown in (b), the smaller the value of the pull-up correction code adj_puv[4:0], the larger the on-resistance (R(MP0~MP4)) of the PMOS transistors MP0, MP1, MP2, MP3, and MP4 in the pull-up correction section 121, and therefore the voltage at node n12 will decrease. As a result, the time until node n14 reaches a low level will become longer. This means that by decreasing the value of the pull-up correction code adj_puv[4:0], the startup voltage level of the semiconductor memory device 1 will become higher.

[0103] Therefore, the startup voltage level of semiconductor memory device 1 varies according to the values ​​of the pull-up correction code adj_puv[4:0] and adj_pdv[4:0], which represent the ZQ correction result.

[0104] Reference Figure 6 and Figure 7 This describes the operation of the semiconductor memory device 1 in this embodiment. Figure 6 A timing diagram showing the time transitions of voltages for each signal within a semiconductor memory device 1 under conditions of slow display element characteristics.

[0105] First, when the semiconductor memory device 1 is powered on, the voltage VDD of the external power supply gradually increases. The detection unit 120 of the control unit 100 uses the pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0] set with an initial value (here, 16) to detect the startup voltage level. Then, when the voltage VDD reaches a specific level (detecting the startup voltage level), the detection unit 120 of the control unit 100 outputs an effective trigger signal onvdd. Herein, the correction circuit 30 performs ZQ correction. (Displayed in...) Figure 6 In the example, ZQ correction first performs pull-up correction, and then pull-down correction is performed after the pull-up correction is completed.

[0106] The pull-up correction result (pull-up correction program code adj_pu[4:0]) in the correction circuit 30 is output from the correction circuit 30 to the selection unit 110 of the control unit 100. The selection unit 110 outputs the pull-up correction program code adj_puv[4:0] corresponding to the input pull-up correction program code adj_pu[4:0] to the detection unit 120. The pull-down correction result (pull-down correction program code adj_pd[4:0]) in the correction circuit 30 is output from the correction circuit 30 to the selection unit 110 of the control unit 100. The selection unit 110 outputs the pull-down correction program code adj_pdv[4:0] corresponding to the input pull-down correction program code adj_pd[4:0] to the detection unit 120.

[0107] Then, when the detection unit 120 receives the pull-up correction code adj_puv[4:0] and the pull-down correction code adj_pdv[4:0] at time t1, it uses the input pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0] to adjust the impedance of the pull-up correction unit 121 and the pull-down correction unit 122. Here, if the component characteristics are slow due to manufacturing deviations, the correction circuit 30 outputs the pull-up correction code adj_pu[4:0] and pull-down correction code adj_pd[4:0] as a larger value (in this case, a value larger than 16) to the control unit 100, indicating that the on-resistance of the MOS transistor has decreased. In this case, as... Figure 5 As the pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0] increase, the start-up voltage detection level in the detection unit 120 decreases. However, since the external power supply voltage VDD is already higher than this start-up voltage detection level, the trigger signal onvdd will not be invalidated, resulting in other operations of the semiconductor memory device 1 (e.g., internal power supply generation).

[0108] Figure 7A timing diagram showing the time transitions of voltages for various signals within a semiconductor memory device 1 under conditions where the display element characteristics are relatively fast.

[0109] After the initial trigger signal onvdd is valid for a time t2, the operation of adjusting the start-up voltage detection level using the pull-up correction code adj_puv[4:0] and the pull-down correction code adj_pdv[4:0] based on the ZQ correction result is displayed. Figure 6 The operation is the same. In cases where component characteristics are faster due to manufacturing deviations, the correction circuit 30 outputs the pull-up correction code adj_pu[4:0] and pull-down correction code adj_pd[4:0] as a smaller value (in this case, smaller than 16) of the increased on-resistance of the MOS transistor to the control unit 100. In this situation, if... Figure 5 As shown, because the pull-up correction code adj_puv[4:0] and the pull-down correction code adj_pdv[4:0] will become smaller, the start-up voltage detection level in the detection unit 120 will become higher. Therefore, if the external power supply voltage VDD rises slowly, the trigger signal onvdd will be temporarily invalidated.

[0110] The detection unit 120 of the control unit 100 uses the pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0] set at time t2 to detect the start-up voltage level. When the voltage VDD reaches a specific level (detection start-up voltage level), the detection unit 120 of the control unit 100 outputs the valid trigger signal onvdd again. Thereby, the correction circuit 30 performs ZQ correction again.

[0111] When the pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0] are input to the detection unit 120 at time t3, the impedances of the pull-up correction unit 121 and pull-down correction unit 122 are adjusted using the input pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0]. This readjusts the start-up voltage detection level in the detection unit 120. If the external environment has not changed significantly from the previous calibration, the values ​​of the pull-up correction code adj_puv[4:0] and pull-down correction code adj_pdv[4:0] input at time t3 are almost identical to the previous values ​​(the values ​​input at time t2). Therefore, the trigger signal onvdd is not invalidated, and other operations of the semiconductor memory device 1 (e.g., internal power generation) are performed.

[0112] As described above, the voltage detection circuit 10, the semiconductor memory device 1 and the control method thereof according to this embodiment detect the start-up voltage level based on the correction results considering the deviation of the manufacturing conditions of the semiconductor memory device 1 or the influence of the usage environment, etc., so the deviation of the start-up voltage level of the semiconductor memory device 1 due to the deviation of the manufacturing conditions of the semiconductor memory device 1 or the influence of the usage environment, etc., can be suppressed.

[0113] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit the invention. Therefore, the elements disclosed in the above embodiments are intended to include all design changes and equivalents that fall within the scope of the present invention.

[0114] In the above embodiments, the example described is based on the case where the pull-up correction section 121 includes PMOS transistors MP0 to MP4, but the present invention is not limited to this case. For example, as Figure 8 As shown, the pull-up correction section 121 may also include resistors R8 to R12 to replace the PMOS transistors MP0 to MP4. The pull-up correction section 121 may also include a PMOS transistor MP15 and a resistor R7 between resistors R1 and R2. In this case, similar to the embodiment described above, deviations in the startup voltage level of the semiconductor memory device 1 due to variations in manufacturing conditions or operating environment can be suppressed.

[0115] In the above embodiment, the pull-down correction unit 122 is described as having NMOS transistors MN0 to MN4 as an example, but the present invention is not limited to this case. For example, the pull-down correction unit 122 may also have a resistor unit instead of NMOS transistors MN0 to MN4. In this case, deviations in the startup voltage level of the semiconductor memory device 1 due to variations in manufacturing conditions or operating environment can also be suppressed.

[0116] In the above embodiments, the semiconductor memory device is described as DRAM, but the present invention is not limited to this case. For example, the semiconductor memory device may also be static random access memory (SRAM), pseudo-static random access memory (pSRAM), flash memory, or other semiconductor memory devices.

[0117] Furthermore, it is displayed in Figure 1 Voltage detection circuit 10, control unit 100, display on Figure 2 Selection section 110 and display Figure 3 and Figure 8The components of the detection unit 120 are one example, but can be appropriately modified, or well-known components or other various types of components can be adopted.

Claims

1. A voltage detection circuit, characterized in that, The voltage detection circuit, disposed in a semiconductor memory device, includes: A control unit is used to detect the startup voltage level of the semiconductor memory device based on a specific calibration result in the semiconductor memory device.

2. The voltage detection circuit according to claim 1, characterized in that, The control unit detects the startup voltage level of the semiconductor memory device based on the ZQ correction result in the semiconductor memory device.

3. The voltage detection circuit according to claim 2, characterized in that, The starting voltage level varies according to the value of the correction code representing the ZQ correction result.

4. The voltage detection circuit according to claim 3, characterized in that, The starting voltage level represents the pull-up correction code value of the ZQ correction result; the smaller the value, the higher the level.

5. The voltage detection circuit according to claim 3, characterized in that, The starting voltage level represents the pull-down correction code value of the ZQ correction result; the smaller the value, the higher the level.

6. The voltage detection circuit according to claim 2, characterized in that, The control unit detects the startup voltage level of the semiconductor memory device by adjusting the impedance of a circuit containing at least one element based on the ZQ correction result.

7. The voltage detection circuit according to claim 6, characterized in that, The circuit includes at least one of the following: Pull-up correction unit, used to perform pull-up correction based on the ZQ correction result; and A pull-down correction unit is used to perform pull-down correction based on the ZQ correction result.

8. The voltage detection circuit according to claim 7, characterized in that, The pull-up correction unit includes: At least one first transistor element is input to a 1-bit signal corresponding to at least one bit representing the ZQ correction result; The first transistor element includes: The first transistor and the second transistor each have a control terminal that is input with the corresponding 1-bit signal; The channels of the first transistor and the second transistor are connected in series.

9. The voltage detection circuit according to claim 7, characterized in that, The pull-up correction unit includes: At least one first transistor element is input to a 1-bit signal corresponding to at least one bit of the ZQ correction result, the first transistor element comprising: A first transistor having a control terminal into which the corresponding 1-bit signal is input; and A resistor unit is connected in series with the channel of the first transistor.

10. The voltage detection circuit according to claim 7, characterized in that, The pull-down correction unit includes: At least one second transistor element is input to a 1-bit signal corresponding to at least one bit of the ZQ correction result, the second transistor element comprising: A third transistor having a control terminal into which the corresponding 1-bit signal is input; and The fourth transistor has its channel connected in series with the channel of the third transistor.

11. The voltage detection circuit according to claim 6, characterized in that, The circuit is located in the control unit.

12. The voltage detection circuit according to claim 6, characterized in that, The control unit detects the startup voltage level of the semiconductor memory device by adjusting the impedance of the circuit using any value within the range of values ​​of the correction program code representing the ZQ correction result as the initial value.

13. The voltage detection circuit according to claim 1, characterized in that, When the voltage of the external power supply reaches a specific value, the control unit detects the startup voltage level of the semiconductor memory device based on a specific calibration result in the semiconductor memory device.

14. A semiconductor memory device, characterized in that, include: A calibration circuit is configured to perform a specific calibration operation in the semiconductor memory device and output a calibration result; as well as Voltage detection circuit, including: A control unit is configured to detect the startup voltage level of the semiconductor memory device based on the calibration result; The control unit includes: The selection unit is configured to select a correction program code from the correction result and a preset initial value; and A detection unit, coupled to the selection unit to receive the calibration program code, is configured to adjust an internal impedance based on the calibration program code to detect a startup voltage level of the semiconductor memory device and output a trigger signal when an external power supply voltage reaches the startup voltage level.

15. The semiconductor memory device according to claim 14, characterized in that, The detection unit includes a pull-up correction unit, which includes a plurality of first transistor elements. Each first transistor element includes a first transistor and a second transistor. The channels of the first transistor and the second transistor are connected in series. The control terminals of the first transistor and the second transistor are controlled based on a corresponding bit of a pull-up correction program code in the correction program code, in order to adjust the pull-up path impedance of the detection unit.

16. The semiconductor memory device according to claim 14, characterized in that, The detection unit includes a pull-down correction unit, which includes a plurality of second transistor elements. Each second transistor element includes a third transistor and a fourth transistor. The channels of the third transistor and the fourth transistor are connected in series. The control terminals of the third transistor and the fourth transistor are controlled based on a corresponding bit of the pull-down correction program code in the correction program code, in order to adjust the pull-down path impedance of the detection unit.

17. The semiconductor memory device according to claim 14, characterized in that, The startup voltage level varies according to the value of the correction program code, and the smaller the value of the correction program code, the higher the startup voltage level.

18. The semiconductor memory device according to claim 14, characterized in that, The selection unit is configured to: After the semiconductor memory device receives power, it first selects the preset initial value as the correction program code for the detection unit to perform initial startup voltage level detection. as well as After the calibration circuit completes the specific calibration operation and outputs the calibration result, the calibration program code based on the calibration result is selected to update the calibration program code used by the detection unit.

19. The semiconductor memory device according to claim 14, characterized in that, The detection unit further includes a feedback path coupled from one point on the path that generates the trigger signal to another point on the detection unit, for providing hysteresis control on the trigger signal to suppress the trigger signal from frequently flipping due to noise when the external power supply voltage is close to the start-up voltage level.

20. A control method for a semiconductor memory device, characterized in that, It includes the step of: enabling a control unit disposed in the voltage detection circuit of the semiconductor memory device to detect the startup voltage level of the semiconductor memory device based on a specific calibration result in the semiconductor memory device.

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