Resource mapping apparatus, fuse system and memory chip

Abstract

The application provides a resource mapping device, a fuse system and a storage chip. The device comprises: a state machine module configured to, in response to a post-hard packaging repair command, transition between different resource programming states based on preset state transition logic, and output a corresponding first mapping control signal according to the transitioned resource programming state; a decoding logic module connected with the state machine module and configured to, in response to the first mapping control signal, extract sub-repair data of a corresponding bit segment in post-hard packaging repair data and gate a corresponding fuse resource group; and a fuse interface module connected with the decoding logic module and a fuse array and configured to perform a programming operation on the gated fuse resource group to store the extracted sub-repair data into the gated fuse resource group. The application supports any combination of post-hard packaging repair resource bit width and fuse resource bit width, effectively reducing the resource specification limit in chip design.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a resource mapping device, a fuse system, and a memory chip. Background Technology

[0002] During normal use of memory, some memory rows and / or columns may fail. To extend the memory's lifespan in the event of row and / or column failure, Post Package Repair (PPR) methods are used to repair these rows and / or columns. Specifically, redundant rows and / or columns can be used to replace the failed ones. PPR methods include Soft Post Package Repair (SPPR) and Hard Post Package Repair (HPPR). SPPR is a temporary repair, while HPPR is a permanent repair.

[0003] In traditional hard-package repair technology for dynamic random access memory (DRAM), hard-package repair (HPPR) resources and fuse resources adopt a strict one-to-one mapping relationship. The core dependency of this design is that the data bit width of the hard-package repair resources and the fuse resources are completely consistent; for example, if the bit width of a set of hard-package repair resources is 16 bits, then the bit width of the corresponding set of fuse resources is also 16 bits.

[0004] The above-mentioned traditional mapping design has the following technical drawbacks:

[0005] (1) The adaptation flexibility is extremely poor. When the bit width of the repair resource after hard packaging is greater than the bit width of the fuse resource (e.g., the bit width of the repair resource after hard packaging is 16 bits and the bit width of the fuse resource is 8 bits), and the bit width of the fuse resource cannot be extended due to other design constraints, the existing mapping mechanism cannot achieve adaptation, which directly leads to the repair data after hard packaging not being stored in the fuse resource normally.

[0006] (2) The design constraints are stringent, requiring the matching of the bit width specifications of the repair resources and fuse resources after hard packaging, which limits the configuration freedom of the dynamic random access memory redundancy repair resources and increases the difficulty of implementing fuse resource planning in the chip design stage.

[0007] (3) The resource utilization efficiency is low. The existing logic cannot realize the extended mapping storage of a single set of hard-encapsulated repair resources to multiple sets of fuse resources, which makes it impossible to fully utilize the potential storage capacity of fuse resources.

[0008] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of this invention is to provide a resource mapping device, a fuse system, and a memory chip. This invention can completely eliminate the bit width matching constraint between repair resources and fuse resources after hard packaging, support any combination of repair resource bit width and fuse resource bit width after hard packaging, and effectively reduce resource specification limitations in chip design.

[0010] To achieve the above objectives, the present invention provides a resource mapping device, comprising: a state machine module configured to respond to a hard-packaged repair command, transition between different resource programming states based on preset state transition logic, and output a corresponding first mapping control signal according to the transitioned resource programming state; a decoding logic module connected to the state machine module, configured to respond to the received first mapping control signal, extract sub-repair data of corresponding bit segments from the hard-packaged repair data and select the corresponding fuse resource group in the fuse array; and a fuse interface module connected to the decoding logic module and the fuse array, configured to perform a programming operation on the selected fuse resource group to store the extracted sub-repair data in the selected fuse resource group.

[0011] Optionally, the state machine module has a built-in timer, and the state machine module is configured to determine whether the fuse interface module has completed the programming operation on the currently selected fuse resource group based on the timing result of the timer.

[0012] Optionally, the state machine module is configured to control the timer to start automatically timing after each transition to a resource programming state, and after the timer reaches a preset time, determine that the fuse interface module has completed the programming operation of the currently selected fuse resource group and transition to the next state.

[0013] Optionally, the state machine module is further configured to enter the programming completion state and output a second mapping control signal of the first level after the fuse interface module completes the programming operation of the last selected fuse resource group.

[0014] Optionally, the resource mapping device provided by the present invention further includes a broadcast module, which is connected to the state machine module and the fuse array. The broadcast module is configured to enter a broadcast mode in response to the received second mapping control signal of the first level, so as to traverse and read out the sub-repair data of all bits stored in all fuse resource groups in the fuse array and send them to the corresponding hard-encapsulated post-repair latch for storage.

[0015] Optionally, the broadcast module is further configured to output a load clock signal in response to the received second mapping control signal of the first level, so that the hard-packaged repair latch can sequentially latch the sub-repair data of each bit segment.

[0016] Optionally, the state machine module is further configured to enter an idle state and output a second-level second-mapped control signal after the fuse system is reset.

[0017] Optionally, the total number of resource programming states of the state machine module corresponds to the ratio of the bit width of the hard-encapsulated repair data to the bit width of the fuse resource group.

[0018] To achieve the above objectives, the present invention also provides a fuse system, including a fuse array and the resource mapping device described above, wherein the fuse array includes multiple sets of fuse resource groups.

[0019] To achieve the above objectives, the present invention also provides a memory chip, including the resource mapping device or the fuse system described above.

[0020] Compared with the prior art, the resource mapping device, fuse system, and memory chip provided by the present invention have the following beneficial effects:

[0021] (1) This invention, by setting a state machine module configured to respond to a hard-packaged repair command, to flow between different resource programming states based on a preset state transition logic, and to output a corresponding first mapping control signal according to the resource programming state entered, and a decoding logic module configured to respond to the received first mapping control signal, to extract the sub-repair data of the corresponding bit segment in the hard-packaged repair data and to select the corresponding fuse resource group in the fuse array, can break the one-to-one mapping between hard-packaged repair resources (HPPR resources) and fuse resources (Fuse resources). The emission limitation enables flexible one-to-many extended mapping, allowing a single set of hard-packaged repair resources to correspond to two or more sets of fuse resources. This allows for flexible adaptation of resources with different bit widths and supports any combination of hard-packaged repair resource bit width and fuse resource bit width (e.g., a 16-bit hard-packaged repair resource is mapped to two sets of 8-bit fuse resources, and a 32-bit hard-packaged repair resource is mapped to four sets of 8-bit fuse resources). This reduces resource specification limitations in chip design and is suitable for scenarios where the hard-packaged repair resource bit width is greater than the fuse resource bit width.

[0022] (2) The state machine module and the decoding logic module can dynamically control the mapping process between the hard-encapsulated repair resources and the fuse resources, and the switching of the first mapping control signal can realize the switching between different fuse resource groups, which is more conducive to the expansion of the mapping dimension.

[0023] (3) The state machine module and decoding logic module in this invention are independently designed and can be seamlessly integrated into the hard-packaged repair architecture of existing DRAM chips without changing the physical structure of the fuse memory unit, thus having strong compatibility.

[0024] (4) The present invention does not require the design of large-width fuse resources to match the bit width of the repair resources after hard packaging. It can meet the storage requirements by combining existing small-width fuse resources, reduce the area overhead of the fuse array, and thus optimize the resource utilization. Attached Figure Description

[0025] Figure 1 This is a schematic diagram illustrating the mapping relationship between repair resources and fuse resources after hard encapsulation in existing technologies.

[0026] Figure 2 This is a block diagram of a resource mapping device provided in one embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of the mapping principle of a resource mapping device provided in one embodiment of the present invention.

[0028] Figure 4 A flowchart illustrating the operation of a resource mapping apparatus provided in one embodiment of the present invention.

[0029] Figure 5 This is a timing diagram of a resource mapping apparatus provided according to an embodiment of the present invention.

[0030] Figure 6 This is a block diagram of a fuse system provided in one embodiment of the present invention.

[0031] The reference numerals in the attached drawings are explained as follows: Hard-packaged repair latch-100; Fuse array-200; Resource mapping device-300; State machine module-310; Decoding logic module-320; Fuse interface module-330; Broadcast module-340. Detailed Implementation

[0032] The resource mapping device, fuse system, and memory chip proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be noted that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read the invention, and are not intended to limit the implementation conditions of the invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided that the effects and objectives achieved by this invention are the same or similar, should still fall within the scope of the technical content disclosed in this invention.

[0033] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0034] Furthermore, it should be noted that in the description of this specification, the reference to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., means that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0035] To facilitate understanding, a brief explanation of the research background of this invention will be given first.

[0036] Hard-encapsulated repair mode serves as a permanent repair method. This mode relies on blowing a fuse to store the fault address and redundant row mapping information. Please refer to [reference needed]. Figure 1 This is a schematic diagram illustrating the mapping relationship between repair resources and fuse resources after hard packaging in existing technologies. Figure 1In the diagram, Hppr0, ..., Hpprn represent the (n+1) groups of hard-packaged repair resources in the hard-packaged repair latch 100, and Fuse0, Fuse1, ..., Fusen represent the (n+1) groups of fuse resources in the fuse array 200. For example... Figure 1 As shown, the (n+1) hard-encapsulated repair resource groups Hppr0, ..., Hpprn correspond one-to-one with the (n+1) fuse resource groups Fuse0, Fuse1, ..., Fusen, and the data bit width of the two types of resources (e.g., the data bit width of both types of resources is 16 bits) must be strictly equal to ensure the integrity and reliability of the stored data.

[0037] Existing technologies rely on the one-time programmable nature of fuses to save repair configuration information. The mapping logic between the two is fixed in hardware circuitry and lacks the ability to dynamically adjust the mapping rules. Furthermore, when different R&D projects have different hard-packaged repair data bit widths, adaptation can only be achieved by modifying the storage bit width of the fuse resource itself, typically by expanding the 8-bit width to 16 bits. However, the data storage bit width of a fuse corresponds one-to-one with its actual storage unit at the layout level. Changing the bit width inevitably requires readjusting the physical size of the fuse storage unit for each project, resulting in poor overall versatility and severely insufficient design flexibility.

[0038] Based on this, the core idea of ​​the present invention is to provide a resource mapping device, a fuse system, and a memory chip. The present invention can completely remove the bit width matching constraint between repair resources and fuse resources after hard packaging, support any combination of repair resource bit width and fuse resource bit width after hard packaging, and effectively reduce the resource specification limitations in chip design.

[0039] To achieve the above-mentioned goals, this invention provides a resource mapping device, please refer to... Figure 2 This is a structural block diagram of a resource mapping device provided in one embodiment of the present invention. Figure 2 As shown, the resource mapping device 300 provided by the present invention includes: a state machine module 310, configured to respond to a hard-packaged repair command, transition between different resource programming states based on a preset state transition logic, and output a corresponding first mapping control signal according to the transitioned resource programming state; a decoding logic module 320, connected to the state machine module 310, configured to respond to the received first mapping control signal, extract sub-repair data of the corresponding bit segment in the hard-packaged repair data and select the corresponding fuse resource group in the fuse array 200; and a fuse interface module 330, connected to the decoding logic module 320 and the fuse array 200, configured to perform a programming operation on the selected fuse resource group to store the extracted sub-repair data in the selected fuse resource group.

[0040] Therefore, by setting up a state machine module 310 and a decoding logic module 320, this invention can break the one-to-one mapping limitation between hard-packaged repair resources (HPPR resources) and fuse resources, achieving a flexible one-to-many extended mapping. This allows a single set of hard-packaged repair resources to correspond to two or more sets of fuse resources, thereby enabling flexible adaptation of resources with different bit widths. It supports any combination of hard-packaged repair resource bit width and fuse resource bit width (e.g., mapping a 16-bit hard-packaged repair resource to two sets of 8-bit fuse resources, or mapping a 32-bit hard-packaged repair resource to four sets of 8-bit fuse resources). This reduces resource specification limitations in chip design and is suitable for scenarios where the hard-packaged repair resource bit width is greater than the fuse resource bit width. Furthermore, this invention can dynamically control the mapping process between hard-packaged repair resources and fuse resources through the state machine module 310 and the decoding logic module 320, and the switching between different fuse resource groups can be achieved by switching the first mapping control signal, further facilitating the expansion of the mapping dimension. Furthermore, the state machine module 310 and decoding logic module 320 in this invention are independently designed and can be seamlessly integrated into the hard-packaged post-repair architecture of existing DRAM chips without modifying the physical structure of the fuse memory cells, thus exhibiting strong compatibility. Simultaneously, this invention eliminates the need to design large-width fuse resources to match the bit width of the hard-packaged post-repair resources; storage requirements can be met through a combination of existing small-width fuse resources, reducing the area overhead of the fuse array 200 and thereby optimizing resource utilization.

[0041] In some exemplary embodiments, the total number of resource programming states of the state machine module 310 corresponds to the ratio of the bit width of the hard-packaged repair data to the bit width of the fuse resource group. This arrangement facilitates more flexible adaptation of resources with different bit widths, better supporting arbitrary combinations of hard-packaged repair resource bit widths and fuse resource bit widths.

[0042] Specifically, when the bit width of the hard-encapsulated repair resource is 16 bits and the bit width of the fuse resource group is 8 bits, the state machine module 310 can switch between two different resource programming states (e.g., R resource programming state and L resource programming state). The hard-encapsulated repair data with a bit width of 16 bits can be split into sub-repair data of the high 8 bit segment (the sub-repair data of the 8th to 15th bit segment, i.e., the sub-repair data of the bit 8 to bit 15 segment) and sub-repair data of the low 8 bit segment (the sub-repair data of the 0th to 7th bit segment, i.e., the sub-repair data of the bit 0 to bit 7 segment). Similarly, when the bit width of the hard-encapsulated repair resource is 32 bits and the bit width of the fuse resource group is 8 bits, the state machine module 310 can switch between four different resource programming states (e.g., R2 resource programming state, R1 resource programming state, L2 resource programming state, and L1 resource programming state). The 32-bit hard-encapsulated repair data can be split into four groups of 8-bit sub-repair data (sub-repair data of the 24th-31st bit segment, sub-repair data of the 16th-23rd bit segment, sub-repair data of the 8th-15th bit segment, and sub-repair data of the 0th-7th bit segment).

[0043] In some exemplary embodiments, the first mapping control signal is a binary control signal. Therefore, by setting the first mapping control signal to a binary control signal, not only can hardware implementation costs be effectively simplified, but it also offers strong scalability, is suitable for multiple expansions, and can be extended to a multi-bit strobe signal when supporting multiple fuse resource group expansions.

[0044] Specifically, taking a 16-bit width for the repaired resource after hard encapsulation and an 8-bit width for the fuse resource group as an example, the first mapping control signal can be a 1-bit binary control signal. When the state machine module 310 enters the R resource programming state, it outputs a high-level first mapping control signal. The decoding logic module 320 extracts the high 8 bits of sub-repair data based on the received high-level first mapping control signal and selects the corresponding fuse resource group (e.g., the R fuse resource group) in the fuse array 200. After the R fuse resource group completes the storage of the high 8 bits of sub-repair data, the state machine module 310 enters the L resource programming state and outputs a low-level first mapping control signal. The decoding logic module 320 extracts the low 8 bits of sub-repair data based on the received low-level first mapping control signal and selects the corresponding fuse resource group (e.g., the L fuse resource group) in the fuse array 200. It should be noted that by expanding the bit width of the first mapping control signal, more sets of fuse resource groups can be made to correspond to the repair resources after hard packaging. For example, when the bit width of the repair resources after hard packaging is 32 bits and the bit width of the fuse resource group is 8 bits, the first mapping control signal can be a 2-bit binary control signal to realize the alternating selection of four sets of fuse resource groups.

[0045] In some exemplary embodiments, the state machine module 310 has a built-in timer (not shown in the figure) configured to determine, based on the timing result of the timer, whether the fuse interface module 330 has completed the programming operation on the currently selected fuse resource group.

[0046] Therefore, with this configuration, the state machine module 310 can switch states without relying on the signal returned by the fuse interface module 330, thereby reducing hardware overhead and saving chip area and wiring.

[0047] In some exemplary embodiments, the state machine module 310 is configured to control the timer to start automatically timing after each transition to a resource programming state, and after the timer reaches a preset time, determine that the fuse interface module 330 has completed the programming operation on the currently selected fuse resource group and transition to the next state.

[0048] Therefore, this setting allows the entire judgment process to be closed-loop within the state machine module 310, greatly simplifying the complexity of the control link and further reducing hardware overhead. It should be noted that the preset time can be set according to the fuse duration required for the fuse resource group to complete one programming operation.

[0049] In some exemplary embodiments, the state machine module 310 is further configured to transition to a programming completion state and output a second mapping control signal of a first level after the fuse interface module 330 completes the programming operation of the last selected fuse resource group.

[0050] Therefore, by configuring the state machine module 310 to enter the programming completion state after the fuse interface module 330 completes the storage of the last segment of the hard-packaged repair data, it can be indicated that all programming operations have been completed, that is, it can be indicated that all hard-packaged repair data has been burned into the fuse array 200. Furthermore, by configuring the state machine module 310 to output a second mapped control signal with a first level (e.g., a high level) after entering the programming completion state, a trigger source can be provided for subsequent broadcast operations.

[0051] Please continue to refer to this. Figure 2 ,like Figure 2 As shown, in some exemplary embodiments, the resource mapping device 300 provided by the present invention further includes a broadcast module 340, which is connected to the state machine module 310 and the fuse array 200. The broadcast module 340 is configured to enter a broadcast mode in response to a received second mapping control signal of the first level, so as to traverse and read out the sub-repair data of all bits stored in all fuse resource groups in the fuse array 200 and send them to the corresponding hard-encapsulated post-repair latch 100 for storage.

[0052] Therefore, by setting up an independent broadcast module 340 to traverse and read all the sub-repair data of all bit segments stored in all fuse resource groups in the fuse array 200 after completing all programming operations, and sending them to the hard-encapsulated post-repair latch 100 for storage, it is convenient to perform independent power consumption and performance optimization for broadcast behavior. This can effectively reduce system noise and power consumption without affecting the main control logic. At the same time, it can also improve the scalability and cross-project design reuse value of the resource mapping device 300 provided by the present invention, and significantly reduce the development cost and cycle of subsequent derivative designs.

[0053] In some exemplary embodiments, the broadcast module 340 is also configured to output a load clock signal while entering broadcast mode in response to a received second mapping control signal at the first level, so that the hard-packaged repair latch 100 can sequentially latch the sub-repair data of each bit segment under the control of the load clock signal.

[0054] Therefore, by setting the broadcast module 340 to output a loading clock signal while entering broadcast mode, the data output and the synchronous clock can be controlled from the same source, ensuring that the timing of the sub-repair data transmission of multiple bit segments is strictly aligned. This greatly improves the reliability of splicing and restoring the sub-repair data of multiple bit segments into complete hard-packaged post-repair data. As a result, the hard-packaged post-repair latch 100 only needs to respond to the loading clock signal to sequentially latch the sub-repair data of each bit segment, which greatly improves the adaptability of the resource mapping device 300 provided by the present invention to the mapping of hard-packaged post-repair resources and fuse resource groups with different bit widths.

[0055] Please continue to refer to this. Figure 3 This is a schematic diagram of the mapping principle of a resource mapping device 300 provided in one embodiment of the present invention. Figure 3 As shown, the sub-repair data R0 of the high 8-bit segment stored in fuse resource group Fuse0 and the sub-repair data L0 of the low 8-bit segment stored in fuse resource group Fuse1 are sequentially latched into the 16-bit hard-packaged repair resource group Hppr0 in the hard-packaged repair latch 100. Similarly, the sub-repair data Rn of the high 8-bit segment stored in fuse resource group Fuse2n and the sub-repair data Ln of the low 8-bit segment stored in fuse resource group Fuse2n+1 are sequentially latched into the 16-bit hard-packaged repair resource group Hpprn in the hard-packaged repair latch 100.

[0056] In some exemplary embodiments, the state machine module 310 is further configured to enter an idle state and output a second-level mapped control signal after the fuse system is reset. Thus, by configuring the state machine module 310 to enter an idle state and output a second-level (e.g., low-level) mapped control signal after the fuse system is reset, the uncertain state of the control logic after reset can be eliminated, the risk of misoperation during the initialization phase can be avoided, and the robustness of the control logic can be significantly improved.

[0057] Specifically, when the fuse system is reset, the state machine module 310 enters an idle state, and the output second mapping control signal defaults to the second level (e.g., low level). The decoding logic module 320, based on the second mapping control signal at the second level (e.g., low level), is in an inactive state where no fuse resource group is selected. It should be noted that in some other embodiments, the first level can also be set to low level and the second level can be set to high level.

[0058] The following describes the workflow of the resource mapping device 300 provided by this invention, taking a 16-bit bit width for the repaired resource after hard encapsulation and an 8-bit bit width for the fuse resource group as an example. Please refer to... Figure 4This is a flowchart illustrating the operation of a resource mapping device 300 provided in one embodiment of the present invention. Figure 4 As shown, the workflow of the resource mapping device 300 provided by the present invention includes the following steps:

[0059] (1) Initialization: After the fuse system is reset, the state machine module 310 enters the idle state, the state machine module 310 outputs the second mapping control signal of the second level (e.g., low level), and the decoding logic module 320 is in the no-operation state where no fuse resource group is selected.

[0060] (2) Start programming: After receiving the hard-encapsulated repair command and hard-encapsulated repair data, the state machine module 310 switches from the idle state to the R resource programming state and outputs a high-level first mapping control signal. The decoding logic module 320 responds to the high-level first mapping control signal and selects the R fuse resource group in the fuse array 200.

[0061] (3) R fuse resource group programming completed: The timer built into the state machine module 310 automatically counts the time, and after the time reaches the preset time, it sends back the R fuse resource group programming completed signal.

[0062] (4) Switch to L resource programming state: After receiving the R fuse resource group programming completion signal, the state machine module 310 switches to the L resource programming state and outputs a low-level first mapping control signal. The decoding logic module 320 responds to the low-level first mapping control signal and selects the L fuse resource group in the fuse array 200.

[0063] (5) Programming complete: After the L fuse resource group is successfully blown (programmed), the state machine module 310 enters the programming complete state and outputs the second mapping control signal (programming complete signal) with the first level (e.g., high level).

[0064] (6) Triggering broadcast: After receiving the second mapping control signal (programming completion signal) of the first level (e.g., high level), the broadcast module 340 triggers the broadcast mode, reads out the sub-repair data of all segments stored in the fuse array 200, sends it to the corresponding hard-packaged post-repair latch 100, and synchronously sends out the relevant loading clock signal. The hard-packaged post-repair latch 100 only needs to store the data in sequence according to the loading clock signal. At this point, the entire hard-packaged post-repair operation is completed.

[0065] Please continue to refer to this. Figure 5 This is a timing diagram of a resource mapping device 300 provided in one embodiment of the present invention. Figure 5As shown, when the large state enable signal is low, the state machine module 310 outputs a second mapping control signal of a second level (e.g., low level) and enters an idle state. When the large state enable signal is high and the reference load clock signal is high (i.e., a hard-packaged repair command has been received), the state machine module 310 outputs a high-level first mapping control signal and enters the R resource programming state, and the decoding logic module 320 selects the corresponding R fuse resource group. After the R fuse resource group is programmed, the state machine module 310 outputs a low-level first mapping control signal and enters the L resource programming state, and the decoding logic module 320 selects the corresponding L fuse resource group. After the L fuse resource group is programmed, the state machine module 310 outputs a first-level (e.g., high level) second mapping control signal (programming completion signal) and enters the programming completion state. After receiving the programming completion signal, the broadcast module 340 triggers the broadcast mode, reads out the sub-repair data of all segments stored in the fuse array 200, and sends them to the corresponding hard-packaged post-repair latch 100 for latching. Figure 5 As shown, when the bit width of the hard-packaged repair resource is 16 bits and the bit width of the fuse resource group is 8 bits, the data latched in the hard-packaged repair latch 100 is composed of two data outputs from the output data bus. It should be noted that after the broadcast module 340 latches all sub-repair data of all segments into the hard-packaged repair latch 100, the state machine module 310 enters an idle state and outputs a second-level (e.g., low-level) second mapping control signal.

[0066] Based on the same inventive concept, this invention also provides a fuse system, please refer to... Figure 6 This is a block diagram of a fuse system provided in one embodiment of the present invention. Figure 6 As shown, the fuse system provided by the present invention includes a fuse array 200 and the resource mapping device 300 described above. Since the fuse system provided by the present invention includes the resource mapping device 300 provided by the present invention, the fuse system provided by the present invention has at least all the beneficial effects of the resource mapping device 300 provided by the present invention. For details, please refer to the relevant description above, which will not be elaborated here.

[0067] It should be noted that, in addition to the fuse array 200 and the resource mapping device 300, the fuse system provided by the present invention also includes an input / output interface control module (not shown in the figure) and other internal read / write logic control modules (not shown in the figure). The specific working principles of the input / output interface control module and other internal read / write logic control modules can be adapted to the understanding by referring to the relevant content in the field of memory chips that are known to those skilled in the art, and will not be elaborated here.

[0068] Based on the same inventive concept, the present invention also provides a memory chip, including the resource mapping device 300 or the fuse system described above. Since the memory chip provided by the present invention includes the resource mapping device 300 provided by the present invention, the memory chip provided by the present invention has at least all the beneficial effects of the resource mapping device 300 provided by the present invention. For details, please refer to the relevant description above; further explanation is not provided here.

[0069] It should be noted that, as those skilled in the art will understand, the memory chip provided by this invention also includes conventional memory chip structures such as core memory arrays, which are known to those skilled in the art. For specific details, please refer to the relevant content in the field of memory chips known to those skilled in the art for an adaptive understanding, which will not be listed here.

[0070] In summary, compared with the prior art, the resource mapping device, fuse system, and memory chip provided by the present invention have the following beneficial effects:

[0071] (1) This invention, by setting a configuration to respond to a hard-packaged repair command, performs a flow between different resource programming states based on a preset state flow logic, outputs a corresponding first mapping control signal according to the resource programming state entered, and is configured to extract the sub-repair data of the corresponding bit segment in the hard-packaged repair data and select the decoding logic module 320 of the corresponding fuse resource group in the fuse array 200 in response to the received first mapping control signal, can break the one-to-one mapping between hard-packaged repair resources (HPPR resources) and fuse resources (Fuse resources). The emission limitation enables flexible one-to-many extended mapping, allowing a single set of hard-packaged repair resources to correspond to two or more sets of fuse resources. This allows for flexible adaptation of resources with different bit widths and supports any combination of hard-packaged repair resource bit width and fuse resource bit width (e.g., a 16-bit hard-packaged repair resource is mapped to two sets of 8-bit fuse resources, and a 32-bit hard-packaged repair resource is mapped to four sets of 8-bit fuse resources). This reduces resource specification limitations in chip design and is suitable for scenarios where the hard-packaged repair resource bit width is greater than the fuse resource bit width.

[0072] (2) The state machine module 310 and the decoding logic module 320 can dynamically control the mapping process between the hard-packaged repair resources and the fuse resources, and the switching of the first mapping control signal can realize the switching between different fuse resource groups, which is more conducive to the expansion of the mapping dimension.

[0073] (3) The state machine module 310 and the decoding logic module 320 in this invention are independently designed and can be seamlessly integrated into the hard-packaged repair architecture of existing DRAM chips without changing the physical structure of the fuse memory unit, thus having strong compatibility.

[0074] (4) The present invention does not require the design of large-width fuse resources to match the bit width of the repair resources after hard packaging. It can meet the storage requirements by combining existing small-width fuse resources, reduce the area overhead of the fuse array 200, and thus optimize the resource utilization.

[0075] It should be noted that the above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A resource mapping device, characterized in that, include: The state machine module is configured to respond to the repair command after hard encapsulation, and to flow between different resource programming states based on the preset state transition logic, and output the corresponding first mapping control signal according to the resource programming state to which it is transitioned. The decoding logic module, connected to the state machine module, is configured to extract the sub-repair data of the corresponding bit segment in the hard-encapsulated repair data and select the corresponding fuse resource group in the fuse array in response to the received first mapping control signal. as well as A fuse interface module, connected to the decoding logic module and the fuse array, is configured to perform programming operations on the selected fuse resource group to store the extracted sub-repair data in the selected fuse resource group.

2. The resource mapping device according to claim 1, characterized in that, The state machine module has a built-in timer, and the state machine module is configured to determine whether the fuse interface module has completed the programming operation on the currently selected fuse resource group based on the timing result of the timer.

3. The resource mapping device according to claim 2, characterized in that, The state machine module is configured to control the timer to start automatically after each transition to a resource programming state, and after the timer reaches a preset time, determine that the fuse interface module has completed the programming operation of the currently selected fuse resource group and transition to the next state.

4. The resource mapping device according to claim 1, characterized in that, The state machine module is further configured to, after the fuse interface module completes the programming operation of the last selected fuse resource group, transition to the programming completion state and output a second mapping control signal of the first level.

5. The resource mapping device according to claim 4, characterized in that, It also includes a broadcast module, which is connected to the state machine module and the fuse array. The broadcast module is configured to enter a broadcast mode in response to the received second mapping control signal of the first level, so as to traverse and read out the sub-repair data of all bits stored in all fuse resource groups in the fuse array and send them to the corresponding hard-encapsulated post-repair latch for storage.

6. The resource mapping device according to claim 5, characterized in that, The broadcast module is also configured to output a load clock signal in response to the received second mapping control signal of the first level, so that the hard-packaged repair latch can sequentially latch the sub-repair data of each bit segment.

7. The resource mapping device according to claim 1, characterized in that, The state machine module is also configured to enter an idle state and output a second-level second mapping control signal after the fuse system is reset.

8. The resource mapping device according to claim 1, characterized in that, The total number of resource programming states of the state machine module corresponds to the ratio of the bit width of the hard-encapsulated repair data to the bit width of the fuse resource group.

9. A fuse system, characterized in that, It includes a fuse array and a resource mapping device as described in any one of claims 1 to 8.

10. A memory chip, characterized in that, Includes the resource mapping device as described in any one of claims 1 to 8 or the fuse system as described in claim 9.

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