Memory module rmt reliability testing method, apparatus, device, and medium

Abstract

The memory module RMT reliability test method, device, equipment and medium provided by the embodiments of the present disclosure comprise: obtaining RMT parameters of a memory module at a test temperature, and determining a margin attenuation rate of the memory module at the test temperature according to the RMT parameters; determining a next test temperature adjacent to the test temperature according to a relationship between the margin attenuation rate of the test temperature and a preset attenuation rate, and obtaining RMT parameters of the memory module at the next test temperature within a preset time; determining failure risk values corresponding to each type of timing margin parameter of the memory module at the test temperature and test voltage according to the same type of timing margin parameter at the same test temperature and the same test voltage; and determining a comprehensive risk value corresponding to each type of timing margin parameter of the memory module according to the failure risk values corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature interval.

Description

Technical Field

[0001] This invention relates to the field of memory technology and related technical fields, specifically to a method, apparatus, device, and medium for RMT reliability testing of memory modules. Background Technology

[0002] Rank Margin Test (RMT) is a core method for verifying the signal integrity and reliability of DDR4 / DDR5 memory modules. It reads the read and write setup / hold timing margins of each memory module through the BIOS and judges whether the signal margin of the memory module meets the specifications.

[0003] In existing technologies, the RMT (Reliability Management) test process for memory modules involves placing the memory module in a constant temperature chamber and unidirectionally increasing the temperature from 0°C to 85°C in fixed 1°C increments. Upon reaching the target temperature, a single RMT data acquisition is triggered by the BIOS, exporting single-temperature margin parameter data. The host computer then plots a temperature-margin curve based on the margin data acquired at different temperature points and determines the memory module's pass / fail status based on the relationship between the margin curve and a set threshold. However, existing technologies only perform a single, instantaneous sampling, failing to distinguish between temporary temperature drift and permanent aging damage. Furthermore, by only conducting a unidirectional temperature increase test, the evaluation result relies solely on the relationship between temperature, the margin curve, and the set threshold, resulting in a binary pass / fail judgment. This approach cannot quantify the actual reliability of the memory module. Summary of the Invention

[0004] In view of this, the embodiments described herein provide a memory module RMT reliability testing method, apparatus, device and medium to improve the defect detection rate of memory modules under all operating conditions.

[0005] Firstly, based on the content of this disclosure, a memory module RMT reliability testing method is provided, including: During the temperature measurement phase, when the temperature of the memory module reaches the test temperature, the RMT parameters of the memory module at the test temperature are acquired within a preset time. Based on the RMT parameters, the margin decay rate of the memory module at the test temperature is determined. The RMT parameters include timing margin parameters and operating condition parameters. The operating condition parameters include test temperature, test voltage, actual temperature, and actual voltage. The temperature measurement phase includes a heating test phase and a cooling test phase. Based on the relationship between the margin decay rate of the test temperature and the preset decay rate, the next test temperature adjacent to the test temperature is determined, and the RMT parameters of the memory module at the next test temperature are obtained within a preset time, until the RMT parameters of the memory module at each test temperature in the heating test phase and at each test temperature in the cooling test phase are obtained. Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the failure risk value corresponding to each type of timing margin parameter of the memory module under the test temperature and the test voltage; Obtain the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and determine the comprehensive risk value of the memory module under each type of timing margin parameter based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range.

[0006] In some embodiments of this disclosure, determining the next test temperature adjacent to the test temperature based on the relationship between the margin decay rate of the test temperature and a preset decay rate includes: The margin decay difference at the test temperature is determined based on the margin decay rate at the test temperature and the preset decay rate. The temperature control step size is determined based on the margin decay difference at the test temperature. Based on the test temperature and the temperature control step size, determine the next test temperature adjacent to the test temperature.

[0007] In some embodiments of this disclosure, determining the failure risk value corresponding to each type of timing margin parameter of the memory module under the same test temperature and test voltage, based on the same type of timing margin parameter under the same test temperature and test voltage, includes: Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the target timing margin parameters of the same type under the same test temperature and the same test voltage. Based on the target timing margin parameters of the same type under the same test temperature and the same test voltage, determine the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the timing margin parameters of the same type under the same test temperature and the same test voltage. Based on the reference margin of the zero-degree rated voltage, the temperature decay coefficient, and the voltage decay coefficient, determine the failure risk value corresponding to the target timing margin parameter of the same type under the same test temperature and the same test voltage.

[0008] In some embodiments of this disclosure, determining the target timing margin parameter of the same type under the same test temperature and test voltage based on the timing margin parameter of the same type under the same test temperature and test voltage includes: Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the average value of the same type of timing margin parameters under the same test temperature and the same test voltage; The standard deviation of the timing margin parameter is determined based on the relationship between the mean value of each timing margin parameter of the same type under the same test temperature and the same test voltage. Based on the relationship between the difference between the mean value of each timing margin parameter of the same type under the same test temperature and the same test voltage and the standard deviation of the timing margin parameter, the target timing margin parameter of the same type under the same test temperature and the same test voltage is determined.

[0009] In some embodiments of this disclosure, determining the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of target timing margin parameters under the same test temperature and the same test voltage, based on the same type of target timing margin parameters under the same test temperature and the same test voltage, includes: Based on the same type of target timing margin parameters under the same test temperature and the same test voltage, determine the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and voltage difference, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin. Based on the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin, determine the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of timing margin parameter under the same test temperature and the same test voltage.

[0010] In some embodiments of this disclosure, determining the comprehensive risk value of the memory module under each type of timing margin parameter, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, includes: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module in different test temperature ranges under each type of timing margin parameter is determined. Based on the sub-risk values ​​corresponding to different test temperature ranges under various types of timing margin parameters, the comprehensive risk value corresponding to the memory module under various types of timing margin parameters is determined.

[0011] In some embodiments of this disclosure, determining the sub-risk value of the memory module for different test temperature ranges under various types of timing margin parameters, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range and the weight value corresponding to each test temperature range, includes: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, the failure risk value with the largest failure risk value is selected as the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range. Based on the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module in different test temperature ranges under each type of timing margin parameter is determined.

[0012] Secondly, according to the present disclosure, a memory module RMT reliability testing device is provided, comprising: The margin decay rate determination module is used to acquire the RMT parameters of the memory module at the test temperature within a preset time during the temperature measurement phase when the temperature of the memory module reaches the test temperature, and determine the margin decay rate of the memory module at the test temperature based on the RMT parameters. The RMT parameters include timing margin parameters and operating condition parameters. The operating condition parameters include test temperature, test voltage, actual temperature and actual voltage. The temperature measurement phase includes a heating test phase and a cooling test phase. The RMT parameter acquisition module is used to determine the next test temperature adjacent to the test temperature based on the relationship between the margin decay rate of the test temperature and the preset decay rate, and to acquire the RMT parameters of the memory module at the next test temperature within a preset time, until the RMT parameters of the memory module at each test temperature in the heating test phase and at each test temperature in the cooling test phase are acquired. The failure risk value determination module is used to determine the failure risk value corresponding to each type of timing margin parameter of the memory module under the same test temperature and the same test voltage, based on the same type of timing margin parameter under the same test temperature and the same test voltage. The comprehensive risk value determination module is used to obtain the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and to determine the comprehensive risk value of the memory module under each type of timing margin parameter based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range.

[0013] Thirdly, according to this disclosure, a computer device is provided, comprising: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any of the first aspects.

[0014] Fourthly, according to this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described in any of the first aspects.

[0015] The memory module RMT reliability testing method provided in this disclosure first determines the step size of the test temperature based on the margin decay rate of the memory module at a test temperature. This enables dynamic switching of the temperature control step size during the heating and cooling test phases, based on the margin decay rate of the memory module at each test temperature. The method acquires the RMT parameters of the memory module at each test temperature. Large step size sampling is used in the margin decay range, while small step size encrypted sampling is automatically switched in the margin sensitive range. This effectively solves the inherent contradiction between the excessive time consumption of high-precision traversal and the easy omission of coarse scanning in the full temperature range test of memory modules. While ensuring high-resolution capture of key failure inflection points, it significantly reduces the invalid test time and significantly improves the overall test efficiency and equipment utilization. Furthermore, this embodiment of the disclosure introduces an extreme value locking mechanism within the interval by first dividing the test temperature range, then obtaining the failure risk value of all test temperature points within each interval, and calculating the comprehensive risk value based on this. Unlike the conventional method of directly averaging data across the entire temperature range, this embodiment of the disclosure can accurately capture the maximum failure risk point (i.e., the "shortest side of the barrel") within each specified temperature range. This technology ensures that even if there is an isolated risk peak in a non-sensitive temperature range, it will not be masked by normal data from other temperature ranges, thereby significantly improving the defect detection rate of the memory module under all operating conditions.

[0016] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a flowchart illustrating a memory module RMT reliability testing method provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a memory module RMT reliability testing device provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure.

[0018] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0021] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] In this article, the terms "or" or "or" are merely a way of describing the relationship between related objects, indicating that there can be three kinds of relationships. For example, A or B can mean that only A exists, both A and B exist, or only B exists.

[0023] Furthermore, in all embodiments of this disclosure, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0024] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two).

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0026] In view of the problems existing in the prior art, the present disclosure provides a memory module RMT reliability testing method. Figure 1 This is a flowchart illustrating a memory module RMT reliability testing method provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the RMT reliability testing method for memory modules includes: S110. During the temperature measurement phase, when the temperature of the memory module reaches the test temperature, the RMT parameters of the memory module at the test temperature are obtained within a preset time, and the margin decay rate of the memory module at the test temperature is determined based on the RMT parameters.

[0027] The RMT parameters include timing margin parameters and operating condition parameters. The operating condition parameters include test temperature, test voltage, actual temperature, and actual voltage. The temperature measurement stage includes a heating test stage and a cooling test stage. The test temperature and test voltage are preset temperatures and preset voltages set by the user, while the actual temperature and actual voltage are the actual temperature and actual voltages collected in real time during the test stage.

[0028] Specifically, the types of timing margin parameters include read setup timing margin parameters, write setup timing margin parameters, read hold timing margin parameters, and write hold timing margin parameters.

[0029] The RMT reliability testing method for memory modules provided in this disclosure includes two temperature testing stages: a heating test stage and a cooling test stage. The specific process of obtaining the RMT parameters of the memory module in the heating test stage will be described below through specific embodiments. The specific process of obtaining the RMT parameters of the memory module in the cooling test stage is the same as that of obtaining the RMT parameters of the memory module in the heating test stage.

[0030] Specifically, during the temperature rise test phase, when the memory module temperature reaches the set first test temperature, multiple timing margin parameters of different types are first obtained at this test temperature, and the average timing margin of the multiple timing margin parameters of different types at this test temperature is calculated. Then, the reciprocal of the average timing margin of the multiple timing margin parameters of different types at this test temperature is calculated relative to the temperature to obtain the margin decay rate of the timing margin parameters of different types at this test temperature. Finally, the timing margin decay rate of the different types of timing margin parameters at this test temperature is selected as the target margin decay rate of the memory module at this test temperature.

[0031] It should be noted that, at a test temperature, by setting a preset constant temperature residence time, RMT data can be collected multiple times at intervals within the constant temperature residence time period.

[0032] Furthermore, it should be noted that in the same round of testing, that is, in the same round of heating or cooling, the test voltage corresponding to the same test temperature is the same. The test voltage corresponding to different test temperatures may be the same or different. However, in different rounds of testing, for example, the test voltage corresponding to the first test temperature in the first round of heating and the first test temperature in the second round of heating may be different, or the test voltage corresponding to the first test temperature in the first round of cooling and the first test temperature in the second round of cooling may be different.

[0033] S120. Based on the relationship between the margin decay rate of the test temperature and the preset decay rate, determine the next test temperature adjacent to the test temperature, and obtain the RMT parameters of the memory module at the next test temperature within a preset time, until the RMT parameters of the memory module at each test temperature in the heating test phase and at each test temperature in the cooling test phase are obtained.

[0034] In the above embodiments, the temperature range for the heating test phase and the cooling test phase is 0-85 degrees Celsius. That is, in the heating test phase, the next test temperature is obtained by sequentially increasing the current test temperature and the temperature control step size; in the cooling test phase, the next test temperature is obtained by sequentially decreasing the current test temperature and the temperature control step size.

[0035] In a specific implementation, the next test temperature adjacent to the test temperature is determined based on the relationship between the margin decay rate of the test temperature and the preset decay rate. This includes: determining the margin decay difference at the test temperature based on the margin decay rate of the test temperature and the preset decay rate; determining the temperature control step size based on the margin decay difference at the test temperature; and determining the next test temperature adjacent to the test temperature based on the test temperature and the temperature control step size.

[0036] Specifically, after step S110 determines the margin decay rate of the memory module at the first test temperature (0 degrees Celsius), the margin decay difference at the first test temperature is determined based on the margin decay rate of the memory module at the first test temperature and the preset margin decay rate. Then, the temperature control step size at the first test temperature is determined based on the correspondence between the margin decay difference and the temperature control step size. Finally, the first test temperature and the temperature control step size are added together to obtain the second test temperature.

[0037] At this point, a control signal is generated to control the temperature rise of the memory module's housing cavity, so that the memory module's temperature reaches the second test temperature. Then, the RMT parameters and margin decay rate of the memory module at the second test temperature are obtained. Based on the margin decay rate corresponding to the second test temperature, the RMT parameters and margin decay rate corresponding to the third test temperature are determined. This process is repeated until the RMT parameters and margin decay rate corresponding to all test temperatures in the temperature rise test phase are determined.

[0038] Similarly, after step S110 determines the margin decay rate of the memory module at the first test temperature (85 degrees Celsius), the margin decay difference at the first test temperature is determined based on the margin decay rate of the memory module at the first test temperature and the preset margin decay rate. Then, the temperature control step size at the first test temperature is determined based on the correspondence between the margin decay difference and the temperature control step size. Finally, the first test temperature is subtracted from the temperature control step size to obtain the second test temperature. This process is repeated until the RMT parameters and margin decay rates corresponding to all test temperatures in the cooling test phase are determined.

[0039] It should be noted that, in the above implementation, the RMT parameters corresponding to all test temperatures in the heating test phase refer to the test temperatures that are gradually increased from the first test temperature (0 degrees Celsius) to 85 degrees Celsius based on the changing temperature control step size, i.e., all test temperatures in the heating test phase are completed. The RMT parameters corresponding to all test temperatures in the cooling test phase refer to the test temperatures that are gradually decreased from the first test temperature (85 degrees Celsius) to 0 degrees Celsius based on the changing temperature control step size, i.e., all test temperatures in the cooling test phase are completed.

[0040] Furthermore, it should be further explained that, based on the correspondence between the margin attenuation difference and the temperature control step size, the temperature control step size at the first test temperature is determined as follows: if the margin attenuation difference at the first test temperature is less than the preset margin attenuation difference, the temperature control step size is automatically increased to 5℃ or 10℃; if the margin attenuation difference at the first test temperature is greater than or equal to the preset margin attenuation difference, the temperature control step size is automatically reduced to 0.5℃ or 1℃ for encrypted sampling.

[0041] S130. Based on the same type of timing margin parameters under the same test temperature and test voltage, determine the failure risk value corresponding to each type of timing margin parameter of the memory module under the test temperature and test voltage.

[0042] In a specific implementation, based on the same type of timing margin parameters under the same test temperature and test voltage, the failure risk value corresponding to each type of timing margin parameter of the memory module under the test temperature and test voltage is determined. This includes: determining the target timing margin parameter of the same type under the same test temperature and test voltage based on the same type of timing margin parameter of the same type under the same test temperature and test voltage; determining the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the target timing margin parameter of the same type under the same test temperature and test voltage based on the target timing margin parameter of the same type under the same test temperature and test voltage; and determining the failure risk value corresponding to the target timing margin parameter of the same type under the same test temperature and test voltage based on the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage.

[0043] Specifically, based on the same type of timing margin parameters under the same test temperature and voltage, the target timing margin parameters of the same type under the same test temperature and voltage are determined, including: determining the mean of the timing margin parameters of the same type under the same test temperature and voltage; determining the standard deviation of the timing margin parameters based on the relationship between each timing margin parameter of the same type under the same test temperature and voltage and the mean of the timing margin parameters; and determining the target timing margin parameters of the same type under the same test temperature and voltage based on the relationship between the difference between each timing margin parameter of the same type under the same test temperature and voltage and the mean of the timing margin parameters and the standard deviation of the timing margin parameters.

[0044] Based on the analysis of step S110, it can be seen that the process of performing heating and cooling tests on the same memory module may involve multiple rounds. The test voltage is the same for heating tests or cooling tests at the same test temperature in the same round, but the test voltage is different for heating tests or cooling tests at the same test temperature in different rounds. Furthermore, the timing margin parameters include different types. Therefore, in this step, the timing margin parameters for the target type (read establish, write establish, read hold, or write hold) at the same test temperature and test voltage are first obtained, and the obtained timing margin parameters at the same test temperature and test voltage are then... The timing margin parameters of the target type are averaged to obtain the mean of the timing margin parameters of the target type under the same test temperature and test voltage. Then, the square of the difference between each timing margin parameter of the target type and the mean of the timing margin parameters under the same test temperature and test voltage is calculated to obtain the standard deviation of the timing margin parameters. Finally, the absolute value of the difference between each timing margin parameter and the mean of the timing margin parameters is calculated. If the absolute value of the difference between the timing margin parameter and the mean of the timing margin parameters is greater than three times the standard deviation of the timing margin parameters, then the timing margin parameter is selected as the target timing margin parameter for the test temperature, test voltage, and target type.

[0045] To give a specific example, during the same round of testing, at the test temperature and test voltage The read setup timing margin parameters obtained during the temperature rise test phase include: At the test temperature and test voltage The read setup timing margin parameters obtained during the cooling test phase include: First, we need to determine the read setup timing margin parameters. The corresponding mean Then, calculate the timing margin parameters for read setup. Relative mean respectively The squares of the differences are used to obtain the read setup timing margin parameters. The standard deviation of the corresponding time margin parameter Finally, the timing margin parameters for reading are established sequentially. with the mean Calculate the difference and analyze the established timing margin parameters. with the mean The absolute value of the difference and 3 times the standard deviation of the time margin parameter The relationship between the timing margin parameters established during reading. with the mean The absolute value of the difference is greater than 3 times the standard deviation of the time series margin parameter. Then read the timing margin parameters. For testing temperature and test voltage The target timing margin parameter for the next read establish type is calculated sequentially, and so on. with the mean The absolute value of the difference and 3 times the standard deviation of the time margin parameter The relationship, ..., read the timing margin parameters. with the mean The absolute value of the difference and 3 times the standard deviation of the time margin parameter The relationship determines the timing margin parameters for read setup. Is this the test temperature? and test voltage The next read establish type target timing margin parameter. Following the above implementation method, the timing margin parameter at the test temperature is determined sequentially. and test voltage Different types of target timing margin parameters.

[0046] Then based on the test temperature and test voltage The read setup timing margin parameters obtained during the temperature rise test phase and at the test temperature and test voltage The read setup timing margin parameters obtained during the cooling test phase are used to determine the test temperature. and test voltage The target timing margin parameters for the read establishment type, and the test temperature. and test voltage Other different types of target timing margin parameters are then determined. Similarly, the target timing margin parameters for the test temperature under different types are determined sequentially.

[0047] It should be noted that the above steps are exemplified at the test temperature. The read setup timing margin parameters for the heating test phase and the read setup timing margin parameters for the cooling test phase are obtained. In other possible implementations, if the heating test phase includes a test temperature... The cooling test phase does not include the test temperature. Therefore, the obtained timing margin parameters only include the test temperature during the heating test phase. The RMT parameters below, if the test temperature is not included in the heating test phase. The cooling test phase includes testing the temperature. Therefore, the obtained timing margin parameters only include the test temperature during the temperature testing phase. The RMT parameters are not described in detail in this embodiment.

[0048] After determining the target timing margin parameters of the same type under the same test temperature and the same test voltage in the above steps, the reference margin, temperature attenuation coefficient and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the target timing margin parameters of the same type under the same test temperature and the same test voltage are determined based on the target timing margin parameters of the same type under the same test temperature and the same test voltage.

[0049] In a specific implementation, based on the same type of target timing margin parameters under the same test temperature and test voltage, the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of target timing margin parameters under the same test temperature and test voltage are determined. This includes: determining the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin based on the same type of target timing margin parameters under the same test temperature and test voltage; and determining the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of timing margin parameters under the same test temperature and test voltage based on the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and voltage difference, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin.

[0050] In the above embodiments, after determining the target timing margin parameters of the same type under the same test temperature and test voltage, a correspondence between test temperature, test voltage, actual temperature, actual voltage, and timing margin parameters is constructed. The sum of temperatures is the sum of the actual temperatures of each target timing margin parameter of the same type under the same test temperature and test voltage. The sum of voltage deviations is the sum of the absolute values ​​of the differences between the actual voltage and the test voltage of each target timing margin parameter of the same type under the same test temperature and test voltage. The sum of timing margins is the sum of the target timing margin parameters of the same type under the same test temperature and test voltage. The variance of the sum of temperatures is the same as that of the target timing margin parameters of the same type under the same test temperature and test voltage. The sum of the squares of the actual temperatures of each target timing margin parameter of the same type under the same test temperature and test voltage; the sum of the variances of the voltage deviations is the sum of the squares of the differences between the actual voltage and the test voltage of each target timing margin parameter of the same type under the same test temperature and test voltage; the sum of the products of temperature and timing margin is the sum of the products of the actual temperature and each target timing margin parameter of the same type under the same test temperature and test voltage; the sum of the products of voltage difference and timing margin is the sum of the products of the voltage difference and each target timing margin parameter of the same type under the same test temperature and test voltage.

[0051] Then construct a binary linear regression model:

[0052] in, These are target timing margin parameters of the same type under test temperature and test voltage. It is a temperature test. It is the voltage deviation between the actual voltage and the test voltage. , and These are the coefficients of the model, which need to be solved using the least squares method.

[0053] This linear regression model can be written in matrix form. ,in, It is column vectors, The number of target timing margin parameters. It is The column vector contains the coefficients to be determined. , It is The matrix, where each row corresponds to a target timing margin parameter of the same type under the same test temperature and test voltage. , The goal of the least squares method is to find This minimizes the sum of squared residuals.

[0054] Its solution is given by the normal equations: Specifically, matrix After conversion, the following conditions are met: .

[0055] in,

[0056]

[0057] in, The temperature and value of the timing margin parameter for the same type of target under the same test temperature and test voltage. The voltage deviation and value of the same type of target timing margin parameter under the same test temperature and the same test voltage. The temperature and variance of the timing margin parameter of the same type under the same test temperature and test voltage. The temperature and variance of the timing margin parameter of the same type under the same test temperature and test voltage. This is the sum of the products of the temperature and voltage differences of the same type of target timing margin parameters under the same test temperature and the same test voltage. This refers to the sum of timing margin parameters for the same type of target under the same test temperature and test voltage. This refers to the sum of the products of temperature and timing margin for the same type of target timing margin parameter under the same test temperature and test voltage. This is the sum of the voltage difference and the product of the timing margin for the same type of target timing margin parameter under the same test temperature and the same test voltage.

[0058] Solving for coefficients using Cramer's Rule and After solving for the coefficients and Subsequently, the reference margin for the zero-degree rated voltage corresponding to the same type of target timing margin parameters under the same test temperature and the same test voltage is: The temperature decay coefficient corresponding to the same type of timing margin parameter under the same test temperature and the same test voltage is - The temperature decay coefficient corresponding to the same type of timing margin parameter under the same test temperature and the same test voltage is - .

[0059] Finally, based on the reference margin, temperature decay coefficient, and voltage decay coefficient of the zero-degree rated voltage corresponding to the same type of timing margin parameters under the same test temperature and the same test voltage, the failure risk value corresponding to the same type of target timing margin parameters under the same test temperature and the same test voltage is determined.

[0060] Among them, the failure risk values ​​corresponding to the same type of target timing margin parameters under the same test temperature and the same test voltage satisfy the following:

[0061] in, For this test temperature, The test voltage at the test temperature. This is a function for the absolute value of floating-point numbers.

[0062] Through the above steps, the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to different types of timing margin parameters under the same test temperature and the same test voltage are determined in sequence, as well as the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to different types of timing margin parameters under different test temperatures and different test voltages. This implementation process does not provide specific explanations for these.

[0063] S140. Obtain the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and determine the comprehensive risk value of the memory module under each type of timing margin parameter based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range.

[0064] In a specific implementation, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, the comprehensive risk value corresponding to the memory module under each type of timing margin parameter is determined, including: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module under different test temperature ranges for each type of timing margin parameter is determined; based on the sub-risk value corresponding to the memory module under different test temperature ranges for each type of timing margin parameter, the comprehensive risk value corresponding to the memory module under each type of timing margin parameter is determined.

[0065] Specifically, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module under different test temperature ranges for each type of timing margin parameter is determined. This includes: selecting the largest failure risk value as the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range; and determining the sub-risk value corresponding to the memory module under different test temperature ranges for each type of timing margin parameter based on the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range.

[0066] After determining the failure risk value corresponding to the same type of target timing margin parameter at each test temperature and test voltage in step S130, according to the pre-set test temperature range division method, for example, the first temperature range is 0 to 40 degrees Celsius with a weight value of 0.2, the second temperature range is 40 to 70 degrees Celsius with a weight value of 0.8, and the third temperature range is 70 to 85 degrees Celsius with a weight value of 0.3, the failure risk value corresponding to the same test voltage and readout timing margin parameter at each test temperature included in the first temperature range is obtained. For example, if the test temperatures included in the first temperature range are 0 degrees Celsius, 2 degrees Celsius, 4 degrees Celsius, 6 degrees Celsius, 8 degrees Celsius, ..., 40 degrees Celsius, then, based on the test temperatures included in the first temperature range, the failure risk value corresponding to the same test voltage and readout timing margin parameter is obtained. By considering the failure risk value corresponding to the read setup timing margin parameter at the same test voltage and the weight value of the first temperature range, the sub-risk value corresponding to the read setup timing margin parameter of the memory module in the first test temperature range is determined. Similarly, the sub-risk values ​​corresponding to the read setup timing margin parameter of the memory module in the second test temperature range and the third test temperature range are determined sequentially. Finally, based on the sub-risk values ​​corresponding to the read setup timing margin parameter of the memory module in the first, second, and third test temperature ranges, the comprehensive risk value corresponding to the read setup timing margin parameter of the memory module at that test voltage is determined.

[0067] Through the above process, the comprehensive risk value corresponding to each type of timing margin parameter of the memory module under different test voltages is determined in sequence.

[0068] Firstly, this embodiment of the present disclosure independently processes timing margin parameters under the same test temperature and voltage, calculating the failure risk value corresponding to each type of margin parameter, such as "read establish," "read hold," "write establish," and "write hold." This setting effectively distinguishes the impact weight of different physical failure mechanisms on the reliability of the memory module: for example, "read / write establish risk" is independently mapped to clock skew and timing alignment accuracy, and "read / write hold risk" is independently mapped to signal reflection and impedance discontinuity characteristics. This overcomes the technical deficiency of traditional single comprehensive scoring methods in being unable to pinpoint the root cause of failure, providing clear data guidance for subsequent hardware debugging and process improvement.

[0069] Secondly, this embodiment of the present disclosure introduces an extreme value locking mechanism within the interval by first dividing the test temperature range, then obtaining the failure risk value of all test temperature points within each test temperature range, and calculating the comprehensive risk value based on this. Unlike the conventional method of directly averaging data across the entire temperature range, this embodiment of the present disclosure can accurately capture the maximum failure risk point (i.e., the "shortest side of the barrel") within each specified temperature range. This technology ensures that even if there is an isolated risk peak in a non-sensitive temperature range, it will not be masked by normal data from other temperature ranges, thereby significantly improving the defect detection rate of the memory module under all operating conditions.

[0070] It should be noted that in the memory module RMT reliability testing method provided in this disclosure, if the memory module includes only one memory unit, then the comprehensive risk value corresponding to the memory module under each type of timing margin parameter is also the comprehensive risk value corresponding to the memory unit included in the memory module under each type of timing margin parameter. If the memory module includes multiple memory units, the RMT parameters corresponding to each memory unit need to be tested separately, and the comprehensive risk value corresponding to each memory unit included in the memory module under each type of timing margin parameter is determined based on the RMT parameters corresponding to each memory unit. This disclosure does not provide specific examples of this.

[0071] The memory module RMT reliability testing method provided in this disclosure first determines the step size of the test temperature based on the acquired margin decay rate of the memory module at a test temperature. This allows for dynamic switching of the temperature control step size during the heating and cooling test phases, based on the margin decay rate of the memory module at each test temperature. This acquires the RMT parameters of the memory module at each test temperature. Large step sizes are used in areas with smooth margin decay, while small step sizes are automatically switched to more intensive sampling in margin-sensitive areas. This effectively resolves the inherent contradiction between the excessive time consumption of high-precision traversal and the potential for missed detections in coarse scanning during full-temperature testing of memory modules. While ensuring high-resolution capture of critical failure inflection points, it significantly reduces invalid test time, thereby significantly improving overall test efficiency and equipment utilization. Furthermore, this disclosure introduces an interval extreme value locking mechanism by first dividing the test temperature range, then acquiring the failure risk value of all test temperature points within each range, and calculating the comprehensive risk value based on this. Unlike conventional methods that directly average data across the entire temperature range, the embodiments disclosed herein can accurately capture the maximum failure risk point (i.e., the "shortest side of the barrel") within each specified temperature range. This technology ensures that even if an isolated risk peak exists in a non-sensitive temperature range, it will not be masked by normal data from other temperature ranges, thereby significantly improving the defect detection rate of the memory module under all operating conditions.

[0072] Based on the above embodiments, this disclosure also provides a memory module RMT reliability testing device. Figure 2 This is a schematic diagram of the structure of a memory module RMT reliability testing device provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the memory module RMT reliability testing device includes: The margin decay rate determination module 210 is used to, during the temperature measurement phase, when the temperature of the memory module reaches the test temperature, acquire the RMT parameters of the memory module at the test temperature within a preset time, and determine the margin decay rate of the memory module at the test temperature based on the RMT parameters. The RMT parameters include timing margin parameters and operating condition parameters. The operating condition parameters include test temperature, test voltage, actual temperature, and actual voltage. The temperature measurement phase includes a heating test phase and a cooling test phase. RMT parameter acquisition module 220 is used to determine the next test temperature adjacent to the test temperature based on the relationship between the margin decay rate of the test temperature and the preset decay rate, and to acquire the RMT parameters of the memory module at the next test temperature within a preset time, until the RMT parameters of the memory module at each test temperature in the heating test phase and the RMT parameters at each test temperature in the cooling test phase are acquired. The failure risk value determination module 230 is used to determine the failure risk value corresponding to each type of timing margin parameter of the memory module under the same test temperature and the same test voltage, based on the same type of timing margin parameter under the same test temperature and the same test voltage. The comprehensive risk value determination module 240 is used to obtain the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and determine the comprehensive risk value of the memory module under each type of timing margin parameter based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range.

[0073] The memory module RMT reliability testing device provided in this disclosure first determines the step size of the test temperature based on the acquired margin decay rate of the memory module at a test temperature. This allows for dynamic switching of the temperature control step size during the heating and cooling test phases, based on the margin decay rate of the memory module at each test temperature. This acquires the RMT parameters of the memory module at each test temperature. Large step sizes are used in the margin decay range, while small step sizes are automatically switched to encrypted sampling in the margin-sensitive range. This effectively resolves the inherent contradiction between the excessive time consumption of high-precision traversal and the potential for missed detections in coarse scanning during full-temperature testing of memory modules. While ensuring high-resolution capture of critical failure inflection points, it significantly reduces invalid test time, thereby significantly improving overall test efficiency and equipment utilization. Furthermore, this disclosure introduces an interval extreme value locking mechanism by first dividing the test temperature range, then acquiring the failure risk value of all test temperature points within each range, and calculating the comprehensive risk value based on this. Unlike conventional methods that directly average data across the entire temperature range, the embodiments disclosed herein can accurately capture the maximum failure risk point (i.e., the "shortest side of the barrel") within each specified temperature range. This technology ensures that even if an isolated risk peak exists in a non-sensitive temperature range, it will not be masked by normal data from other temperature ranges, thereby significantly improving the defect detection rate of the memory module under all operating conditions.

[0074] In some embodiments of this disclosure, determining the next test temperature adjacent to the test temperature based on the relationship between the margin decay rate of the test temperature and a preset decay rate includes: The margin decay difference at the test temperature is determined based on the margin decay rate at the test temperature and the preset decay rate. The temperature control step size is determined based on the margin decay difference at the test temperature. Based on the test temperature and the temperature control step size, determine the next test temperature adjacent to the test temperature.

[0075] In some embodiments of this disclosure, determining the failure risk value corresponding to each type of timing margin parameter of the memory module under the same test temperature and test voltage, based on the same type of timing margin parameter under the same test temperature and test voltage, includes: Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the same type of target timing margin parameters under the same test temperature and the same test voltage. Based on the target timing margin parameters of the same type under the same test temperature and the same test voltage, determine the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the timing margin parameters of the same type under the same test temperature and the same test voltage. Based on the reference margin of the zero-degree rated voltage, the temperature decay coefficient, and the voltage decay coefficient, determine the failure risk value corresponding to the target timing margin parameter of the same type under the same test temperature and the same test voltage.

[0076] In some embodiments of this disclosure, determining the target timing margin parameter of the same type under the same test temperature and test voltage based on the timing margin parameter of the same type under the same test temperature and test voltage includes: Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the average value of the timing margin parameters of the same type under the same test temperature and the same test voltage. The standard deviation of the timing margin parameter is determined based on the relationship between the mean value of each timing margin parameter of the same type under the same test temperature and the same test voltage. Based on the relationship between the difference between the mean value of each timing margin parameter of the same type under the same test temperature and the same test voltage and the standard deviation of the timing margin parameter, the target timing margin parameter of the same type under the same test temperature and the same test voltage is determined.

[0077] In some embodiments of this disclosure, determining the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of target timing margin parameters under the same test temperature and the same test voltage, based on the same type of target timing margin parameters under the same test temperature and the same test voltage, includes: Based on the same type of target timing margin parameters under the same test temperature and the same test voltage, determine the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and voltage difference, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin. Based on the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin, determine the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of timing margin parameter under the same test temperature and the same test voltage.

[0078] In some embodiments of this disclosure, determining the comprehensive risk value of the memory module under each type of timing margin parameter, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, includes: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module in different test temperature ranges under each type of timing margin parameter is determined. Based on the sub-risk values ​​corresponding to different test temperature ranges under various types of timing margin parameters, the comprehensive risk value corresponding to the memory module under various types of timing margin parameters is determined.

[0079] In some embodiments of this disclosure, determining the sub-risk value of the memory module for different test temperature ranges under various types of timing margin parameters, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range and the weight value corresponding to each test temperature range, includes: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, the failure risk value with the largest failure risk value is selected as the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range. Based on the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module in different test temperature ranges under each type of timing margin parameter is determined.

[0080] This application also provides a computer device, please refer to the following for details. Figure 3 , Figure 3 This is a basic structural block diagram of the computer device in this embodiment.

[0081] The computer device includes a memory 510 and a processor 520 that are interconnected via a system bus. It should be noted that only a computer device with components 510-520 is shown in the figure; however, it should be understood that it is not required to implement all the shown components, and more or fewer components may be implemented alternatively. Those skilled in the art will understand that the computer device described herein is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0082] Computer devices can include desktop computers, laptops, handheld computers, and cloud servers. These devices allow for human-computer interaction with users through keyboards, mice, remote controls, touchpads, or voice-activated devices.

[0083] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, or flash card equipped on the computer device. Of course, the memory 510 may include both internal storage units and external storage devices of the computer device. In this embodiment, the memory 510 is typically used to store the operating system and various application software installed on the computer device, such as the program code of the method described above. In addition, the memory 510 may also be used to temporarily store various types of data that have been output or will be output.

[0084] The processor 520 is typically used to perform the overall operation of a computer device. In this embodiment, the memory 510 is used to store program code or instructions, including computer operation instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or to process data, such as program code that runs the methods described above.

[0085] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. This bus system can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0086] Another embodiment of this application also provides a computer-readable medium, which may be a computer-readable signal medium or a computer-readable medium. A processor in a computer reads computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or combination of steps in the above method; and to generate means for implementing the functional actions specified in each block or combination of blocks in the block diagram.

[0087] Computer-readable media include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared memory or semiconductor systems, devices or apparatuses, or any suitable combination thereof, wherein the memory is used to store program code or instructions, the program code including computer operation instructions, and the processor is used to execute the program code or instructions of the above-described methods stored in the memory.

[0088] The definitions of memory and processor can be found in the description of the foregoing computer device embodiments, and will not be repeated here.

[0089] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0090] In the various embodiments of this application, the functional units or modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0091] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0092] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0093] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0094] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A memory module RMT reliability testing method, characterized in that, include: During the temperature measurement phase, when the temperature of the memory module reaches the test temperature, the RMT parameters of the memory module at the test temperature are acquired within a preset time. Based on the RMT parameters, the margin decay rate of the memory module at the test temperature is determined. The RMT parameters include timing margin parameters and operating condition parameters. The operating condition parameters include test temperature, test voltage, actual temperature, and actual voltage. The temperature measurement phase includes a heating test phase and a cooling test phase. Based on the relationship between the margin decay rate of the test temperature and the preset decay rate, the next test temperature adjacent to the test temperature is determined, and the RMT parameters of the memory module at the next test temperature are obtained within a preset time, until the RMT parameters of the memory module at each test temperature in the heating test phase and at each test temperature in the cooling test phase are obtained. Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the failure risk value corresponding to each type of timing margin parameter of the memory module under the test temperature and the test voltage; Obtain the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and determine the comprehensive risk value of the memory module under each type of timing margin parameter based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range.

2. The method according to claim 1, characterized in that, The step of determining the next test temperature adjacent to the test temperature based on the relationship between the margin decay rate of the test temperature and the preset decay rate includes: The margin decay difference at the test temperature is determined based on the margin decay rate at the test temperature and the preset decay rate. The temperature control step size is determined based on the margin decay difference at the test temperature. Based on the test temperature and the temperature control step size, determine the next test temperature adjacent to the test temperature.

3. The method according to claim 1, characterized in that, The step of determining the failure risk value corresponding to each type of timing margin parameter of the memory module under the same test temperature and test voltage, based on the same type of timing margin parameter under the same test temperature and test voltage, includes: Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the same type of target timing margin parameters under the same test temperature and the same test voltage. Based on the target timing margin parameters of the same type under the same test temperature and the same test voltage, determine the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the timing margin parameters of the same type under the same test temperature and the same test voltage. Based on the reference margin of the zero-degree rated voltage, the temperature decay coefficient, and the voltage decay coefficient, determine the failure risk value corresponding to the target timing margin parameter of the same type under the same test temperature and the same test voltage.

4. The method according to claim 3, characterized in that, The step of determining the target timing margin parameters of the same type under the same test temperature and test voltage based on the same type of timing margin parameters under the same test temperature and test voltage includes: Based on the same type of timing margin parameters under the same test temperature and the same test voltage, determine the average value of the same type of timing margin parameters under the same test temperature and the same test voltage; The standard deviation of the timing margin parameter is determined based on the relationship between the mean value of each timing margin parameter of the same type under the same test temperature and the same test voltage. Based on the relationship between the difference between the mean value of each timing margin parameter of the same type under the same test temperature and the same test voltage and the standard deviation of the timing margin parameter, the target timing margin parameter of the same type under the same test temperature and the same test voltage is determined.

5. The method according to claim 3, characterized in that, The process of determining the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of target timing margin parameters under the same test temperature and test voltage, based on the same type of target timing margin parameters under the same test temperature and test voltage, includes: Based on the same type of target timing margin parameters under the same test temperature and the same test voltage, determine the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and voltage difference, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin. Based on the sum of temperature, sum of voltage deviation, sum of timing margin, variance of temperature, variance of voltage deviation, sum of the products of temperature and timing margin, and sum of the products of voltage difference and timing margin, determine the reference margin, temperature attenuation coefficient, and voltage attenuation coefficient of the zero-degree rated voltage corresponding to the same type of timing margin parameter under the same test temperature and the same test voltage.

6. The method according to claim 1, characterized in that, The determination of the comprehensive risk value of the memory module under each type of timing margin parameter, based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter within each test temperature range, includes: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module in different test temperature ranges under each type of timing margin parameter is determined. Based on the sub-risk values ​​corresponding to different test temperature ranges under various types of timing margin parameters, the comprehensive risk value corresponding to the memory module under various types of timing margin parameters is determined.

7. The method according to claim 6, characterized in that, The process of determining the sub-risk values ​​of the memory module for different test temperature ranges under various types of timing margin parameters, based on the failure risk values ​​corresponding to the same test voltage and the same type of timing margin parameters within each test temperature range, and the weight values ​​corresponding to each test temperature range, includes: Based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, the failure risk value with the largest failure risk value is selected as the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range. Based on the target failure risk value corresponding to the same test voltage and the same type of timing margin parameter at the test temperature included in each test temperature range, and the weight value corresponding to each test temperature range, the sub-risk value corresponding to the memory module in different test temperature ranges under each type of timing margin parameter is determined.

8. A memory module RMT reliability testing device, characterized in that, include: The margin decay rate determination module is used to acquire the RMT parameters of the memory module at the test temperature within a preset time during the temperature measurement phase when the temperature of the memory module reaches the test temperature, and determine the margin decay rate of the memory module at the test temperature based on the RMT parameters. The RMT parameters include timing margin parameters and operating condition parameters. The operating condition parameters include test temperature, test voltage, actual temperature and actual voltage. The temperature measurement phase includes a heating test phase and a cooling test phase. The RMT parameter acquisition module is used to determine the next test temperature adjacent to the test temperature based on the relationship between the margin decay rate of the test temperature and the preset decay rate, and to acquire the RMT parameters of the memory module at the next test temperature within a preset time, until the RMT parameters of the memory module at each test temperature in the heating test phase and at each test temperature in the cooling test phase are acquired. The failure risk value determination module is used to determine the failure risk value corresponding to each type of timing margin parameter of the memory module under the same test temperature and the same test voltage, based on the same type of timing margin parameter under the same test temperature and the same test voltage. The comprehensive risk value determination module is used to obtain the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range, and to determine the comprehensive risk value of the memory module under each type of timing margin parameter based on the failure risk value corresponding to the same test voltage and the same type of timing margin parameter under the test temperature included in each test temperature range.

9. A computer device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 7.

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