A power-down test method and apparatus for a memory chip

Abstract

The application discloses a power-off test method and device for a storage chip. The storage chip is arranged in a test device, the test device is connected with a control end, and the control end supplies power for the test device. The method comprises the following steps: the test device runs a test program to test the storage chip, generates a power-off test instruction when the test program runs to any power-off test point, and sends the power-off test instruction to the control end, so that the control end stops supplying power for the test device; the test device feeds back relevant information of the power-off test point to the control end in response to the power supply of the control end again. The application can effectively improve the test efficiency, and further improve the coverage of the test, so as to ensure the performance of the storage chip.

Description

Technical Field

[0001] This invention relates to the technical field of equipment testing, and in particular to a power-down testing method and equipment for memory chips. Background Technology

[0002] In the manufacturing process of storage devices, abnormal power outage tests are usually required to ensure the performance of the storage devices.

[0003] In practice, the inventors of this application found that the current testing method is usually to conduct stress tests for abnormal power outages through black-box testing, but this is relatively blind. That is, the power outage is triggered by blind testing, which cannot accurately measure the coverage of the test. It is unclear what tasks the storage device is performing, which can easily lead to insufficient testing and low testing efficiency. Summary of the Invention

[0004] The technical solution that this invention mainly solves is to provide a power-down testing method and device for memory chips. By actively triggering the memory chip, power-down can be accurately triggered in the test state that needs to be tested, which can effectively improve test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: providing a power-down testing method for a memory chip, comprising: a power-down testing method for a memory chip, wherein the memory chip is disposed in a testing device, the testing device is connected to a control terminal, the control terminal supplies power to the testing device, and the method comprises: the testing device running a test program to test the memory chip, and when the test program runs to any power-down test point, generating a power-down test command and sending the power-down test command to the control terminal, so that the control terminal stops supplying power to the testing device; the testing device responding to the control terminal by resupplying power and feeding back relevant information of the power-down test point to the control terminal.

[0006] In one embodiment of this application, the testing device runs a test program to test the memory chip, and when the test program reaches any power-down test point, generates a power-down test instruction and sends the power-down test instruction to the control terminal so that the control terminal stops supplying power to the testing device. This includes: in response to the test program reaching a target power-down test point, the testing device obtains a target power-down test instruction triggered by the test program at the target power-down test point, wherein the target power-down test point is the current power-down test point reached by the test program; the testing device sends the target power-down test instruction to the control terminal so that the control terminal determines a power-down execution instruction based on the target power-down test instruction and uses the power-down execution instruction to stop supplying power to the testing device.

[0007] In one embodiment of this application, in response to the test program running to the target power-down test point, the test device acquires the target power-down test instruction triggered by the test program at the target power-down test point, including: determining at least one power-down test point that needs to be tested, and setting a trigger signal for each of the power-down test points; in response to the test device running the test program to the target power-down test point, the test program triggers the target power-down test instruction through the trigger signal, and sends the target power-down test instruction to the test device.

[0008] In one embodiment of this application, the method further includes: acquiring an operation identifier bit for each of the power-down test points; in response to stopping power supply to the test device at the target power-down test point, acquiring the operation identifier bit corresponding to the target power-down test point; and using the operation identifier bit to determine the test state of the target power-down test point.

[0009] In one embodiment of this application, the testing device sends the target power-down test command to the control terminal, so that the control terminal determines a power-down execution command based on the target power-down test command, and stops supplying power to the testing device using the power-down execution command. This includes: responding to the testing device sending the target power-down test command to the control terminal, so that the control terminal determines power-down configuration information based on the target power-down test command, wherein the power-down configuration information includes at least preset power-down information; using the preset power-down information, determining the power-down execution command, so that the control terminal executes the power-down execution command, and stops supplying power to the testing device according to the power-down timing and the power-down slope.

[0010] In one embodiment of this application, the preset power-down information includes a power-down timing sequence and a power-down slope; determining the power-down execution instruction using the preset power-down information includes: determining the power-down execution instruction using the power-down timing sequence and the power-down slope.

[0011] In one embodiment of this application, the testing device, in response to the control terminal re-energizing, feeds back relevant information about the power-down test points to the control terminal, including: acquiring the operation identifier bit and test status of each power-down test point, and using the operation identifier bit and the test status to determine the power-down test points that need to be re-energized; the testing device, in response to the control terminal re-energizing, causes the testing program to run again at the power-down test points that need to be re-energized, and feeds back relevant information about the power-down test points that need to be re-energized to the control terminal, wherein the relevant information includes the operation identifier bit and the test status.

[0012] In one embodiment of this application, the method further includes: in response to the power outage time reaching a preset power failure time, the testing device acquires the power supply re-energized by the control terminal using a power restoration command.

[0013] In one embodiment of this application, the method further includes: in response to the test device obtaining the power supply to the control terminal again, obtaining the test state corresponding to each power failure test point where the power supply stops; comparing all the test states with a preset test state to obtain a power failure test coverage rate; and optimizing the power failure test command using the power failure test coverage rate so that the preset test state is covered.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a power-down test device for a memory chip, comprising: a test device and a control terminal, wherein the memory chip is disposed in the test device, and the test device is coupled to the control terminal; during operation, instructions are executed to realize the above-mentioned power-down test method.

[0015] Unlike current technologies, the power-down testing method for memory chips provided in this application includes: a testing device running a test program to test the memory chip, and generating a power-down test command when the test program reaches any power-down test point, and sending the power-down test command to the control terminal so that the control terminal stops supplying power to the testing device; the testing device responding to the control terminal by resupplying power and feeding back relevant information about the power-down test point to the control terminal; that is, this application, through the active triggering of the memory chip, accurately triggers power-down in the test state that needs to be tested, which can effectively improve test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0017] Figure 1 This is a flowchart illustrating an embodiment of the power-down testing method for the memory chip of this application;

[0018] Figure 2 This is a schematic diagram of an embodiment of the power-down testing device for memory chips in this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] The reference to "embodiment" in this application means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] The steps in the embodiments of this application are not necessarily processed in the order described. The steps can be rearranged, deleted, or added as needed. The step descriptions in the embodiments of this application are only optional combinations of sequences and do not represent all possible combinations of steps in the embodiments of this application. The order of steps in the embodiments should not be considered as a limitation of this application.

[0022] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0023] For storage firmware, especially storage chips, abnormal power loss is a crucial testing item. Currently, the main testing method is to conduct stress tests for abnormal power loss through black-box testing, which involves triggering power loss blindly. At this time, the storage chip is unaware of what processing it is performing. As a result, the test can take a long time but only covers a very small number of scenarios, leading to low testing efficiency and incomplete product verification. In other words, the test coverage cannot be accurately measured, resulting in insufficient testing and the release of defective products.

[0024] Therefore, this application provides a power-down testing method for memory chips. By actively triggering the memory chip, power-down is accurately triggered in the test state that needs to be tested, which can effectively improve test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip.

[0025] Please see Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the power-down testing method for the memory chip of this application.

[0026] like Figure 1 As shown, the power-down testing method for the memory chip of this application involves placing the memory chip in a testing device connected to a control terminal, which supplies power to the testing device. The method includes the following operations:

[0027] S10. The test device runs the test program to test the memory chip, and when the test program runs to any power-down test point, it generates a power-down test command and sends the power-down test command to the control terminal so that the control terminal stops supplying power to the test device.

[0028] Among them, the test device refers to the test terminal used to test the memory chip; the test program refers to the test script used to test the memory chip; the power-down test point refers to the specific power-down location where a power-down test needs to be performed; and the power-down test instruction refers to the signal triggered when the test program runs to the power-down test point, which indicates that the test program has run to the power-down test point and can perform a power-down test.

[0029] Specifically, when a power-down test is required, the memory chip is placed in the test device. The test device then runs a test program to test the memory chip. During the test, the position of the test program is obtained, and when the test program reaches any power-down test point, the memory chip actively triggers and generates a power-down test command. The test device then sends the power-down test command to the control terminal, so that the control terminal stops supplying power to the test device according to the power-down test command, thereby causing the memory chip to lose power.

[0030] S20. The test device responds to the control terminal by re-energizing the power supply and sends back relevant information about the power failure test point to the control terminal.

[0031] Here, "re-powering" refers to restoring power so that the test program can continue to run, that is, the memory chip on the test device is powered on again and continues to run; the relevant information of the power failure test point refers to the location information, status information, etc. of the power failure test point.

[0032] Specifically, after the power supply to the test terminal is stopped, the control terminal restores power to the test device so that the memory chip on the test device can be powered on again and the test device can continue to run the test program; and obtains relevant information of the power failure test point after power is restored, and feeds the relevant information back to the control terminal.

[0033] Understandably, if the test program runs to the next power-down test point, it will generate a corresponding power-down test command again, causing the control terminal to stop supplying power to the test device at the corresponding power-down test point, and then supply power again.

[0034] In this embodiment, during the testing process of the memory chip by the test device running the test program, a power-down test command is generated by the memory chip actively triggering the test. The power-down test command is then transmitted to the control terminal through the test device, so that the control terminal stops supplying power to the test device. This accurately triggers the power-down in the test state that needs to be tested, which can effectively improve the test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip.

[0035] In some embodiments, the S10 test device runs a test program to test the memory chip, and when the test program runs to any power-down test point, it generates a power-down test command and sends the power-down test command to the control terminal so that the control terminal stops supplying power to the test device. This may include the following operations.

[0036] First, in response to the test program running to the target power-down test point, the test device obtains the target power-down test command triggered by the test program at the target power-down test point.

[0037] There can be one or more power-down test points. When the test program runs to each power-down test point, it will generate a corresponding power-down test instruction so that the corresponding power-down test point can perform a power-down test on the memory chip. The target power-down test point is the current power-down test point to which the test program runs.

[0038] Specifically, the test device obtains the running position corresponding to the test program, and when the test program runs to the target power-down test point, that is, the current power-down test point at the current position, the memory chip generates a trigger signal at the target power-down test point. The test program then triggers the target power-down test instruction at the target power-down test point according to the trigger signal, and the test device obtains the target power-down test instruction triggered by the test program at the target power-down test point.

[0039] Then, the testing device sends the target power-down test command to the control terminal, so that the control terminal determines the power-down execution command based on the target power-down test command, and uses the power-down execution command to stop the power supply to the testing device.

[0040] The target power failure test command is triggered by the memory chip at the target power failure test point, while the control to stop the power supply is the control terminal. Therefore, the target power failure test command needs to be sent to the control terminal.

[0041] Specifically, after the memory chip triggers and generates a target power-down test command at the target power-down test point, the test device obtains the target power-down test command and then sends the target power-down test command to the control terminal. The control terminal then determines the power-down execution command for the current target power-down test point based on the target power-down test command, and then executes the power-down execution command to stop the power supply to the test device, so as to make the memory chip on the test device lose power.

[0042] Furthermore, the following operations may also be included.

[0043] Identify at least one power-down test point that needs to be tested, and set a trigger signal for each power-down test point.

[0044] There can be multiple locations where power-down testing is required, i.e., multiple power-down test points. In order to generate the corresponding power-down test command at each power-down test point, a signal needs to be set at each power-down test point to trigger the generation of the corresponding power-down test command.

[0045] Specifically, the location where the memory chip needs to be tested for power loss is identified and designated as the power loss test point. A trigger mechanism is set for each power loss test point, i.e., a trigger signal is set so that the test program is triggered when it reaches the power loss test point.

[0046] Then, in response to the test device running the test program to the target power-down test point, the test program generates a target power-down test command through a trigger signal and sends the target power-down test command to the test device.

[0047] Specifically, when the test device runs the test program to the target power failure test point, the test program can trigger the trigger signal set at the current target power failure test point, thereby generating the corresponding target power failure test command at the current target power failure test point, and sending the target power failure test command to the test device through the test device.

[0048] Furthermore, the following operations may also be included.

[0049] First, obtain the operation flag bit for each power failure test point.

[0050] Multiple power-down test points can be set, meaning that one or more power-down test points are set for each test state. The test state can be a power-down scenario, such as a write scenario, erase scenario, read scenario, standby scenario, etc. under power-on conditions. The operation flag bit refers to the status flag of the power-down test point, indicating whether the power-down test point has been activated or not activated. The activated state means that the power-down test has been executed, and the inactive state means that the power-down test has not been executed.

[0051] Specifically, after all the power-down test points are identified, a corresponding status flag is obtained for each power-down test point to determine which power-down test point performs the power-down test and which power-down test point does not perform the power-down test.

[0052] Understandably, at the beginning of the run, no power-down test was performed at any of the power-down test points, and the operation flags were all in an inactive state.

[0053] Next, in response to stopping the power supply to the test device at the target power failure test point, the operation flag bit corresponding to the target power failure test point is obtained.

[0054] The operation flag can also indicate the power supply stop state when it is already activated.

[0055] Specifically, when the control terminal stops supplying power to the test device, the current target power failure test point is determined to be in an activated state, and in response to stopping the power supply to the test device at the target power failure test point, the current target power failure test point is further determined to be in a stopped power supply state.

[0056] Then, the test status of the target power-off test point is determined using the operation flag bit.

[0057] The operation flag can determine the status of the current target test point, and thus determine the test state under which the power outage was triggered, i.e., determine the test state of the current target power outage test point and record it.

[0058] Furthermore, the following operations may also be included.

[0059] First, in response to the test device sending the target power-down test command to the control terminal, the control terminal determines the power-down configuration information based on the target power-down test command, wherein the power-down configuration information includes at least the preset power-down information.

[0060] After the testing device obtains the target power-down test command, it also needs to send the target power-down test command to the control terminal. Then, after the control terminal receives the target power-down test command, it determines the power-down configuration information for the target power-down test point corresponding to the target power-down test command. The power-down configuration information includes at least the preset power-down information.

[0061] Then, using the preset power-down information, the power-down execution command is determined so that the control terminal executes the power-down execution command and stops supplying power to the test device according to the power-down sequence and power-down slope.

[0062] Among them, the preset power-off information refers to the parameter information required to perform a power-off.

[0063] Specifically, after obtaining the preset power-down information, the control terminal uses the preset power-down information to construct a power-down execution command, that is, the power-down execution command contains the preset power-down information, and then the control terminal executes the power-down execution command, that is, stops the power supply to the test device according to the preset power-down information, thereby causing the memory chip on the test device to enter a power-down state.

[0064] Furthermore, the following operations may also be included.

[0065] The preset power-down information includes the power-down sequence and the power-down slope.

[0066] By using preset power failure information to determine the power failure execution command, the following operations can be included:

[0067] The power-down execution command is determined by using the power-down timing and power-down slope.

[0068] Among them, power-down timing refers to the timing requirements based on power-down; power-down slope refers to the rate at which the voltage drops in the circuit, usually used to describe the rate of change of the power supply voltage. Here, power-down timing and power-down slope are used to control the power-down test of the test device so that the power-down process is executed smoothly.

[0069] Power-down can be achieved through the following embodiments: For example, a GPIO (General-purpose input / output) triggering mechanism is added to each power-down test point, that is, an input and output triggering mechanism is added; that is, a GPIO input is set on the test device and a corresponding triggering method is set, such as edge triggering. The GPIO is pulled high and then pulled low inside the memory chip to generate a power-down test command. The control terminal determines the power-down execution command based on the power-down test command, and then stops the power supply to the test device so that the memory chip on the test device is powered down.

[0070] In this embodiment, during the testing process of the memory chip by the test device running the test program, a power-down test command is generated by the memory chip actively triggering the test. The power-down test command is then transmitted to the control terminal through the test device, so that the control terminal stops supplying power to the test device. This accurately triggers the power-down in the test state that needs to be tested, which can effectively improve the test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip.

[0071] In some embodiments, the S20 test device responds to the control terminal when power is restored and feeds back relevant information about the power failure test point to the control terminal, which may include the following operations.

[0072] First, obtain the operation flag and test status of each power failure test point, and use the operation flag and test status to determine the power failure test points that need to be re-energized.

[0073] Among them, the operation flag bit refers to the status flag of the power-down test point, indicating whether the power-down test point has been activated or not activated. The activated state means that the power-down test has been executed, and the inactive state means that the power-down test has not been executed. The test state refers to the current state corresponding to the power-down test point. For example, the test state can be a power-down scenario, such as a write scenario, erase scenario, read scenario, standby scenario, etc. under power-on conditions.

[0074] Specifically, for all power-down test points, the operation flag and test status of each power-down test point are obtained. Since the operation flag indicates whether the power-down test point has performed a power-down test, and the test status indicates the power-down scenario of the power-down test, the operation flag and test status can be used to determine whether each power-down test point has performed a power-down test, and thus identify the power-down test points that have lost power and need to be powered back.

[0075] In some embodiments, the operation flag bit can also represent the power supply stop state when it is already in the activated state, and the power supply restore state.

[0076] Then, the test device responds to the control terminal by re-energizing the power supply so that the test program can run again at the power-down test point that requires re-energization, and feeds back the relevant information of the power-down test point that requires re-energization to the control terminal, including the operation flag bit and the test status.

[0077] Since the control terminal provides power, if a power-off test point that has lost power needs to be powered back, i.e., power is restored, the control terminal needs to supply power again.

[0078] Specifically, when a power-down test point that has already lost power needs to be restored, the control terminal restores power as required. In response to the control terminal's restoration of power, the storage chip on the test device is powered on again, so that the test program can run again at the power-down test point that needs to be restored. The test device also obtains relevant information about the power-down test point that needs to be restored, and then feeds back the operation flag and test status in the relevant information to the control terminal, so that the control terminal can clearly identify the power-down test point that has undergone power-down testing and the corresponding power-down scenario.

[0079] Furthermore, the following operations may also be included.

[0080] In response to the preset power outage time, the test device obtains the power supply re-energized by the control terminal using the power restoration command.

[0081] If a power outage occurs, power must be restored before proceeding with subsequent operations.

[0082] Specifically, during the operation of the test program, for power failure test points where a power failure occurs, a preset power failure time is set. After the preset power failure time, the power failure test point where a power failure occurs is powered on again, that is, the test device is powered on again, so that the memory chip on the test device can run again, and the corresponding test program also runs again, until the next power failure test point is reached for power failure testing.

[0083] Optionally, the preset power-off time can be set according to the actual situation, such as a preset power-off time range of 3s-5s.

[0084] Furthermore, the following operations may also be included.

[0085] First, in response to the test device receiving power again from the control terminal, the test status corresponding to each power failure test point where power supply stops is obtained.

[0086] The test states can be power-off scenarios, such as write scenarios, erase scenarios, read scenarios, standby scenarios, etc., under power-on conditions.

[0087] Specifically, for each power-down test point that has undergone a power-down test, when the test device obtains power again from the control terminal, the test state corresponding to each power-down test point that has experienced a power-down stop is obtained, that is, the power-down scenario corresponding to each power-down test point that has experienced a power-down stop is obtained.

[0088] Compare all test states with preset test states to obtain power-down test coverage.

[0089] Among them, the preset test state refers to the pre-set power-down scenarios. The preset test state can include multiple power-down scenarios, such as write scenarios, erase scenarios, read scenarios, standby scenarios, etc. under power-on conditions. The power-down test coverage refers to the comparison between the power-down scenarios that have occurred in the current power-down test of the memory chip and the power-down scenarios corresponding to the preset test state. It is used to characterize whether the current memory chip has completed the full-scenario power-down test.

[0090] Specifically, first, the power-down scenarios corresponding to the preset test states are set, and then the power-down scenarios corresponding to all the test states of the current memory chip are obtained. Then, the power-down scenarios corresponding to all the test states of the current memory chip are compared with the power-down scenarios corresponding to the preset test states to determine the power-down test coverage of the current memory chip. For example, if there are 5 power-down scenarios corresponding to the preset test states, and there are 3 power-down scenarios corresponding to all the test states of the current memory chip, then the power-down test coverage of the current memory chip is 60%.

[0091] Optimize power-down test commands using power-down test coverage to ensure that preset test states are covered.

[0092] Among them, optimizing the power-down test command refers to further creating various power-down scenarios and improving the triggering accuracy of various power-down scenarios, so that all power-down scenarios corresponding to the preset test state will be triggered by the memory chip that needs to be tested at the corresponding power-down test point.

[0093] Specifically, for power outage scenarios that are not triggered in the preset test state, new power outage test points are added to the optimized power outage test instructions; while for existing power outage scenarios that have not been triggered, new trigger instructions can be added to make the triggering more accurate, so that all power outage scenarios corresponding to the preset test state will be covered.

[0094] In some embodiments, if new power outage scenarios need to be added, the power outage test instructions can be further optimized, such as adding power outage test points corresponding to the new power outage scenarios.

[0095] In this embodiment, during the testing process of the memory chip by the test device running the test program, a power-down test command is generated by the memory chip actively triggering the test. The power-down test command is then transmitted to the control terminal through the test device, so that the control terminal stops supplying power to the test device. This accurately triggers the power-down in the test state that needs to be tested, which can effectively improve the test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip.

[0096] This application also provides a power-down testing device for memory chips.

[0097] Please see Figure 2, Figure 2 This is a schematic diagram of an embodiment of the power-down testing device for memory chips in this application.

[0098] like Figure 2 As shown, the power-down test device 400 for memory chips includes a test device 410 and a control terminal 420. The memory chip 500 is disposed in the test device 410, and the test device 410 is coupled to the control terminal 420. During operation, it executes instructions to implement the above-mentioned power-down test method.

[0099] In some embodiments, the test device 410 provides at least two power input interfaces and at least one signal output interface, and the control terminal 420 provides at least two power output interfaces and at least one signal input interface. The test device 410 is connected to the signal input interface of the control terminal through the signal output interface to send a power failure test command to the control terminal 420. The control terminal 420 is connected to at least two power input interfaces corresponding to the test device 410 through at least two power output interfaces, so that the control terminal 420 performs power outage and power restoration to the test device 410 through at least two power output interfaces.

[0100] In the control terminal 420, at least two power output interfaces can be VCCQ power output interface and VCC power output interface, and the signal input interface can be GPIO signal input interface; in the test device, at least two power input interfaces can be VCCQ power input interface and VCC power input interface, and the signal output interface can be GPIO signal output interface.

[0101] In some embodiments, the testing device 410 is further provided with a test port, which is connected to the memory chip 500 so that the memory chip 500 is disposed on the testing device 410.

[0102] The above technical solution provides a power-down testing method for memory chips. The testing device runs a test program to test the memory chip, and when the test program reaches any power-down test point, it generates a power-down test command and sends the command to the control terminal, causing the control terminal to stop supplying power to the testing device. The testing device responds to the control terminal by resuming power supply and feeds back relevant information about the power-down test point to the control terminal. In other words, this application uses an active triggering method of the memory chip to accurately trigger power-down in the test state that needs to be tested, which can effectively improve test efficiency, thereby increasing the test coverage and ensuring the performance of the memory chip.

[0103] In the several embodiments provided in this application, it should be understood that the disclosed storage devices, electronic devices, and methods can be implemented in other ways. For example, the embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0104] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A power-down testing method for a memory chip, characterized in that, The memory chip is disposed in a testing device, the testing device being connected to a control terminal, the control terminal supplying power to the testing device, the method comprising: The testing device runs a test program to test the memory chip, and when the test program reaches any power-down test point, it generates a power-down test command and sends the power-down test command to the control terminal so that the control terminal stops supplying power to the testing device. The testing device responds to the control terminal by re-energizing the power supply and sends back relevant information about the power failure test point to the control terminal.

2. The method according to claim 1, characterized in that, The testing device runs a test program to test the memory chip, and when the test program reaches any power-down test point, it generates a power-down test command and sends the power-down test command to the control terminal to cause the control terminal to stop supplying power to the testing device, including: In response to the test program reaching the target power failure test point, the test device acquires the target power failure test instruction triggered by the test program at the target power failure test point, wherein the target power failure test point is the current power failure test point to which the test program has reached; The testing device sends the target power-down test command to the control terminal, so that the control terminal determines the power-down execution command based on the target power-down test command, and uses the power-down execution command to stop supplying power to the testing device.

3. The method according to claim 2, characterized in that, In response to the test program reaching the target power-down test point, the test device acquires the target power-down test command triggered by the test program at the target power-down test point, including: Identify at least one power-down test point that needs to be tested, and set a trigger signal for each power-down test point; In response to the test device running the test program to the target power failure test point, the test program generates the target power failure test command through the trigger signal and sends the target power failure test command to the test device.

4. The method according to claim 3, characterized in that, Also includes: Obtain the operation flag bit for each of the power-down test points; In response to stopping power supply to the test device at the target power failure test point, the operation flag bit corresponding to the target power failure test point is acquired; The test status of the target power-off test point is determined using the operation flag bit.

5. The method according to claim 2, characterized in that, The testing device sends the target power-down test command to the control terminal, so that the control terminal determines a power-down execution command based on the target power-down test command, and uses the power-down execution command to stop supplying power to the testing device, including: In response to the test device sending the target power-down test command to the control terminal, the control terminal determines power-down configuration information based on the target power-down test command, wherein the power-down configuration information includes at least preset power-down information; Using the preset power-down information, the power-down execution command is determined, so that the control terminal executes the power-down execution command and stops supplying power to the test device according to the preset power-down information.

6. The method according to claim 5, characterized in that, The preset power-down information includes the power-down sequence and the power-down slope; The step of determining the power failure execution command using the preset power failure information includes: The power-down execution command is determined using the power-down timing and the power-down slope.

7. The method according to claim 1, characterized in that, The testing device, in response to the control terminal re-energizing, feeds back relevant information about the power failure test point to the control terminal, including: Obtain the operation flag and test status of each power failure test point, and use the operation flag and test status to determine the power failure test points that need to be re-energized; The testing device responds to the control terminal by re-energizing the power supply, so that the testing program runs again at the power-down test point where power needs to be re-energized, and feeds back to the control terminal relevant information about the power-down test point where power needs to be re-energized, wherein the relevant information includes the operation flag bit and the test status.

8. The method according to claim 7, characterized in that, Also includes: In response to the preset power outage time being reached after the power supply was stopped, the testing device obtains the power supply re-energized by the control terminal using the power restoration command.

9. The method according to claim 8, characterized in that, Also includes: In response to the test device receiving power again from the control terminal, the test status corresponding to each power failure test point where power supply stops is obtained; The power outage test coverage is obtained by comparing all the test states with the preset test states. The power-down test command is optimized using the power-down test coverage to ensure that the preset test state is covered.

10. A power-down testing device for a memory chip, characterized in that, include: A testing device and a control terminal, wherein a memory chip is disposed in the testing device and the testing device is coupled to the control terminal; During operation, the instructions are executed to implement the power-off test method as described in any one of claims 1 to 9.

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