Sram test method and storage medium
Patent Information
- Application Number
- CN202611162047.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-31
- Publication Date
- 2026-10-23
AI Technical Summary
[0006]第一，数据可靠性低
[0026]如上配置，本发明将“读失效”与“读反转失效”两个测试流程整合为一次连续的测试流程，芯片仅需经历一次扎针即可完成“读失效”与“读反转失效”的全部测试。测试环境统一、接触电阻稳定，从根本上避免了因多次测试引入的干扰因素，确保了失效电压值等关键数据的准确性，为后续失效机理分析提供了可靠的数据依据。经实测证明，采用本发明所述的SRAM测试方法后，每片晶圆（wafer）的测试时长由原来的240分钟降至150分钟，单片晶圆节省测试时间90分钟；每批次（lot）晶圆有效节约测试时长37小时，测试时间的显著缩短直接降低了测试机台占用成本，提升了产能利用率。同时，本发明的芯片仅需经历一次扎针即可完成“读失效”与“读反转失效”的全部测试项目，最大限度地减少了针卡对芯片焊垫的物理冲击，降低了芯片的损伤风险，同时延长了测试针卡的使用寿命，进一步降低了测试成本。综上所述，本发明通过将“读失效”与“读反转失效”两个独立测试流程整合为一次连续测试，在保证测试数据准确性和可分析性的前提下，显著缩短了测试时间、降低了测试成本，同时减少了对芯片焊垫和测试针卡的损伤，为SRAM芯片的失效分析提供了一种高效、可靠、低成本的测试解决方案。
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Figure CN122967743A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to an SRAM testing method and a storage medium. Background Technology
[0002] In the semiconductor manufacturing industry, testing is a crucial step in the production process. Testing is used to select good products and also to perform engineering testing and analysis on failed chips to identify and resolve the causes of failure. This is of great significance for improving R&D progress, enhancing process health, and achieving customer yield expectations. Testing is an indispensable step in ensuring product quality throughout the entire integrated circuit manufacturing process.
[0003] Due to the compact and regular structure of SRAM chips and their manufacturing process, which more closely resembles the design characteristics of logic products, SRAM is one of the most commonly used tools in the industry for continuously monitoring the health of mature process platforms and developing new process platforms. Therefore, SRAM testing methods have always been a crucial aspect of the semiconductor testing field.
[0004] In existing technologies, failure analysis of SRAM chips typically requires establishing separate test procedures for different failure types. Specifically, when a chip fails, engineers need to test the failed sample independently according to three test procedures: "read failure," "write failure," and "read reversal failure," and then combine the data for analysis.
[0005] However, the existing testing methods described above have the following obvious drawbacks:
[0006] First, the data reliability is low. For chip defects of the soft fail type, the failure behavior is unstable and is greatly affected by factors such as the test environment, contact resistance, and voltage fluctuations. Fluctuations from multiple tests can interfere with the final data results, leading to poor data analyzability and seriously affecting the accuracy of failure analysis.
[0007] Second, the testing cost is high. Multiple tests are required to make contact with the chip's solder pads, which significantly increases testing time. Testing time directly determines testing cost, and repeated use of the test pins also accelerates wear and tear, further increasing testing costs.
[0008] Third, it is detrimental to subsequent packaging. When the same chip undergoes multiple pin punctures during testing, it is very easy to cause physical damage to the solder pads. Damage to the solder pads will directly affect the reliability and yield of subsequent packaging processes, and may even lead to new failure modes of the chip after packaging. Summary of the Invention
[0009] The purpose of this invention is to provide an SRAM testing method and storage medium that integrates the two independent testing processes of "read failure" and "read reversal failure" into a single continuous test, significantly shortening the testing time and reducing the testing cost, thus providing an efficient, reliable, and low-cost testing solution for SRAM chip failure analysis.
[0010] To achieve the above objectives, the present invention provides an SRAM testing method, comprising:
[0011] The read failure test procedure and read reversal failure test procedure of SRAM chip are integrated into a continuous test procedure. The integrated test procedure includes:
[0012] Step 1: Write test data to the SRAM chip under normal pressure conditions;
[0013] Step 2: Read the test data written to the SRAM chip under buck conditions to obtain the first read result;
[0014] Step 3: Determine whether a failure has occurred based on the first read result. If a failure has occurred, mark it as a read failure.
[0015] Step 4: Under normal pressure conditions, read the test data written to the SRAM chip again to obtain the second read result;
[0016] Step 5: Determine whether a failure has occurred based on the second read result. If a failure has occurred, mark it as a read reversal failure and end the test.
[0017] Optionally, before step one, an electrical contact test is performed on the SRAM chip under normal pressure. If the electrical contact test fails, the test ends; if the electrical contact test passes, step one is executed.
[0018] Optionally, the voltage value under normal pressure is the normal operating voltage value of the SRAM chip, and the voltage value under buck conditions is lower than the normal operating voltage value of the SRAM chip.
[0019] Optionally, in step five, if no failure occurs, the voltage value in step two is reduced, and the cycle continues from step two.
[0020] Optionally, in step three, if no failure occurs, the voltage value in step two is reduced, and the cycle continues from step two.
[0021] Optionally, each time the loop restarts from step two, the voltage value in step two is decreased sequentially by a preset voltage step size.
[0022] Optionally, the voltage value in step two shall not be lower than a preset test voltage value. If the voltage value in step two drops to the preset test voltage value, the test ends and the preset test voltage value is output.
[0023] Optionally, in step three, if a failure occurs, the failure voltage value under the current step-down condition is output, and this failure voltage value is recorded as the failure critical voltage value only when step three is executed for the first time.
[0024] Optionally, in step five, if a failure occurs, the failure voltage value output in step three is output.
[0025] According to another aspect of the present invention, the present invention also provides a storage medium storing a program that can be read and written, which, when executed, can implement the SRAM testing method as described above.
[0026] As configured above, this invention integrates the two test processes of "read failure" and "read reversal failure" into a single continuous test process. The chip only needs to undergo one pin puncture to complete all tests for "read failure" and "read reversal failure". The unified test environment and stable contact resistance fundamentally avoid interference factors introduced by multiple tests, ensuring the accuracy of key data such as failure voltage values and providing reliable data for subsequent failure mechanism analysis. Actual testing has proven that using the SRAM testing method described in this invention reduces the testing time per wafer from 240 minutes to 150 minutes, saving 90 minutes per wafer; and effectively saving 37 hours of testing time per batch (lot). This significant reduction in testing time directly lowers the cost of test equipment and improves production capacity utilization. Furthermore, since the chip only needs to undergo one pin puncture to complete all tests for "read failure" and "read reversal failure", this invention minimizes the physical impact of the pin puncture card on the chip pads, reducing the risk of chip damage and extending the lifespan of the test pin puncture card, further reducing testing costs. In summary, this invention integrates the two independent test processes of "read failure" and "read reversal failure" into a single continuous test. While ensuring the accuracy and analyzability of the test data, it significantly shortens the test time, reduces the test cost, and minimizes damage to the chip pads and test pins. This provides an efficient, reliable, and low-cost test solution for SRAM chip failure analysis. Attached Figure Description
[0027] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0028] Figure 1This is a flowchart of an SRAM testing method according to an embodiment of the present invention. Detailed Implementation
[0029] In this document, unless otherwise stated, the terms “upper,” “lower,” “left,” “right,” “inner,” “outer,” “front,” “back,” “top,” “bottom,” etc., are used to indicate orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a characteristic orientation and operation, and therefore should not be construed as a limitation of the invention.
[0030] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0031] Figure 1 This is a flowchart of an SRAM testing method according to an embodiment of the present invention. Please refer to it. Figure 1 This invention provides an SRAM testing method that integrates the read failure test process and the read reversal failure test process of an SRAM chip into a single continuous test process. The integrated test process includes:
[0032] Step one: Write test data to the SRAM chip under normal pressure conditions. Figure 1 The voltage value under constant voltage is the normal operating voltage value of the SRAM chip.
[0033] Understandably, prior to step one, an electrical contact test is performed on the SRAM chip under normal pressure conditions. Figure 1 The test is conducted under normal pressure. If the electrical contact test fails, the SRAM chip is filtered out (i.e., skipped / discarded) and the test ends; if the electrical contact test passes, step one is executed.
[0034] Step 2: Read the test data written to the SRAM chip under buck conditions. Figure 1 The first read result is obtained by stepping down the voltage. The voltage value under the step-down condition is lower than the normal operating voltage value of the SRAM chip.
[0035] Step 3: Determine whether an error has occurred based on the first read result. If an error has occurred (i.e., the read fails), mark it as a read failure and then proceed to Step 4.
[0036] Furthermore, in step three, if a failure is determined to have occurred based on the first reading result, the failure voltage value under the current step-down condition is output. This failure voltage value is recorded as the critical failure voltage value for reading failure only when step three is executed for the first time. It is understood that in subsequent loops, the voltage is further reduced, but the subsequent reading failure voltage value no longer possesses the "critical" property.
[0037] If the first reading result indicates that no failure has occurred (i.e., the test passed), then proceed to step two, reduce the voltage value in step two, and continue the loop from step two.
[0038] Step 4: Under normal pressure conditions, read the test data written to the SRAM chip again. Figure 1 The reading is performed at normal pressure to obtain the second reading result, and then proceed to step five.
[0039] Step 5: Determine whether a failure has occurred based on the second reading result. If a failure occurs (i.e., it fails), mark it as a read reversal failure and end the test.
[0040] Furthermore, in step five, if a failure is determined to have occurred based on the second reading result, the failure voltage value output in step three is output, and this failure voltage value is used as the critical voltage value for read reversal failure. It is understood that there may be cases where multiple loops have occurred; in this case, the failure voltage value from the most recently executed step three is output.
[0041] In step five, if it is determined that no failure has occurred (i.e., the test passed) based on the second reading result, then proceed to step two, and reduce the voltage value in step two, and continue the loop from step two.
[0042] Preferably, each time the cycle restarts at step two, the voltage value in step two is decreased sequentially with a preset voltage step size. For example, in one embodiment, the voltage value under normal pressure is set to 1.0V, and it is decreased sequentially with a voltage step size of 0.05V. The voltage value in step two must not be lower than a preset test voltage value. If the voltage value in step two drops to the preset test voltage value, the test ends, and the preset test voltage value is output.
[0043] In some embodiments, in step three, if each time the first read result indicates that no failure has occurred, the voltage value in step two will decrease sequentially until a preset test voltage value is reached, and then the test ends. This indicates that the SRAM chip has no read failure or read reversal failure issues, and the preset test voltage value is output, which can be used as the minimum operating voltage of the SRAM chip.
[0044] In other embodiments, each time the first read result is used to determine that a failure has occurred, and each time the second read result is used to determine that a failure has not occurred, it means that the SRAM chip does not have a read reversal failure problem, but has a read failure problem, and the failure threshold voltage value of the read failure is the failure voltage value output when step three is executed for the first time.
[0045] According to another aspect of the present invention, the present invention also provides a storage medium storing a program that can be read and written, which, when executed, can implement the SRAM testing method as described above.
[0046] As configured above, this invention integrates the two test processes of "read failure" and "read reversal failure" into a single continuous test process. The chip only needs to undergo one pin puncture to complete all tests for "read failure" and "read reversal failure". The unified test environment and stable contact resistance fundamentally avoid interference factors introduced by multiple tests, ensuring the accuracy of key data such as failure voltage values and providing reliable data for subsequent failure mechanism analysis. Actual testing has proven that using the SRAM testing method described in this invention reduces the testing time per wafer from 240 minutes to 150 minutes, saving 90 minutes per wafer; and effectively saving 37 hours of testing time per batch (lot). This significant reduction in testing time directly lowers the cost of test equipment and improves production capacity utilization. Furthermore, since the chip only needs to undergo one pin puncture to complete all tests for "read failure" and "read reversal failure", this invention minimizes the physical impact of the pin puncture card on the chip pads, reducing the risk of chip damage and extending the lifespan of the test pin puncture card, further reducing testing costs. In summary, this invention integrates the two independent test processes of "read failure" and "read reversal failure" into a single continuous test. While ensuring the accuracy and analyzability of the test data, it significantly shortens the test time, reduces the test cost, and minimizes damage to the chip pads and test pins. This provides an efficient, reliable, and low-cost test solution for SRAM chip failure analysis.
[0047] Previously, SRAM chip testing required separate test procedures and two tests to analyze read failures and read reversal failures. Multiple tests damaged the chip pads and wore out the test pins, and variations in contact resistance caused significant differences in the test results for already soft failures. The testing method described in this invention provides all data for read failures and read reversal failures in a single test, solving the problems of long testing times and unstable data caused by the original testing procedures. This testing method has now been extended to testing other process nodes.
[0048] It should be noted that references to "an embodiment," "an embodiment," "a specific embodiment," "some embodiments," etc., in the specification only indicate that the described embodiment may include a specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.
[0049] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.
[0050] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
[0051] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.
[0052] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of the invention. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.
Claims
1. An SRAM testing method, characterized in that, include: The read failure test procedure and read reversal failure test procedure of SRAM chip are integrated into a continuous test procedure. The integrated test procedure includes: Step 1: Write test data to the SRAM chip under normal pressure conditions; Step 2: Read the test data written to the SRAM chip under buck conditions to obtain the first read result; Step 3: Determine whether a failure has occurred based on the first read result. If a failure has occurred, mark it as a read failure. Step 4: Under normal pressure conditions, read the test data written to the SRAM chip again to obtain the second read result; Step 5: Determine whether a failure has occurred based on the second read result. If a failure has occurred, mark it as a read reversal failure and end the test.
2. The SRAM testing method as described in claim 1, characterized in that, Before step one, the SRAM chip is subjected to an electrical contact test under normal pressure. If the electrical contact test fails, the test ends; if the electrical contact test passes, step one is executed.
3. The SRAM testing method as described in claim 1, characterized in that, The voltage value under normal pressure is the normal operating voltage value of the SRAM chip, and the voltage value under buck conditions is lower than the normal operating voltage value of the SRAM chip.
4. The SRAM testing method as described in claim 1, characterized in that, If no failure occurs in step five, the voltage value in step two is reduced, and the cycle continues from step two.
5. The SRAM testing method as described in claim 1, characterized in that, If no failure occurs in step three, the voltage value in step two is reduced, and the cycle continues from step two.
6. The SRAM testing method as described in claim 5 or 4, characterized in that, Each time the loop restarts from step two, the voltage value in step two is decreased sequentially by a preset voltage step size.
7. The SRAM testing method as described in claim 5 or 4, characterized in that, The voltage value in step two shall not be lower than the preset test voltage value. If the voltage value in step two drops to the preset test voltage value, the test ends and the preset test voltage value is output.
8. The SRAM testing method as described in claim 5 or 4, characterized in that, In step three, if a failure occurs, the failure voltage value under the current step-down condition is output, and this failure voltage value is recorded as the failure critical voltage value only when step three is executed for the first time.
9. The SRAM testing method as described in claim 8, characterized in that, In step five, if a failure occurs, the failure voltage value output in step three is then output.
10. A storage medium having a program stored thereon, characterized in that, When the program is executed, it implements the SRAM testing method as described in any one of claims 1-9.