Temperature-voltage cooperative-based DDR3 memory chip aging test method and system

Abstract

The application relates to the technical field of memory chip testing, and discloses a temperature-voltage cooperative DDR3 memory chip aging test method and system, the method comprises the following steps: obtaining a first leakage current and a first charge-discharge delay under the simultaneous action of high-temperature stress and overvoltage stress, performing damage characteristic calculation to obtain a resultant damage characteristic, calculating the hot carrier injection amount and the defect accumulation amount of a gate oxide layer according to the first leakage current and the resultant damage characteristic and determining a degradation stage, obtaining a second leakage current and a second charge-discharge delay under the degradation stage, performing life prediction by adopting a pre-trained random forest regression model, obtaining a life quantization numerical value and determining a failure state, and obtaining a degradation determination result. The method can solve the problem of low accuracy of the aging test result of the DDR3 memory chip in the prior art.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing technology, and in particular to a method and system for aging testing DDR3 memory chips based on temperature-voltage coordination. Background Technology

[0002] In the field of memory chip testing technology, DDR3 memory chips are core components that undertake high-speed data access tasks in critical systems such as industrial control, communication equipment, and automotive electronics. Their stability during long-term operation is directly related to the reliability of the entire system. Conducting aging tests on the chips before leaving the factory and during use to accurately determine their remaining lifespan has become a key task to ensure product quality.

[0003] In a current technology, aging tests typically apply temperature and voltage stress separately. The chip is first subjected to high-temperature burn-in, then overvoltage is applied separately, or the two stresses are applied alternately in a fixed sequence, treating temperature and voltage as two independent acceleration channels. This separate approach ignores the fact that high temperature and voltage fluctuations often occur simultaneously in actual chip use. This leads to a significant deviation between the aging curve obtained from the test and the actual operating conditions, failing to reflect the combined damage caused to the chip's internal structure by the superposition of the two stresses. When high temperature and overvoltage act simultaneously on the memory cell, the degradation process of the gate oxide layer—a thin layer controlling charge entry and exit—is driven by both stresses. Heat accelerates electron transitions, and voltage increases the risk of breakdown. The interplay of these two factors causes the oxide layer damage to exhibit a completely different trend than under single stress. Physical quantities reflecting the chip's health, such as leakage current and charge / discharge delay, fluctuate under dual stress. If the chip shows an increase in leakage current during testing, it's impossible to distinguish whether it's primarily due to hot carrier injection damage or oxide layer defect accumulation damage using traditional single-point measurements. Therefore, it's impossible to determine whether the chip is in early aging, moderate degradation, or nearing failure.

[0004] Existing technologies suffer from low accuracy in aging test results for DDR3 memory chips. Summary of the Invention

[0005] This invention provides a temperature-voltage coordinated DDR3 memory chip aging test method and system to solve the problem of low accuracy of DDR3 memory chip aging test results in the prior art.

[0006] Firstly, to address the aforementioned technical problems, this invention provides a temperature-voltage coordinated aging test method for DDR3 memory chips, comprising:

[0007] The first leakage current and the first charge / discharge delay of the target memory chip under the simultaneous action of high temperature stress and overpressure stress are obtained.

[0008] Damage characteristics of the target memory chip are obtained by calculating the damage characteristics based on the first leakage current and the first charge / discharge delay.

[0009] The amount of hot carrier injection and the amount of defect accumulation in the gate oxide layer of the target memory chip are calculated based on the first leakage current and the resultant force damage characteristics, and the degradation stage of the gate oxide layer is determined based on the amount of hot carrier injection and the amount of defect accumulation.

[0010] Obtain the second leakage current and the second charge / discharge delay of the target memory chip during the degradation phase;

[0011] A pre-trained random forest regression model is used to predict the lifetime of the second leakage current and the second charge-discharge delay to obtain a quantified lifetime value of the target memory chip. The failure state of the target memory chip is determined based on the quantified lifetime value to obtain a degradation determination result.

[0012] In a second aspect, the present invention provides a temperature-voltage coordinated DDR3 memory chip aging test system, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method described above.

[0013] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] (1) The present invention calculates the damage characteristics of the first leakage current and the first charge and discharge delay under the simultaneous action of high temperature stress and overvoltage stress, and integrates the damage caused by the intertwining of temperature and voltage stress into a resultant damage characteristic; through this processing, the test process no longer regards temperature and voltage as two independent acceleration channels, and the obtained damage characterization is closer to the aging state under the actual working conditions of the chip.

[0016] (2) The present invention calculates the amount of hot carrier injection in the gate oxide layer based on the first leakage current, and obtains the amount of defect accumulation by querying a preset defect degradation mapping table with the resultant damage characteristics and the amount of hot carrier injection as an index, thereby determining the degradation stage of the gate oxide layer; through this process, the measurable physical quantities such as leakage current and charge-discharge delay are established in correspondence with the internal damage of the gate oxide layer, and two quantitative indicators characterizing the degree of hot carrier injection and the degree of defect accumulation are obtained respectively, thereby determining the degradation stage of the chip and providing targeted conditions for subsequent measurements.

[0017] (3) The present invention obtains the second leakage current and the second charge and discharge delay for the determined degradation stage, and uses a pre-trained random forest regression model to predict the lifetime, obtain the lifetime quantification value and determine the failure state; through this processing, a quantifiable remaining lifetime judgment is given for chip wear, thereby improving the accuracy of DDR3 memory chip aging test results. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a temperature-voltage coordinated aging test method for DDR3 memory chips provided in the first embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram illustrating the determination of the gate oxide layer degradation stage provided in the first embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Reference Figure 1 The first embodiment of the present invention provides a temperature-voltage coordinated aging test method for DDR3 memory chips, including the following steps:

[0022] S1, obtain the first leakage current and the first charge / discharge delay of the target memory chip under the simultaneous action of high temperature stress and overpressure stress;

[0023] S2, based on the first leakage current and the first charging and discharging delay, damage characteristics are calculated to obtain the combined force damage characteristics of the target memory chip;

[0024] S3, calculate the amount of hot carrier injection and the amount of defect accumulation in the gate oxide layer of the target memory chip based on the first leakage current and the resultant damage characteristics, and determine the degradation stage of the gate oxide layer based on the amount of hot carrier injection and the amount of defect accumulation;

[0025] S4, obtain the second leakage current and the second charge / discharge delay of the target memory chip during the degradation stage;

[0026] S5, a pre-trained random forest regression model is used to predict the lifetime of the second leakage current and the second charge-discharge delay to obtain the lifetime quantification value of the target memory chip. The failure state of the target memory chip is determined based on the lifetime quantification value to obtain the degradation determination result.

[0027] In step S1, the first leakage current and the first charge / discharge delay of the target memory chip under the simultaneous action of high temperature stress and overpressure stress are obtained.

[0028] First, the target memory chip is placed in an aging test fixture, and a preset high-temperature stress temperature and a preset overvoltage stress voltage are applied to the target memory chip. The two stresses are applied synchronously over time and maintained continuously. The preset high-temperature stress temperature is determined based on the allowable junction temperature range of the DDR3 memory chip. In this embodiment, it is set to 125°C, but it can be adjusted within the range of 105°C to 150°C depending on the chip packaging material and the upper limit of the junction temperature. The preset overvoltage stress voltage is determined based on the chip's rated supply voltage. In this embodiment, it is set to 1.5 times the rated voltage, that is, 2.25V is applied to a DDR3 memory chip with a rated voltage of 1.5V. It should be noted that the preset high-temperature stress temperature and preset overvoltage stress voltage are determined only for the target model DDR3 memory chip that has been verified by pre-experiments. The determination method is to conduct multiple sets of pre-experiments on sample chips of the same model, with the constraint that no new failure modes are introduced and the failure modes are consistent with the failure modes under normal use conditions. The upper limit of stress that can stably accelerate aging without changing the failure mechanism is selected. The overvoltage multiple is determined based on the rated parameters and ultimate stress of the target model under this constraint, and can be adjusted in the range of 1.2 times to 1.8 times.

[0029] Secondly, during the continuous application of dual-path stress, the leakage current of the target memory chip storage array is collected through the current measurement channel of the test fixture. In order to obtain the first leakage current reflecting the leakage current of the storage array, the total static current including the storage array and peripheral circuits is measured in the static standby state when the chip is powered on and no read / write operations are performed. Then, the pre-calibrated peripheral circuit reference current is subtracted to obtain the leakage current of the storage array, which is used as the first leakage current. The peripheral circuit reference current is measured in the test mode with the same temperature, the same supply voltage and no activation of the storage array. It is updated synchronously at each sampling time using the same model reference sample or the array shutdown test mode supported by the target memory chip to reduce the influence of the current change of the peripheral circuit due to aging on the storage array leakage current measurement results. Using the timing measurement channel of the test fixture, under fixed clock frequency, fixed CAS timing parameters, and a fixed test sequence, the time interval between the read / write commands and data output of the charging / discharging operation of the memory cell is measured to obtain the equivalent charging / discharging response delay under fixed measurement conditions, which is used as the first charging / discharging delay. The fixed clock frequency, fixed CAS timing parameters, and fixed test sequence remain consistent in each measurement of the first leakage current and the first charging / discharging delay, as well as the subsequent measurements of the second leakage current and the second charging / discharging delay. The preset stress duration is consistent with the integration duration of the subsequent hot carrier injection, which is 1000 hours in this embodiment. The measured value at the end of the preset stress duration is taken as the first leakage current and the first charging / discharging delay. For example, after being subjected to 125°C and 2.25V simultaneously for 1000 hours, the first leakage current was measured to be 8 μA, and the first charging / discharging delay was measured to be 12.5 ns. Before applying high-temperature stress and overpressure stress, the initial leakage current and initial charge / discharge delay of the target memory chip under unstressed conditions are acquired through the current measurement channel and timing measurement channel of the test fixture. To ensure comparability with the first set of measurements, the two initial values ​​are corrected using the instantaneous response difference measured briefly under the same temperature, voltage, and test parameters as the first set of measurements from an unaged reference sample of the same model. The corrected values ​​are used as the initial leakage current and initial charge / discharge delay as the benchmark for subsequent drift rate calculation. The short-time measurement of the reference sample is only used to determine the instantaneous temperature and voltage response difference and is not included in the aging stress duration. For example, the initial leakage current is 1 μA and the initial charge / discharge delay is 10 ns.

[0030] In step S2, damage characteristics are calculated based on the first leakage current and the first charge / discharge delay to obtain the combined force damage characteristics of the target memory chip, including:

[0031] Obtain the initial leakage current and initial charge / discharge delay of the target memory chip before the application of the high-temperature stress and the overpressure stress;

[0032] Calculate the first drift rate of the first leakage current relative to the initial leakage current, and the second drift rate of the first charge / discharge delay relative to the initial charge / discharge delay;

[0033] The first drift rate and the second drift rate are weighted and summed according to a preset weight to obtain the resultant force damage characteristics.

[0034] First, it is worth noting that the initial leakage current and initial charge / discharge delay are the baseline values ​​measured before stress was applied and corrected by the aforementioned instantaneous response difference. The acquisition channel of the original initial value is the same as that of the first leakage current and the first charge / discharge delay. When correcting, the instantaneous response difference obtained by the same model of unaged reference sample under the same temperature, voltage, clock frequency, CAS timing parameters and test sequence is used to ensure that the initial value and the first set of measured values ​​are comparable in terms of measurement conditions.

[0035] Secondly, the drift rate is used to characterize the degree of degradation of the measured parameters relative to the initial reference after stress. The first drift rate is the difference between the first leakage current and the initial leakage current divided by the initial leakage current, and the second drift rate is the difference between the first charge / discharge delay and the initial charge / discharge delay divided by the initial charge / discharge delay. For example, if the first leakage current is 8 μA and the initial leakage current is 1 μA, the first drift rate is 700%; if the first charge / discharge delay is 12.5 ns and the initial charge / discharge delay is 10 ns, the second drift rate is 25%.

[0036] Finally, it is worth noting that the preset weights are used to reflect the contribution ratio of the two types of drift to the damage of the gate oxide layer. In this embodiment, the preset weight of the first drift rate is 0.9, and the preset weight of the second drift rate is 0.1. The weights are statistically calibrated from historical dual-stress aging test samples: the leakage current drift rate, charge / discharge delay drift rate, and the actual damage degree confirmed by failure analysis are recorded for historically aged chips. The two types of drift rates are used as independent variables to perform linear regression on the damage degree, and the regression coefficients are normalized and used as the preset weights. According to the above example, the combined force damage characteristic is a dimensionless quantity, and it is uniformly used in the weighted calculation as a percentage value. That is, the drift rate is substituted into the percentage value (700, 25), and the combined force damage characteristic is 0.9×700+0.1×25=632.5.

[0037] In step S3, the hot carrier injection amount and defect accumulation amount of the gate oxide layer of the target memory chip are calculated based on the first leakage current and the resultant force damage characteristics, and the degradation stage of the gate oxide layer is determined based on the hot carrier injection amount and the defect accumulation amount, including:

[0038] Based on the first leakage current, the preset injection allocation coefficient and the effective area of ​​the gate oxide layer of the target memory chip, the amount of charge injected into the gate oxide layer per unit time and per unit area is calculated to obtain the carrier injection flux.

[0039] The carrier injection flux is accumulated over a preset stress duration to obtain the hot carrier injection amount;

[0040] Using the combined force damage characteristics and the hot carrier injection amount as indexes, a preset defect degradation mapping table is queried to obtain the defect accumulation amount of the gate oxide layer of the target memory chip.

[0041] The preset defect degradation mapping table records the resultant damage characteristics of historical aging test chips under the simultaneous action of high temperature stress and overpressure stress, the correspondence between the amount of hot carrier injection and the amount of measured defect accumulation, and is established by statistical analysis of multiple sets of historical accelerated aging test data.

[0042] The amount of hot carrier injection is compared with a preset first threshold, and the amount of defect accumulation is compared with a preset second threshold.

[0043] If the amount of hot carrier injection is greater than the preset first threshold and the amount of defect accumulation is greater than the preset second threshold, then the gate oxide layer is determined to have entered the first degradation stage.

[0044] If the amount of hot carrier injection is not greater than the preset first threshold or the amount of defect accumulation is not greater than the preset second threshold, then the gate oxide layer is determined to be in the second degradation stage.

[0045] Collect data on the amount of hot carrier injection and defect accumulation when historical aging test chips fail under the simultaneous action of high temperature stress and overpressure stress.

[0046] The value corresponding to the preset quantile in the statistical distribution of the hot carrier injection amount is used as the preset first threshold, and the value corresponding to the preset quantile in the statistical distribution of the defect accumulation amount is used as the preset second threshold.

[0047] First, it is worth noting that the hot carrier injection amount characterizes the equivalent injected charge amount injected into the gate oxide layer within a preset stress duration, and accumulated per unit effective gate oxide area. That is, the hot carrier injection amount is the cumulative equivalent injected charge amount per unit effective gate oxide area, with units of C / cm². The proportion of the injected gate oxide layer component in the first leakage current is characterized by a preset injection allocation coefficient, which is a dimensionless coefficient. Its calibration method is as follows: Leakage current is measured on historical aging test chips, and gate injection current is measured on a transistor test structure using the same process as the target memory chip. The gate injection current within the same stress duration is integrated to obtain the corresponding actual injected charge amount. Using leakage current as input and the ratio of the actual injected charge amount to the product of leakage current and stress duration as output, proportional fitting is performed on multiple sets of historical data. The fitted proportional coefficient is used as the preset injection allocation coefficient. In this embodiment, we take... The effective area of ​​the gate oxide layer is calculated by multiplying the effective gate area of ​​a single transistor participating in the statistics by the number of effective transistors to obtain the equivalent gate oxide area. The effective gate area of ​​a single transistor is determined by the process node of the target memory chip, and the number of effective transistors is determined by the memory array size. In this embodiment, the target model is calculated based on the effective gate area of ​​sample transistors at the same process node and the number of array transistors, with the effective area of ​​the gate oxide layer taken as 1 cm². The formula for calculating carrier injection flux is as follows:

[0048] ;

[0049] In the formula, Injecting flux to charge carriers For the preset injection allocation coefficient, This is the first leakage current. This represents the effective area of ​​the gate oxide layer. The carrier injection flux is accumulated over a preset stress time to obtain the hot carrier injection rate, i.e.

[0050] ;

[0051] In the formula, This refers to the hot carrier injection rate, expressed in C / cm². The preset stress duration is consistent with the stress application duration in step S1; in this embodiment, it is set to 1000 hours. s. For example, the first leakage current is 8μA, and substituting it into the above calculation formula yields the hot carrier injection amount as: That is, 200 μC / cm².

[0052] Secondly, it is worth noting that the defect accumulation amount is a dimensionless normalized index characterizing the degree of defect accumulation in the gate oxide layer. A higher value indicates a higher degree of accumulation of traps and interface states within the gate oxide layer. A preset defect degradation mapping table records the correlation between the combined force damage characteristics, hot carrier injection amount, and measured defect accumulation amount of historical aging test chips under simultaneous high-temperature stress and overvoltage stress. This table is established by statistically analyzing multiple sets of historical accelerated aging experimental data. Specifically, dual-stress accelerated aging experiments were conducted on multiple historical chips at multiple temperature points within the range of 105℃ to 150℃ and multiple overvoltage points within the range of 1.2 to 1.8 times the rated voltage. Experimental data were organized according to the target chip model and specific combinations of temperature stress and overvoltage stress. Within the same preset defect degradation mapping table, the same temperature stress and overvoltage stress conditions were used, and the combined force damage characteristics and hot carrier injection amount of each historical chip were recorded synchronously at different stress times. For the defect accumulation amount of the historical chips, a transistor test structure using the same process as the target memory chip was used for charge testing. Charge pump testing, or charge pump testing and failure analysis of the internal test structure of historical chips after unpacking, is performed to measure the interface trap density. The measured trap density of each historical chip is divided by a preset benchmark trap density for normalization to obtain the dimensionless measured defect accumulation. The preset benchmark trap density is the average value of the initial interface trap density measured under the same test conditions as the transistor test structure of the target memory chip using the same process and without accelerated aging treatment. The recorded data is organized into index entries according to the value range of the resultant damage characteristics and the hot carrier injection amount to form a preset defect degradation mapping table. During the query, the corresponding preset defect degradation mapping table is first selected based on the current temperature stress and overpressure stress conditions of the target memory chip. Then, the corresponding table entries are retrieved using the resultant force damage characteristics and hot carrier injection amount of the target memory chip as indexes to obtain the defect accumulation amount. When both the resultant force damage characteristics and hot carrier injection amount fall between adjacent table entries, the four neighboring table entries surrounding the index point are taken, and bilinear interpolation is performed on the defect accumulation amounts of the four neighboring table entries to obtain the defect accumulation amount. When either the resultant force damage characteristics or the hot carrier injection amount exceeds the index range of the preset defect degradation mapping table, the defect accumulation amount of the nearest boundary table entry is taken as the defect accumulation amount. For example, if the resultant force damage characteristics are 632.5 and the hot carrier injection amount is 200 μC / cm², querying the preset defect degradation mapping table yields a defect accumulation amount of 600.

[0053] Then, the physical meaning of the preset quantile is the quantile point in the distribution of failure samples that leaves a safety margin. In this embodiment, the 5% quantile is used, that is, the injection amount and accumulation amount corresponding to the 5% quantile in the historical failure samples are taken as two thresholds. Below this value, it indicates that the damage degree of the gate oxide layer is still within the margin of failure. After statistical analysis of multiple sets of historical failure chips, the preset first threshold in this embodiment is 180 μC / cm², and the preset second threshold is 550. The preset first threshold and the hot carrier injection amount use the same dimension, and the preset second threshold and the defect accumulation amount use the same dimensionless normalized scale. The defect accumulation amount in the mapping table, the preset second threshold, and the defect accumulation amount in the judgment examples all use the same normalized scale. After the two thresholds are determined, cross-validation is performed using historical samples of the same model that have not failed. The hot carrier injection amount and defect accumulation amount are calculated for each sample in the same way, and the consistency between the double limit judgment result and the actual failure state is checked. If the verification result cannot stably distinguish between failed samples and non-failed samples, the historical sample range or the preset quantile is readjusted and the two thresholds are determined again.

[0054] Furthermore, it is worth noting that the degradation stage is determined by comparing the hot carrier injection amount with a preset first threshold and the defect accumulation amount with a preset second threshold. For example, if the hot carrier injection amount of 200 μC / cm² is greater than the preset first threshold of 180 μC / cm², and the defect accumulation amount of 600 is greater than the preset second threshold of 550, satisfying the dual threshold conditions, the gate oxide layer is determined to have entered the first degradation stage. The first degradation stage characterizes a state where both the hot carrier injection amount and the defect accumulation amount exceed their corresponding thresholds, indicating a significantly increased risk of degradation but before irreversible hard breakdown. If the hot carrier injection amount is not greater than the preset first threshold, or the defect accumulation amount is not greater than the preset second threshold, the gate oxide layer is determined to be in the second degradation stage. The second degradation stage characterizes a degradation state where the hot carrier injection amount and the defect accumulation amount do not simultaneously satisfy the dual threshold conditions, and at least one indicator has not reached the joint determination threshold.

[0055] For example, Figure 2 This is a schematic diagram for determining the degradation stage of the gate oxide layer. In 179 sets of sample data, 80 sets of samples where the hot carrier injection amount and the defect accumulation amount both exceed the corresponding thresholds are determined to be in the first degradation stage, and the remaining 99 sets of samples are determined to be in the second degradation stage. Among them, 14 sets of samples have only one indicator exceeding the corresponding threshold and do not meet the joint determination conditions of the first degradation stage.

[0056] For example, another target chip calculates a hot carrier injection amount of 150 μC / cm², and queries a preset defect degradation mapping table to obtain a defect accumulation amount of 420. Since the hot carrier injection amount of 150 μC / cm² is not greater than the preset first threshold of 180 μC / cm², the gate oxide layer of the chip is determined to be in the second degradation stage.

[0057] In step S4, the second leakage current and the second charge / discharge delay of the target memory chip under the degradation stage are obtained.

[0058] First, high-temperature stress and overvoltage stress are simultaneously applied to the target memory chip, and the stress conditions are kept consistent with those when the first leakage current and first charge / discharge delay are collected, i.e., the temperature stress is kept at 125°C and the overvoltage stress is kept at 2.25V. At the subsequent sampling time corresponding to the determined degradation stage, measurement data of the target memory chip continues to be collected. During subsequent sampling, the degradation stage is reviewed according to the determination method in step S3. Only when the review result is consistent with the aforementioned degradation stage is the corresponding sampled value used as the second leakage current and the second charge / discharge delay. If the review result changes, step S3 is re-executed to determine the current degradation stage, and subsequent sampling is performed under the determined current degradation stage.

[0059] Secondly, under the same stress conditions as the first set of measurements, the leakage current of the target memory chip array is collected through the current measurement channel of the test fixture as the second leakage current; the charge and discharge response delay of the memory cell is measured through the timing measurement channel of the test fixture as the second charge and discharge delay. For example, at a subsequent sampling time (stress continues for 1200 hours, i.e., 200 hours after the first set of measurements), after verification in step S3 confirming that it is still in the aforementioned first degradation stage, the second leakage current is measured to be 15μA and the second charge and discharge delay is 18.5ns.

[0060] In step S5, a pre-trained random forest regression model is used to predict the lifetime of the second leakage current and the second charge / discharge delay to obtain a quantified lifetime value of the target memory chip. Based on the quantified lifetime value, the failure state of the target memory chip is determined to obtain a degradation determination result, including:

[0061] The second leakage current and the second charge / discharge delay are input into the random forest regression model;

[0062] The predicted lifetime values ​​are output by the multiple regression decision trees within the random forest regression model.

[0063] Calculate the average value of the predicted lifetime output by each of the regression decision trees, and use the average value as the lifetime quantification value;

[0064] The random forest regression model is trained using the leakage current and charge / discharge delay of the historical aging test chip as input and the measured remaining lifespan value as label.

[0065] The quantified lifespan value is compared with a preset third threshold.

[0066] If the lifetime quantification value is less than the preset third threshold, the target memory chip is determined to be in a state of impending failure.

[0067] If the lifetime quantification value is not less than the preset third threshold, then the target memory chip is determined to be in a usable aging state.

[0068] First, it is worth noting that the random forest regression model is used to map the second leakage current and the second charge / discharge delay into lifetime quantification values. Its input is a two-dimensional feature vector, with the two dimensions corresponding to the second leakage current and the second charge / discharge delay, respectively. The output is a lifetime quantification value in hours, which represents the equivalent estimated remaining lifetime of the target memory chip under the determined degradation stage and after being converted to the preset reference usage conditions.

[0069] Secondly, it's worth noting that the structure of the random forest regression model consists of 100 regression decision trees, each with a maximum depth of 10 and a minimum of 5 samples per leaf node. Each regression decision tree is independently constructed on the training set using sampling with replacement. When splitting nodes, the splitting feature and split point are selected based on maximizing the reduction in squared error. The training method for the random forest regression model involves using the leakage current and charge / discharge delay of a historically aged chip under dual stress as input, and the measured remaining lifespan as the label. Supervised offline training is employed, with the mean squared error as the loss function. The training set for the random forest regression model is grouped according to degradation stage and dual stress conditions. Under each degradation stage, corresponding sub-models are trained according to specific combinations of temperature stress and overpressure stress. Training samples for the same sub-model are collected from the same degradation stage and the same dual stress conditions. In the online stage, the corresponding sub-model is invoked based on the current degradation stage and the actual temperature stress and overpressure stress combinations used, ensuring that the online input feature space matches the training feature space. Consistency is maintained; input features undergo standardized preprocessing during both training and online phases. Each sub-model uses the mean and standard deviation of its training set, and the standardized parameters are stored along with the corresponding sub-model. The measured remaining lifetime value is determined by recording the sampling time when the historical aging test chip collected training samples in the accelerated aging experiment, and the failure time when the chip finally failed. The remaining stress time corresponding to the training sample is obtained by subtracting the sampling time from the failure time. The remaining stress time is then converted according to the acceleration factor to obtain the measured remaining lifetime value. The acceleration factor is the product of the temperature acceleration factor and the voltage acceleration factor. The temperature acceleration factor is calculated according to the Arrhenius relation, and the calculation formula is:

[0070] ;

[0071] In the formula, As a temperature acceleration factor, The activation energy for oxide layer degradation was determined by fitting the failure times of historical dual-stress aging samples of the same model under different temperature conditions according to the Arrhenius relation. In this embodiment, it was taken as 0.7 eV. Boltzmann's constant, This refers to the thermodynamic temperature corresponding to the actual operating temperature of the chip. In this embodiment, the stress temperature corresponds to the thermodynamic temperature. Take 328K corresponding to 55℃. Taking 398K corresponding to 125℃, substituting it into the calculation formula, the temperature acceleration factor is approximately 78; the voltage acceleration factor is calculated using the exponential voltage model, and the formula is as follows:

[0072] ;

[0073] In the formula, As the voltage acceleration factor, The voltage acceleration factor is determined by fitting data from voltage-accelerated aging experiments; in this embodiment, it is taken as 3.5 / V. This is an overvoltage stress voltage. The rated operating voltage of the chip is specified in this embodiment. Take 2.25V, Taking 1.5V, substituting it into the calculation formula, the voltage acceleration factor is approximately 14; the total acceleration factor is the product of the temperature acceleration factor and the voltage acceleration factor, approximately 1100; the temperature acceleration parameter and the voltage acceleration parameter are both jointly calibrated by historical aging samples under simultaneous high temperature stress and overpressure stress. The product is used to convert the remaining stress time under the current dual stress condition to the equivalent remaining life under the preset reference usage conditions. The preset reference usage conditions in this embodiment are 55℃ and 1.5V. The measured remaining lifetime value is equal to the remaining stress time multiplied by the total acceleration factor. The criterion for determining the failure time is that the target memory chip experiences hard breakdown, or the read / write error rate within a fixed statistical window reaches or exceeds the preset error rate limit. The read / write error rate is calculated by counting the number of read / write errors occurring in 1000 consecutive read / write operations under a fixed read / write test sequence, relative to the total number of read / write operations within the statistical window. The preset error rate limit is determined based on the read / write function test requirements of the target memory chip and the error rate statistics of historical failure samples. In this embodiment, it is set to 0.1%, that is, when one or more read / write errors occur in 1000 consecutive read / write operations, a failure review is triggered, and the same read / write test sequence is immediately repeated under the same test conditions. If the read / write error can be reproduced, the failure condition is confirmed and the failure time is recorded. If it is not reproduced, the anomaly is not considered the failure time. After the model is trained offline, it is validated using historical chip samples of the same model that are independent of the training samples. The mean absolute error between the predicted lifetime value and the measured remaining lifetime value is used as the validation index. The standard deviation of the measured remaining lifetime under the same degradation stage and the same dual stress conditions in the same historical repeated aging test of the same model is used as the upper limit of the allowable mean absolute error. When the mean absolute error of the independent validation samples is not greater than the upper limit of the allowable mean absolute error, the model parameters are fixed and deployed on the test control terminal. Only forward calculation is performed in the online stage.

[0074] Then, during the online phase, the second leakage current and the second charge / discharge delay are standardized using the mean and standard deviation stored during the training phase to form a two-dimensional feature vector. This vector is then input into the random forest regression model. Multiple regression decision trees within the model output predicted lifetime values, and the average of the predicted lifetime values ​​output by each regression decision tree is calculated. This average value is used as the quantified lifetime value. For example, after inputting the feature vector consisting of the second leakage current of 15μA and the second charge / discharge delay of 18.5ns into the model, the predicted lifetime values ​​output by each regression decision tree are distributed between 9000h and 11000h. The average value is calculated to obtain a quantified lifetime value of 9500h converted to the reference operating conditions of 55℃ and 1.5V.

[0075] Finally, it's worth noting that the failure status is determined by comparing the quantified lifetime value with a preset third threshold. The preset third threshold is the lower limit of the remaining lifetime corresponding to the target memory chip entering a failure edge state. It is set based on statistically analyzing the remaining lifetime distribution of historical failed chips before failure, determining the safety margin ratio in conjunction with the safety margin of engineering applications, and setting the preset third threshold by multiplying the rated design lifetime of the target memory chip by the safety margin ratio. In this embodiment, the safety margin ratio is 20% based on the lower quantile of the remaining lifetime distribution of historical failed samples before failure. The rated design lifetime is derived from the design reliability index of the target memory chip, given by the sample specification or design reliability target of the target model. In this embodiment, the rated design lifetime of the target memory chip is 50,000 hours, and the preset third threshold is 10,000 hours. The rated design lifetime and the quantified lifetime value use the same reference usage conditions to ensure direct comparison. Since the quantified lifetime value of 9,500 hours is less than the preset third threshold of 10,000 hours, the target memory chip is determined to be in a failure edge state, resulting in a degradation judgment. The chip should be taken out of service or downgraded. If the lifetime quantification value is not less than the preset third threshold, the target memory chip is determined to be in a usable aging state, and a degradation determination result is obtained. The chip can continue to be used and the next round of aging test can be arranged. For example, the lifetime quantification value of another target chip is 12000h, which is not less than the preset third threshold, and the chip is determined to be in a usable aging state.

[0076] In summary, this embodiment simultaneously applies high-temperature stress and overpressure stress, collects the first leakage current and the first charge-discharge delay, calculates the resultant force damage characteristics, calculates the hot carrier injection amount and defect accumulation amount based on the first leakage current and resultant force damage characteristics, and determines the degradation stage of the gate oxide layer. For the determined degradation stage, a second leakage current and a second charge-discharge delay are collected, and a pre-trained random forest regression model is used for lifetime prediction to obtain a quantified lifetime value and determine the failure state, thus obtaining the degradation determination result. It should be noted that for those skilled in the art, several improvements and additions can be made without departing from the principle of this invention, and these improvements and additions should also be considered within the scope of protection of this invention.

[0077] The second embodiment of the present invention provides a temperature-voltage coordinated DDR3 memory chip aging test system, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps of the method described above.

[0078] It should be noted that the temperature-voltage coordinated DDR3 memory chip aging test system provided in this embodiment of the invention is used to execute all the process steps of the temperature-voltage coordinated DDR3 memory chip aging test method in the above embodiment. The working principle and beneficial effect of the two are one-to-one, so they will not be described again.

[0079] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0080] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A temperature-voltage coordinated aging test method for DDR3 memory chips, characterized in that, include: The first leakage current and the first charge / discharge delay of the target memory chip under the simultaneous action of high temperature stress and overpressure stress are obtained. Damage characteristics of the target memory chip are obtained by calculating the damage characteristics based on the first leakage current and the first charge / discharge delay. The amount of hot carrier injection and the amount of defect accumulation in the gate oxide layer of the target memory chip are calculated based on the first leakage current and the resultant force damage characteristics, and the degradation stage of the gate oxide layer is determined based on the amount of hot carrier injection and the amount of defect accumulation. The second leakage current and the second charge / discharge delay of the target memory chip during the degradation phase are obtained; A pre-trained random forest regression model is used to predict the lifetime of the second leakage current and the second charge-discharge delay to obtain a quantified lifetime value of the target memory chip. The failure state of the target memory chip is determined based on the quantified lifetime value to obtain a degradation determination result.

2. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 1, characterized in that, The step of calculating the combined force damage characteristics of the target memory chip based on the first leakage current and the first charge / discharge delay includes: Obtain the initial leakage current and initial charge / discharge delay of the target memory chip before the application of the high-temperature stress and the overpressure stress; Calculate the first drift rate of the first leakage current relative to the initial leakage current, and the second drift rate of the first charge / discharge delay relative to the initial charge / discharge delay; The first drift rate and the second drift rate are weighted and summed according to a preset weight to obtain the resultant force damage characteristics.

3. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 1, characterized in that, The calculation of the hot carrier injection amount of the gate oxide layer of the target memory chip includes: Based on the first leakage current, the preset injection allocation coefficient and the effective area of ​​the gate oxide layer of the target memory chip, the amount of charge injected into the gate oxide layer per unit time and per unit area is calculated to obtain the carrier injection flux. The carrier injection flux is accumulated over a preset stress duration to obtain the hot carrier injection amount.

4. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 1, characterized in that, The calculation of the defect accumulation in the gate oxide layer of the target memory chip includes: Using the combined force damage characteristics and the hot carrier injection amount as indexes, a preset defect degradation mapping table is queried to obtain the defect accumulation amount of the gate oxide layer of the target memory chip. The preset defect degradation mapping table records the combined force damage characteristics of historical aging test chips under the simultaneous action of high temperature stress and overpressure stress, the correspondence between the amount of hot carrier injection and the amount of measured defect accumulation, and is established by statistical analysis of multiple sets of historical accelerated aging test data.

5. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 1, characterized in that, The step of determining the degradation stage of the gate oxide layer based on the hot carrier injection amount and the defect accumulation amount includes: The amount of hot carrier injection is compared with a preset first threshold, and the amount of defect accumulation is compared with a preset second threshold. If the amount of hot carrier injection is greater than the preset first threshold and the amount of defect accumulation is greater than the preset second threshold, then the gate oxide layer is determined to have entered the first degradation stage. If the amount of hot carrier injection is not greater than the preset first threshold or the amount of defect accumulation is not greater than the preset second threshold, then the gate oxide layer is determined to be in the second degradation stage.

6. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 5, characterized in that, The preset first threshold and the preset second threshold are determined in the following way: Collect data on the amount of hot carrier injection and defect accumulation when historical aging test chips fail under the simultaneous action of high temperature stress and overpressure stress. The value corresponding to the preset quantile in the statistical distribution of the hot carrier injection amount is used as the preset first threshold, and the value corresponding to the preset quantile in the statistical distribution of the defect accumulation amount is used as the preset second threshold.

7. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 1, characterized in that, The method of using a pre-trained random forest regression model to predict the lifetime of the second leakage current and the second charge / discharge delay to obtain a quantitative value of the lifetime of the target memory chip includes: The second leakage current and the second charge / discharge delay are input into the random forest regression model; The predicted lifetime values ​​are output by the multiple regression decision trees within the random forest regression model. Calculate the average value of the predicted lifetime output by each of the regression decision trees, and use the average value as the lifetime quantification value; The random forest regression model is trained using the leakage current and charge / discharge delay of historical aging test chips as inputs and the measured remaining lifespan values ​​as labels.

8. The DDR3 memory chip aging test method based on temperature-voltage coordination according to claim 1, characterized in that, The step of determining the failure state of the target memory chip based on the lifetime quantification value includes: The quantified lifespan value is compared with a preset third threshold. If the lifetime quantification value is less than the preset third threshold, the target memory chip is determined to be in a state of impending failure. If the lifetime quantification value is not less than the preset third threshold, then the target memory chip is determined to be in a usable aging state.

9. A temperature-voltage coordinated DDR3 memory chip aging test system, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the method described in any one of claims 1 to 8.

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