Single-cell wireless BMS chip control system

Abstract

The application provides a single-cell wireless BMS chip control system and relates to the technical field of battery management.The control system is integrated in a single-cell wireless BMS chip connected with a single cell, and a CPU system, a first one-wire communication unit, a second one-wire communication unit, an AFE control logic, an EIS excitation end, an ADC, an SRAM, an EIS calculation unit, a CMP comparison unit and an RF unit are arranged in the chip; the CPU system sends a collection command to the AFE control logic through the first one-wire communication unit, the AFE control logic controls the EIS excitation end to output an excitation signal and controls the ADC to collect response data; the first one-wire communication unit and the second one-wire communication unit return the response data of the same sampling point to the CMP comparison unit for comparison, and the CPU system stores the response data in the SRAM or discards the response data according to the comparison result; the EIS calculation unit reads the response data in the SRAM to generate impedance data, and the RF unit sends the impedance data.The application is favorable for reducing the wiring fault risk of a battery pack and improving the reliability of single-cell impedance diagnosis.

Description

Technical Field

[0001] This invention relates to the field of battery management technology, and in particular to a single-cell wireless BMS chip control system. Background Technology

[0002] In power battery packs, energy storage battery clusters, and secondary battery systems, battery management systems (BMS) need to continuously acquire operating parameters such as voltage, current, and temperature of each cell to perform status monitoring and safety protection. Existing multi-cell battery management systems mostly employ wired sampling and daisy-chain communication architectures. As the number of battery cells increases, the number of sampling harnesses and connectors also increases, leading to increased wiring space, assembly difficulty, and maintenance costs. Poor connector contact, cable corrosion, or loose terminals can cause localized sampling signal distortion and may trigger overheating risks, resulting in decreased reliability of the battery pack during long-term operation.

[0003] In a daisy-chain communication architecture, anomalies in a single slave node or a local link can easily affect data transmission in subsequent nodes. Fault localization relies on manual troubleshooting and segmented detection, making it difficult to adapt to application scenarios such as adding or removing battery modules, tiered utilization, and dynamic reconfiguration. Traditional battery management systems typically rely on basic operating parameters to estimate battery status, but they lack the ability to identify changes in internal impedance of the cells and early aging characteristics, making it difficult to form a complete diagnosis of the sampling link, communication link, and computing link.

[0004] Existing wireless battery management or impedance diagnostic solutions have reduced external wiring burden to some extent. However, these solutions often employ discrete device combinations, resulting in off-chip connections and cross-device transmission processes between analog sampling, diagnostic calculations, and wireless transmission. Discrete device combinations are susceptible to limitations in signal integrity, power consumption, and synchronization control accuracy, and it is also difficult to complete hardware-level consistency verification before data enters the diagnostic calculations. Therefore, a highly integrated wireless BMS chip control solution for single-cell operation is still needed. Summary of the Invention

[0005] To address the problems of existing multi-cell battery management systems, such as the large number of sampling harnesses and connectors, the susceptibility of daisy-chain communication links to single-point failures, the difficulty of performing data consistency verification on-chip in discrete wireless BMS solutions, and the lack of cell impedance diagnostic capabilities in traditional BMS, this invention provides a single-cell wireless BMS chip control system.

[0006] The single-cell wireless BMS chip control system provided by this invention is integrated into a single-cell wireless BMS chip connected to a single cell. The system includes a CPU system, a first single-wire communication unit, a second single-wire communication unit, AFE control logic, an EIS excitation terminal, an ADC, SRAM, an EIS calculation unit, a CMP comparison unit, and an RF unit. The CPU system sends acquisition commands to the AFE control logic via the first single-wire communication unit. The AFE control logic instructs the EIS excitation terminal to output an excitation signal and instructs the ADC to acquire response data. The AFE control logic causes the first and second single-wire communication units to send back response data from the same sampling point for comparison by the CMP comparison unit. The CPU system stores the response data in the SRAM or discards it according to the comparison result. The EIS calculation unit reads the response data in the SRAM to generate impedance data, and the RF unit transmits the impedance data.

[0007] Preferably, the first single-wire communication unit and the second single-wire communication unit each include a transmit / receive control circuit, a transmitting end, a data receiving register, a communication verification circuit, a communication monitoring circuit, and a communication diagnostic circuit. The process of issuing acquisition commands and writing back response data includes: the CPU system writes the acquisition command to the transmitting end of the first single-wire communication unit, and the first single-wire communication unit transmits the acquisition command to the AFE control logic in a bidirectional time-division transmission mode; after the AFE control logic starts the ADC, it controls the first single-wire communication unit and the second single-wire communication unit to send back the response data output by the ADC, and forms the same sampling point response data in the data receiving registers of the first single-wire communication unit and the second single-wire communication unit.

[0008] Preferably, the process by which the AFE control logic causes the EIS excitation terminal to output an excitation signal and the ADC to acquire response data includes: the AFE control logic obtains the number of acquisition points carried in the acquisition command before the excitation signal is output; the EIS excitation terminal outputs a sinusoidal excitation signal to a single cell anode through the EISPIN; the ADC forms continuous sampling points according to the sampling sequence during the application of the sinusoidal excitation signal; and for each sampling point formed by the ADC, the AFE control logic triggers the first single-wire communication unit and the second single-wire communication unit to send back the response data of the same sampling point.

[0009] Preferably, the process of the CMP comparison unit comparing the response data of the same sampling point and the CPU system storing the response data into SRAM or discarding it according to the comparison result includes: the first single-wire communication unit and the second single-wire communication unit are respectively provided with data receiving registers; the CMP comparison unit compares whether the response data of the same sampling point in the data receiving registers of the first single-wire communication unit and the second single-wire communication unit are the same; when the two response data are the same, the CPU system reads the response data returned by the first single-wire communication unit and stores it into SRAM; when the two response data are different, the CPU system discards the two response data corresponding to the same sampling point.

[0010] Preferably, the process of the CPU system storing the response data returned by the first single-wire communication unit into the SRAM includes: the CPU system storing the response data into the SRAM according to the ADC sampling timing, and forming a sampling sequence in the SRAM corresponding to the number of sampling points pre-configured by the CPU system.

[0011] Preferably, the EIS calculation unit includes a first EIS calculation unit and a second EIS calculation unit; when the CPU system stores response data in the SRAM according to the sampling time sequence and the number reaches the number of sampling points pre-configured by the CPU system, the first EIS calculation unit or the second EIS calculation unit is started to read the response data from the SRAM and generate impedance data; when the EIS calculation unit is in diagnostic state, the CPU system uses the same set of response data in the SRAM or pre-stored reference data to diagnose the EIS calculation unit.

[0012] Preferably, in normal acquisition mode, the CPU system starts the first EIS calculation unit to read response data from SRAM and generate impedance data, while the second EIS calculation unit does not participate in impedance calculation in normal acquisition mode. When the CPU system uses the same set of response data in SRAM to diagnose the first and second EIS calculation units, the first and second EIS calculation units are started sequentially. The first and second EIS calculation units read the same set of response data from SRAM and generate first impedance data and second impedance data, respectively. When the first impedance data and the second impedance data are the same, the CPU system records the normal diagnostic state of the EIS calculation unit. When the first impedance data and the second impedance data are different, the CPU system records the abnormal diagnostic state of the EIS calculation unit.

[0013] Preferably, the process of the CPU system diagnosing the EIS calculation unit using pre-stored reference data includes: the CPU system calling the pre-stored reference data and the pre-stored reference output data corresponding to the pre-stored reference data; when the CPU system inputs the pre-stored reference data into the first EIS calculation unit, the first EIS calculation unit generates a first reference calculation result based on the pre-stored reference data, and the CPU system records the diagnostic status of the first EIS calculation unit according to the comparison result between the first reference calculation result and the pre-stored reference output data; when the CPU system inputs the pre-stored reference data into the second EIS calculation unit, the second EIS calculation unit generates a second reference calculation result based on the pre-stored reference data, and the CPU system records the diagnostic status of the second EIS calculation unit according to the comparison result between the second reference calculation result and the pre-stored reference output data.

[0014] Preferably, the CPU system performs reference voltage cross-readback in the idle state. The reference voltage cross-readback includes: the CPU system sending a reference voltage sampling command to the AFE control logic through a first single-wire communication unit; the AFE control logic controlling the ADC to sample the reference voltage; and the CPU system reading back the first reference voltage sampling data through a second single-wire communication unit. Alternatively, the CPU system sending a reference voltage sampling command to the AFE control logic through the second single-wire communication unit; the AFE control logic controlling the ADC to sample the reference voltage; and the CPU system reading back the second reference voltage sampling data through the first single-wire communication unit.

[0015] Preferably, the process by which the CPU system generates the on-chip sampling path state based on the first reference voltage sampling data and the second reference voltage sampling data includes: the CPU system calculating the difference between the first reference voltage sampling data and the second reference voltage sampling data; when the difference falls within the error range corresponding to the sampling resolution of the ADC, the CPU system records the normal state of the on-chip sampling path; when the difference does not fall within the error range corresponding to the sampling resolution of the ADC, the CPU system records the abnormal state of the on-chip sampling path.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0017] By integrating the CPU system, AFE control logic, ADC, EIS computing unit, CMP comparison unit, and RF unit into a single-cell wireless BMS chip that connects a single battery cell, the impact of external sampling harnesses and connectors on battery pack reliability is reduced, and the operational risks caused by complex wiring, contact failures, and difficulties in link expansion in wired daisy-chain architecture are mitigated.

[0018] By transmitting the same sampling point response data back through the first single-wire communication unit and the second single-wire communication unit, the CMP comparison unit can perform a consistency comparison before the response data is written to the SRAM, reducing the probability of abnormal data from a single path transmission entering the impedance calculation process.

[0019] By applying an excitation signal to a single cell through the EIS excitation terminal, and then having the ADC synchronously collect the response data, the EIS calculation unit generates impedance data, thus extending battery management from basic operating parameter monitoring to single-cell impedance diagnosis and improving the ability to identify changes in the internal state of the cell.

[0020] The CPU system stores the response data into SRAM or discards it according to the comparison result, and forms a sampling sequence corresponding to the number of sampling points in SRAM. This allows the impedance calculation to be based on the response data that has undergone dual-channel consistency verification, reducing the impact of abnormal sampling points on the impedance data.

[0021] The first and second EIS calculation units perform diagnostic comparisons on the same set of response data, and use pre-stored benchmark data to diagnose the EIS calculation units, thereby enhancing the ability to identify anomalies in the calculation link.

[0022] The CPU system reads back the reference voltage via the first and second single-wire communication units in the idle state, and generates the on-chip sampling path status based on the two reference voltage sampling data. This enables the sampling link and communication link to perform status checks during non-acquisition phases, improving the diagnostic reliability of the single-cell wireless BMS chip during long-term operation. Attached Figure Description

[0023] Figure 1 This is a structural diagram of a single-cell wireless BMS chip control system.

[0024] Figure 2 This is a schematic diagram of the internal communication structure of a single-cell wireless BMS chip. Detailed Implementation

[0025] This embodiment provides a single-cell wireless BMS chip control system. The single-cell wireless BMS chip connects to a single battery cell and internally performs tasks such as issuing acquisition commands, EIS excitation, ADC sampling, dual-channel data transmission, CMP comparison, SRAM storage, EIS calculation, RF unit transmission, and cross-reading of reference voltage in idle state.

[0026] The battery pack includes When saving battery cells, This indicates the number of battery cells in the battery pack. Traditional wired BMS typically require... The system includes one sampling line and two communication lines. A single-cell wireless BMS chip uses one chip corresponding to one battery cell as its management boundary. Multiple single-cell wireless BMS chips connected to the same wireless BMS network form a battery pack-level management structure. In one implementation, the battery pack-level management structure is adapted to 1 to 200 battery cells.

[0027] like Figure 1 As shown, the single-cell wireless BMS chip includes a CPU system, a first single-wire communication unit, a second single-wire communication unit, AFE control logic, an EIS excitation terminal, an ADC, SRAM, an EIS calculation unit, a CMP comparator unit, and an RF unit. The CPU system is connected to the SRAM, EIS calculation unit, CMP comparator unit, and RF unit via an internal chip bus. The AFE control logic is connected to the EIS excitation terminal, ADC, first single-wire communication unit, and second single-wire communication unit. The first and second single-wire communication units are used for point-to-point bidirectional time-division multiplexing transmission between the CPU system and the AFE control logic.

[0028] like Figure 2As shown, both the first and second single-wire communication units employ SSWU circuit modules. The SSWU circuit module is used to implement single-wire point-to-point bidirectional time-division multiplexing transmission, and is represented within the chip as a single-wire connection and corresponding control circuit. The SSWU circuit module includes a transmit / receive control circuit, a transmitting end, a data receive register, a communication verification circuit, a communication monitoring circuit, and a communication diagnostic circuit. Figure 2 The transmit and receive control circuit is labeled SSWU_TRX_CTRL, the transmit end is labeled SSWU_TX_REG, the data receive register is labeled SSWU_RX_REG, the communication verification circuit is labeled SSWU_ECC and SSWU_CRC16, the communication monitoring circuit is labeled SSWU_WDG, and the communication diagnostic circuit is labeled SSWU_DIAG.

[0029] The CPU system generates the acquisition command. The acquisition command carries the number of acquisition points. , This represents the number of sampling points that need to be formed within one acquisition cycle. In one implementation, the number of sampling points... The values ​​are 512, 1024, or 2048. The CPU system writes the acquisition command to the sending end of the first single-wire communication unit, and the first single-wire communication unit transmits the acquisition command to the AFE control logic in a bidirectional time-division transmission mode.

[0030] After receiving the acquisition command, the AFE control logic obtains the number of acquisition points carried in the acquisition command before outputting the excitation signal. The AFE control logic controls the EIS excitation terminal to output a sinusoidal excitation signal, which is then superimposed onto the anode of a single cell via the EIS PIN.

[0031] During the application of a sinusoidal excitation signal to the EIS excitation terminal, the ADC synchronously acquires the response data of a single cell under the action of the sinusoidal excitation signal. The response data includes voltage response data and current response data. In one implementation, the response data also includes temperature data, deformation data, or pressure sensor data.

[0032] The sampling point number is denoted as , The ADC forms consecutive sampling points according to the sampling sequence during the application of the excitation signal. Each time the ADC forms a sampling point... At the sampling point, the AFE control logic triggers the first and second single-wire communication units to send back the first single-wire communication unit. The response data corresponding to each sampling point.

[0033] The data receiving register of the first single-wire communication unit The response data of each sampling point is denoted as The data receive register of the second single-wire communication unit The response data of each sampling point is denoted as CMP Comparison Unit Comparison and Are they the same? The difference between the two response data is recorded as:

[0034] ;

[0035] In the formula, Indicates the first The difference between the two response data corresponding to each sampling point.

[0036] The CMP comparison unit forms the first [value] according to a fixed threshold of 0. Comparison results of sampling points :

[0037] ;

[0038] In the formula, Indicates the first The two response data corresponding to each sampling point are the same. Indicates the first The two response data corresponding to each sampling point are different.

[0039] when At that time, the CPU system reads the first single-wire communication unit's returned data. The response data for each sampling point is recorded and stored in SRAM according to the ADC sampling timing. When At that time, the CPU system discards the first Two response data points correspond to each sampling point, and the data generated in the current acquisition cycle is recorded as an invalid acquisition sequence. Invalid acquisition sequences are not used as input to the EIS calculation unit. The CPU system reissues the acquisition command in the next acquisition cycle to regenerate the acquisition sequence.

[0040] The CPU system sequentially records the comparison results of each sampling point within one acquisition cycle. .when The corresponding comparison results are all At that time, the CPU system records the response data stored in SRAM as a valid acquisition sequence. The valid acquisition sequence is denoted as:

[0041] ;

[0042] In the formula, Indicates the first Each sampling point corresponds to a response data that is stored in SRAM.

[0043] When the response data includes both voltage and current response data, the effective acquisition sequence includes both voltage and current acquisition sequences. The voltage acquisition sequence is denoted as:

[0044] ;

[0045] The current acquisition sequence is denoted as:

[0046] ;

[0047] In the formula, Indicates the first Each sampling point corresponds to and stores the voltage response data in SRAM. Indicates the first Each sampling point corresponds to and stores the current response data in SRAM.

[0048] The EIS calculation unit includes a first EIS calculation unit and a second EIS calculation unit. The CPU system records response data in SRAM as valid acquisition sequences, and the number of data points in the valid acquisition sequences reaches the required number of acquisition points. When the CPU system receives 1024 or 2048 points of response data from the SRAM, it starts the EIS calculation unit.

[0049] Excitation frequency is denoted as , The excitation frequency is determined by the sinusoidal excitation signal output from the EIS excitation terminal. The EIS calculation unit performs frequency domain transformation on the voltage and current acquisition sequences to obtain the excitation frequency. Corresponding voltage response components and current response components The impedance data is generated using the following formula:

[0050] ;

[0051] In the formula, Indicates the excitation frequency of a single cell The impedance data is obtained from the following data. Frequency domain transformation can be performed using Discrete Fourier Transform, Fast Fourier Transform, or Orthogonal Coherence Calculation. The impedance data corresponding to multiple excitation frequencies constitute the impedance spectrum data of a single cell.

[0052] During normal data acquisition, the CPU system activates the first EIS calculation unit to read response data from SRAM and generate impedance data. The second EIS calculation unit does not participate in impedance calculation during normal acquisition. The impedance data generated by the EIS calculation unit is transmitted to the RF unit, which then sends the impedance data. The impedance data can be stored within the single-cell wireless BMS chip for subsequent diagnostic reading.

[0053] In EIS calculation unit diagnostic mode, the CPU system uses the same set of response data from SRAM to diagnose the first and second EIS calculation units. The CPU system sequentially starts the first and second EIS calculation units. The first EIS calculation unit reads the same set of response data from SRAM and generates first impedance data; the second EIS calculation unit reads the same set of response data from SRAM and generates second impedance data. The first impedance data is denoted as... The second impedance data is denoted as .

[0054] CPU System Comparison and When the first impedance data and the second impedance data are the same, the CPU system records the normal diagnostic status of the EIS calculation unit; when the first impedance data and the second impedance data are different, the CPU system records the abnormal diagnostic status of the EIS calculation unit. The diagnostic status is written to the diagnostic flag bit in SRAM, or sent through the RF unit along with the impedance data.

[0055] The CPU system also uses pre-stored reference data to diagnose the EIS computing unit. The pre-stored reference data is denoted as... The pre-stored baseline output data is denoted as Pre-stored baseline data and pre-stored baseline output data Write to SRAM or the internal readable storage area of ​​the chip before EIS computing unit diagnostics; pre-store benchmark data. Includes reference voltage acquisition sequence and reference current acquisition sequence, and pre-stores reference output data. To process pre-stored reference data according to frequency domain transformation and impedance data generation methods The calculated impedance reference data.

[0056] The CPU system will pre-store the baseline data. When the first EIS calculation unit is input, the first EIS calculation unit calculates based on the pre-stored reference data. Generate the first baseline calculation results The CPU system compares the results of the first benchmark calculation. Output data with pre-stored baseline The diagnostic status of the first EIS calculation unit is recorded according to the comparison results.

[0057] The CPU system will pre-store the baseline data. When inputting data into the second EIS calculation unit, the second EIS calculation unit calculates data based on pre-stored reference data. Generate second benchmark calculation results The CPU system compares the results of the second benchmark calculation. Output data with pre-stored baseline The diagnostic status of the second EIS calculation unit is recorded according to the comparison results.

[0058] The CPU system performs reference voltage cross-readback in idle state. The reference voltage is denoted as... The reference voltage is provided by the internal reference voltage circuit of the single-cell wireless BMS chip. The CPU system sends a reference voltage sampling command to the AFE control logic through the first single-wire communication unit. The AFE control logic controls the ADC to sample the reference voltage. The CPU system reads back the first reference voltage sampling data through the second single-wire communication unit. .

[0059] The CPU system completes the first reference voltage sampling data. After reading back, a reference voltage sampling command is sent to the AFE control logic via the second single-wire communication unit. The AFE control logic controls the ADC to sample the reference voltage, and the CPU system reads back the second reference voltage sampling data via the first single-wire communication unit. First reference voltage sampling data Second reference voltage sampling data This corresponds to two opposite command sending and data readback paths.

[0060] The CPU system samples data based on the first reference voltage. Second reference voltage sampling data Generate on-chip sampling path state. The CPU system calculates the difference between the first reference voltage sampling data and the second reference voltage sampling data:

[0061] ;

[0062] In the formula, This represents the difference between two reference voltage sampling data.

[0063] The sampling resolution of the ADC is denoted as When the ADC bit width is The full-scale range of the ADC input is At that time, the sampling resolution of the ADC is:

[0064] ;

[0065] In the formula, Indicates the number of bits in the ADC. This represents the full-scale range of the ADC input. In one implementation, the ADC is a 16-bit Σ-Δ ADC, where b=16.

[0066] The CPU system records the sampling path status on the chip according to the following formula. :

[0067] ;

[0068] In the formula, This indicates the status of the on-chip sampling path. The reference voltage cross-readback covers the CPU system, the first single-wire communication unit, the second single-wire communication unit, the AFE control logic, the ADC, and the reference voltage sampling readback link.

[0069] In one implementation, the first and second single-wire communication units are configured with Manchester encoding, frame header ECC(4,1), CRC-16 / DNP, frame header echoing, and independent IWDG monitoring. Communication bit error rate. satisfy The link failure rate is less than 0.1 ppm, where ppm represents parts per million; the hardware response time of the CMP comparison unit is less than 1 μs. Diagnostic coverage represents the ratio between the number of fault types that the on-chip diagnostic link can identify and the predefined number of on-chip fault types. The first single-wire communication unit, the second single-wire communication unit, the CMP comparison unit, the EIS calculation unit, and the reference voltage cross-readback are used to construct an on-chip diagnostic link with a diagnostic coverage greater than 99%.

[0070] The single-cell wireless BMS chip connects to the battery pack-level wireless BMS network via an RF unit. The battery pack-level wireless BMS network supports the removal of abnormal cell nodes from the network and the addition of new cell nodes. In one implementation, the RF unit communicates and transmits data with other nodes in the wireless BMS network, and records the RF unit's communication status based on the communication data transmission and reception results.

[0071] The working process of a single-cell wireless BMS chip includes: the CPU system sends a data acquisition command to the AFE control logic via the first single-wire communication unit; the AFE control logic controls the EIS excitation terminal to output a sinusoidal excitation signal and controls the ADC to acquire response data; the first single-wire communication unit and the second single-wire communication unit transmit response data from the same sampling point; the CMP comparison unit compares the two response data; the CPU system stores the response data in SRAM or discards it according to the comparison result; the response data in SRAM forms a valid acquisition sequence and the number of data in the valid acquisition sequence reaches the number of acquisition points. Then, the CPU system starts the EIS calculation unit to generate impedance data; the RF unit sends the impedance data; the CPU system performs reference voltage cross-readback and generates on-chip sampling path status in idle state.

[0072] The above embodiments are only used to illustrate the technical methods of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical methods of the present invention without departing from the spirit and scope of the technical methods of the present invention.

Claims

1. A single-cell wireless BMS chip control system, characterized in that, The control system is integrated into a single-cell wireless BMS chip connected to a single battery cell. The system includes: a CPU system, a first single-wire communication unit, a second single-wire communication unit, AFE control logic, an EIS excitation terminal, an ADC, SRAM, an EIS calculation unit, a CMP comparison unit, and an RF unit. The CPU system sends acquisition commands to the AFE control logic via the first single-wire communication unit. The AFE control logic instructs the EIS excitation terminal to output an excitation signal and instructs the ADC to acquire response data. The AFE control logic causes the first and second single-wire communication units to send back response data from the same sampling point for comparison by the CMP comparison unit. The CPU system stores the response data in the SRAM or discards it according to the comparison result. The EIS calculation unit reads the response data in the SRAM to generate impedance data, and the RF unit sends the impedance data.

2. The single-cell wireless BMS chip control system according to claim 1, characterized in that, The first single-wire communication unit and the second single-wire communication unit respectively include a transmit / receive control circuit, a transmitting end, a data receiving register, a communication verification circuit, a communication monitoring circuit, and a communication diagnostic circuit; The process of issuing acquisition commands and writing back response data includes: the CPU system writes the acquisition command to the sending end of the first single-line communication unit, and the first single-line communication unit transmits the acquisition command to the AFE control logic in a bidirectional time-division transmission mode; After the AFE control logic starts the ADC, it controls the first single-wire communication unit and the second single-wire communication unit to send back the response data output by the ADC, and forms the same sampling point response data in the data receiving registers of the first single-wire communication unit and the second single-wire communication unit.

3. The single-cell wireless BMS chip control system according to claim 2, characterized in that, The process by which the AFE control logic causes the EIS excitation terminal to output an excitation signal and the ADC to acquire response data includes: before the excitation signal is output, the AFE control logic obtains the number of acquisition points carried in the acquisition command; the EIS excitation terminal outputs a sinusoidal excitation signal to the anode of a single cell through the EIS PIN; the ADC forms continuous sampling points according to the sampling sequence during the application of the sinusoidal excitation signal; each time the ADC forms a sampling point, the AFE control logic triggers the first single-wire communication unit and the second single-wire communication unit to send back the response data of the same sampling point.

4. The single-cell wireless BMS chip control system according to claim 1, characterized in that, The process by which the CMP comparison unit compares the response data at the same sampling point and the CPU system stores or discards the response data according to the comparison result includes: the first single-wire communication unit and the second single-wire communication unit are respectively equipped with data receiving registers; the CMP comparison unit compares whether the response data at the same sampling point in the data receiving registers of the first single-wire communication unit and the second single-wire communication unit are the same; when the two response data are the same, the CPU system reads the response data returned by the first single-wire communication unit and stores it in SRAM; when the two response data are different, the CPU system discards the two response data corresponding to the same sampling point.

5. The single-cell wireless BMS chip control system according to claim 4, characterized in that, The process by which the CPU system stores the response data returned by the first single-wire communication unit into the SRAM includes: the CPU system stores the response data into the SRAM according to the ADC sampling timing, and forms a sampling sequence in the SRAM corresponding to the number of sampling points pre-configured by the CPU system.

6. The single-cell wireless BMS chip control system according to claim 1, characterized in that, The EIS calculation unit includes a first EIS calculation unit and a second EIS calculation unit. When the CPU system stores response data in SRAM according to the sampling time sequence and the number reaches the number of sampling points pre-configured by the CPU system, the first EIS calculation unit or the second EIS calculation unit is started to read the response data from SRAM and generate impedance data. When the CPU system is in EIS computing unit diagnostic state, it uses the same set of response data in SRAM or pre-stored reference data to diagnose the EIS computing unit.

7. The single-cell wireless BMS chip control system according to claim 6, characterized in that, In normal acquisition mode, the CPU system starts the first EIS calculation unit to read response data from SRAM and generate impedance data. The second EIS calculation unit does not participate in impedance calculation in normal acquisition mode. When the CPU system uses the same set of response data in SRAM to diagnose the first EIS calculation unit and the second EIS calculation unit, the first EIS calculation unit and the second EIS calculation unit are started sequentially. The first EIS calculation unit and the second EIS calculation unit read the same set of response data from SRAM and generate first impedance data and second impedance data respectively. When the first impedance data and the second impedance data are the same, the CPU system records the normal diagnostic state of the EIS calculation unit. When the first impedance data and the second impedance data are different, the CPU system records the abnormal diagnostic state of the EIS calculation unit.

8. The single-cell wireless BMS chip control system according to claim 6, characterized in that, The process of the CPU system diagnosing the EIS computing unit using pre-stored reference data includes: the CPU system calling the pre-stored reference data and the corresponding pre-stored reference output data; when the CPU system inputs the pre-stored reference data into the first EIS computing unit, the first EIS computing unit generates a first reference calculation result based on the pre-stored reference data, and the CPU system records the diagnostic status of the first EIS computing unit according to the comparison result between the first reference calculation result and the pre-stored reference output data; when the CPU system inputs the pre-stored reference data into the second EIS computing unit, the second EIS computing unit generates a second reference calculation result based on the pre-stored reference data, and the CPU system records the diagnostic status of the second EIS computing unit according to the comparison result between the second reference calculation result and the pre-stored reference output data.

9. The single-cell wireless BMS chip control system according to claim 1, characterized in that, The CPU system performs reference voltage cross-readback in idle state. The reference voltage cross-readback includes: the CPU system sending a reference voltage sampling command to the AFE control logic through a first single-wire communication unit; the AFE control logic controlling the ADC to sample the reference voltage; and the CPU system reading back the first reference voltage sampling data through a second single-wire communication unit. The CPU system then sends a reference voltage sampling command to the AFE control logic through the second single-wire communication unit; the AFE control logic controlling the ADC to sample the reference voltage; and the CPU system reading back the second reference voltage sampling data through the first single-wire communication unit.

10. The single-cell wireless BMS chip control system according to claim 9, characterized in that, The process by which the CPU system generates the on-chip sampling path status based on the first reference voltage sampling data and the second reference voltage sampling data includes: the CPU system calculates the difference between the first reference voltage sampling data and the second reference voltage sampling data; when the difference falls within the error range corresponding to the sampling resolution of the ADC, the CPU system records the normal status of the on-chip sampling path; when the difference does not fall within the error range corresponding to the sampling resolution of the ADC, the CPU system records the abnormal status of the on-chip sampling path.

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