Vertical cavity surface emitting laser and method of manufacturing and chip thereof

Abstract

The application provides a vertical cavity surface emitting laser and a preparation method and a chip thereof, and belongs to the technical field of semiconductors. The vertical cavity surface emitting laser comprises a substrate; an N-type distributed Bragg reflector, an active region, a P-type distributed Bragg reflector and a passivation layer on the substrate; a plurality of vertical injection holes penetrating through the passivation layer and distributed around a light-emitting hole; and a line connecting the center of each vertical injection hole to the light-emitting hole and a defect propagation direction of the substrate form a non-parallel angle, so that all the vertical injection holes are not located on the extension line of the defect propagation direction, thereby inhibiting the extension of defects along the defect propagation direction. The application has the advantages of inhibiting the generation of defects from the source, improving the light-emitting efficiency and reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a vertical cavity surface-emitting laser, its fabrication method, and a chip. Background Technology

[0002] A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser that emits laser light vertically from the surface of a chip. It has advantages such as low threshold current, circular beam, and easy integration into two-dimensional arrays, and is widely used in optical communication, 3D sensing, lidar and other fields.

[0003] In existing technologies, conventional vertical injection apertures (VIAs) are arranged along the GaAs

[110] crystal orientation. Since the

[110] crystal orientation is the natural cleavage plane of the GaAs substrate, dicing and splitting along this direction are easy and the edges are neat. At the same time, the etching rate is uniform, which facilitates process control. However, the

[110] crystal orientation is also a direction in which defects are prone to multiply. An unreasonable current injection path leads to current concentration, causing local overheating, accelerating the multiplication of dislocations and point defects, and thus causing a decrease in the luminous efficiency of the active region. Summary of the Invention

[0004] This application provides a vertical cavity surface-emitting laser and its fabrication method and chip, which aims to solve the problems of unreasonable current injection path, local overheating caused by current concentration, accelerated proliferation of dislocations and point defects caused by the traditional VIA hole along the crystal orientation of GaAs

[110] defects, which leads to the decay of the luminous efficiency of the active region. It has the advantages of suppressing defect generation from the source, realizing uniform current injection, and improving the luminous efficiency and reliability of the device.

[0005] In a first aspect, this application provides a vertical-cavity surface-emitting laser, comprising: Substrate; An N-type distributed Bragg reflector, an active region, a P-type distributed Bragg reflector, and a passivation layer are located on the substrate. Multiple vertical injection holes penetrate the passivation layer; the arrangement direction of the multiple vertical injection holes is at a non-parallel angle to the defect growth crystal direction of the substrate, so that the vertical injection holes do not fall on the defect growth crystal direction, thereby suppressing defect extension along the defect growth crystal direction.

[0006] In some embodiments, the substrate is a gallium arsenide substrate, the defect proliferation crystal orientation is the

[110] crystal orientation of the gallium arsenide substrate, and the non-parallel angle is 30° to 45°.

[0007] In some embodiments, the sidewalls of the vertical injection hole have a doping concentration that gradually increases from the outer surface to the inner surface along the hole wall thickness direction, and the gradually increasing doping concentration is used to guide the operating current to diffuse uniformly to the active region.

[0008] In some embodiments, the doping concentration is 1 × 10⁻⁶ from the outer surface to the inner surface. 18 cm-3 to 5×10 19 Gradual distribution of cm-3.

[0009] In some embodiments, the vertical injection holes are arranged in a hexagonal array, the diameter of the vertical injection holes is 8 to 12 μm, and the spacing between adjacent vertical injection holes is 30 to 40 μm.

[0010] In some embodiments, deep etching trenches are also included, the deep etching trenches comprising: An annular main trench is provided around the periphery of the active area; Multiple radial branch trenches, which are connected to the annular main trench and extend outward; The annular main trench and the radial branch trench are filled with a high thermal conductivity metal material.

[0011] In some embodiments, the high thermal conductivity metal material is a Cu-Ag alloy, wherein the Ag content is 4-8 wt%; the width of the annular main groove is 20-25 μm and the depth is 300-350 μm; the number of radial branch grooves is 12-16, and the width is 8-10 μm.

[0012] In some embodiments, the inner walls of the annular main trench and the radial branch trench are covered with an insulating layer, the insulating layer being SiNx with a thickness of 50–100 nm.

[0013] In some embodiments, an ion implantation passivation isolation region is also included, which is located between adjacent vertical implantation holes to isolate adjacent light-emitting holes and passivate interface defects.

[0014] In some embodiments, the passivation layer comprises a multilayer composite passivation film covering the sidewalls of the vertical injection hole and the device surface, comprising a multilayer structure formed by alternating stacking of at least two different materials, and subjected to mixed plasma hydrogenation treatment of H2 and Ar.

[0015] In some embodiments, the multilayer composite passivation film includes: The first composite layer comprises multiple sublayers formed by alternating stacking of AlN and GaN; The second composite layer, located above the first composite layer, comprises multiple sublayers formed by alternating stacking of SiNx, Al2O3 and Ta2O3; The first composite layer and the second composite layer together constitute a multilayer structure.

[0016] In some embodiments, the volume ratio of H2 to Ar in the H2 and Ar mixed plasma hydrogenation treatment is 3:1 to 5:1, the treatment power is 300 to 350 W, the treatment time is 10 to 15 min, and the pressure is 0.8 to 1.2 Pa.

[0017] In some embodiments, a stress buffer transition layer is disposed above the P-type distributed Bragg mirror; wherein the stress buffer transition layer comprises GaAs and AlGaAs superlattice structures with a period number of 15 to 20 and a single period thickness of 25 to 35 nm.

[0018] In some embodiments, the active region is a multi-cascaded quantum well structure, which includes multiple cascaded units, each of which includes multiple InGaAs well layers and at least one AlGaAs strain compensation layer.

[0019] In some embodiments, a patterned AlN heat sink is further included, which is bonded above the P-type distributed Bragg mirror; the patterned AlN heat sink has a light-transmitting window with a diameter of 12–18 μm.

[0020] In some embodiments, the vertical injection hole includes a stacked metal layer of Ti, Pt and Au, wherein the thickness of the Ti metal layer is 40-60 nm, the thickness of the Pt metal layer is 60-100 nm, and the thickness of the Au metal layer is 1.5-2.5 μm.

[0021] Secondly, this application also provides a method for fabricating a vertical-cavity surface-emitting laser, characterized by comprising: Provide a substrate; An N-type distributed Bragg mirror, an active region, a P-type distributed Bragg mirror, and a passivation layer are sequentially formed on the substrate. Multiple vertical injection holes are formed, the vertical injection holes penetrating the passivation layer; wherein, when forming the vertical injection holes, a photolithographic mask is used to make the line connecting each vertical injection hole to the center of the light-emitting hole form a non-parallel angle with the defect growth crystal direction of the substrate, so that all vertical injection holes do not fall on the extension line of the defect growth crystal direction, thereby suppressing defect extension along the defect growth crystal direction.

[0022] In some embodiments, the sidewalls of the vertical injection hole have a doping concentration that gradually increases from the outer surface to the inner surface along the hole wall thickness direction. This gradually increasing doping concentration guides the uniform diffusion of the operating current to the active region; the doping concentration from the outer surface to the inner surface is 1 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 The gradual distribution is achieved through multiple ion implantations.

[0023] In some embodiments, the step of forming deep etch trenches is further included, the formation of which includes: An annular main trench is formed by etching, and the annular main trench is arranged around the periphery of the active region; Etching forms multiple radial branch trenches, which are connected to the annular main trench and extend outward; The annular main trench and the radial branch trench are filled with a high thermal conductivity metal material.

[0024] In some embodiments, the step of forming a multilayer composite passivation film is also included, the multilayer composite passivation film covering the sidewalls of the vertical injection hole and the device surface, the multilayer composite passivation film comprising a multilayer structure formed by alternating stacking of at least two different materials, and the device undergoing hydrogenation treatment with a mixed plasma of H2 and Ar.

[0025] In some embodiments, after forming the P-type distributed Bragg reflector, a step of forming a stress buffer transition layer is further included; wherein the stress buffer transition layer comprises a GaAs and AlGaAs superlattice structure with a period number of 15 to 20 and a single period thickness of 25 to 35 nm. Thirdly, this application also provides a chip including a vertical-cavity surface-emitting laser as described in any of the first aspects.

[0026] Compared with the prior art, the beneficial effects of this application are as follows: This application addresses the problems of unreasonable current injection paths, localized overheating caused by current concentration, accelerated dislocation and point defect proliferation, and consequently, reduced luminous efficiency in the active region caused by the arrangement of traditional VIA holes along the GaAs

[110] defect proliferation crystal direction in the following manner: First, an N-type distributed Bragg reflector, an active region, a P-type distributed Bragg reflector, and a passivation layer are sequentially formed on the substrate; then, multiple vertical injection holes are formed, which penetrate the passivation layer and are distributed around the light-emitting holes, and the line connecting each vertical injection hole to the center of the light-emitting hole is at a non-parallel angle with the defect proliferation crystal direction (i.e., the

[110] crystal direction) of the substrate, so that all vertical injection holes do not fall on the extension line of the defect proliferation crystal direction, thereby suppressing defect extension along the defect proliferation crystal direction, spatially avoiding the direction in which defects are prone to propagate, and reducing defect proliferation caused by current injection. Through the above structural design, the generation of defects is suppressed from the source, significantly improving the luminous efficiency and reliability of the device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a top view of a vertical cavity surface-emitting laser provided in an embodiment of this application; Figure 2 This is a cross-sectional view of a vertical cavity surface-emitting laser provided in an embodiment of this application; Figure 3 This is one of the flowcharts for the fabrication method of a vertical-cavity surface-emitting laser provided in the embodiments of this application; Figure 4 This is the second flowchart of the fabrication method of the vertical cavity surface-emitting laser provided in the embodiments of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] A vertical-cavity surface-emitting laser (VCSEL) is a semiconductor laser that emits laser light vertically from the surface of a chip. Its working principle involves sequentially growing an N-type distributed Bragg mirror, an active region, and a P-type distributed Bragg mirror on a substrate, and then creating a vertical injection aperture (VIA). Injected current causes stimulated emission of light from the active region, generating laser light. This device is widely used in applications requiring high power, long lifespan, and resistance to harsh operating conditions, such as automotive lidar and extreme environment 3D sensing.

[0031] However, the existing technical solutions have three major problems: First, the traditional VIA holes are arranged along the defect growth crystal direction of GaAs

[110] , which leads to an unreasonable current injection path. The current concentration causes local overheating, which accelerates the growth of dislocations and point defects (that is, the extra energy provided by local overheating makes the existing dislocations and point defects in the crystal more likely to move, climb or generate new defects, resulting in an increase in defect density. These defects become non-radiative recombination centers, reducing luminous efficiency), causing the luminous efficiency of the active region to decay; Second, the heterogeneous interface (such as P-DBR (P-type distributed Bragg mirror) / AlN (aluminum nitride) heat sink, epitaxial layer / substrate) has a large difference in thermal expansion coefficient. The thermal cycle generates 2-3GPa stress, which lacks an active release structure and is prone to cracking or peeling; Third, the single plasma hydrogenation passivation effect is limited. It can only temporarily passivate defects. There is no subsequent protective layer. Defects are easy to regenerate under high power conditions, and water vapor and ion intrusion will accelerate passivation failure. These problems result in the continuous working life of existing devices being generally less than 10,000 hours and the defect state density being ≥5×10 15 cm -3 It cannot meet the long lifespan (≥15,000 hours) requirements of automotive and industrial applications.

[0032] Based on the above problems, this application provides a vertical cavity surface-emitting laser and its fabrication method and chip, which solves the above three problems through the following synergistic solutions: First, for the defect proliferation caused by unreasonable current injection path, an asymmetric crystal orientation VIA hole array (such as having an angle of 30° to 45° with the defect proliferation crystal orientation of GaAs

[110] ) is adopted and the hole wall gradient doping is set (such as the doping concentration gradually increases from the outer surface to the inner surface), guiding the current to diffuse uniformly to the active region, and suppressing the generation of defects from the source; Second, for the insufficient release of interface stress, deep etching composite trenches (such as an annular main trench wrapping the periphery of the active region and radial branch trenches being uniformly distributed) and filling with high thermal conductivity and toughness metal (the thermal expansion coefficient is between that of GaAs substrate and epitaxial layer) are used to actively buffer the tensile and compressive stress generated by thermal cycling, so that the interface stress is reduced from the traditional 2.5GPa to below 0.6GPa; Third, for the limited passivation effect, mixed plasma hydrogenation (such as H2 and Ar=4:1) combined with a double passivation layer (such as ALD (Atomic Layer)) is adopted. Atomic layer deposition (ALD) of an AlN / GaN composite layer and PECVD (Plasma Enhanced Chemical Vapor Deposition) of a SiNx / Al2O3 / Ta2O3 chip-level film achieve long-term passivation protection, preventing defect regeneration and water vapor ion intrusion. Therefore, these three processes form a closed-loop synergy across the entire chain of "suppressing defect generation - actively releasing stress - long-term passivation protection," significantly improving device luminous efficiency and reliability.

[0033] The present application will be described in detail below with reference to embodiments and accompanying drawings.

[0034] Please refer to Figure 1 , Figure 2 , Figure 1 This is a top view of a vertical-cavity surface-emitting laser provided in an embodiment of this application. Figure 2 This is a cross-sectional view of a vertical-cavity surface-emitting laser provided in an embodiment of this application. Specifically, Figure 1 This is a top view of the light-emitting unit array of this high-reliability vertical cavity surface-emitting laser. The seven light-emitting units are arranged in a hexagonal close-fitting arrangement, with star-shaped deep etched trenches with radial branches on the periphery. The light-emitting units are surrounded by a passivation layer (the passivation layer includes a multilayer composite passivation film), a vertical injection hole at a non-parallel angle to the crystal direction of substrate defect proliferation, and an annular P-plane ohmic contact layer. The arrangement maximizes the utilization of the effective area of ​​the substrate. Figure 2The longitudinal cross-sectional structure corresponding to this high-power vertical cavity surface-emitting laser consists of, from bottom to top, an N-side ohmic contact layer, a substrate, a buffer layer, and an N-type distributed Bragg mirror. Above the N-type distributed Bragg mirror, a multi-cascaded active region composed of multiple quantum wells and cascaded tunnel junctions, an oxide confinement layer with oxide holes, and a P-type distributed Bragg mirror are integrated in sequence. The device mesa sidewalls and the inner walls of the vertical injection holes are fully covered by passivation layers. The vertical injection holes are set through the passivation layers, and P-side electrode pads are led out from the top of the vertical injection holes. This structure solves the performance problems of traditional high-power VCSELs through multi-dimensional innovation: First, the vertical injection hole axis and the defect proliferation crystal direction of the GaAs substrate

[110] are set at a non-parallel angle of 30° to 45°, and the hole wall is gradually doped from the outside to the inside. This not only blocks the expansion path of dislocations along the crystal direction, but also realizes the uniform diffusion of the working current to the active region, avoiding local current overload. Second, a deep etched trench with a connecting radial branch trench and filled with a high thermal conductivity Cu-Ag alloy is set around the active region. Combined with the stress buffer transition layer of the GaAs / AlGaAs superlattice on the P-DBR side, the thermal mismatch stress at the heterostructure interface is reduced from the traditional 2.5GPa to below 0.6GPa. This significantly reduces the risk of thermal cycling cracking while further enhancing the device's lateral heat dissipation capability. Third, a multi-layer composite passivation film with alternating high and low temperature dielectrics is used. On the basis of plasma hydrogenation pretreatment to passivate the point defects in the active region, a dense water vapor and impurity barrier layer is constructed to avoid defect regeneration under high power conditions. Finally, a leapfrog improvement in the long-term working reliability of high-power VCSELs is achieved. For example, a vertical cavity surface-emitting laser includes: a substrate; an N-type distributed Bragg mirror, an active region, a P-type distributed Bragg mirror, and a passivation layer located on the substrate; a plurality of vertical injection holes penetrating the passivation layer and distributed around the emission holes; the line connecting the center of each vertical injection hole to the emission hole forms a non-parallel angle with the defect growth crystal direction of the substrate, such that all vertical injection holes do not fall on the extension line of the defect growth crystal direction, thereby suppressing defect extension along the defect growth crystal direction.

[0035] Preferably, the sidewall of the vertical injection hole has a doping concentration that gradually increases from the outer surface to the inner surface along the hole wall thickness direction, and the gradually increasing doping concentration is used to guide the working current to diffuse uniformly to the active region.

[0036] Traditional VIA holes are arranged along the

[110] defect growth direction of the GaAs substrate, which leads to current concentration and local overheating, accelerating the growth of dislocations and point defects, and thus reducing the luminous efficiency of the active region. This application sets the arrangement direction of multiple vertical injection holes to be at a non-parallel angle with the defect growth direction, thereby avoiding the direction in which defects are easy to propagate in space and reducing defect growth caused by current injection; at the same time, it uses gradient doped sidewalls to guide the uniform diffusion of current, avoiding excessively high local current density and reducing the generation of defects induced by heat accumulation, thereby suppressing defect generation from the source and improving the long-term reliability of the device.

[0037] Preferably, the substrate is a gallium arsenide (GaAs) substrate, the defect growth crystal orientation is the

[110] crystal orientation of the gallium arsenide substrate, and the non-parallel angle is 30° to 45°.

[0038] Since the

[110] crystal orientation of gallium arsenide substrates is the direction in which dislocations and point defects are prone to multiply and expand, the conventional VIA holes arranged along this crystal orientation will exacerbate defect growth. Arranging multiple vertically implanted holes at an angle of 30° to 45° to the

[110] crystal orientation (e.g., 35° in the specific embodiment) can spatially avoid the defect-prone expansion direction, reduce defect growth caused by current injection, thereby suppressing the decay of the active region's luminous efficiency and improving the long-term reliability of the device. During the fabrication process, a dedicated photolithography mask (e.g., at a 35° angle to the

[110] crystal orientation) is used, and ICP etching is employed to form hexagonally arranged VIA holes (e.g., 10 μm aperture, 35 μm spacing). Subsequently, Si is achieved through multiple ion implantations. 0.2 Ge 0.8 Gradient doping is performed, followed by sequential deposition of Ti (50nm) / Pt (80nm) / Au (2μm) using electron beam evaporation to fill the voids, achieving a filling rate of 99.9%, thereby forming a complete asymmetric VIA pore structure.

[0039] Optionally, the doping concentration from the outer surface to the inner surface is 1 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 The gradient doping distribution, achieved by gradually increasing the doping concentration on the hole walls from the outside to the inside, guides the operating current to diffuse uniformly from the outside of the hole walls to the active region, avoiding excessively high local current density (e.g., deviation ≤ ±3%), reducing the generation of defects induced by thermal accumulation, thereby improving current injection uniformity and device stability.

[0040] For example, the vertical injection holes are arranged in a hexagonal array, with a diameter of 8–12 μm and a spacing of 30–40 μm between adjacent vertical injection holes. The hexagonal array arrangement achieves the highest space fill density. Combined with optimized hole diameter and spacing (e.g., 10 μm diameter and 35 μm spacing in a specific embodiment), it avoids thermal crosstalk between holes while ensuring sufficient current injection area, and promotes uniformity in subsequent gradient doping and metal filling processes, thereby improving device power density and reliability.

[0041] Preferably, the vertical cavity surface-emitting laser further includes deep etching trenches, which include: an annular main trench surrounding the periphery of the active region; and multiple radial branch trenches communicating with the annular main trench and extending outward; wherein the annular main trench and the radial branch trenches are filled with a high thermal conductivity metal material.

[0042] Specifically, a heterojunction refers to the contact interface between two different semiconductor materials (such as GaAs and AlN, or epitaxial layers and substrates with different compositions). Due to the differences in lattice constants and coefficients of thermal expansion, this interface is prone to stress during thermal cycling, making it a critical area affecting device reliability. Heterogeneous interfaces (such as P-DBR and AlN heat sinks, epitaxial layers and substrates) can generate stresses of 2–3 GPa during thermal cycling due to differences in their coefficients of thermal expansion, easily leading to cracking or delamination. By deeply etching to form annular main trenches and radial branch trenches, the stress release area can be maximized. At the same time, filling with a high thermal conductivity metal material (such as Cu-Ag alloy) can actively buffer the tensile and compressive stresses generated by thermal cycling and quickly dissipate heat, reducing the interface stress from the traditional 2.5 GPa to below 0.6 GPa, significantly improving the device's resistance to thermal fatigue.

[0043] Optionally, the high thermal conductivity metal material is a Cu-Ag alloy, wherein the Ag content is 4-8 wt%; the width of the annular main groove is 20-25 μm and the depth is 300-350 μm; the number of radial branch grooves is 12-16, and the width is 8-10 μm.

[0044] Specifically, the coefficient of thermal expansion of the Cu-Ag alloy is between that of the GaAs substrate and the epitaxial layer, which can effectively match thermal stress; the Ag content is controlled at 4-8 wt% (e.g., 6 wt% in the specific embodiment) to balance thermal conductivity and mechanical strength. The trench width of 20-25 μm and the depth of 300-350 μm (e.g., 22 μm width and 320 μm depth in the specific embodiment) can ensure sufficient stress release without damaging the device structure; the uniform distribution of 12-16 radial branch trenches (e.g., 14) can further disperse stress concentration points and improve the overall stress release efficiency. In the specific process, DRIE (deep reactive ion etching) is used to form an annular main trench (e.g., 22 μm wide, 320 μm deep, and 400 μm substrate thickness) and 14 radial branch trenches (e.g., 9 μm wide). Then, a 70 nm thick SiNx insulating layer is deposited on the inner wall of the annular main trench and the radial branch trenches. Next, a Cu-Ag alloy (e.g., 6 wt% Ag content) is sputtered and filled into the trenches using a hot-pressing filling process (e.g., 290 °C, 7 MPa). Finally, the surface roughness is ground to 0.2 nm, thus completely realizing the fabrication of the stress-relieving structure.

[0045] For example, the inner walls of the annular main trench and the radial branch trench are covered with an insulating layer, which is SiNx and has a thickness of 50-100 nm.

[0046] Preferably, it further includes an ion implantation passivation isolation region, which is located between adjacent vertical implantation holes and is used to isolate adjacent light-emitting holes and passivate interface defects.

[0047] Specifically, depositing an insulating layer (such as SiNx with a thickness of 70nm) on the inner wall of the trench before filling with a high thermal conductivity metal can prevent the metal from directly contacting the semiconductor material, which could lead to leakage or short circuit. At the same time, the insulating layer itself also plays a certain role in stress buffering, ensuring that the filling metal only performs the functions of thermal conduction and stress relief without affecting the electrical properties.

[0048] Preferably, the passivation layer comprises a multilayer composite passivation film, which covers the sidewall of the vertical injection hole and the device surface, comprising a multilayer structure formed by alternating stacking of at least two different materials, and is subjected to mixed plasma hydrogenation treatment of H2 and Ar.

[0049] Specifically, single passivation layers are prone to failure under high-power conditions, and moisture and ion intrusion accelerate passivation failure. Using multilayer composite passivation films (e.g., AlN / GaN composite layers combined with SiNx, Al2O3, and Ta2O3 composite layers) can form a dense protective barrier. Simultaneously, hydrogenation treatment with a mixed H2 and Ar plasma (e.g., H2:Ar = 4:1) can penetrate deep into quantum well passivation point defects and dislocations, improving passivation efficiency by 40% compared to single H2 hydrogenation. This achieves long-term defect passivation, prevents defect regeneration, and extends device lifespan.

[0050] Optionally, the multilayer composite passivation film includes: a first composite layer comprising multiple sublayers formed by alternating stacking of AlN and GaN; and a second composite layer located above the first composite layer comprising multiple sublayers formed by alternating stacking of SiNx, Al2O3, and Ta2O3; wherein the first composite layer and the second composite layer together constitute a multilayer structure.

[0051] Specifically, the first composite layer of AlN / GaN alternating stacks (e.g., ALD deposition of 120 nm) The first composite layer (AlN / 60nm GaN, total thickness 180nm) possesses high dielectric strength and good interface matching, effectively passivating dangling bonds on the VIA via sidewalls and device surface. The total thickness of this first composite layer is 150–200nm. The second composite layer (e.g., PECVD-deposited 180nm SiNx / 120nm Al2O3 / 60nm Ta2O3, total thickness 360nm) provides stronger moisture barrier and ion shielding capabilities, with a total thickness of 300–400nm. The synergistic effect of these two layers achieves both deep passivation and long-term protection, meeting the reliability requirements of high-power, harsh environments.

[0052] For example, in the H2 and Ar mixed plasma hydrogenation treatment, the volume ratio of H2 to Ar is 3:1 to 5:1, the treatment power is 300 to 350 W, the treatment time is 10 to 15 min, and the pressure is 0.8 to 1.2 Pa.

[0053] For example, a volume ratio of H2 to Ar of 4:1, a power of 320W, a time of 12min, and a pressure of 1.0Pa can generate high-density active hydrogen atoms. At the same time, the physical bombardment of Ar ions helps to clean the surface and promotes the diffusion of hydrogen atoms into the quantum well region, thereby efficiently passivating point defects and dislocations, improving the passivation depth and uniformity, and avoiding damage to the epitaxial layer by excessive power or long processing time.

[0054] Preferably, a stress buffer transition layer is disposed above the P-type distributed Bragg reflector; wherein the stress buffer transition layer comprises GaAs and AlGaAs superlattice structures, with a period number of 15 to 20 and a single period thickness of 25 to 35 nm.

[0055] Specifically, the P-DBR (P-type distributed Bragg reflector) and the active region experience significant stress due to differences in lattice constant and thermal expansion coefficient, which can easily lead to interface defects and decreased luminous efficiency. Using a GaAs / AlGaAs superlattice as a stress buffer transition layer (e.g., a period thickness of 30 nm and 18 layers) can release interface stress layer by layer. Simultaneously, the superlattice structure itself possesses high thermal stability, preventing stress concentration-induced cracking. Combined with deep etching trenches, the overall stress level is reduced to below 0.6 GPa.

[0056] Optionally, the active region is a multi-cascaded quantum well structure, which includes multiple cascaded units, each of which includes multiple InGaAs well layers and at least one AlGaAs strain compensation layer.

[0057] For example, 38 pairs of Al3+ ions were grown on an N-type GaAs substrate using metal-organic chemical vapor deposition (MOCVD). 0.9 G 0.1 As / Al 0.3 Ga 0.7 An N-type distributed Bragg reflector (N-DBR) composed of As, and a multi-cascaded quantum well structure (e.g., 6 cascaded units, each cascaded unit including 3 In). 0.3 Ga 0.7 As well layer (8nm thick) and 1 Al 0.15 Ga 0.85 An As strain-compensated layer (5.5 nm thick) can significantly improve gain and optical output power. Simultaneously, by balancing the compressive strain generated in the well layer through the strain-compensated layer, it avoids defect proliferation caused by lattice mismatch, thus ensuring device reliability while improving power. Based on this, further hydrogenation treatment using a mixed H2 and Ar plasma (320 W power, 12 min time, 1.0 Pa pressure) was performed to grow 25 Al pairs. 0.85 Ga 0.15 As / Al 0.25 Ga 0.75 As P-DBR (P-type distributed Bragg mirror) and a 180nm GaAs / AlGaAs superlattice stress buffer transition layer (30nm period, 18 layers) form a complete epitaxial structure.

[0058] For example, the vertical cavity surface-emitting laser further includes a patterned AlN heat sink bonded above the P-type distributed Bragg mirror; the patterned AlN heat sink has a light-transmitting window with a diameter of 12–18 μm.

[0059] Specifically, AlN heat sinks have high thermal conductivity (e.g., about 170 W / m·K), which can quickly dissipate the heat generated by the device and reduce the junction temperature; the patterned design (e.g., a light-transmitting window with a diameter of 15 μm) can ensure that the laser light output path is unobstructed, and the bonding between the heat sink and P-DBR can also provide mechanical support, reduce the impact of thermal stress on the device, and improve the reliability of high-power continuous operation.

[0060] Preferably, the vertical injection hole includes a stacked metal layer of Ti, Pt and Au, i.e., a vertical injection hole metal layer, wherein the thickness of the Ti metal layer is 40-60 nm, the thickness of the Pt metal layer is 60-100 nm, and the thickness of the Au metal layer is 1.5-2.5 μm.

[0061] Specifically, the Ti metal layer (50 nm thick) serves as both an adhesion layer and an ohmic contact layer, enabling low-resistance contact with p-type GaAs; the Pt metal layer (80 nm thick) acts as a diffusion barrier layer, preventing Au from diffusing into the semiconductor and causing failure; and the Au metal layer (2 μm thick) serves as a conductive and thermally conductive substrate with a high fill rate (99.9%), ensuring uniform current injection and low thermal resistance. This three-layer metal stack structure achieves a specific contact resistance ≤2 × 10⁻⁶. -6 Ω·cm 2 At the same time, in conjunction with the gradient-doped sidewalls, it guides the uniform diffusion of current, avoids local overheating, and improves device power and lifespan.

[0062] In summary, this application constructs a full-link synergistic scheme of "suppressing defect generation - actively releasing stress - long-term passivation protection". Specifically, it arranges multiple vertical injection holes at a non-parallel angle (e.g., 30° to 45°) to the

[110] defect growth crystal direction of the GaAs substrate, and designs sidewalls with gradually increasing doping concentration from the outside to the inside (e.g., 1×10⁻⁶). 18 cm -3 →5×10 19 cm -3 The process involves guiding the current to diffuse uniformly, suppressing defect proliferation at its source. Simultaneously, annular main trenches and radial branch trenches are etched on the substrate and filled with a Cu-Ag alloy (with an Ag content of 4–8 wt%) whose thermal expansion coefficient is between that of GaAs and the epitaxial layer, actively buffering thermal cycling stress and reducing interface stress to below 0.6 GPa. Furthermore, a combination of H2 and Ar mixed plasma hydrogenation treatment and dual passivation layers (such as an AlN / GaN composite layer deposited by ALD and a SiNx / Al2O3 / Ta2O3 chip-level film deposited by PECVD) achieves long-term passivation and protection against defects. The synergistic effect of these three methods significantly improves the high-power output capability and long-term reliability of the VCSEL, meeting the demanding requirements of ≥15,000 hours for applications such as automotive LiDAR.

[0063] The fabrication method of the vertical-cavity surface-emitting laser provided in this application is described below. The fabrication method of the vertical-cavity surface-emitting laser described below can be referred to in correspondence with the vertical-cavity surface-emitting laser described above.

[0064] Please refer to Figure 3 , Figure 3 This is one of the flowcharts illustrating a method for fabricating a vertical-cavity surface-emitting laser (VCSEL) according to an embodiment of this application. A method for fabricating a VCSEL includes: S301 provides a substrate; S302, an N-type distributed Bragg mirror, an active region, a P-type distributed Bragg mirror, and a passivation layer are formed on the substrate; S303, a plurality of vertical injection holes are formed in the P-type distributed Bragg mirror, the vertical injection holes penetrating the passivation layer and distributed around the light-emitting holes; wherein, when forming the vertical injection holes, a photolithographic mask is used to make the line connecting each vertical injection hole to the center of the light-emitting hole form a non-parallel angle with the defect growth crystal direction of the substrate, so that all vertical injection holes do not fall on the extension line of the defect growth crystal direction, thereby suppressing defect extension along the defect growth crystal direction; S304, a doping concentration that gradually increases from the outer surface to the inner surface along the thickness direction of the hole wall is formed on the sidewall of the vertical injection hole, and the gradually increasing doping concentration is used to guide the working current to diffuse uniformly to the active region.

[0065] Specifically, traditional VIA holes are arranged along the defect growth crystal direction of the GaAs substrate

[110] , which leads to current concentration causing local overheating, accelerating the growth of dislocations and point defects, and thus causing the luminous efficiency of the active region to decrease and the device reliability to decline. This application avoids the direction in which defects are easily propagated by spatially avoiding the arrangement direction of multiple vertical injection holes at a non-parallel angle (e.g., 30° to 45°) with the defect growth crystal direction, thereby reducing the defect growth caused by current injection; at the same time, a doping concentration (e.g., 1×10⁻⁶) is formed on the sidewall of the vertical injection holes, which gradually increases from the outer surface to the inner surface. 18 cm -3 →5×10 19 cm -3 This guides the operating current to diffuse evenly throughout the active region, preventing excessively high local current density and reducing heat-induced defects. The combined effect of these two mechanisms suppresses defect generation at its source, significantly improving the long-term reliability of VCSELs and meeting the requirements of applications such as automotive LiDAR with a lifespan of ≥15,000 hours.

[0066] In some embodiments, the doping concentration is 1 × 10⁻⁶ from the outer surface to the inner surface. 18 cm -3 Up to 5×10 19 cm-3 The gradual distribution is achieved through multiple ion implantations.

[0067] Specifically, the sidewall doping concentration of the vertical implantation hole gradually varies from the outer surface (the side closer to the P-DBR) to the inner surface (the side closer to the active region), ranging from 1 × 10⁻⁶. 18 cm -3 Gradually increase to 5×10 19 cm -3 This gradient doping is achieved through multiple ion implantation processes. Its purpose is to guide the uniform diffusion of the operating current to the active region, avoiding excessively high local current densities (e.g., deviation ≤ ±3%). This is achieved through gradient doping sidewall design, ensuring a highly uniform current distribution during implantation in the active region, with the actual current density in each region deviating from the design average within ±3%, thus preventing overheating and defect proliferation caused by excessive local current density. This reduces heat-induced defect generation, suppresses defect proliferation, and improves device reliability. The reason for using multiple ion implantations is that a single ion implantation is insufficient to create a continuous, gradual concentration distribution from low to high, and high-concentration implantation easily causes lattice damage. Multiple ion implantations allow for individual adjustment of the energy, dose, and angle of each implantation, gradually constructing a precise concentration gradient while controlling the degree of damage, ensuring doping uniformity and sidewall integrity.

[0068] In some embodiments, the method further includes the step of forming deep etching trenches, the formation of which includes: etching to form an annular main trench, the annular main trench being disposed around the periphery of the active region; etching to form a plurality of radial branch trenches, the plurality of radial branch trenches being connected to the annular main trench and extending outward; and filling the annular main trench and the radial branch trenches with a high thermal conductivity metal material.

[0069] Specifically, heterogeneous interfaces (such as P-DBR / AlN heat sinks and epitaxial layers / substrates) generate stresses as high as 2-3 GPa during thermal cycling due to differences in thermal expansion coefficients, leading to cracking and delamination, which severely affects device reliability. This application addresses this by etching an annular main trench surrounding the active region and multiple radial branch trenches connected to it, maximizing the stress release area. Furthermore, it fills the trench with a high thermal conductivity metal material (such as Cu-Ag alloy) with a thermal expansion coefficient between the GaAs substrate and the epitaxial layer, actively buffering the tensile and compressive stresses generated during thermal cycling. This reduces the interface stress from the traditional 2.5 GPa to below 0.6 GPa, effectively preventing stress-induced structural failures and significantly improving the long-term reliability of VCSELs.

[0070] In some embodiments, the step of forming a multilayer composite passivation film is also included, the multilayer composite passivation film covering the sidewalls of the vertical injection hole and the device surface, the multilayer composite passivation film comprising a multilayer structure formed by alternating stacking of at least two different materials, and the device undergoing hydrogenation treatment with a mixed plasma of H2 and Ar.

[0071] Specifically, since single plasma hydrogenation can only temporarily passivate defects without a subsequent protective layer, defects are prone to regeneration under high-power conditions, and moisture and ion intrusion accelerate passivation failure. This application utilizes H2 and Ar mixed plasma hydrogenation treatment (passivation efficiency is 40% higher than that of single H2) to deeply passivate defects and dislocations in the quantum well. Combined with multilayer composite passivation films (such as alternating stacks of AlN / GaN composite layers deposited by ALD and SiNx / Al2O3 / Ta2O3 chip-level films deposited by PECVD), a physical barrier is formed to block moisture and ion intrusion, achieving long-term passivation and protection of defects, preventing defect regeneration under high power, and thus significantly improving the long-term reliability of VCSELs.

[0072] In some embodiments, after forming the P-type distributed Bragg mirror, a step of forming a stress buffer transition layer is further included; wherein the stress buffer transition layer comprises a GaAs and AlGaAs superlattice structure with a period number of 15 to 20 and a single period thickness of 25 to 35 nm.

[0073] Specifically, the interface stress of up to 2-3 GPa between the P-DBR and subsequent structures (such as heat sinks or substrates) due to the difference in thermal expansion coefficients can easily lead to cracking or delamination, affecting device reliability. This application addresses this issue by forming a GaAs / AlGaAs superlattice stress buffer transition layer (15-20 cycles, 25-35 nm thickness per cycle). The multi-interface structure of the superlattice gradually transitions thermal stress, effectively mitigating the thermal mismatch between the P-DBR and subsequent layers. Combined with active stress-relieving structures such as deep etched trenches and tough metal filling, the interface stress is reduced from the traditional 2.5 GPa to below 0.6 GPa, significantly improving the long-term reliability of VCSELs.

[0074] Please refer to Figure 4 , Figure 4 This is the second flowchart of a method for fabricating a vertical-cavity surface-emitting laser (VCSEL) according to an embodiment of this application. A method for fabricating a VCSEL includes: S401 provides the substrate.

[0075] Specifically, an N-type GaAs substrate is selected, whose

[110] crystal orientation is the direction in which defects are prone to multiply.

[0076] S402, epitaxial growth.

[0077] Specifically, N-type distributed Bragg mirrors (such as 38 pairs of Al) are sequentially grown on the substrate by MOCVD (MOCVD). 0.9 G 0.1 As / Al 0.3 Ga 0.7 As), multi-cascaded quantum well active regions (e.g., 6 cascaded units, each containing 3 InGaAs well layers and 1 AlGaAs strain-compensated layer), P-type distributed Bragg mirrors (e.g., 25 pairs of AlGaAs well layers), and P-type distributed Bragg mirrors (e.g., 25 pairs of AlGaAs well layers). 0.85 Ga 0.15 As / Al 0.25 Ga 0.75 As), and a stress buffer transition layer of GaAs / AlGaAs superlattice (period 15-20, single period 25-35nm) is grown on top of P-DBR.

[0078] S403 forms a vertical injection hole.

[0079] Specifically, a photolithographic mask is used to make the hole axis form an angle of 30° to 45° with the

[110] crystal orientation (e.g., 35°), and ICP (Inductively Coupled Plasma Etching, used for high-precision etching of VIA holes) is used to form a hexagonal array of VIA holes (e.g., hole diameter 8 to 12 μm, hole spacing 30 to 40 μm); the sidewall doping concentration is gradually changed from the outer surface to the inner surface through multiple ion implantations (e.g., 1 × 10⁻⁶). 18 cm -3 →5×10 19 cm -3 Ti / Pt / Au filler is then evaporated by electron beam (e.g., filler content ≥ 99.9%).

[0080] S404 forms deep etched grooves.

[0081] Specifically, DRIE (Deep Reactive Ion Etching, used for the fabrication of deep etching trenches (annular main trench and radial branch trenches)) etches annular main trench (e.g., width 20-25 μm, depth 300-350 μm) surrounding the active region and 12-16 radial branch trenches (e.g., width 8-10 μm) connected to it, deposits a SiNx insulating layer (e.g., 50-100 nm), then sputters and fills it with Cu-Ag alloy (e.g., Ag content 4-8 wt%), hot-presses and grinds it to a surface roughness ≤0.2 nm.

[0082] S405 forms a passivation layer.

[0083] Specifically, the passivation layer includes a multilayer composite passivation film. The formation process of the multilayer composite passivation film includes: first, H2 and Ar mixed plasma hydrogenation treatment (e.g., H2:Ar volume ratio 3:1 to 5:1, power 300 to 350W, time 10 to 15min), then ALD (Atomic Layer Deposition) to deposit an AlN (aluminum nitride) and GaN (aluminum nitride) composite layer (e.g., 120nm / 60nm), and finally PECVD (Plasma Enhanced Chemical Vapor Deposition) to deposit a SiNx / Al2O3 / Ta2O3 chip-level passivation film (e.g., 180nm / 120nm / 60nm).

[0084] S406, bonding heat sink and electrode preparation.

[0085] Specifically, after completing the epitaxial growth, vertical injection hole preparation, deep etching trench, and multilayer composite passivation film preparation, the patterned AlN heat sink (e.g., 160 μm thick, 15 μm transparent window diameter) is fixed to the substrate using a hot-press bonding process (temperature 290℃, pressure 7 MPa). Figure 2 Above the P-type distributed Bragg reflector, a structure is used for efficient heat dissipation and mechanical support. Subsequently, electron beam evaporation technology is employed to deposit... Figure 1 The P-side ohmic contact layer, and Figure 2 Ti / Pt / Au P-type electrode corresponding to the P-side electrode pad (i.e. Figure 2 A vertically injected hole metal layer (three layers with thicknesses of, for example, 50 nm / 80 nm / 2 μm) was simultaneously fabricated. Figure 2 The N-side ohmic contact layer corresponds to Ti / Al / Ni / Au N-type electrodes (e.g., thicknesses of 20nm / 100nm / 40nm / 60nm respectively), and is annealed at 430°C for 40 seconds in a nitrogen atmosphere to form a low-resistance ohmic contact between the electrode and the semiconductor (the specific contact resistance of the P-type electrode is ≤2×10⁻⁶). -6 (Ω·cm²). This application aligns the light-transmitting window of the patterned AlN heat sink with... Figure 2 The active region (including multi-cascaded quantum well structures) ensures a smooth laser output path; in the multi-layer structure of the electrode material, Ti acts as an adhesion layer, Pt / Au blocks diffusion, and Al / Ni / Au reduces contact resistance, thus synergistically optimizing the electrical performance and thermal stability of the device.

[0086] This application also provides a chip, which includes the vertical cavity surface-emitting laser described in any of the above embodiments.

[0087] Specifically, by integrating the aforementioned vertical-cavity surface-emitting laser (VCSEL) structure, the chip can solve the problem of rapid performance degradation and drastic lifespan reduction caused by dislocation multiplication, thermal stress cracking, current congestion, and passivation layer failure in traditional high-power VCSEL chips under long-term high-current-density operation. This application utilizes the non-parallel angle (e.g., 30°~45°) between the vertical injection hole and the substrate defect multiplication crystal orientation, combined with sidewall gradient doping, to effectively block dislocation slip paths and achieve uniform current diffusion, avoiding localized overheating. Through the synergistic effect of deep etching trenches (e.g., annular main trenches and radial branch trenches filled with Cu-Ag alloy) and the GaAs / AlGaAs superlattice stress buffer transition layer, the thermal mismatch stress at the heterostructure interface is reduced to below 0.6 GPa, significantly suppressing thermal cycling cracking. Combined with H2 and Ar mixed plasma hydrogenation pretreatment and multilayer composite passivation films (e.g., alternating stacking of AlN / GaN and SiNx / Al2O3 / Ta2O3), long-term defect passivation and dense protection are achieved, preventing defect regeneration under high-power conditions. Ultimately, this enables the chip to possess high power output, ultra-low thermal resistance, and long-term reliability, making it suitable for demanding applications such as lidar, 3D sensing, and optical communication.

[0088] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A vertical-cavity surface-emitting laser, characterized in that, include: Substrate; An N-type distributed Bragg reflector, an active region, a P-type distributed Bragg reflector, and a passivation layer are located on the substrate. Multiple vertical injection holes penetrate the passivation layer and are distributed around the light-emitting holes; the line connecting each vertical injection hole to the center of the light-emitting hole forms a non-parallel angle with the defect growth crystal direction of the substrate, so that all vertical injection holes do not fall on the extension line of the defect growth crystal direction, thereby suppressing defect extension along the defect growth crystal direction.

2. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The substrate is a gallium arsenide substrate, the defect growth crystal orientation is the [110] crystal orientation of the gallium arsenide substrate, and the non-parallel included angle is 30° to 45°.

3. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The sidewall of the vertical injection hole has a doping concentration that gradually increases from the outer surface to the inner surface along the hole wall thickness direction. The gradually increasing doping concentration is used to guide the working current to diffuse uniformly to the active region.

4. The vertical-cavity surface-emitting laser according to claim 3, characterized in that, The doping concentration from the outer surface to the inner surface is 1×10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 The gradual distribution.

5. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The vertical injection holes are arranged in a hexagonal array, with a diameter of 8–12 μm and a spacing of 30–40 μm between adjacent vertical injection holes.

6. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, It also includes deep etching trenches, which include: An annular main trench is provided around the periphery of the active area; Multiple radial branch trenches, which are connected to the annular main trench and extend outward; The annular main trench and the radial branch trench are filled with a high thermal conductivity metal material.

7. The vertical-cavity surface-emitting laser according to claim 6, characterized in that, The high thermal conductivity metal material is a Cu-Ag alloy, wherein the Ag content is 4-8 wt%; the width of the annular main groove is 20-25 μm and the depth is 300-350 μm; the number of radial branch grooves is 12-16, and the width is 8-10 μm.

8. The vertical-cavity surface-emitting laser according to claim 6, characterized in that, The inner walls of the annular main trench and the radial branch trench are covered with an insulating layer, which is SiNx and has a thickness of 50-100 nm.

9. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, It also includes an ion implantation passivation isolation region, which is located between adjacent vertical implantation holes and is used to isolate adjacent light-emitting holes and passivate interface defects.

10. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The passivation layer comprises a multilayer composite passivation film, which covers the sidewalls of the vertical injection hole and the device surface. The multilayer composite passivation film comprises a multilayer structure formed by alternating stacking of at least two different materials and is subjected to mixed plasma hydrogenation treatment of H2 and Ar.

11. The vertical-cavity surface-emitting laser according to claim 10, characterized in that, The multilayer composite passivation film includes: The first composite layer comprises multiple sublayers formed by alternating stacking of AlN and GaN; The second composite layer, located above the first composite layer, comprises multiple sublayers formed by alternating stacking of SiNx, Al2O3 and Ta2O3; The first composite layer and the second composite layer together constitute a multilayer structure.

12. The vertical-cavity surface-emitting laser according to claim 10, characterized in that, In the H2 and Ar mixed plasma hydrogenation treatment, the volume ratio of H2 to Ar is 3:1 to 5:1, the treatment power is 300 to 350 W, the treatment time is 10 to 15 min, and the pressure is 0.8 to 1.2 Pa.

13. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, A stress buffer transition layer is disposed above the P-type distributed Bragg reflector; wherein the stress buffer transition layer comprises GaAs and AlGaAs superlattice structures, with a period number of 15 to 20 and a single period thickness of 25 to 35 nm.

14. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The active region is a multi-cascaded quantum well structure, which includes multiple cascaded units. Each cascaded unit includes multiple InGaAs well layers and at least one AlGaAs strain compensation layer.

15. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, It also includes a patterned AlN heat sink, which is bonded above the P-type distributed Bragg mirror; the patterned AlN heat sink has a light-transmitting window with a diameter of 12-18 μm.

16. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The vertical injection hole includes stacked metal layers of Ti, Pt, and Au, wherein the thickness of the Ti metal layer is 40–60 nm, the thickness of the Pt metal layer is 60–100 nm, and the thickness of the Au metal layer is 1.5–2.5 μm.

17. A method for fabricating a vertical-cavity surface-emitting laser, characterized in that, include: Provide a substrate; An N-type distributed Bragg mirror, an active region, a P-type distributed Bragg mirror, and a passivation layer are sequentially formed on the substrate. Multiple vertical injection holes are formed, which penetrate the passivation layer and are distributed around the light-emitting hole. When forming the vertical injection holes, a photolithographic mask is used to make the line connecting each vertical injection hole to the center of the light-emitting hole form a non-parallel angle with the defect growth crystal direction of the substrate, so that all vertical injection holes do not fall on the extension line of the defect growth crystal direction, thereby suppressing defect extension along the defect growth crystal direction.

18. The method for fabricating a vertical-cavity surface-emitting laser according to claim 17, characterized in that, The sidewalls of the vertical injection hole have a doping concentration that gradually increases from the outer surface to the inner surface along the hole wall thickness direction. This gradually increasing doping concentration guides the uniform diffusion of the operating current to the active region. The doping concentration from the outer surface to the inner surface is 1 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 The gradual distribution is achieved through multiple ion implantations.

19. The method for fabricating a vertical-cavity surface-emitting laser according to claim 17, characterized in that, It also includes the step of forming deep etch trenches, the formation of which includes: An annular main trench is formed by etching, and the annular main trench is arranged around the periphery of the active region; Etching forms multiple radial branch trenches, which are connected to the annular main trench and extend outward; The annular main trench and the radial branch trench are filled with a high thermal conductivity metal material.

20. The method for fabricating a vertical-cavity surface-emitting laser according to claim 17, characterized in that, It also includes the step of forming a multilayer composite passivation film, which covers the sidewall of the vertical injection hole and the surface of the device. The multilayer composite passivation film comprises a multilayer structure formed by alternating stacking of at least two different materials, and the device is subjected to hydrogenation treatment by a mixed plasma of H2 and Ar.

21. The method for fabricating a vertical-cavity surface-emitting laser according to claim 17, characterized in that, After forming the P-type distributed Bragg reflector, the process further includes forming a stress buffer transition layer; wherein the stress buffer transition layer comprises a GaAs and AlGaAs superlattice structure with a period number of 15 to 20 and a single period thickness of 25 to 35 nm.

22. A chip, characterized in that, Includes the vertical cavity surface-emitting laser according to any one of claims 1 to 16.

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