An overcurrent protection circuit with configurable overcurrent threshold

Abstract

The present application belongs to the technical field of integrated circuits, and particularly relates to an over-current protection circuit with configurable over-current threshold. The circuit of the present application comprises a reference circuit, an LDO circuit, an over-current threshold generation circuit, a high-side over-current comparator circuit and a low-side over-current comparator circuit, wherein the reference circuit is used to provide a reference voltage which does not change with temperature; the LDO circuit is used to convert the reference voltage into an LDO voltage, and generate an input reference voltage after voltage division by a resistor; the over-current threshold generation circuit is used to provide configurable over-current threshold voltage for the high-side over-current comparator circuit and the low-side over-current comparator circuit according to the input reference voltage; the high-side over-current comparator circuit is used to output a high-side over-current logic signal; and the low-side over-current comparator circuit is used to output a low-side over-current logic signal. The circuit of the present application has small structure error and high accuracy, and can well protect the chip from damage of the chip power tube under large current at high and low temperatures.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an overcurrent protection circuit with a configurable overcurrent threshold. Background Technology

[0002] As consumer electronics, smart homes, and automotive micro-motor devices evolve towards miniaturization, integration, and reliability, integrated motor driver chips are gradually replacing traditional drive circuits built from discrete components. These chips highly integrate logic control units, charge pump units, motor drive units, current sampling units, and basic protection circuits, offering advantages such as fewer external components, strong adaptability, and high mass production consistency. They are widely used in stepper motors, three-phase motors, and DC motors. However, in actual motor operation, various situations arise, including motor stall, rotor jamming, sudden load changes, output pin short circuits, PCB trace soldering issues, and instantaneous current oscillations under high-frequency PWM drive. These conditions can easily generate excessive current, leading to overheating and breakdown of power MOSFETs, circuit burnout, and even complete equipment failure. Therefore, overcurrent protection performance is a core indicator determining the lifespan and operational stability of the driver chip.

[0003] The overcurrent protection mechanisms built into existing mainstream motor drive chips still have significant technical flaws. Currently, most industry-standard protection architectures use fixed overcurrent thresholds for detection. These threshold parameters are factory-fixed and cannot be dynamically adapted to different motor operating conditions. If the threshold is too low, it can easily trigger false protection for peak currents during normal motor startup, causing motor stalling or abnormal start-stop. If the threshold is set too high, it cannot promptly identify minor overload faults, and the long-term accumulation of abnormal current will accelerate chip aging, posing a potential risk of protection failure.

[0004] In addition, existing on-chip overcurrent detection circuits suffer from poor temperature characteristics and significant temperature drift. During motor operation, the power transistors continuously heat up as they switch, causing the chip junction temperature to vary widely depending on the load conditions and ambient temperature. The sampling accuracy and reference voltage of traditional overcurrent protection circuits are easily affected by temperature, leading to deviations in the overcurrent protection threshold and false triggering. Temperature drift causes instability in the protection critical point, significantly reducing the reliability of overcurrent protection for motor drive chips under wide temperature ranges and varying load conditions. Summary of the Invention

[0005] To address the problems of unconfigurable overcurrent thresholds and poor temperature characteristics in existing overcurrent protection circuits, this invention proposes a novel overcurrent protection circuit with a high-precision configurable overcurrent threshold.

[0006] The technical solution of this invention is as follows:

[0007] An overcurrent protection circuit with a configurable overcurrent threshold is characterized by comprising a reference circuit, an LDO circuit, an overcurrent threshold generation circuit, a high-side overcurrent comparator circuit, and a low-side overcurrent comparator circuit.

[0008] The reference circuit is used to provide a reference voltage that does not change with temperature;

[0009] The LDO circuit is used to convert the reference voltage into an LDO voltage, and then generate an input reference voltage after voltage division by resistors.

[0010] The overcurrent threshold generation circuit is used to provide a configurable overcurrent threshold voltage for the high-side overcurrent comparator circuit and the low-side overcurrent comparator circuit based on the input reference voltage. Specifically, the overcurrent threshold generation circuit includes a first error amplifier, a high-voltage NMOS transistor NLDMOS2, NMOS transistors MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19, MN20, MN21, MN22, MN23, PMOS transistors MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, and resistors R12, R13, R14; and the positive input terminal of the first error amplifier. Connect the input reference voltage, with the negative terminal connected to the junction of MN11 and R12. The output of the first error amplifier is connected to the gate of MN11. The source of MP6 is connected to the low-voltage power supply, and its gate and drain are interconnected. The source of MP5 is connected to the drain of MP6, and the gate and drain of MP5 are interconnected. The drain of MN11 is connected to the drain of MP5, and its source is grounded through R12. The source of MP8 is connected to the low-voltage power supply, and its gate is connected to the drain of MP6. The source of MP7 is connected to the drain of MP8, and the gate of MP7 is connected to the drain of MP5. The drain and gate of MN12 are connected to the drain of MP7. The drain and gate of MN13 are connected to the source of MN12, and the source of MN13 is grounded. The source of MP10 is connected to the low-voltage power supply, and its gate and drain are interconnected. The source of MP9 is connected to the drain of MP10. The drain of MP9 is interconnected with its gate; the drain of MN15 is connected to the drain of MP9, and the gate of MN15 is connected to the drain of MP7; the drain of MN14 is connected to the source of MN15, the gate of MN14 is connected to the source of MN12, and the source of MN14 is grounded; the drain of MN17 is connected to the source of MP9, and the gate of MN17 is connected to the drain of MP7; the drain of MN16 is connected to the source of MN17, and the gate of MN16 is connected to the second overcurrent configuration word signal; the drain of MN19 is connected to the drain of MP9, and the gate of MN19 is connected to the drain of MP7; the drain of MN18 is connected to the source of MN19, the gate of MN18 is connected to the first overcurrent configuration word signal, and the source of MN18 is grounded; the source of MP11 is connected to the low-voltage power supply, and its gate is connected to MP10. The drain of MP11 is connected to the drain of MP12; the source of MP12 is connected to the drain of MP11, the gate of MP12 is connected to the drain of MP9, and the drain of MP12 is connected to the overcurrent detection signal through R13; the source of MP13 is connected to the low-voltage power supply, and the gate of MP13 is connected to the drain of MP10; the source of MP14 is connected to the drain of MP13, and the gate of MP14 is connected to the drain of MP9; the drain and gate of MN20 are connected to the drain of MP14; the gate and drain of MN21 are connected to the source of MN20, and the source of MN20 is grounded; the drain of NLDMOS2 is connected to the external power supply voltage (VM) through R14, and the gate of NLDMOS2 is connected to the low-voltage power supply enable signal; the drain of MN23 is connected to the source of NLDMOS2, and the gate of MN23 is connected to the drain of MP14;The drain of MN22 is connected to the source of MN23, the gate of MN22 is connected to the source of MN20, and the source of MN22 is grounded. The connection point between the drain of MP12 and R13 outputs a low-side overcurrent comparison threshold voltage (Vocp_L), and the connection point between R14 and the drain of NLDMOS2 outputs a high-side overcurrent comparison threshold voltage (Vocp_H) relative to the external power supply voltage (VM). The first overcurrent configuration word signal and the second overcurrent configuration word signal form a configuration word (OCPTH) used to configure the current flowing through R13 and R14, thereby configuring the overcurrent switching level. The low-voltage power supply is 5V.

[0011] The high-side overcurrent comparator circuit is used to compare the source voltage of the high-side power transistor of the half-bridge with the overcurrent threshold voltage and output a high-side overcurrent logic signal.

[0012] The low-side overcurrent comparator circuit is used to compare the drain voltage of the low-side power transistor of the half-bridge with the overcurrent threshold voltage and output a low-side overcurrent logic signal.

[0013] Furthermore, the reference circuit includes NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10; PMOS transistors MP1, MP2, MP3, and MP4; transistors Q1 and Q2; and resistors R1, R2, R3, R4, R5, R6, and R7. The source of MP1 is connected to a low-voltage power supply, and its gate and drain are interconnected. The collector of Q1 is connected to the drain of MP1, and the base of Q1 is connected to the source of MN5. The transmitter of Q1 is connected sequentially through R5, R4, R3, and R7. 2. R1 is grounded; the drain of MN3 is connected to the junction of R4 and R3, the gate of MN3 is connected to the first adjustment signal, and the source of MN3 is connected to the junction of R3 and R2; the drain of MN2 is connected to the source of MN3, the gate of MN2 is connected to the second adjustment signal, and the source of MN2 is connected to the junction of R2 and R1; the drain of MN1 is connected to the source of MN2, the gate of MN1 is connected to the third adjustment signal, and the source of MN1 is grounded; the source of MP2 is connected to the low-voltage power supply, and its gate is connected to the drain of MP1; the collector of Q2 is connected to the drain of MP2, and the base of Q2 is connected to... The source of MN5 and the transmitter of Q2 are connected to the junction of R5 and R4; the drain of MN4 is connected to the low-voltage power supply, and its gate is connected to the drain of MP4 through R7; the drain of MN6 is connected to the source of MN4 and the drain of MP2, the gate of MN6 is connected to the enable signal (the enable signal is an external enable signal), and the source of MN6 is grounded; the drain of MN5 is connected to the low-voltage power supply, its gate is connected to the drain of MP2, and the source of MN5 is grounded through R6; the drain of MN7 is connected to the source of MN5, the gate of MN7 is connected to the enable signal, and the source of MN7 is grounded; MP The source of Q3 is connected to a low-voltage power supply, and its gate is connected to the drain of MP1; the drain of MN9 is connected to the drain of MP3, the gate and drain of MN9 are interconnected, and the source of MN9 is grounded; the drain of MN10 is connected to the drain of MP4 through R7, the gate of MN10 is connected to the drain of MP3, and the source of MN10 is grounded; the source of MP4 is connected to a low-voltage power supply, and its gate is connected to an enable signal; the drain of MN8 is connected to the drain of MP4 through R7, the gate of MN8 is connected to an enable signal, and the source of MN8 is grounded; the connection point between the bases of Q1 and Q2 outputs a reference voltage.

[0014] Furthermore, the LDO circuit includes a second error amplifier, a high-voltage NMOS transistor NLDMOS1, and resistors R8, R9, R10, and R11. The positive input terminal of the second error amplifier is connected to the reference voltage, and the negative input terminal is connected to the connection point of R8 and R9. The drain of NLDMOS1 is connected to the external power supply voltage, the gate is connected to the output terminal of the second error amplifier, and the source is grounded through two parallel branches. The two parallel branches are formed by R8 and R9 in series and R10 and R11 in series. The connection point of R10 and R11 outputs the input reference voltage obtained by voltage division.

[0015] Furthermore, the high-side overcurrent comparator circuit includes high-voltage NMOS transistors NDEMOS1, NDEMOS2, and NDEMOS3; high-voltage PMOS transistors PDEMOS1, PDEMOS2, and PDEMOS3; Zener transistors ZD1 and ZD2; bias currents IBIAS1, IBIAS2, and IBIAS3; NMOS transistors MN24, MN25, MN26, MN27, MN28, and MN29; PMOS transistors MP15, MP16, and MP17; resistors R15 and R16; and an AND gate AND1. The anode of ZD2 is connected to the external power supply voltage, and the cathode is connected to the cathode of ZD2. The anode of ZD2 is connected to the external power supply voltage after passing through R15 and R16. External power supply voltage; the drain of NDEMOS1 is connected to the anode of ZD2, and the gate of NDEMOS1 is connected to the low-voltage power supply enable signal; the gate and drain of MN24 are connected to the source of NDEMOS1; the inflow terminal of IBIAS1 is connected to the source of MN24, and the outflow terminal of IBIAS1 is grounded; the drain of NDEMOS2 is connected to the external power supply voltage, and the gate is connected to the connection point of R16 and R5; the source of PDEMOS1 is connected to the source of NDEMOS2, the gate of PDEMOS1 is connected to the anode of ZD1, and the drain of PDEMOS1 is grounded; the inflow terminal of IBIAS2 is connected to the external power supply voltage, and the outflow terminal is connected to the drain and gate of MN25; the gates of MN25 and MN26 are also connected to the external power supply voltage. The gate of MN27 is interconnected with the gate of MN25; the source of MN25 is connected to the source of NDEMOS2; the source of MP15 is connected to the external power supply voltage, and its gate and drain are interconnected; the drain of MN28 is connected to the drain of MP15, and the gate of MN28 is connected to the high-side overcurrent comparison threshold voltage (Vocp_H); the source of MP16 is connected to the external power supply voltage, and its gate is connected to the drain of MP15; the drain of MN29 is connected to the drain of MP16, and the gate of MN29 is connected to the source of PDEMOS3; the drain of MN26 is connected to the sources of MN28 and MN29, and the source of MN26 is connected to the source of MN25; the gate of PDEMOS3 is connected to the source of MN25, and the drain of PDEMOS3 is connected to the midpoint of the half-bridge. Voltage; the source of MP17 is connected to the external power supply voltage, and the gate is connected to the drain of MP16; the drain of MN27 is connected to the drain of MP17, and the source of MN27 is connected to the source of MN25; the source of PDEMOS2 is connected to the external power supply voltage, and the gate is connected to the drain of MP17; the drain of NDEMOS3 is connected to the source of PDEMOS2, the gate of NDEMOS3 is connected to the output of AND1, the source of NDEMOS3 is connected to the inflow terminal of IBIAS3, and the outflow terminal of IBIAS3 is grounded; the two input terminals of AND1 are connected to the low-voltage power supply enable signal and the PWM signal of the high-side power transistor of the half-bridge, respectively; the connection point of NDEMOS3 and IBIAS3 outputs the high-side overcurrent logic signal.

[0016] Furthermore, the low-side overcurrent comparator circuit includes a bias current IBIAS4, NMOS transistors MN30, MN31, MN32, MN33, and MN34, and PMOS transistors MP18, MP19, MP20, MP21, and MP22; the inflow terminal of IBIAS4 is connected to a low-voltage power supply; the drain and gate of MN30 are connected to the outflow terminal of IBIAS4, and the source of MN30 is grounded; the source of MP18 is connected to a low-voltage power supply, and its gate and drain are interconnected; the drain of MN31 is connected to the drain of MP18, the gate of MN31 is connected to the outflow terminal of BIAS4, and the source of MN31 is grounded; the source of MP19 is connected to a low-voltage power supply, and its gate is connected to the drain of MP18; MP21... The source of MN21 is connected to the drain of MP19, and the gate of MP21 is connected to the low-side overcurrent comparison threshold voltage (Vocp_L). The gate and drain of MN32 are connected to the drain of MP21, and the source of MN32 is grounded. The source of MP22 is connected to the drain of MP19, and the gate of MP22 is connected to the midpoint voltage of the half-bridge. The drain of MN33 is connected to the drain of MP22, the gate of MN33 is connected to the drain of MP21, and the source of MN33 is grounded. The source of MP20 is connected to the low-voltage power supply voltage, and the gate is connected to the drain of MP18. The drain of MN34 is connected to the drain of MP20, the gate of MN34 is connected to the drain of MP22, and the source of MN34 is grounded. The connection point between the gate of MP20 and MN34 outputs the low-side overcurrent logic signal.

[0017] Furthermore, when the high-side overcurrent comparator circuit is turned on, if the midpoint voltage of the half-bridge is lower than the high-side overcurrent comparison threshold voltage (Vocp_H), it outputs a high-level signal to indicate that the high-side power transistor is overcurrent.

[0018] When the low-side power transistor of the half-bridge is turned on, if the voltage at the midpoint of the half-bridge is higher than the low-side overcurrent comparison threshold voltage (Vocp_L), the low-side overcurrent comparator circuit outputs a high-level signal indicating overcurrent of the low-side power transistor.

[0019] The overcurrent logic signal is processed by digital logic to turn off the corresponding power transistor, putting the chip into a protection state.

[0020] The beneficial effects of this invention are that the overcurrent threshold is more configurable, and users can flexibly adjust the overcurrent comparison threshold according to different operating conditions of the motor; secondly, the circuit has better temperature characteristics and less temperature drift, which greatly improves the reliability of overcurrent protection of the motor drive chip under wide temperature range and variable load conditions. Attached Figure Description

[0021] Figure 1 A schematic diagram of the overall framework of an overcurrent protection circuit with a configurable overcurrent threshold;

[0022] Figure 2 This is a reference circuit diagram;

[0023] Figure 3 Here is the circuit structure diagram of an LDO;

[0024] Figure 4 Circuit diagram for generating overcurrent threshold;

[0025] Figure 5 This is the circuit diagram for the high-side overcurrent comparator.

[0026] Figure 6 This is a circuit diagram of a low-side current comparator.

[0027] Figure 7 A simulation diagram of the full process corner temperature for configuring the word OCPTH=00;

[0028] Figure 8 A simulation diagram of the full process corner temperature for configuring the word OCPTH=01;

[0029] Figure 9 A simulation diagram of the full process corner temperature for configuring the word OCPTH=10;

[0030] Figure 10 A simulation diagram of the full process corner temperature for configuring word OCPTH=11. Detailed Implementation

[0031] The present invention will now be described in detail with reference to the accompanying drawings and simulation examples.

[0032] This invention proposes a novel high-precision configurable overcurrent threshold overcurrent protection circuit, comprising: a reference circuit, an LDO circuit, an overcurrent threshold generation circuit, a high-side overcurrent comparator circuit, and a low-side overcurrent comparator circuit. In the circuit shown in the attached figures, VM is connected to the motor power supply with a maximum voltage of 60V, gnd is grounded, V5 is connected to the low-voltage 5V power supply, vdd is connected to the 5V pre-power rail, EN_5V is connected to the 5V enable signal, HP is connected to the 5V PWM signal of the high-side power transistor, XISENP is connected to the positive terminal of the current sensing resistor, and vint_v0p6 is a 0.6V reference voltage obtained by dividing the 1.8V LDO. The error amplifiers in the figure all operate between the 5V power rail and ground potential.

[0033] like Figure 2 As shown, the basic principle of the bandgap reference is that the currents in the two branches Q1 and Q2 are equal. Due to the mirror images of MP1 and MP2, the base voltages of the transistors Q1 and Q2 in the two branches are equal. Therefore, it is easy to calculate the current I flowing through resistor R5. R5 = (V BE2 -V BE1 ) / R5, where Q2 is a single-unit transistor, Q1 is composed of n single-unit transistors connected in parallel, each single-unit transistor is identical to Q1, and V BE =V Tln(I) C / I S ), so I R5 =V T If lnn / R5, and trim1=trim2=trim3=5V, then the output reference voltage V ref =V BE +V T lnn(R4 / R5), because V at room temperature BE It is a voltage with a negative temperature coefficient, and V T Since it is a voltage with a positive temperature coefficient, properly setting the ratio n of the two transistors Q1 and Q2, as well as the two resistors R4 and R5, can make V... ref It outputs a voltage reference with zero temperature coefficient. The bandgap reference circuit also includes a startup circuit consisting of MP3, MP4, R7, MN4, MN9, and MN10. After the enable is established, the external enable signal EN flips low, MP4 is in the on state, which pulls the gate of MN4 high to Vdd, turning on MN4. MN4 further pulls up the gate of MN5, turning on MN5 as well. After MN5 turns on, the current flowing through resistor R6 generates the bias voltage of transistors Q1 and Q2. Due to the leakage of the transistors, the main reference circuit works normally. The PTAT current generated then feeds back to the gate of MN4 through the mirror relationship of MP1, MP3, MN9, and MN10, thus pulling down MN4 to turn off after startup.

[0034] After the reference voltage is generated, it is passed through Figure 3 The LDO circuit shown converts to a 1.8V LDO voltage, and the resulting 0.6V voltage, vint_v0p6, after being divided by resistors, will be used as the input reference voltage for the overcurrent threshold generation circuit. This results in an overcurrent threshold voltage with high accuracy and good temperature characteristics.

[0035] Reference voltage vint_v0p6 passed Figure 4The BUFFER and resistor R12 shown are converted into a reference current, which is then converted into a low-side overcurrent comparison threshold voltage Vocp_L via a current mirror and low-side resistor R13. This is then converted into a high-side overcurrent comparison threshold voltage Vocp_H relative to the power supply voltage VM via high-side resistor R14. Since the generated Vocp_H and Vocp_L are generated relative to VM and XISENP respectively, the high and low-side overcurrent comparison threshold voltages can be directly compared with the half-bridge midpoint voltage XOUTX. If XOUTX is lower than Vocp_H when the high-side power transistor is on, the high-side comparator will output a high-level signal indicating that the high-side power transistor is overcurrent. Similarly, if XOUTX is higher than Vocp_L when the low-side power transistor is on, the low-side comparator will output a high-level signal indicating that the low-side power transistor is overcurrent. After digital logic processing, the overcurrent signal will promptly turn off the corresponding power transistor, causing the chip to enter a stop-work state. The overcurrent threshold generation circuit also allows users to configure the current flowing through R13 and R14 via the configuration word OCPTH, thereby configuring the overcurrent switching level (OCPTH1 and OCPTH0 in the diagram correspond to the high and low bits of OCPTH; for example, if OCPTH=10, then OCPTH1=1 and OCPTH0=0). When OCPTH=00, 01, 10, and 11, the overcurrent thresholds are configured as 250mV, 500mV, 750mV, and 1000mV, respectively. Users can adjust the resistance values ​​of R13 and R14 and the number of bits in the OCPTH configuration word to achieve more different combinations of overcurrent thresholds. Figure 5 The high-side overcurrent comparator shown also includes a simple VM-5V power rail generation circuit, consisting of PDEMOS1, NDEMOS1, NDEMOS2, MN24, R15, R16, ZD1, ZD2, and IBIAS1, which serves as the reference ground for the high-side comparator.

[0036] Simulation example:

[0037] Figure 7 , 8Tables 9 and 10 show the simulation results when the motor power supply VM=24V has the overcurrent configuration word OCPTH configured as 00, 01, 10, and 11, respectively. The simulation results show that when OCPTH=00, the overcurrent output rises when the source XOUTX of the power transistor is 260mV lower than VM; when OCPTH=01, the overcurrent output rises when the source XOUTX of the power transistor is 510mV lower than VM; when OCPTH=10, the overcurrent output rises when the source XOUTX of the power transistor is 760mV-770mV lower than VM; and when OCPTH=11, the overcurrent output rises when the source XOUTX of the power transistor is 1000mV-1020mV lower than VM. The simulation results demonstrate that this circuit structure has small errors and high accuracy, effectively protecting the chip from damage to the power transistor under high current conditions at both high and low temperatures.

Claims

1. An overcurrent protection circuit with a configurable overcurrent threshold, characterized in that, It includes a reference circuit, an LDO circuit, an overcurrent threshold generation circuit, a high-side overcurrent comparator circuit, and a low-side overcurrent comparator circuit; The reference circuit is used to provide a reference voltage that does not change with temperature; The LDO circuit is used to convert the reference voltage into an LDO voltage, and then generate an input reference voltage after voltage division by resistors. The overcurrent threshold generation circuit is used to provide a configurable overcurrent threshold voltage for the high-side overcurrent comparator circuit and the low-side overcurrent comparator circuit based on the input reference voltage. Specifically, the overcurrent threshold generation circuit includes a first error amplifier, a high-voltage NMOS transistor NLDMOS2, NMOS transistors MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19, MN20, MN21, MN22, MN23, PMOS transistors MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, and resistors R12, R13, R14; and the positive input terminal of the first error amplifier. Connect the input reference voltage, with the negative terminal connected to the junction of MN11 and R12. The output of the first error amplifier is connected to the gate of MN11. The source of MP6 is connected to the low-voltage power supply, and its gate and drain are interconnected. The source of MP5 is connected to the drain of MP6, and the gate and drain of MP5 are interconnected. The drain of MN11 is connected to the drain of MP5, and its source is grounded through R12. The source of MP8 is connected to the low-voltage power supply, and its gate is connected to the drain of MP6. The source of MP7 is connected to the drain of MP8, and the gate of MP7 is connected to the drain of MP5. The drain and gate of MN12 are connected to the drain of MP7. The drain and gate of MN13 are connected to the source of MN12, and the source of MN13 is grounded. The source of MP10 is connected to the low-voltage power supply, and its gate and drain are interconnected. The source of MP9 is connected to the drain of MP10. The drain of MP9 is interconnected with its gate; the drain of MN15 is connected to the drain of MP9, and the gate of MN15 is connected to the drain of MP7; the drain of MN14 is connected to the source of MN15, the gate of MN14 is connected to the source of MN12, and the source of MN14 is grounded; the drain of MN17 is connected to the source of MP9, and the gate of MN17 is connected to the drain of MP7; the drain of MN16 is connected to the source of MN17, and the gate of MN16 is connected to the second overcurrent configuration word signal; the drain of MN19 is connected to the drain of MP9, and the gate of MN19 is connected to the drain of MP7; the drain of MN18 is connected to the source of MN19, the gate of MN18 is connected to the first overcurrent configuration word signal, and the source of MN18 is grounded; the source of MP11 is connected to the low-voltage power supply, and its gate is connected to MP10. The drain of MP11 is connected to the drain of MP12; the source of MP12 is connected to the drain of MP11, the gate of MP12 is connected to the drain of MP9, and the drain of MP12 is connected to the overcurrent detection signal through R13; the source of MP13 is connected to the low-voltage power supply, and the gate of MP13 is connected to the drain of MP10; the source of MP14 is connected to the drain of MP13, and the gate of MP14 is connected to the drain of MP9; the drain and gate of MN20 are connected to the drain of MP14; the gate and drain of MN21 are connected to the source of MN20, and the source of MN20 is grounded; the drain of NLDMOS2 is connected to the external power supply voltage (VM) through R14, and the gate of NLDMOS2 is connected to the low-voltage power supply enable signal; the drain of MN23 is connected to the source of NLDMOS2, and the gate of MN23 is connected to the drain of MP14;The drain of MN22 is connected to the source of MN23, the gate of MN22 is connected to the source of MN20, and the source of MN22 is grounded. The connection point between the drain of MP12 and R13 outputs a low-side overcurrent comparison threshold voltage (Vocp_L), and the connection point between R14 and the drain of NLDMOS2 outputs a high-side high-side overcurrent comparison threshold voltage (Vocp_H) relative to the external power supply voltage (VM). The first overcurrent configuration word signal and the second overcurrent configuration word signal form a configuration word (OCPTH) to configure the magnitude of the current flowing through R13 and R14, thereby configuring the overcurrent switching level. The low-voltage power supply is 5V. The high-side overcurrent comparator circuit is used to compare the source voltage of the high-side power transistor of the half-bridge with the overcurrent threshold voltage and output a high-side overcurrent logic signal. The low-side overcurrent comparator circuit is used to compare the drain voltage of the low-side power transistor of the half-bridge with the overcurrent threshold voltage and output a low-side overcurrent logic signal.

2. The overcurrent protection circuit with a configurable overcurrent threshold according to claim 1, characterized in that, The reference circuit includes NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, and MN10; PMOS transistors MP1, MP2, MP3, and MP4; transistors Q1 and Q2; and resistors R1, R2, R3, R4, R5, R6, and R7. The source of MP1 is connected to a low-voltage power supply, and its gate and drain are interconnected. The collector of Q1 is connected to the drain of MP1, and the base of Q1 is connected to the source of MN5. The transmitter of Q1 is connected sequentially through resistors R5, R4, R3, and R2. R1 is grounded; the drain of MN3 is connected to the junction of R4 and R3, the gate of MN3 is connected to the first adjustment signal, and the source of MN3 is connected to the junction of R3 and R2; the drain of MN2 is connected to the source of MN3, the gate of MN2 is connected to the second adjustment signal, and the source of MN2 is connected to the junction of R2 and R1; the drain of MN1 is connected to the source of MN2, the gate of MN1 is connected to the third adjustment signal, and the source of MN1 is grounded; the source of MP2 is connected to the low-voltage power supply, and its gate is connected to the drain of MP1; the collector of Q2 is connected to the drain of MP2, and the collector of Q2 is connected to the drain of MP2. The base of Q2 is connected to the source of MN5, and the transmitter of Q2 is connected to the junction of R5 and R4. The drain of MN4 is connected to the low-voltage power supply, and its gate is connected to the drain of MP4 through R7. The drain of MN6 is connected to the source of MN4 and the drain of MP2. The gate of MN6 is connected to the enable signal, and the source of MN6 is grounded. The drain of MN5 is connected to the low-voltage power supply, and its gate is connected to the drain of MP2. The source of MN5 is connected to ground through R6. The drain of MN7 is connected to the source of MN5, and its gate is connected to the enable signal. The source of MN7 is grounded. The source of MP3 is connected to the low-voltage power supply. The low-voltage power supply is connected to the drain of MP1 via its gate; the drain of MN9 is connected to the drain of MP3, the gate and drain of MN9 are interconnected, and the source of MN9 is grounded; the drain of MN10 is connected to the drain of MP4 via R7, the gate of MN10 is connected to the drain of MP3, and the source of MN10 is grounded; the source of MP4 is connected to the low-voltage power supply, and the gate is connected to an external enable signal; the drain of MN8 is connected to the drain of MP4 via R7, the gate of MN8 is connected to an enable signal, and the source of MN8 is grounded; the connection point between the bases of Q1 and Q2 outputs a reference voltage.

3. The overcurrent protection circuit with a configurable overcurrent threshold according to claim 1, characterized in that, The LDO circuit includes a second error amplifier, a high-voltage NMOS transistor NLDMOS1, and resistors R8, R9, R10, and R11. The positive input terminal of the second error amplifier is connected to the reference voltage, and the negative input terminal is connected to the junction of R8 and R9. The drain of NLDMOS1 is connected to the external power supply voltage, the gate is connected to the output terminal of the second error amplifier, and the source is grounded through two parallel branches. The two parallel branches are formed by R8 and R9 in series and R10 and R11 in series. The junction of R10 and R11 outputs the input reference voltage obtained by voltage division.

4. The overcurrent protection circuit with a configurable overcurrent threshold according to claim 1, characterized in that, The high-side overcurrent comparator circuit includes high-voltage NMOS transistors NDEMOS1, NDEMOS2, and NDEMOS3; high-voltage PMOS transistors PDEMOS1, PDEMOS2, and PDEMOS3; Zener transistors ZD1 and ZD2; bias currents IBIAS1, IBIAS2, and IBIAS3; NMOS transistors MN24, MN25, MN26, MN27, MN28, and MN29; PMOS transistors MP15, MP16, and MP17; resistors R15 and R16; and an AND gate AND1. The anode of ZD2 is connected to the external power supply voltage, and the cathode is connected to the cathode of ZD2. The anode of ZD2 is connected to the external power supply after passing through resistors R15 and R16. Voltage; the drain of NDEMOS1 is connected to the anode of ZD2, and the gate of NDEMOS1 is connected to the low-voltage power supply enable signal; the gate and drain of MN24 are connected to the source of NDEMOS1; the inflow terminal of IBIAS1 is connected to the source of MN24, and the outflow terminal of IBIAS1 is grounded; the drain of NDEMOS2 is connected to the external power supply voltage, and the gate is connected to the connection point of R16 and R5; the source of PDEMOS1 is connected to the source of NDEMOS2, the gate of PDEMOS1 is connected to the anode of ZD1, and the drain of PDEMOS1 is grounded; the inflow terminal of IBIAS2 is connected to the external power supply voltage, and the outflow terminal is connected to the drain and gate of MN25; the gate of MN25, the gate of MN26, and M The gate of N27 is interconnected; the source of MN25 is connected to the source of NDEMOS2; the source of MP15 is connected to the external power supply voltage, and its gate and drain are interconnected; the drain of MN28 is connected to the drain of MP15, and the gate of MN28 is connected to the high-side overcurrent comparison threshold voltage (Vocp_H); the source of MP16 is connected to the external power supply voltage, and its gate is connected to the drain of MP15; the drain of MN29 is connected to the drain of MP16, and the gate of MN29 is connected to the source of PDEMOS3; the drain of MN26 is connected to the sources of MN28 and MN29, and the source of MN26 is connected to the source of MN25; the gate of PDEMOS3 is connected to the source of MN25, and the drain of PDEMOS3 is connected to the midpoint of the half-bridge. The source of MP17 is connected to the external power supply voltage, and its gate is connected to the drain of MP16; the drain of MN27 is connected to the drain of MP17, and the source of MN27 is connected to the source of MN25; the source of PDEMOS2 is connected to the external power supply voltage, and its gate is connected to the drain of MP17; the drain of NDEMOS3 is connected to the source of PDEMOS2, the gate of NDEMOS3 is connected to the output of AND1, the source of NDEMOS3 is connected to the inflow terminal of IBIAS3, and the outflow terminal of IBIAS3 is grounded; the two input terminals of AND1 are connected to the low-voltage power supply enable signal and the PWM signal of the high-side power transistor of the half-bridge, respectively; the connection point of NDEMOS3 and IBIAS3 outputs the high-side overcurrent logic signal.

5. The overcurrent protection circuit with a configurable overcurrent threshold according to claim 1, characterized in that, The low-side overcurrent comparator circuit includes a bias current IBIAS4, NMOS transistors MN30, MN31, MN32, MN33, and MN34, and PMOS transistors MP18, MP19, MP20, MP21, and MP22. The inflow terminal of IBIAS4 is connected to a low-voltage power supply. The drain and gate of MN30 are connected to the outflow terminal of IBIAS4, and the source of MN30 is grounded. The source of MP18 is connected to a low-voltage power supply, and its gate and drain are interconnected. The drain of MN31 is connected to the drain of MP18, the gate of MN31 is connected to the outflow terminal of IBIAS4, and the source of MN31 is grounded. The source of MP19 is connected to a low-voltage power supply, and its gate is connected to the drain of MP18. The source of MP21... The gate of MP21 is connected to the drain of MP19, and the gate of MP22 is connected to the low-side overcurrent comparison threshold voltage (Vocp_L). The gate and drain of MN32 are connected to the drain of MP21, and the source of MN32 is grounded. The source of MP22 is connected to the drain of MP19, and the gate of MP22 is connected to the midpoint voltage of the half-bridge. The drain of MN33 is connected to the drain of MP22, the gate of MN33 is connected to the drain of MP21, and the source of MN33 is grounded. The source of MP20 is connected to the low-voltage power supply voltage, and the gate is connected to the drain of MP18. The drain of MN34 is connected to the drain of MP20, the gate of MN34 is connected to the drain of MP22, and the source of MN34 is grounded. The connection point between the gate of MP20 and MN34 outputs the low-side overcurrent logic signal.

6. The overcurrent protection circuit with a configurable overcurrent threshold according to claim 1, characterized in that, When the high-side overcurrent comparator circuit is turned on, if the midpoint voltage of the half-bridge is lower than the high-side overcurrent comparison threshold voltage (Vocp_H), it outputs a high-level signal to indicate that the high-side power transistor is overcurrent. When the low-side power transistor of the half-bridge is turned on, if the voltage at the midpoint of the half-bridge is higher than the low-side overcurrent comparison threshold voltage (Vocp_L), the low-side overcurrent comparator circuit outputs a high-level signal indicating overcurrent of the low-side power transistor. The overcurrent logic signal is processed by digital logic to turn off the corresponding power transistor, putting the chip into a protection state.

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