A half-bridge architecture

Abstract

The application discloses a kind of half bridge architecture.The half bridge architecture includes first bridge arm, second bridge arm, the drain of the first bridge arm is connected with input end, the gate of the first bridge arm is connected to control module, the source of the second bridge arm is grounded, the gate of the second bridge arm is connected to control module, the source of the first bridge arm is connected with the drain of second bridge arm, and connection point is connected to load circuit as output end, wherein, the first bridge arm is enhancement mode device, the specific on-resistance of the second bridge arm is smaller than the specific on-resistance of the first bridge arm, and the first bridge arm and the second bridge arm are integrally arranged.The upper bridge arm of the present scheme uses enhancement mode device, the lower bridge arm uses low on-resistance device, and both are integrally arranged, while considering the needs of high speed, small system size.

Description

Technical Field

[0001] This invention relates to the field of half-bridge circuit technology, and more particularly to a half-bridge architecture. Background Technology

[0002] In half-bridge architecture design, the devices in the upper bridge arm need to have a sufficiently fast switching speed to ensure a rapid transition from the on to the off state during the switching process, thereby reducing switching losses. Simultaneously, the on-resistance of the devices in the lower bridge arm must be as low as possible. On-resistance refers to the internal resistance of a device in the on state, and it directly affects the voltage drop and energy loss when current flows through the device. A smaller on-resistance can reduce energy loss within the device, thereby improving the efficiency of the entire half-bridge circuit.

[0003] In traditional half-bridge architecture designs, silicon-based MOSFET (SiMOS) devices are typically used in both the upper and lower bridge arms, such as... Figure 1 As shown. Currently, the upper and lower arms of the half-bridge architecture are gradually shifting to use third-generation semiconductor devices, including GaNHEMT (gallium nitride high electron mobility transistor) and SiC MOS (silicon carbide metal oxide semiconductor), such as... Figure 2 As shown. Compared to traditional silicon-based devices, third-generation semiconductor devices offer faster switching speeds and, overall, a better factor of quality (FOM), i.e., a smaller Ron*C, where Ron is the on-resistance and C is the gate charge. Therefore, in high-speed half-bridge architecture designs, using third-generation devices as the switching devices in the upper bridge arm can achieve faster switching speeds, thereby improving overall performance.

[0004] In highly integrated applications, there are strict requirements regarding the size of half-bridge modules. For example... Figure 3 As shown, the lower transistor occupies most of the layout area. If the specific on-resistance (Rsp) of the lower transistor is too high, it will be impossible to achieve a suitable layout within the limited space. Typically, lateral GaN devices tend to have a large area, especially in low-voltage applications below 50V, where GaN's Rsp is much larger than that of silicon devices. Therefore, using GaN devices will not meet the system's size requirements. More importantly, in high-speed half-bridge architectures, a large Rsp in the lower bridge arm results in a larger capacitance, significantly increasing charging losses when the upper bridge arm is on, thus reducing the overall system efficiency. In summary, traditional silicon half-bridge architectures suffer from slow speed and cannot meet the stringent requirements of high speed and small size in applications. While modules based on third-generation semiconductor materials offer improved performance, the design of the lower transistor often requires increasing the chip area to achieve a lower resistance value, which cannot meet the module's small size requirements. Summary of the Invention

[0005] The main objective of this invention is to provide a half-bridge architecture that overcomes the shortcomings of the prior art.

[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0007] This invention provides a half-bridge architecture, including a first bridge arm and a second bridge arm. The drain of the first bridge arm is connected to the input terminal, and the gate of the first bridge arm is connected to a control module. The source of the second bridge arm is grounded, and the gate of the second bridge arm is connected to the control module. The source of the first bridge arm and the drain of the second bridge arm are connected, and the connection point is connected to the load circuit as an output terminal. The first bridge arm is an enhancement-mode device, and the specific on-resistance of the second bridge arm is smaller than that of the first bridge arm.

[0008] In some more specific designs, the first bridge arm and the second bridge arm are set up separately.

[0009] In some more specific solutions, the first bridge arm and the second bridge arm are integrated and configured, including:

[0010] Substrate; a semiconductor layer grown on the surface of the substrate.

[0011] Both the first bridge arm and the second bridge arm are formed by processing a semiconductor layer and are distributed along a first direction, which is parallel to the surface of the substrate.

[0012] Furthermore, the first bridge arm includes a buffer layer, a barrier layer, a first gate, a first source, and a first drain. The barrier layer is disposed on the buffer layer along a second direction, the first gate is disposed on the barrier layer along a second direction, the first source penetrates the barrier layer and part of the buffer layer along a second direction, and the first drain penetrates the barrier layer and part of the buffer layer along a second direction. The second direction is perpendicular to the surface of the substrate, and the first gate, first source, and first drain are distributed along a first direction.

[0013] Furthermore, an isolation region is provided within the semiconductor layer, the isolation region being formed by etching the semiconductor layer along a second direction, and the first bridge arm is disposed within the isolation region.

[0014] Furthermore, the first bridge arm is eGaN, and the second bridge arm is SiMOS.

[0015] Furthermore, the semiconductor layer includes an epitaxial layer and a doped layer. The epitaxial layer is grown on the surface of the substrate, and the doped layer is grown on the surface of the epitaxial layer. A heavily doped source region is etched on the doped layer. The second bridge arm includes a second gate and a second source. The second source is disposed outside the heavily doped source region and a portion of the doped layer is etched along a second direction. The second gate is disposed within the heavily doped source region and penetrates the doped layer and a portion of the epitaxial layer along the second direction. The substrate serves as the second drain.

[0016] Furthermore, the semiconductor layer also includes a separation gate and an oxide layer. The separation gate is disposed below the second gate along the second direction, and the oxide layer is disposed between the separation gate and the second gate.

[0017] Furthermore, the substrate is an n-type silicon substrate, the epitaxial layer is a lightly doped n-type epitaxial layer, the doped layer is a p-type doped layer, and the heavily doped source region is an n-type heavily doped source region.

[0018] Furthermore, the oxide layer includes a first oxide layer and a second oxide layer, the first oxide layer being in contact with the second gate, the second oxide layer being in contact with the delimiter gate, and the thickness of the first oxide layer being less than the thickness of the second oxide layer.

[0019] Compared with the prior art, the advantages of the present invention include at least the following:

[0020] This design employs an enhanced gallium nitride (GaN) device in the upper bridge arm and a low-Rsp SiMOS device in the lower bridge arm. In the input-to-output path, the eGaN is directly connected in series with the input power supply. The eGaN has a "normal shutdown" characteristic, ensuring that in the event of an unexpected power failure or controller undervoltage, the power supply to the subsequent circuits can be naturally cut off by the eGaN device, completely avoiding the risk of input short circuits. This not only ensures safety but also significantly improves switching speed due to its high-speed switching characteristics, thereby enhancing the efficiency and performance of the entire circuit. The SiMOS, acting as a pull-down device, provides a discharge path for the load. By using this low specific on-resistance SiMOS device, the required resistance value can be achieved in a smaller area, ensuring a compact system size. Furthermore, the low specific on-resistance SiMOS device also has a smaller parasitic capacitance, which helps to effectively reduce losses and further improve the efficiency of the entire system. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a traditional all-silicon half-bridge architecture;

[0022] Figure 2 This is a schematic diagram of the traditional GaN half-bridge architecture;

[0023] Figure 3This is a schematic diagram of the layout of the half-bridge architecture provided in an embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the half-bridge architecture provided in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the structure of integrating eGaN and SiMOS on a silicon substrate provided in an embodiment of the present invention. Attached image description:

[0027] 01. n-type silicon substrate; 02. n-type epitaxial layer; 03. p-type doped layer; 04. n-type heavily doped source region; 05. Second gate; 06. Oxide layer; 07. Separated gate; 08. Second source contact via; 20. Isolation region; 21. Buffer layer; 22. Barrier layer; 23. First gate; 24. First source contact via; 25. First drain contact via. Detailed Implementation

[0028] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0029] Please refer to Figure 4 A half-bridge architecture includes a first bridge arm and a second bridge arm. Each bridge arm is composed of a single-transistor switch; the first bridge arm uses an eGaN device, and the second bridge arm uses a SiMOS device. Specifically, the drain of the eGaN device is directly connected to the input terminal, and its gate is driven by a controller. The source of the SiMOS device is grounded, and its gate is also connected to the controller for control. The source of the eGaN device is connected to the drain of the SiMOS device, and the connection point serves as the output terminal, directly connected to the load circuit. The load circuit consists of load elements, including resistors, inductors, and capacitors. It is worth noting that the specific on-resistance of SiMOS is smaller than that of eGaN.

[0030] In the input-to-output path, the eGaN is directly connected in series with the input power supply, exhibiting a "normal shutdown" characteristic. This means that the device is in a default off state under 0V conditions. This characteristic ensures that in the event of an unexpected power outage or controller undervoltage, the power supply to the subsequent circuits can be naturally cut off by the eGaN device, completely avoiding the risk of input short circuits. This not only guarantees safe operation of the system without power shutdown but also significantly improves switching speed due to its high-speed switching characteristics. This directly leads to a significant reduction in the size of passive devices, thereby improving the efficiency and performance of the entire circuit.

[0031] SiMOS, used as a pull-down device, provides a discharge path for the load. In practical applications, the on-time of the pull-down transistor is typically much longer than its off-time, placing higher demands on its performance. To ensure efficient circuit operation, the resistance of the pull-down transistor must be as low as possible to reduce energy loss. Simultaneously, the strict limitations on overall device size pose a significant challenge to the resistor's resistance (Rsp). Therefore, this solution selects SiMOS, with an Rsp that is one-tenth or even smaller than that of GaN devices. By employing this low specific on-resistance SiMOS device, the required resistance value can be achieved within a smaller area, thus ensuring a small overall system size. Furthermore, the low specific on-resistance SiMOS device also has a smaller parasitic capacitance, which helps to effectively reduce losses and further improve the overall system efficiency.

[0032] Please refer to Figure 5 In this solution, eGaN and SiMOS are integrated, specifically including:

[0033] n-type silicon substrate 01,

[0034] A lightly doped n-type epitaxial layer 02 is located on the n-type silicon substrate 01.

[0035] A p-type doped layer 03 is located on the low-doped n-type epitaxial layer 02.

[0036] First, the structure of eGaN is introduced: To optimize performance, an isolation region 20 is provided. The isolation region 20 is formed by etching a p-type doped layer 03 and an n-type epitaxial layer 02. An eGaN is disposed within the isolation region 20, including: a buffer layer 21, a barrier layer 22, a first gate 23, a first source, and a first drain. The barrier layer 22 is disposed on the buffer layer 21 along a second direction, the first gate 23 is disposed on the barrier layer 22 along a second direction, the first source penetrates the barrier layer 22 and a portion of the buffer layer 21 along the second direction, and the first drain penetrates the barrier layer 22 and a portion of the buffer layer 21 along the second direction. The second direction is perpendicular to the surface of the substrate, and the first gate 23, the first source, and the first drain are distributed along a first direction. The first source includes a first source contact via 24 and conductive material filling the first source contact via 24, and the first drain includes a first drain contact via 25 and conductive material filling the first drain contact via 25. eGaN exhibits extremely fast switching speeds, high internal electron mobility, and low parasitic capacitance, enabling it to complete the turn-on and turn-off processes in a short time. Using it as a power transistor can effectively reduce switching losses and increase the operating frequency of the circuit.

[0037] Next, the structure of SiMOS will be introduced:

[0038] n-type silicon substrate 01, which serves as the second drain of the SiMOS device;

[0039] The n-type epitaxial layer 02 is located on the n-type silicon substrate 01 and serves as the drift region of the SiMOS device.

[0040] The p-type doped layer 03 is located on the lightly doped n-type epitaxial layer 02 and serves as the channel of the SiMOS device.

[0041] The n-type heavily doped source region 04 is formed by etching the p-type doped layer 03;

[0042] The second gate 05 is disposed within the heavily doped source region and penetrates the p-type doped layer 03 and part of the n-type epitaxial layer 02 along the second direction;

[0043] The separation gate 07 is disposed below the second gate 05 along the second direction and is connected to the second source at the interdigitated end position. As a field plate of the drift region, the separation gate 07 increases the depletion effect, thereby improving the withstand voltage performance and the figure of merit of the resistance of the drift region.

[0044] Oxide layer 06 is disposed between the separation gate 07 and the second gate 05; two sets of structures (second gate 05 + oxide layer 06 + separation gate 07) are set here, indicating that the left side repeats continuously. In the actual chip manufacturing process, in order to carry devices with large currents, multiple units need to be connected in parallel. Therefore, on the left side of the chip, there are multiple sets of units connected in parallel to form a complete device. The same principle also applies to the right side of the chip, where there is not just one unit, but multiple sets of units connected in parallel. The specific connection between these units is achieved through multiple metal layers on top of the chip, which are responsible for effectively connecting the parallel units to ensure that the current can flow smoothly through the entire device. Of course, it can also be simplified to represent it with only one such structure.

[0045] The second source is located outside the heavily doped source region, and a portion of the p-type doped layer 03 is etched along the second direction. Specifically, during manufacturing, the heavily doped n-type source region 04 and the p-type doped layer 03 are tightly connected through a second source contact via 08 to form the second source, ensuring efficient electron and hole transport. Two second sources are shown here, indicating that the left side repeats continuously. Of course, it can also be simplified to using only one.

[0046] In this design, oxide layer 06 is further refined, comprising two distinct parts: a first oxide layer and a second oxide layer. The first oxide layer contacts the second gate 05 and forms the gate oxide layer. The thickness of the gate oxide layer needs to be considered to ensure that the electronic device can operate at the optimal switching speed. If the gate oxide layer is too thick, the switching speed will be slower, affecting the overall performance of the device; conversely, if the gate oxide layer is too thin, it may not be able to withstand the required gate voltage, thus affecting the device's voltage withstand capability. Therefore, to balance these two requirements, the thickness of the gate oxide layer is 3nm to 50nm, ensuring that the gate oxide layer can withstand the necessary voltage without excessively affecting the switching speed, thereby maintaining the electronic device's performance at its best.

[0047] The second oxide layer contacts the separation gate 07, forming the oxide layer of the separation gate 07. Compared to the first oxide layer, the oxide layer of the separation gate 07 must be able to withstand a stronger electric field, therefore its thickness needs to be increased accordingly. In this scheme, the oxide layer thickness of the separation gate 07 is 5nm to 200nm. This plays a crucial role in optimizing the breakdown voltage performance and the figure-of-fact resistance of the drift region, affecting the performance and efficiency of the entire electronic device.

[0048] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A half-bridge architecture, characterized in that, It includes a first bridge arm and a second bridge arm. The drain of the first bridge arm is connected to the input terminal, and the gate of the first bridge arm is connected to the control module. The source of the second bridge arm is grounded, and the gate of the second bridge arm is connected to the control module. The source of the first bridge arm and the drain of the second bridge arm are connected, and the connection point is connected to the load circuit as an output terminal. The first bridge arm is an enhancement-mode device, and the specific on-resistance of the second bridge arm is smaller than that of the first bridge arm.

2. The half-bridge architecture according to claim 1, characterized in that, The first bridge arm and the second bridge arm are set separately.

3. The half-bridge architecture according to claim 1, characterized in that, The first bridge arm and the second bridge arm are integrated and configured, including: Substrate; a semiconductor layer grown on the surface of the substrate. Both the first bridge arm and the second bridge arm are formed by processing a semiconductor layer and are distributed along a first direction, which is parallel to the surface of the substrate.

4. The half-bridge architecture according to claim 3, characterized in that, The first bridge arm includes a buffer layer, a barrier layer, a first gate, a first source, and a first drain. The barrier layer is disposed on the buffer layer along a second direction. The first gate is disposed on the barrier layer along a second direction. The first source penetrates the barrier layer and part of the buffer layer along a second direction. The first drain penetrates the barrier layer and part of the buffer layer along a second direction. The second direction is perpendicular to the surface of the substrate, and the first gate, first source, and first drain are distributed along a first direction.

5. The half-bridge architecture according to claim 3, characterized in that, An isolation region is provided within the semiconductor layer, and the isolation region is formed by etching the semiconductor layer along a second direction. The first bridge arm is disposed within the isolation region.

6. The half-bridge architecture according to claim 3, characterized in that, The first bridge arm is eGaN, and the second bridge arm is SiMOS.

7. The half-bridge architecture according to claim 3, characterized in that, The semiconductor layer includes an epitaxial layer and a doped layer. The epitaxial layer is grown on the surface of the substrate, and the doped layer is grown on the surface of the epitaxial layer. A heavily doped source region is etched on the doped layer. The second bridge arm includes a second gate and a second source. The second source is disposed outside the heavily doped source region and a portion of the doped layer is etched along a second direction. The second gate is disposed within the heavily doped source region and penetrates the doped layer and a portion of the epitaxial layer along the second direction. The substrate serves as the second drain.

8. The half-bridge architecture according to claim 7, characterized in that, It also includes a separation gate and an oxide layer, wherein the separation gate is disposed below the second gate along the second direction, and the oxide layer is disposed between the separation gate and the second gate.

9. The half-bridge architecture according to claim 8, characterized in that, The substrate is an n-type silicon substrate. And / or, the epitaxial layer is a lightly doped n-type epitaxial layer. And / or, the doped layer is a p-type doped layer. And / or, the heavily doped source region is an n-type heavily doped source region.

10. The half-bridge architecture according to claim 8, characterized in that, The oxide layer includes a first oxide layer and a second oxide layer. The first oxide layer is in contact with the second gate, and the second oxide layer is in contact with the delimiter gate. The thickness of the first oxide layer is less than the thickness of the second oxide layer.

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