A hierarchical redundant power supply circuit and timing control method of a dual-mainboard network barrier

Abstract

The application discloses a kind of hierarchical redundancy power supply circuits and timing control methods of double mainboard network gate, belong to network security equipment power supply technical field.Circuit includes dual-redundancy input power module, FPGA hierarchical redundancy control module, voltage monitoring module, two-way multi-power rail DC-DC conversion unit;FPGA built-in hierarchical power-on timing logic, priority starts core control board power supply, after voltage stabilizes, delay 12ms~15ms starts data isolation board power supply, realizes double mainboard staggered peak power-on;Voltage monitoring module uses bus level + power rail level double-layer architecture, when detecting main path power failure, FPGA controls high-speed power switching chip to complete millisecond-level seamless switching, while automatically recording fault information.The application solves the problems of configuration loss, link interruption caused by double mainboard network gate parallel power-on, and power supply switching lag downtime, can be compatible with different power-on timing CPU architecture, improve power supply reliability and operation efficiency.

Description

Technical Field

[0001] This invention belongs to the field of power supply technology for network security equipment. Specifically, it relates to a hierarchical redundant power supply circuit and timing control method for a dual-motherboard network gateway. Background Technology

[0002] Network gateways are core network security devices that enable physical isolation between internal and external networks and one-way data transfer. The industry mainstream adopts a dual-motherboard architecture, consisting of a core control board responsible for permission verification and policy storage, and a data isolation board responsible for data forwarding and isolation exchange. The two motherboards are equipped with independent processors to meet the compliance requirements of Level 3 and above of the Information Security Protection System.

[0003] With the technological iteration of cybersecurity equipment, existing network gateways are generally equipped with dual redundant input power supplies as standard. However, their power supply scheme follows the redundant power supply design logic of general servers, which can only achieve cold and hot backup of the two power supplies. This has the following shortcomings for the specific scenario of dual-motherboard network gateways: First, there is a lack of cross-board timing control mechanism. When the whole machine is powered on, the two motherboards start up at the same time. The peak instantaneous current of the bus is too high, which can easily cause voltage drop. In addition, the fault tolerance of different architecture CPUs for power-on timing is low. Parallel power-on can easily lead to inconsistent firmware configuration verification between the internal and external network motherboards, resulting in faults such as loss of internal network access permissions and blockage of the external network one-way transfer link, resulting in insufficient equipment reliability. Second, traditional redundant power supplies mostly use diode or gate switching schemes, with switching delays generally ranging from 20 to 50 ms. During the switching process, the bus voltage drops significantly, which can easily trigger the CPU power supply reset of the two motherboards, causing the network gateway to temporarily disconnect and resulting in the loss of un-ferryed data, which cannot meet the requirements of high-reliability operation scenarios. Third, the power supply timing is fixed and cannot be compatible with processor architectures with different power-on logic. When replacing the motherboard CPU, the power supply PCB needs to be redesigned, resulting in a long product iteration cycle and high modification costs. Meanwhile, the existing solution only monitors the input bus voltage and does not monitor the status of the CPU's local power rail. It cannot identify the inter-rail voltage drift caused by the aging of the DC-DC chip, making fault tracing difficult and manual troubleshooting time-consuming.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a hierarchical redundant power supply circuit and timing control method for a dual-mainboard network gate, thereby solving the problems mentioned in the background art.

[0006] To solve the above-mentioned technical problems, the basic concept of the technical solution adopted by the present invention is as follows: A hierarchical redundancy power supply circuit for a dual-motherboard network gateway includes a dual-redundant input power supply module, an FPGA hierarchical redundancy control module, a voltage monitoring module, a first multi-power rail DC-DC conversion unit, and a second multi-power rail DC-DC conversion unit. The dual-redundant input power module includes a first input power supply and a second input power supply that are independent of each other. The output terminals of both input power supplies are connected to a high-speed power switching chip. The output bus of the high-speed power switching chip is connected to the input terminal of the voltage monitoring module, the input terminal of the first multi-rail DC-DC conversion unit, and the input terminal of the second multi-rail DC-DC conversion unit, respectively. The FPGA hierarchical redundancy control module is electrically connected to the control terminal of the high-speed power switching chip, the signal output terminal of the voltage monitoring module, the enable terminal of the first multi-power rail DC-DC conversion unit, and the enable terminal of the second multi-power rail DC-DC conversion unit, respectively. The FPGA hierarchical redundancy control module is used to receive multiple PowerGood signals fed back by the first multi-power rail DC-DC conversion unit and the second multi-power rail DC-DC conversion unit. The first multi-rail DC-DC converter unit includes three independent DC-DC chips: core rail, IO rail, and memory rail. Its power output is used to connect to the three power rails of the CPU built into the core control board of the network gateway. The second multi-rail DC-DC converter unit includes three independent DC-DC chips: core rail, IO rail, and memory rail. Its power output is used to connect to the three power rails of the CPU built into the data isolation board of the network gateway. The FPGA hierarchical redundancy control module is used to perform hierarchical power-on timing control: first, it sends an enable signal to the first multi-power rail DC-DC conversion unit; after the PowerGood signal of all power rails on the corresponding side of the core control board is pulled high and the voltage is stable, it sends an enable signal to the second multi-power rail DC-DC conversion unit after an interval of 12-15ms, so as to realize the dual motherboard staggered power-on; at the same time, it is used to control the high-speed power switching chip to complete the millisecond-level seamless switching between the two input power supplies when the bus voltage and branch power rail voltage collected by the voltage monitoring module are detected to be undervoltage or overvoltage faults in the current main input power supply.

[0007] Furthermore, the FPGA hierarchical redundancy control module includes a power state arbitration unit, a hierarchical timing configuration unit, a fault marker storage unit, and a switching drive unit. The hierarchical timing configuration unit has built-in programmable timing parameters and pre-stores at least two sets of independent single-board power-up parameters, corresponding to two CPU architectures with different power-up timing sequences: the first type of CPU single-board power-up sequence is core rail → memory rail → IO rail, with an interval of 5-10ms between rails; the second type of CPU single-board power-up sequence is IO rail → memory rail → core rail, with an interval of 8-12ms between rails; the power-up interval across dual-boards is uniformly 12-15ms, and the timing parameters support online programming modification.

[0008] Furthermore, the voltage monitoring module is divided into a bus-level monitoring subunit and a power rail-level monitoring subunit. The bus-level monitoring subunit simultaneously collects the output voltage of the two input power supplies and the bus voltage after switching, realizing input fault prediction and real-time monitoring of the bus status. The voltage judgment threshold range is DC 10.8V to 13.2V. If it exceeds the range, it is judged as an input power supply fault. The power rail-level monitoring subunit is used to synchronously sample the static voltage and ripple amplitude of the three power rails output from the two DC-DC conversion units. The ripple judgment threshold is no greater than 50mV, which is used to identify voltage drift caused by DC-DC chip aging.

[0009] Furthermore, the high-speed power switching chip adopts a zero-dead-time switching architecture, with a built-in reverse current blocking circuit. The switching delay is ≤2ms, and the bus voltage drop amplitude during the switching process is lower than the CPU reset threshold, thus not triggering the power reset of the back-end motherboard.

[0010] Furthermore, both input power supplies of the dual redundant input power supply module are AC-DC power supply modules with built-in surge suppression and common-mode filtering circuits. The two power supplies use independent ground wire wiring with a ground wire spacing of ≥8mm to avoid voltage misjudgment caused by common-mode interference.

[0011] Furthermore, each DC-DC chip in the first and second multi-power-rail DC-DC conversion units has its own independent PowerGood signal output terminal; the FPGA hierarchical redundancy control module combines the PowerGood signal level with the voltage data collected by the power rail-level monitoring subunit to dual-determine the power-on readiness status of the corresponding power rail, thereby improving the accuracy of the determination.

[0012] On the other hand, the present invention provides a hierarchical redundancy timing control method for a dual-motherboard network gateway, applied to the above-mentioned hierarchical redundancy power supply circuit, comprising the following steps: S1: The entire device is powered on, the FPGA hierarchical redundancy control module completes initialization, automatically identifies the CPU architecture type of the two motherboards, and matches the corresponding power rail power-on timing parameters of the board. S2: The high-speed power switching chip is switched to the first input power supply by default. The voltage monitoring module collects the bus voltage of the dual input power supply and the voltage and ripple data of the three power rails output by the two DC-DC conversion units in real time and in parallel. S3: First, start the first multi-power rail DC-DC conversion unit corresponding to the core control board, and power it on in sequence according to the matching CPU rail timing. After all power rails on the corresponding side of the core control board are stable, the core control board is determined to be ready for power supply. S4: After a delay of 12-15ms, the second multi-rail DC-DC conversion unit corresponding to the data isolation board is started, and the CPU on the isolation board side is powered on in stages simultaneously. The independent power supply timing of the two motherboards is established, and the system enters normal operation. S5: During operation, the voltage monitoring data is compared with the preset threshold in real time. If the current main input power supply fails, the FPGA immediately drives the high-speed power switching chip to switch to the backup input power supply. After the switching is completed, the fault parameters are recorded to the fault mark storage unit. S6: If the backup power supply also malfunctions after switching, or the number of switching times within the set period reaches the threshold, the power rails corresponding to the data isolation board and the core control board will be shut down in reverse order, and the equipment will be safely powered down according to the graded power-down sequence, and an alarm signal will be output synchronously.

[0013] Furthermore, in step S6, the power-down sequence and power-up sequence are strictly matched in reverse order: the power rails corresponding to the data isolation board are turned off first in the reverse order of power-up, and after an interval of ≥15ms, the power rails corresponding to the core control board are turned off in the reverse order of power-up to avoid reverse current backflow damaging the DC-DC chip.

[0014] Furthermore, the specific conditions for determining that the core control board is ready for power supply in step S3 are: the PowerGood signal of all three power rails is at a high level, and the output voltage deviation does not exceed ±2%, and this state remains stable for more than 10ms.

[0015] Furthermore, the fault parameters recorded in step S5 include fault type, occurrence time, and voltage waveform snapshot at the time of the fault; after the switching is completed, continuous monitoring is performed for 30 seconds. If the number of power switching times within 30 seconds is ≥3, it is determined that both power supplies are abnormal, triggering the graded safety power-off process.

[0016] By adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art. Of course, any product implementing the present invention does not necessarily need to achieve all of the following advantages at the same time: This invention features a hierarchical staggered power-on logic based on the functional priority design of dual motherboards in a network gateway. This staggers the peak bus current, eliminates the risk of voltage drops, and solves the problems of inconsistent configuration verification and data transmission interruptions caused by parallel power-on of dual motherboards. Coupled with a zero-dead-zone high-speed switching architecture, it achieves millisecond-level seamless power switching, avoiding device reset and shutdown during the switching process, and significantly reducing the failure rate related to network gateway power supply. Furthermore, it boasts strong multi-architecture CPU compatibility, employing an FPGA programmable timing configuration scheme with multiple built-in power-on timing parameters. It can adapt to different processor architectures with different power-on logic without modifying the hardware circuit, shortening product iteration cycles, reducing hardware modification costs, and significantly improving fault maintenance efficiency. This invention adopts a dual-layer voltage monitoring architecture at the bus level and power rail level, coupled with a non-volatile fault marker storage unit, which can automatically distinguish fault types such as input mains surges, power module aging, and DC-DC chip drift, directly locating the fault point and significantly shortening manual troubleshooting time. Moreover, all components in the entire chain are independently controllable, with domestic alternatives available for core components, meeting the compliance and access requirements for classified network security equipment.

[0017] The specific embodiments of the present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings described below are merely some embodiments. Those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings: Figure 1 This is a hardware topology diagram of the hierarchical redundant power supply circuit described in this invention; Figure 2 This is a flowchart of the hierarchical redundancy timing control method described in this invention; Figure 3 This is a schematic diagram of the timing waveforms for the dual-motherboard hierarchical power-on of the present invention.

[0019] It should be noted that these accompanying drawings and textual descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art by referring to specific embodiments. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to specific embodiments. These embodiments are only used to explain the present invention and are not intended to limit the scope of protection of the present invention.

[0021] like Figure 1 As shown, this embodiment is adapted to a 2U rack-mounted dual-motherboard unidirectional network gateway. The internal network side is a core control board equipped with Phytium D2000 / 8 CPU, and the external network side is a data isolation board equipped with Hygon 3490 CPU. The whole machine is deployed in a classified data center, requiring zero packet loss during power failure switching and meeting the Level 3 compliance requirements of information security protection.

[0022] I. Specific Implementation of Circuit Hardware This hierarchical redundant power supply circuit adopts a four-layer architecture of "dual-input redundancy + FPGA centralized timing control + dual-layer voltage monitoring + dual independent DC-DC power rails". The specific implementation of each module is as follows: The dual-redundant input power supply module employs two independent AC-DC power modules. The input is 220V AC mains power, and the output is a 12V DC bus. The rated power of each module meets the peak load requirements of the entire unit. Both power input circuits are equipped with thermistors and common-mode inductors to achieve surge suppression and electromagnetic interference filtering. The two power supplies use independent grounding wiring with a grounding distance ≥8mm to avoid voltage sampling misjudgments caused by common-mode crosstalk. There is no hardware distinction between primary and backup power supplies; the primary / backup status is dynamically arbitrated by the FPGA.

[0023] The high-speed power switching chip adopts a zero-dead-time architecture and has a built-in reverse current blocking circuit. It supports a maximum bus current of 40A, and the measured average switching delay is ≤1.7ms. During the switching process, the bus voltage drops by a maximum of 0.12V, which is far below the CPU reset threshold of 0.5V and meets the design specification of ≤0.15V. The switching process will not trigger the motherboard reset, achieving seamless redundant switching.

[0024] The voltage monitoring module adopts a two-layer monitoring architecture: Bus-level monitoring subunit: Real-time voltage of 12V bus is acquired through differential sampling resistor at a sampling frequency of 1kHz. The undervoltage threshold is set to 10.8V and the overvoltage threshold is set to 13.2V. If the voltage exceeds the range, it is determined to be an input power supply fault. Power rail level monitoring subunit: The static voltage and ripple amplitude of the core rail (1.2V), IO rail (3.3V), and memory rail (1.8V) output by the two DC-DC conversion units are collected by high-precision operational amplifiers. The ripple judgment threshold is 50mV, which can identify voltage drift caused by DC-DC chip aging.

[0025] The FPGA hierarchical redundancy control module uses a low-power domestic FPGA chip with a static power consumption of ≤50mW and an operating temperature range of -40℃ to 85℃, making it suitable for complex computer room environments. The I / O ports directly interface with 6 DC-DC PowerGood signals without requiring additional level conversion. The FPGA integrates four major functional units: Hierarchical timing configuration unit: Stores two independent sets of single-board timing parameters and cross-board delay parameters, which correspond to the power-on logic of Phytium series and Hygon series CPUs respectively. It supports JTAG online programming modification and can adapt to different CPUs without modifying the hardware. Power status arbitration unit: It integrates three information channels, namely bus voltage, power rail voltage and DC-DC PowerGood signal, to comprehensively determine the fault status. Compared with single bus determination, the fault identification accuracy is higher and false switching is avoided. Switching drive unit: Outputs nanosecond-level drive level to control high-speed power switching chip, ensuring rapid response of switching action; Fault marking storage unit: Built-in 128KB non-volatile storage space, automatically records fault type, occurrence time, voltage waveform snapshot at the time of fault, supports direct output of fault code, no need for manual segment-by-segment troubleshooting.

[0026] The first and second multi-rail DC-DC converters both use integrated three-output DC-DC chips, with each output having its own independent PowerGood signal. The static power consumption is less than 0.6W, and the power ripple is controlled within 32mV, meeting the power supply accuracy requirements of domestic CPUs and adapting to 24 / 7 uninterrupted operation scenarios.

[0027] II. Specific Configuration of Hierarchical Timing For the dual-CPU architecture in this embodiment, the timing parameters are configured as follows: Core control board (Phytium D2000 / 8): The power-on sequence of the board is core rail → memory rail → IO rail, with an interval of 7ms between rails; Data isolation board (Hygon 3490): The power-on sequence of the board is IO rail → memory rail → core rail, with an interval of 10ms between rails; The timing waveforms of the dual-motherboard staged power-on are as follows: Figure 3 As shown, the power-on delay of the dual motherboards across boards is fixed at 13ms. Actual testing shows that this timing configuration can reduce the instantaneous peak current of the bus from 32A to 19A, effectively eliminating the bus voltage drop at power-on.

[0028] III. Complete Process of Timing Control Method like Figure 2 As shown, the control flow of this embodiment is divided into five stages: initialization self-test, core board priority power-on, cross-board delayed power-on, normal real-time monitoring, fault switching and graded power-off. The specific steps are as follows: Initialization self-test phase: After the whole machine is powered on, the FPGA first reads the CPU version registers of the two motherboards, automatically identifies the CPU architecture type, and calls the corresponding built-in timing parameters; at the same time, it self-tests the integrity of the dual input power supply and voltage monitoring module link, and enters the power-on process after confirming that there are no hardware faults.

[0029] Core board priority power-on phase: The FPGA controls the high-speed power switching chip to switch to the first input power supply by default, and then sends an enable signal to the first multi-power rail DC-DC conversion unit. The core rail, memory rail and IO rail are started in sequence according to the Phytium CPU's native timing sequence. The FPGA reads the three PowerGood signals in a loop. When all signals are high and the voltage error is ≤±2% for more than 10ms, it is determined that the core control board is ready for power supply.

[0030] Cross-board delayed power-on stage: After the core control board is powered on, the FPGA executes a fixed 13ms delay to avoid the peak value of the bus surge current; then it sends an enable signal to the second multi-power rail DC-DC conversion unit, and starts the IO rail, memory rail and core rail in sequence according to the native timing of the Hygon CPU, completing the hierarchical power-on of the data isolation board; at this point, the independent power supply timing of the dual motherboards is established, and the system enters normal operation.

[0031] In the normal real-time monitoring phase: the dual-layer voltage monitoring modules run in parallel, and the FPGA completes full-point sampling every 1ms, comparing the bus voltage, power rail voltage and ripple preset thresholds in real time to distinguish between two types of abnormalities: slight voltage drift and power hard fault.

[0032] Fault switching and graded power-down phases: Single-channel power supply failure: When the current main input power supply voltage is detected to exceed the threshold, the FPGA switching drive unit immediately outputs a drive signal, and the high-speed power switching chip completes the seamless switching to the backup power supply within 2ms; after the switching is completed, the fault mark storage unit records the fault parameters; then it continuously monitors for 30s. If the number of switching times is less than 3 and there are no secondary abnormalities within 30s, normal operation is restored.

[0033] Dual power supply failure: If the number of switching operations is ≥3 within 30 seconds, or if the backup power supply also experiences voltage abnormalities after switching, a reverse hierarchical safety power-off will be triggered: the power rails corresponding to the data isolation board will be shut down first, and the power rails corresponding to the core control board will be shut down after an interval of 15ms to avoid reverse current damage to the DC-DC chip; at the same time, an alarm signal will be output to the host computer to complete the safe shutdown of the equipment.

[0034] IV. Verification of Actual Results Based on actual measurements, the solution in this embodiment, compared to traditional diode or gate redundant power supplies, shows the following: The failure rate of power-on links related to dual motherboards decreased from 11.3% to 0.09%; There was no data packet loss or device reset during the power switching process, resulting in a 99.2% reduction in downtime failure rate. The average troubleshooting time for power supply failures has been reduced from 2.3 hours to less than 12 minutes, improving maintenance efficiency by 91%.

[0035] This invention is not limited to the embodiments described above. Anyone should understand that structural changes made under the guidance of this invention, and any technical solutions that are the same as or similar to this invention, fall within the protection scope of this invention. Technical aspects, shapes, and structures not described in detail in this invention are all publicly known technologies.

Claims

1. A hierarchical redundant power supply circuit for a dual-mainboard network gateway, characterized in that, It includes a dual-redundant input power supply module, an FPGA hierarchical redundancy control module, a voltage monitoring module, a first multi-power rail DC-DC conversion unit, and a second multi-power rail DC-DC conversion unit; The dual-redundant input power module includes a first input power supply and a second input power supply that are independent of each other. The output terminals of both input power supplies are connected to a high-speed power switching chip. The output bus of the high-speed power switching chip is connected to the input terminal of the voltage monitoring module, the input terminal of the first multi-rail DC-DC conversion unit, and the input terminal of the second multi-rail DC-DC conversion unit, respectively. The FPGA hierarchical redundancy control module is electrically connected to the control terminal of the high-speed power switching chip, the signal output terminal of the voltage monitoring module, the enable terminal of the first multi-power rail DC-DC conversion unit, and the enable terminal of the second multi-power rail DC-DC conversion unit, respectively. The FPGA hierarchical redundancy control module is used to receive multiple PowerGood signals fed back by the first multi-power rail DC-DC conversion unit and the second multi-power rail DC-DC conversion unit. The first multi-power rail DC-DC conversion unit includes three independent DC-DC chips: core rail, IO rail, and memory rail. Its power output terminal is used to connect to the three power rails of the CPU built into the network gateway core control board. The second multi-power rail DC-DC conversion unit includes three independent DC-DC chips: core rail, IO rail, and memory rail. Its power output terminal is used to connect to the three power rails of the CPU built into the network gateway data isolation board. The FPGA hierarchical redundancy control module is used to perform hierarchical power-on timing control: first, it sends an enable signal to the first multi-power rail DC-DC conversion unit; after the PowerGood signal of all power rails on the corresponding side of the core control board is pulled high and the voltage is stable, it sends an enable signal to the second multi-power rail DC-DC conversion unit after an interval of 12-15ms, so as to realize the dual motherboard staggered power-on; at the same time, it is used to control the high-speed power switching chip to complete the millisecond-level seamless switching of the two input power supplies when the bus voltage and branch power rail voltage collected by the voltage monitoring module are detected to be undervoltage or overvoltage faults in the current main input power supply.

2. The hierarchical redundant power supply circuit for a dual-motherboard network gateway according to claim 1, characterized in that, The FPGA hierarchical redundancy control module includes a power state arbitration unit, a hierarchical timing configuration unit, a fault mark storage unit, and a switching drive unit. The hierarchical timing configuration unit has built-in programmable timing parameters and pre-stores at least two sets of independent single-board power-on parameters, corresponding to two different CPU architectures with different power-on timing sequences: For the first type of CPU, the power-on sequence of a single motherboard is core rail, memory rail, and I / O rail, with an interval of 5ms to 10ms between rails; for the second type of CPU, the power-on sequence of a single motherboard is I / O rail, memory rail, and core rail, with an interval of 8ms to 12ms between rails; the power-on interval for dual motherboards across boards is uniformly 12ms to 15ms. The timing parameters support online programming modification.

3. The hierarchical redundant power supply circuit for a dual-motherboard network gateway according to claim 1, characterized in that, The voltage monitoring module is divided into a bus-level monitoring subunit and a power rail-level monitoring subunit. The bus-level monitoring subunit is used to sample the DC bus output voltage of the dual-input power supply. The voltage judgment threshold range is DC 10.8V to 13.2V. If it exceeds the range, it is judged as an input power supply fault. The power rail level monitoring subunit is used to synchronously sample the static voltage and ripple amplitude of the three power rails output by the two DC-DC conversion units. The ripple judgment threshold is no greater than 50mV, which is used to identify voltage drift caused by DC-DC chip aging.

4. The hierarchical redundant power supply circuit for a dual-motherboard network gateway according to claim 1, characterized in that, The high-speed power switching chip adopts a zero-dead-time switching architecture and has a built-in reverse current blocking circuit. The switching delay is ≤2ms. During the switching process, the bus voltage drop amplitude is lower than the CPU reset threshold, and the power reset of the back-end motherboard is not triggered.

5. The hierarchical redundant power supply circuit for a dual-motherboard network gateway according to claim 1, characterized in that, Both input power supplies of the dual-redundant input power supply module are AC-DC power supply modules with built-in surge suppression and common-mode filtering circuits. The two power supplies use independent ground wire wiring with a ground wire spacing of ≥8mm.

6. The hierarchical redundant power supply circuit for a dual-motherboard network gateway according to claim 1, characterized in that, Each DC-DC chip in the first multi-power rail DC-DC converter unit and the second multi-power rail DC-DC converter unit has its own independent PowerGood signal output terminal; The FPGA hierarchical redundancy control module combines the PowerGood signal level with the voltage data collected by the power rail-level monitoring subunit to dually determine the power-on readiness status of the corresponding power rail.

7. A hierarchical redundancy timing control method for a dual-mainboard network gateway, applied to the hierarchical redundancy power supply circuit according to any one of claims 1-6, characterized in that, Includes the following steps: S1: The entire device is powered on, the FPGA hierarchical redundancy control module completes initialization, automatically identifies the CPU architecture type of the two motherboards, and matches the corresponding power rail power-on timing parameters of the board. S2: The high-speed power switching chip is switched to the first input power supply by default. The voltage monitoring module collects the bus voltage of the dual input power supply and the voltage and ripple data of the three power rails output by the two DC-DC conversion units in real time and in parallel. S3: First, start the first multi-power rail DC-DC conversion unit corresponding to the core control board, and power it on in sequence according to the matching CPU rail timing. After all power rails on the corresponding side of the core control board are stable, the core control board is determined to be ready for power supply. S4: After a delay of 12-15ms, the second multi-rail DC-DC conversion unit corresponding to the data isolation board is started, and the CPU on the isolation board side is powered on in stages simultaneously. The independent power supply timing of the two motherboards is established, and the system enters normal operation. S5: During operation, the voltage monitoring data is compared with the preset threshold in real time. If the current main input power supply fails, the FPGA immediately drives the high-speed power switching chip to switch to the backup input power supply. After the switching is completed, the fault parameters are recorded to the fault mark storage unit. S6: If the backup power supply also malfunctions after switching, or the number of switching times within the set period reaches the threshold, the power rails corresponding to the data isolation board and the core control board will be shut down in reverse order, and the equipment will be safely powered down according to the graded power-down sequence, and an alarm signal will be output synchronously.

8. The hierarchical redundancy timing control method for a dual-mainboard network gateway according to claim 7, characterized in that, In step S6, the power-down sequence and power-up sequence are strictly matched in reverse order: the power rails corresponding to the data isolation board are turned off first in the reverse order of power-up, and after an interval of ≥15ms, the power rails corresponding to the core control board are turned off in the reverse order of power-up to avoid reverse current backflow damaging the DC-DC chip.

9. A hierarchical redundancy timing control method for a dual-mainboard network gateway according to claim 7, characterized in that, The specific conditions for determining that the core control board is ready for power supply in step S3 are: the PowerGood signal of all three power rails is at a high level, the output voltage deviation does not exceed ±2%, and this state remains stable for more than 10ms.

10. A hierarchical redundancy timing control method for a dual-mainboard network gateway according to claim 7, characterized in that, The fault parameters recorded in step S5 include fault type, occurrence time, and voltage waveform snapshot at the time of fault. After the switching is completed, continuous monitoring is performed for 30 seconds. If the number of power switching times is ≥3 within 30 seconds, it is determined that both power supplies are abnormal, triggering the graded safety power-off process.

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