Multi-slot electric energy remote terminal

Abstract

The application provides a multi-slot electric energy remote terminal, and belongs to the technical field of electric power monitoring. The multi-slot electric energy remote terminal comprises a master control unit, a USB HUB chip, a plurality of USB-to-serial chip and a plurality of physical slots fixedly connected, and the physical slots are used for connecting external serial port devices. The master control unit has a USB port independent power supply control circuit. The master control unit is configured to sequentially power on and enumerate each USB-to-serial chip in the order determined by the slot number of the connected physical slot. In the enumeration process of the USB-to-serial chip, the target slot number is determined, and a fixed symbolic link node is generated based on the target slot number. A symbolic link mapping between the fixed symbolic link node and the original serial port device node is established to access the original serial port device node based on the fixed symbolic link node, and permanent binding of the physical slot and the serial port device access entry is realized. The application can improve the stability and reliability of the electric energy remote terminal serial port acquisition channel.

Description

Technical Field

[0001] This application belongs to the field of power monitoring technology, and more specifically, relates to a multi-slot power energy remote terminal. Background Technology

[0002] The remote power terminal is a core business device in substations for acquiring, freezing, and remotely transmitting power data, requiring extremely high stability and reliability of the acquisition channels. Existing multi-channel power terminals generally use a USB hub to expand multiple USB-to-serial ports to achieve multi-serial port data acquisition, command issuance, and remote communication. This traditional architecture has the following technical drawbacks: Linux system USB device enumeration is susceptible to interference from factors such as power-on timing differences, bus bandwidth contention, and hot-plug level jitter. After a device reboot or hot-plugging, serial port drift may occur, meaning that the serial port character device name assigned by the system will change randomly, causing misalignment between the physical slot and the software acquisition channel, which in turn leads to problems such as incorrect matching of power energy acquisition data and abnormal channel services.

[0003] To address the serial port drift issue, existing technologies commonly employ software binding schemes based on the serial numbers of USB-to-serial chips. Since each USB-to-serial chip has a unique and non-repeating serial number, mass production requires reading the serial number for each board and configuring binding rules for each device individually, resulting in low production efficiency. Furthermore, during later field maintenance, if a board fails and needs replacement, the new board's serial number will differ from the original configuration, necessitating a complete overhaul of the system binding rules and acquisition channel configurations, preventing direct board replacement and reuse. Additionally, this binding method uses the board's identity as the anchor point rather than the physical slot; after board swapping, the acquisition channel migrates with the board, failing to meet the requirement of fixed slot channels, leading to poor adaptability and a heavy maintenance workload. Summary of the Invention

[0004] The purpose of this application is to provide a multi-slot remote power terminal to solve the technical problems of serial port drift and mismatch of serial port channels that occur in existing multi-channel USB to serial port methods, thereby improving the stability and reliability of the serial port acquisition channel operation of the remote power terminal. To achieve the above objective, the technical solution of this application is as follows: A multi-slot remote power terminal includes a main control unit, a USB HUB chip, multiple USB to serial port chips, and multiple physical slots; The uplink port of the USB HUB chip is connected to the main control unit, and the multiple downlink ports of the USB HUB chip are respectively connected to the USB ports of multiple USB to serial port chips. The serial port signal terminal of each USB to serial port chip is connected to the corresponding physical slot to connect to an external serial port device. The main control unit has an independent power management circuit for the USB port, and the main control unit is configured as follows: According to the order determined by the slot number of the connected physical slot, each USB to serial port chip is powered on and enumerated in turn. Specifically, for each slot number, the power-on enumeration steps for the corresponding USB-to-serial chip include: Read the physical serial number of the downstream port to which the USB-to-serial chip is connected; Perform USB device enumeration on the USB-to-serial chip to generate the original serial device node; Based on the slot number, find the preset slot port mapping relationship and determine the target port number; If the target port number is consistent with the physical number, then the slot number is used as the target slot number; If the target port number is inconsistent with the physical number, the slot port mapping relationship is found based on the physical number to obtain the target slot number; A fixed symbolic link node is generated based on the target slot number, and a symbolic link mapping is established between the fixed symbolic link node and the original serial port device node, so as to access the original serial port device node based on the fixed symbolic link node, thereby realizing the permanent binding of the physical slot and the serial port device access entry.

[0005] In one embodiment of this application, when performing USB device enumeration on the USB-to-serial chip, the main control unit is configured as follows: If all downstream ports of the corresponding USB HUB chip are online during the first monitoring period after the USB-to-serial chip is powered on, then USB device enumeration is performed on the USB-to-serial chip.

[0006] In one embodiment of this application, the multiple downlink ports of the USB HUB chip are connected to the USB ports of the multiple USB-to-serial chips, and the serial port signal terminal of each USB-to-serial chip is connected to the physical slot through PCB wiring.

[0007] In one embodiment of this application, the physical slots are connected to different external serial port devices through different types of plug-in boards. Each physical slot is provided with an ID identification pin. The ID identification pin is connected to the main control unit through a pull-up resistor. The plug-in board is provided with an ID matching pin that is plugged into the ID identification pin. Each type of plug-in board outputs the corresponding high and low level codes by grounding or floating the ID matching pin. After performing USB device enumeration, the host control unit is configured as follows: Read the level signal of the ID identification pin; The model of the plug-in board is determined based on the level signal of the ID identification pin; If the plug-in board is a smart plug-in board, then determine the slot number of the physical slot corresponding to the plug-in board, and send an identity query command to the plug-in board through the serial port device node corresponding to the slot number; In response to receiving the identity information returned by the plug-in board, the corresponding driver dynamic library is dynamically loaded from the preset HAL driver library based on the identity information.

[0008] In one embodiment of this application, before sending an identity query command to the board via the serial port device node corresponding to the slot number, the main control unit is configured as follows: The serial port device node corresponding to the slot number sends an integrated request packet to the board; the integrated request packet carries the master control random challenge, the master control identity signature and the master control key negotiation public key. The integrated response packet returned by the plug-in board is received to complete the mutual exchange of the master key negotiation public key and the peripheral key negotiation public key; the integrated response packet is generated by the plug-in board after verifying the legality of the master identity signature, and the integrated response packet carries the peripheral identity signature, the peripheral random challenge and the peripheral key negotiation public key; Verify the validity of the peripheral device identity signature; If the validity of the master control identity signature and the validity of the peripheral identity signature are both verified, then a session key negotiation is performed based on the exchanged master control key negotiation public key and peripheral key negotiation public key. The step of sending an identity query command to the board via the serial port device node corresponding to the slot number includes: The identity query command is encrypted using the negotiated session key, and then sent to the board via the serial port device node corresponding to the slot number.

[0009] In one embodiment of this application, for each physical slot, the main control unit is configured as follows: If all the in-situ pins of the physical slot are displayed as disconnected within the preset second monitoring period, the power-down process will be executed in the order of service callback stop, driver instance unload, device node deregistration, and slot power cut-off.

[0010] In one embodiment of this application, the multi-slot power remote terminal further includes a clock module; the clock module is configured to: Detect the validity of the B-code input signal; If a valid B-code input signal is detected, B-code phase-locked loop calibration is performed to synchronize the local RTC clock to the time base of the B-code master clock, thus obtaining the system clock after initial synchronization. If no B code input signal is detected, the system enters the initial timekeeping mode, reads the time stored in the local RTC clock as the timing reference, and obtains the system clock after initial synchronization. After obtaining the system clock after initial synchronization, continuously monitor the B code input signal; If multiple consecutive frames of invalid B code input signals are detected, it is determined that the B code input signal is lost, and the working mode of the clock module is seamlessly switched to the steady-state timekeeping mode. If multiple consecutive frames of valid B-code input signals are detected in steady-state timekeeping mode, the current time of the local RTC clock and the reference clock time of the B-code input signal are read, the time deviation between the current time of the local RTC clock and the reference clock time of the B-code input signal is calculated, and the current time of the local RTC clock is uniformly adjusted to the reference clock time of the B-code input signal within a preset calibration time, so as to smoothly switch the working mode of the clock module to the B-code synchronization mode.

[0011] In one embodiment of this application, after obtaining the initially synchronized system clock, the clock module is configured as follows: Output PPS pulse signals to the main control unit and the GPIO interrupt pins of each physical slot; Within the first millisecond-level time window after the rising edge of the PPS pulse signal, a serial time message carrying absolute calendar time information is sent to the main control unit so that the main control unit forwards the serial time message to each physical slot. The PPS pulse signal and serial time message are used to indicate the start time of the second locked by each physical slot based on the rising edge of the PPS pulse signal, and to parse the absolute time by combining the received serial time message, so as to realize the clock synchronization between each physical slot and the main control unit.

[0012] In one embodiment of this application, the clock module is further configured to: Start the first timer; the counting frequency of the first timer is proportional to the frequency of the local crystal oscillator; A reference PPS pulse signal is obtained from a preset pin. If the reference PPS pulse signal meets the preset validity verification conditions, the reference PPS pulse signal is used as the reference PPS signal. In the periodic interrupt routine of the reference PPS signal, the total value of the first timer is read; Calculate the average count of multiple consecutive total values; Calculate the count difference between the average count value and the preset ideal count value; The local microsecond timing is compensated and calibrated based on the count difference.

[0013] In one embodiment of this application, when compensating and calibrating the local microsecond timing based on the count difference, the clock module is further configured to: The timing interval corresponding to a single microsecond compensation is calculated based on the count difference. The timing duration is incremented in the interrupt routine of the second timer; When the timing duration reaches the specified timing interval, perform a microsecond compensation on the local microsecond timing and reset the timing duration to zero.

[0014] The beneficial effects of the multi-slot remote power terminal provided in this application embodiment are as follows: The application embodiment first solidifies the connection relationship between multiple downstream ports of the USB HUB chip, multiple USB-to-serial chips, and multiple physical slots. Then, based on the independent power management capability of the USB ports of the main control unit, the onboard USB-to-serial chips of each USB HUB chip are powered on in time-sharing order according to the physical slot number, and the devices are enumerated one by one. The power supply of the next slot is started only after the previous slot is enumerated. This eliminates the bus race and timing disorder problems of concurrent enumeration from the source and accurately controls the device enumeration order.

[0015] Furthermore, a slot-port mapping relationship between multiple physical slots and multiple downlink ports is pre-constructed. During the power-on enumeration phase of the USB-to-serial chip, the main control unit reads the physical serial number of the downlink port of the USB HUB chip and the corresponding current slot number, and performs a consistency check with the preset slot-port mapping relationship. That is, based on the current slot number, the preset slot-port mapping relationship is searched to determine the target port number. If the target port number is consistent with the physical serial number, the current slot number is used as the target slot number; if the target port number is inconsistent with the physical serial number, the slot-port mapping relationship is searched based on the physical serial number to obtain the target slot number.

[0016] Based on the verified target slot number M, the original serial port device node / dev / ttyN dynamically generated after the USB to serial port chip is enumerated upon power-up is bound to the fixed mapping node / dev / ttymapM that corresponds one-to-one with the physical slot through symbolic links. By accessing the serial port device through the fixed / dev / ttymapM node, the serial port device access entry can be permanently and firmly bound to the physical slot, effectively avoiding the serial port device node sequence number drift problem caused by enumeration anomalies and power fluctuations. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a hardware system architecture diagram of a multi-slot power remote terminal provided in an embodiment of this application; Figure 2 This is a schematic diagram of the power-on enumeration process of a USB-to-serial port chip provided in an embodiment of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] To facilitate understanding, the main terms used in this application will be explained first.

[0021] USB device enumeration: After the USB host (such as the main control unit in this embodiment) detects that a USB device (such as the USB to serial port chip in this embodiment) is powered on and connected, a standard identification and configuration interaction process is completed between the host and the USB device: The host first identifies the device connection, reads the device descriptor and configuration descriptor, allocates a USB address, loads the corresponding driver, and finally generates a hardware device node that the operating system can access.

[0022] PPS (Pulse Per Second) signal: Outputs a pulse signal once per second. The rising edge of the pulse represents the start time of the whole second. It only provides the edge of the second time and does not carry absolute calendar time such as year, month, day, hour, and minute.

[0023] B-code input signal (IRIG-B time code): Abbreviated as B code, it is the standard time code for substation power systems. It adopts serial encoding, and one signal carries the absolute calendar time (year, month, day, hour, minute, second) at the same time. It can also parse and output one PPS second pulse.

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0025] Please refer to Figure 1 , Figure 1 A hardware system architecture diagram of a multi-slot power remote terminal provided in an embodiment of this application includes: (1) Motherboard It adopts the domestically produced industrial-grade RK3568 processor (main control unit) as the core of global computing power and the carrier of the root of trust. The quad-core Cortex-A55 architecture is responsible for core functions such as service scheduling, protocol parsing, data storage, security monitoring, and clock management; it is pre-installed with a national cryptographic key as the hardware root of trust for the whole machine to boot.

[0026] (2) Multi-protocol pluggable slot unit The motherboard can be inserted into 8 physical slots simultaneously for connecting external multi-function expansion boards, including: Common serial port boards: RS485 acquisition board, RS232 expansion board, pure hardware level conversion architecture, serial port type is identified by hardware IO level; supports multi-protocol meter acquisition such as DL / T645-07, DL / T698, DLMS, etc. Intelligent plug-in board: The board is equipped with a domestically produced real-time coprocessor chip GD32F303, including a remote control output plug-in board, a remote signaling input plug-in board, and a CAN communication plug-in board; the plug-in board has a built-in unique national cryptographic identity key and a standardized identity recognition protocol, and actively reports the identity message after power-on.

[0027] (3) Multi-link master station communication unit A wired + wireless dual-redundancy architecture is adopted to achieve parallel communication with multiple master stations that are physically isolated: Wired communication: Equipped with 6 Gigabit Ethernet ports, 2 of which are implemented through the RK3568 native RGMII interface, and 4 of which are implemented through PCIe bus expansion of independent network cards; each network port corresponds to an independent network namespace and protocol stack instance, supporting the parallel operation of multiple protocols such as IEC102, 1376.1, MQTTS, and IEC61850; Wireless communication: The 4G communication module adopts a dual-interface design of TTL configuration port + USB ECM data port, supporting remote communication with multi-protocol master stations.

[0028] (4) Domestically produced high-precision clock module The independent clock subsystem serves as the unified time reference for the entire station. Its core consists of a domestically produced GD32F303 clock co-control chip, a domestically produced industrial-grade RTC clock chip, a backup lithium-ion battery, and an IRIG-B code receiving serial port. It is directly connected to the RK3568 main control unit through a TTL timing serial port and a PPS second pulse pin.

[0029] (5) Human-computer interaction unit The local configuration serial port LCD screen communicates with the RK3568 main controller through an independent UART channel to realize local status display, parameter configuration and operation and maintenance debugging.

[0030] Each physical slot corresponds to one USB-to-serial chip (U to 4-channel serial) chip soldered on the motherboard. The external interface is 4-channel TTL level signals. The 8 USB-to-serial chips are uniformly connected to the 8 downstream ports of the domestic industrial-grade USB HUB chip on the motherboard. The specific connection relationship is as follows: the upstream port of the USB HUB chip is connected to the main control unit, the multiple downstream ports of the USB HUB chip are respectively connected to the USB ports of the multiple USB-to-serial chips, and the serial port signal terminal of each USB-to-serial chip is connected to the corresponding physical slot to connect to external serial devices.

[0031] Furthermore, the main control unit has an independent power management circuit for the USB port, and the main control unit is configured as follows: According to the slot number determined by the connected physical slots, each USB to serial port chip is powered on and enumerated in turn. After the enumeration of the USB to serial port chip of the previous downstream port is completed, the power supply of the next downstream port is turned on.

[0032] like Figure 2 As shown, for each slot number, the power-on enumeration steps of the USB-to-serial chip corresponding to that slot number include: S101: Read the physical serial number of the downstream port to which the USB to serial port chip is connected; S102: Perform USB device enumeration on the USB to serial port chip to generate the original serial port device node; S103: Based on the slot number, find the preset slot port mapping relationship and determine the target port number; S104: If the target port number is consistent with the physical number, then the slot number shall be used as the target slot number; S105: If the target port number is inconsistent with the physical number, the slot port mapping relationship is found based on the physical number to obtain the target slot number; S106: Generate a fixed symbolic link node based on the target slot number, and establish a symbolic link mapping between the fixed symbolic link node and the original serial port device node, so as to access the original serial port device node based on the fixed symbolic link node, thereby realizing the permanent binding between the physical slot and the serial port device access entry.

[0033] In this embodiment, the connection relationships between multiple downstream ports of the USB HUB chip, multiple USB-to-serial chips, and multiple physical slots are first solidified. Then, based on the independent power management capability of the USB ports of the main control unit RK3568, the onboard USB-to-serial chips of each USB HUB chip's downstream port are powered on in time-sharing order according to the physical slot number, with an interval of 200ms. The kernel enumerates the devices one by one according to the power-on sequence, and the next slot is powered on only after the previous slot is enumerated. This eliminates the bus race and timing disorder problems of concurrent enumeration from the source and accurately controls the device enumeration order.

[0034] It should be noted that powering on the downstream ports of the USB hub must be performed after the kernel has booted up to ensure that the kernel driver recognizes each USB hub chip individually. If each downstream port of the USB hub corresponds to multiple serial port numbers, for example, in this embodiment, each downstream port is connected to a USB-to-serial chip that is a U-to-4 serial chip, then the serial port numbers are sorted according to the interface descriptor order.

[0035] Furthermore, a slot-port mapping relationship between multiple physical slots and multiple downlink ports is pre-constructed. Based on this, during the power-on enumeration phase of the USB-to-serial chip, the main control unit reads the physical serial number of the downlink port of the USB HUB chip and the corresponding current slot number, and performs a consistency check with the preset slot-port mapping relationship. That is, based on the current slot number, the preset slot-port mapping relationship is searched to determine the target port number. If the target port number is consistent with the physical serial number, the current slot number is used as the target slot number; if the target port number is inconsistent with the physical serial number, the slot-port mapping relationship is searched based on the physical serial number to obtain the target slot number.

[0036] Based on the verified target slot number M, each raw serial port device node / dev / ttyN dynamically generated after the USB to serial port chip is powered on and enumerated is bound to a fixed mapping node / dev / ttymapM that corresponds one-to-one with the physical slot through symbolic links (if a physical slot corresponds to multiple serial ports, each serial port is numbered and a corresponding fixed mapping node / dev / ttymapM-x is generated). By accessing the serial port device through the fixed / dev / ttymapM node, the serial port device access entry can be permanently and firmly bound to the physical slot, effectively avoiding the serial port device node sequence number drift problem caused by enumeration anomalies and power fluctuations.

[0037] In one embodiment of this application, multiple downstream ports of the USB HUB chip are connected to the USB ports of multiple USB-to-serial chips, and the serial port signal terminal of each USB-to-serial chip is connected to the physical slot via PCB wiring.

[0038] In one embodiment of this application, for scenarios where the onboard USB-to-serial chip experiences power jitter, the first monitoring period after the USB-to-serial chip powers on is designated as the port power-on state stabilization window. Binding or unbinding logic is only executed when the port's online status remains stable without fluctuations within this window. This prevents power jitter from triggering false device online / offline events and avoids erroneous updates to the mapping relationship. The first monitoring period is a preset constant; those skilled in the art can set its specific value according to actual needs, for example, 200ms.

[0039] In one embodiment of this application, physical slots are connected to different external serial port devices through different types of plug-in boards. Each physical slot is provided with an ID identification pin, which is connected to the main control unit through a pull-up resistor. The plug-in board is provided with an ID matching pin that is plugged into the ID identification pin. Each type of plug-in board outputs the corresponding high and low level codes by grounding or floating the ID matching pin. After performing USB device enumeration, the host unit is configured as follows: Read the level signal of the ID identification pin; The board model is determined based on the level signal of the ID identification pin; If the plug-in board is a smart plug-in board, then determine the slot number of the physical slot corresponding to the plug-in board, and send an identity query command to the plug-in board through the serial port device node corresponding to the slot number; in response to receiving the identity information returned by the plug-in board, dynamically load the corresponding driver dynamic library from the preset Hardware Abstraction Layer Library (HAL driver library) based on the identity information.

[0040] In this embodiment, taking two ID recognition pins as an example, the encoding rules for the two ID recognition pins can be as follows: level 01 corresponds to the RS485 serial port board, level 10 corresponds to the RS232 serial port board, level 11 corresponds to the GD32F303 smart plug-in board, and level 00 is empty. The recognition action is completed within 20ms after the slot is powered on, which belongs to the first level of fast recognition.

[0041] Furthermore, an RC filter circuit can be added to the ID recognition pin to filter out transient spikes during insertion and removal. The main control unit uses a judgment logic that ensures consistency across three consecutive samples to avoid initial judgment errors caused by contact jitter. This mechanism achieves millisecond-level type screening through hardware level, separating ordinary serial port boards (RS485 and RS232 serial port boards) from intelligent plug-in boards: after ordinary serial port boards complete recognition, they directly enable the corresponding serial port channel for data interaction; after intelligent plug-in boards complete recognition, they need to initiate identity authentication through the corresponding serial port node, and load the corresponding driver dynamic library after successful authentication.

[0042] Specifically, during the authentication of the smart board, a two-way handshake mechanism of active query by the main control unit and response confirmation by the smart board can be adopted: After the ID recognition pin initially determines that it is a smart board, the main control unit sends an identity query command through the fixed serial port node corresponding to the physical slot; after the smart board is powered on and initialized, it immediately replies with a standardized description information frame upon receiving the command. The frame format adopts a fixed length design, with the frame header fixed at 0xEB 0x90 for frame synchronization, followed by the board type code (distinguishing between remote signaling / remote control / CAN subcategories), hardware major version number, hardware minor version number, and number of channels. A 16-bit CRC checksum is appended to the end of the frame to cover the entire frame data. The main control unit first verifies the frame header and frame length, and then verifies the data integrity through CRC. Only after receiving two consecutive valid responses with consistent content is the complete identity of the board locked; an 800ms total timeout window is set, and the board automatically retryes twice after the timeout. If the retry fails, an identification anomaly event is reported.

[0043] After identity verification, the main controller automatically matches the corresponding business configuration. For the three types of smart boards—remote signaling, remote control, and CAN—dynamic on-demand driver loading is implemented based on the HAL hardware abstraction layer. All three types of drivers are encapsulated as independent dynamic libraries, conforming to the unified slot device standard interface, and are completely decoupled from the upper-layer business logic.

[0044] Using the method in this embodiment, upper-layer services only need to call capabilities through a unified abstract interface, without needing to be aware of the differences in underlying board models and drivers; adding new board types only requires extending the corresponding HAL driver library, without modifying the business code, thus possessing good scalability and maintainability.

[0045] In one embodiment of this application, when authenticating the identity of a smart plug-in board, a national cryptographic algorithm (such as SM2) can be used to encrypt the identity query command. Existing embedded SM2 two-way authentication schemes all adopt a step-by-step challenge-response mode with at least two rounds of interaction (master controller sends challenge → peripheral device responds → peripheral device sends challenge → master controller responds). This embodiment packages the two-way identity signature, random challenge, and key negotiation public key into one request and one response, halving the number of interaction rounds without reducing security strength, making it suitable for low-computing-power peripherals and low-speed bus scenarios.

[0046] Step 1: The master control unit sends out an integrated request packet (1 request). The master control unit packages the master control random challenge R1, the master control SM2 identity signature, and the master control key negotiation public key into a single message and sends it to the peripheral device.

[0047] Step 2: The peripheral device (smart plug-in) returns an integrated response packet (1 response). The peripheral device completes all verifications and responses in one go, sending a single message back to the master controller to verify the validity of the master controller's SM2 signature and confirm that the master controller has not been tampered with and its identity is trustworthy. A random challenge R2 for the peripheral device is generated, and the peripheral device identity signature + random challenge R2 + peripheral device key negotiation public key are packaged and uploaded in one go.

[0048] Step 3: Both parties complete the remaining verifications and session key negotiation locally. Upon receiving the response, the master controller verifies the peripheral device's identity. If both the master controller's signature and the peripheral device's signature are verified, the peripheral device uses the negotiated public key exchanged by both parties to synchronously calculate the same session key using the master controller's negotiated public key.

[0049] Step 4: Encrypt the identity query command using the negotiated session key, and send the encrypted identity query command to the plugboard.

[0050] Furthermore, before performing two-way authentication between the main control unit and the smart plug-in board, the national cryptographic key built into the RK3568 can be used as a root of trust to build a complete trust chain step by step, with verification and transmission at each level, eliminating trust breakpoints. Specifically, after U-Boot starts, the integrity of the kernel image and device tree is verified through a digital signature algorithm. If the verification passes, the kernel starts; if it fails, the terminal is locked and system boot is prohibited. After the kernel starts, the digital signatures and file integrity of all driver modules to be loaded and core business applications are verified. If the verification passes, the main business program starts; if it fails, a restricted security maintenance mode is entered, prohibiting all data acquisition and communication services. The main business program verifies dynamically loaded protocol plugins and core configuration files. If the verification passes, the peripheral authentication process is initiated; if it fails, illegal configurations are disabled and business initialization is terminated. The above verification process, together with identity authentication, constitutes a four-level progressive complete trust chain.

[0051] The main controller and the slot board processor complete identity authentication through the national cryptographic algorithm; after the national cryptographic authentication is successful, the business identity handshake interaction is performed to obtain the board type information reported by the board, and the main controller loads the corresponding driver accordingly; if the single slot authentication fails, the slot power is immediately cut off and the illegal device is isolated without affecting the normal operation of the other slots.

[0052] In one embodiment of this application, for each physical slot, the main control unit is configured as follows: If all the in-situ pins of the physical slot are displayed as disconnected within the preset second monitoring period, the power-down process will be executed in the order of service callback stop, driver instance unload, device node deregistration, and slot power cut-off.

[0053] In this embodiment, to address the three core issues of contact jitter, resource residue, and bus interference in the hot-swapped scenario, a dual guarantee mechanism of jitter determination and orderly power-down can be adopted to achieve reliable hot-swapping and ensure uninterrupted service in other slots.

[0054] Debouncing determination: A second monitoring duration (e.g., 50ms) is preset as the stable window period for the port power-off state. The main control unit detects the pin level of the slot in real time. Only when the disconnected state is maintained continuously within the window period without any jump is it determined to be a valid unplugging event. Transient level changes caused by pin bounce and contact jitter during plugging and unplugging are directly determined as invalid events and filtered to avoid triggering repeated device deregistration and loading processes and prevent system resource oscillation.

[0055] Orderly Power Down: After confirming successful unplugging, the power down process is executed in the following order: service callback stop, driver instance unloading, device node deregistration, and slot power disconnection. First, the service layer is notified to stop all data interaction and task scheduling for that slot. Then, hardware resources such as memory and serial ports occupied by the driver are released, the corresponding device node and symbolic link are deregistered, and finally, the slot power supply is cut off. This sequence avoids driver resource leakage and device node residue caused by direct power-off, and prevents resource conflicts during subsequent board insertion.

[0056] In one embodiment of this application, the multi-slot power remote terminal further includes a clock module (GD32F303); the clock module is configured to: The validity of the B code input signal (IRIG-B code) is detected. If a valid B code input signal is detected, B code phase-locked loop calibration is performed to synchronize the local RTC clock to the time base of the B code master clock, thus obtaining the system clock after initial synchronization. If no B code input signal is detected, the system enters the initial timekeeping mode, reads the time stored in the local RTC clock as the timing base, and obtains the system clock after initial synchronization. After obtaining the system clock after initial synchronization, the B-code input signal is continuously monitored. If multiple consecutive frames of invalid B-code input signals are detected, it is determined that the B-code input signal is lost, and the clock module's operating mode is seamlessly switched to steady-state timekeeping mode. If multiple consecutive frames of valid B-code input signals are detected in steady-state timekeeping mode, the current time of the local RTC clock and the reference clock time of the B-code input signal are read, the time deviation between the current time of the local RTC clock and the reference clock time of the B-code input signal is calculated, and the current time of the local RTC clock is uniformly adjusted to the reference clock time of the B-code input signal within a preset calibration period, so as to smoothly switch the clock module's operating mode to B-code synchronization mode.

[0057] This embodiment switches to timekeeping mode when the B-code input signal is detected to be lost, and performs progressive calibration and smoothing after a valid B-code input signal is detected, switching back to B-code synchronization mode, which can ensure the time continuity of the power acquisition service.

[0058] In one embodiment of this application, after obtaining the initially synchronized system clock, the clock module is configured as follows: Output PPS pulse signals to the main control unit and the GPIO interrupt pins of each physical slot; Within the first millisecond-level time window after the rising edge of the PPS pulse signal, a serial time message carrying absolute calendar time information is sent to the master control unit so that the master control unit forwards the serial time message to the physical slot. The PPS pulse signal and serial time message are used to indicate the start time of the second locked by each physical slot based on the rising edge of the PPS pulse signal, and to parse the absolute time by combining the received serial time message, so as to realize the clock synchronization between each physical slot and the main control unit.

[0059] In this embodiment, the clock module, main control unit, and multiple physical slots adopt the above-mentioned dual-mode time synchronization mechanism of "hardware second-edge synchronization (PPS pulse signal) + software absolute time alignment (TTL message)". This mechanism combines the high precision of the PPS pulse signal with the absolute time information of the TTL message to ensure that the system has complete calendar clock functions while achieving nanosecond-level synchronization.

[0060] The PPS pulse signal is a standard TTL level signal with a fixed pulse width of 50ms to 200ms, and the rising edge represents the absolute start time of the second. The serial time message uses a custom binary protocol or standard ASCII code and contains complete date and time information (year, month, day, hour, minute, second, millisecond).

[0061] Specifically, the USART serial port of the clock module is connected to the master control unit (RK3568), and the USART serial port of the master control unit is connected to the processor of each physical slot. Within the first millisecond time window immediately following the rising edge of the PPS pulse, the clock module actively sends a serial time message to the master control unit, which is then forwarded to each physical slot by the master control unit, thereby achieving clock synchronization between the master control unit and each physical slot.

[0062] In one embodiment of this application, the clock module is further configured to: Start the first timer; the counting frequency of the first timer is proportional to the frequency of the local crystal oscillator; A reference PPS pulse signal is obtained from a preset pin. If the reference PPS pulse signal meets the preset validity verification conditions, the reference PPS pulse signal is used as the reference PPS signal. In the periodic interrupt routine of the reference PPS signal, read the total value of the first timer; Calculate the average count of multiple consecutive total values; Calculate the difference between the average count value and the preset ideal count value; The local microsecond timing is compensated and calibrated based on the count difference.

[0063] In this embodiment, the reference PPS pulse signal can be a PPS pulse signal obtained by parsing the B code input signal, or it can be an externally accessed independent PPS pulse signal. If a reference PPS pulse signal passes the validity check (e.g., pulse width of 50ms to 200ms, pulse period of 980ms to 1020ms), then the reference PPS pulse signal is used as the reference PPS signal. Using the reference PPS signal as the standard time reference, the hardware PPS interrupt of the clock module is used to count the cycles and compare and calculate the local crystal oscillator frequency deviation, dynamically correcting the microsecond clock, and realizing closed-loop accurate calibration of the local clock. The specific implementation details are as follows: Connect the reference PPS signal to a GPIO pin (e.g., PA0) of the clock module and configure it as an external interrupt (EXTI0). Use the timer register to latch the count value at the moment of the interrupt (denoted as TIMx->CNT). To achieve higher counting accuracy and a longer overflow period, the crystal oscillator clock frequency can be down-divided using a timer prescaler. Assume the system clock frequency Fclk is 72MHz. Configure the timer prescaler register (TIMx_PSC) with a prescaler coefficient PSC=71. Then, the actual timer counting frequency Fcnt is: 72MHz / (71+1)=1MHz, and each timer count represents 1 microsecond.

[0064] Since the count value in 1 second (1,000,000) exceeds the maximum count value of the 16-bit timer (65535), the total count is synthesized using the method of "hardware CNT remainder + software overflow count". A global variable overflow_count is defined, which increments by 1 each time the timer overflows. When the reference PPS signal interrupt occurs, capture_cnt = TIMx->CNT is read, and the total count is synthesized as TotalCount = overflow_count × 65536 + capture_cnt.

[0065] The average count is calculated every 10 seconds (10 interruptions) to obtain the average count value TotalCountavg. The average count value TotalCountavg is then subtracted from the ideal count value (10,000,000) to obtain the count difference: ΔN = TotalCountavg 10,000,000.

[0066] Based on this, local microsecond timing can be compensated and calibrated based on the count difference. The specific steps include: The timing interval corresponding to a single microsecond compensation is calculated based on the counting difference. The timing duration is incremented in the interrupt routine of the second timer; When the timing interval is reached, perform a microsecond compensation on the local microsecond timer and reset the timing duration to zero.

[0067] Assuming ΔN is 200, the count value required for each 1µs error is 10,000,000 / 200 = 50,000, meaning a 1µs error needs to be compensated every 50ms. Configure a ms timer as a second timer; the microsecond clock is used for calculation and compensation in the second timer, with an interrupt occurring every 1ms, compensating for a 1µs error every 50ms.

[0068] Based on this, since the PPS signal is only accurate to the second, the microsecond time can be determined based on the local clock: When the baseline PPS pulse signal is interrupted, refresh the absolute second baseline value: BaseTotalUs = overflow_count × 65536 + TIMx_CNT; When it is necessary to obtain the current microsecond-level timestamp, read overflow_count (denoted as overflow_count') and capture_cnt (denoted as TIMx_CNT') again, and calculate the current time NowTotalUs=overflow_count'×65536+TIMx_CNT'; Calculate the difference between the current time and the absolute second baseline value: ΔUS = NowTotalUs BaseTotalUs is the microsecond time within the current second time.

[0069] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multi-slot electrical energy remote terminal, characterized in that, Includes a main control unit, a USB hub chip, multiple USB-to-serial chips, and multiple physical slots; The uplink port of the USB HUB chip is connected to the main control unit, and the multiple downlink ports of the USB HUB chip are respectively connected to the USB ports of multiple USB to serial port chips. The serial port signal terminal of each USB to serial port chip is connected to the corresponding physical slot to connect to an external serial port device. The main control unit has an independent power management circuit for the USB port, and the main control unit is configured as follows: According to the order determined by the slot number of the connected physical slot, each USB to serial port chip is powered on and enumerated in turn. Specifically, for each slot number, the power-on enumeration steps for the corresponding USB-to-serial chip include: Read the physical serial number of the downstream port to which the USB-to-serial chip is connected; Perform USB device enumeration on the USB-to-serial chip to generate the original serial device node; Based on the slot number, find the preset slot port mapping relationship and determine the target port number; If the target port number is consistent with the physical number, then the slot number is used as the target slot number; If the target port number is inconsistent with the physical number, the slot port mapping relationship is found based on the physical number to obtain the target slot number; A fixed symbolic link node is generated based on the target slot number, and a symbolic link mapping is established between the fixed symbolic link node and the original serial port device node, so as to access the original serial port device node based on the fixed symbolic link node, thereby realizing the permanent binding of the physical slot and the serial port device access entry.

2. The multi-slot remote power terminal as described in claim 1, characterized in that, When performing USB device enumeration on the USB-to-serial chip, the main control unit is configured as follows: If all downstream ports of the corresponding USB HUB chip are online during the first monitoring period after the USB-to-serial chip is powered on, then USB device enumeration is performed on the USB-to-serial chip.

3. The multi-slot remote power terminal as described in claim 1, characterized in that, The multiple downstream ports of the USB HUB chip are connected one-to-one with the USB ports of the multiple USB-to-serial chips, and the serial port signal terminal of each USB-to-serial chip is connected to the physical slot via PCB wiring.

4. The multi-slot remote power terminal as described in claim 1, characterized in that, The physical slots are connected to different external serial port devices through different types of plug-in boards. Each physical slot is equipped with an ID identification pin, which is connected to the main control unit through a pull-up resistor. The plug-in board is equipped with an ID matching pin that is plugged into the ID identification pin. Each type of plug-in board outputs the corresponding high and low level codes by grounding or floating the ID matching pin. After performing USB device enumeration, the host control unit is configured as follows: Read the level signal of the ID identification pin; The model of the plug-in board is determined based on the level signal of the ID identification pin; If the plug-in board is a smart plug-in board, then determine the slot number of the physical slot corresponding to the plug-in board, and send an identity query command to the plug-in board through the serial port device node corresponding to the slot number; In response to receiving the identity information returned by the plug-in board, the corresponding driver dynamic library is dynamically loaded from the preset HAL driver library based on the identity information.

5. The multi-slot remote power terminal as described in claim 4, characterized in that, Before the serial port device node corresponding to the slot number sends the identity query command to the board, the main control unit is configured as follows: The serial port device node corresponding to the slot number sends an integrated request packet to the board; the integrated request packet carries the master control random challenge, the master control identity signature and the master control key negotiation public key. The integrated response packet returned by the plug-in board is received to complete the mutual exchange of the master key negotiation public key and the peripheral key negotiation public key; the integrated response packet is generated by the plug-in board after verifying the legality of the master identity signature, and the integrated response packet carries the peripheral identity signature, the peripheral random challenge and the peripheral key negotiation public key; Verify the validity of the peripheral device identity signature; If the validity of the master control identity signature and the validity of the peripheral identity signature are both verified, then a session key negotiation is performed based on the exchanged master control key negotiation public key and peripheral key negotiation public key. The step of sending an identity query command to the board via the serial port device node corresponding to the slot number includes: The identity query command is encrypted using the negotiated session key, and then sent to the board via the serial port device node corresponding to the slot number.

6. The multi-slot remote power terminal as described in claim 1, characterized in that, For each physical slot, the main control unit is configured as follows: If all the in-situ pins of the physical slot are displayed as disconnected within the preset second monitoring period, the power-down process will be executed in the order of service callback stop, driver instance unload, device node deregistration, and slot power cut-off.

7. The multi-slot remote power terminal as described in claim 1, characterized in that, It also includes a clock module; the clock module is configured to: Detect the validity of the B-code input signal; If a valid B-code input signal is detected, B-code phase-locked loop calibration is performed to synchronize the local RTC clock to the time base of the B-code master clock, thus obtaining the system clock after initial synchronization. If no B code input signal is detected, the system enters the initial timekeeping mode, reads the time stored in the local RTC clock as the timing reference, and obtains the system clock after initial synchronization. After obtaining the system clock after initial synchronization, continuously monitor the B code input signal; If multiple consecutive frames of invalid B code input signals are detected, it is determined that the B code input signal is lost, and the working mode of the clock module is seamlessly switched to the steady-state timekeeping mode. If multiple consecutive frames of valid B-code input signals are detected in steady-state timekeeping mode, the current time of the local RTC clock and the reference clock time of the B-code input signal are read, the time deviation between the current time of the local RTC clock and the reference clock time of the B-code input signal is calculated, and the current time of the local RTC clock is uniformly adjusted to the reference clock time of the B-code input signal within a preset calibration time, so as to smoothly switch the working mode of the clock module to the B-code synchronization mode.

8. The multi-slot remote power terminal as described in claim 7, characterized in that, After obtaining the initially synchronized system clock, the clock module is configured as follows: Output PPS pulse signals to the main control unit and the GPIO interrupt pins of each physical slot; Within the first millisecond-level time window after the rising edge of the PPS pulse signal, a serial time message carrying absolute calendar time information is sent to the main control unit so that the main control unit forwards the serial time message to each physical slot. The PPS pulse signal and serial time message are used to indicate the start time of the second locked by each physical slot based on the rising edge of the PPS pulse signal, and to parse the absolute time by combining the received serial time message, so as to realize the clock synchronization between each physical slot and the main control unit.

9. The multi-slot remote power terminal as described in claim 7, characterized in that, The clock module is also configured to: Start the first timer; the counting frequency of the first timer is proportional to the frequency of the local crystal oscillator; A reference PPS pulse signal is obtained from a preset pin. If the reference PPS pulse signal meets the preset validity verification conditions, the reference PPS pulse signal is used as the reference PPS signal. In the periodic interrupt routine of the reference PPS signal, the total value of the first timer is read; Calculate the average count of multiple consecutive total values; Calculate the count difference between the average count value and the preset ideal count value; The local microsecond timing is compensated and calibrated based on the count difference.

10. The multi-slot remote power terminal as described in claim 9, characterized in that, When performing compensation calibration on the local microsecond timing based on the count difference, the clock module is also configured to: The timing interval corresponding to a single microsecond compensation is calculated based on the count difference. The timing duration is incremented in the interrupt routine of the second timer; When the timing duration reaches the specified timing interval, perform a microsecond compensation on the local microsecond timing and reset the timing duration to zero.

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