Power conversion circuit and control method thereof

Abstract

The application provides a power conversion circuit and a control method thereof. The power conversion circuit comprises a transformer, a primary switch, a first switch, a second switch and a control circuit. The transformer comprises a primary coil and a secondary coil. The primary coil receives an input voltage, and the secondary coil generates a secondary current. The primary switch electrically connects the primary coil to a ground end based on a primary control signal. The first switch supplies the secondary current to a first output voltage based on a first signal. The second switch supplies the secondary current to a second output voltage based on a second signal. The control circuit generates the first signal based on the first output voltage, generates the second signal based on the second output voltage, and generates the primary control signal based on the first output voltage and the second output voltage. The power conversion circuit and the control method thereof can significantly reduce the cost, greatly reduce the circuit complexity, and improve the conversion efficiency.

Description

Technical Field

[0001] This invention relates to a power conversion circuit and its control method, and more particularly to a flyback power conversion circuit and its control method for generating multiple output voltages. Background Technology

[0002] Many devices require multi-output power conversion circuits, such as mobile phones, power banks, laptops, digital cameras, tablets, speakers, game consoles, portable computing devices, and wearable devices. Traditional multi-output flyback power conversion circuits require multiple coils on the secondary side and additional independent voltage regulator circuits to regulate the individual output voltages, significantly increasing component costs and circuit complexity. To reduce costs and circuit complexity, it is necessary to optimize multi-output power conversion circuits. Summary of the Invention

[0003] This invention proposes a power conversion circuit with multiple output voltages and its control method. Compared to the traditional method of using multiple secondary coils (or multiple transformers) and additional voltage regulators to regulate individual output voltages, the power conversion circuit with multiple output voltages proposed in this invention can use a transformer with a single secondary coil and multiple switches to supply multiple output voltages in a time-sharing manner. Because this invention uses a transformer with a single secondary coil and multiple switches, it significantly reduces costs and circuit complexity, while also improving conversion efficiency. Furthermore, the multiple output voltages of the power conversion circuit proposed in this invention can be set to different voltage values.

[0004] In view of this, the present invention proposes a power conversion circuit comprising a transformer, a primary switch, a first switch, a second switch, and a control circuit. The transformer includes a primary coil and a secondary coil, wherein the primary coil receives an input voltage, and the secondary coil generates a primary current. The primary switch electrically connects the primary coil to a ground terminal based on a primary control signal. The first switch supplies power to a first output voltage via the secondary current based on a first signal. The second switch supplies power to a second output voltage via the secondary current based on a second signal. The control circuit generates the first signal based on the first output voltage and the second signal based on the second output voltage. The control circuit generates the primary control signal based on both the first and second output voltages.

[0005] According to one embodiment of the present invention, the control circuit includes a first error amplifier, a first comparator, and a first signal generation circuit. The first error amplifier generates a first error signal based on the difference between the first output voltage and a first reference voltage. The first comparator compares the first error signal with a first sawtooth wave to generate a first comparison signal. The first signal generation circuit generates the first signal based on the first comparison signal. When the primary switch is off, the control circuit enables the first signal to turn on the first switch. When the first sawtooth wave is not less than the first error signal, the first signal generation circuit disables the first signal and simultaneously enables the second signal, causing the first switch to turn off and the second switch to turn on.

[0006] According to one embodiment of the present invention, the first signal generating circuit disables the second signal based on the secondary current dropping below a current threshold, thereby turning off the second switch.

[0007] According to one embodiment of the present invention, the control circuit further includes a second error amplifier, an isolation circuit, and a third signal generation circuit. The second error amplifier generates a second error signal based on the difference between the second output voltage and a second reference voltage. The isolation circuit generates a feedback signal based on the first error signal and the second error signal. The third signal generation circuit generates the primary control signal based on the feedback signal.

[0008] According to one embodiment of the present invention, when the first output voltage is less than the first reference voltage or the second output voltage is less than the second reference voltage, the third signal generating circuit extends the enable time of the primary control signal to extend the magnetization time of the primary coil.

[0009] According to one embodiment of the present invention, the control circuit further includes a current comparator. The current comparator compares the secondary current with a current threshold to generate a current comparison signal. When the secondary current is lower than the current threshold, the first signal generation circuit disables the second signal based on the current comparison signal, thereby turning off the second switch.

[0010] According to another embodiment of the present invention, the control circuit further includes a second comparator and a second signal generation circuit. The second comparator compares the second error signal and a second sawtooth wave to generate a second comparison signal. The second signal generation circuit disables the second signal based on the second comparison signal. When the second sawtooth wave is not less than the second error signal, the second signal generation circuit disables the second signal, thereby turning off the second switch.

[0011] According to another embodiment of the present invention, the power conversion circuit further includes a third switch. The third switch supplies power to a third output voltage via the secondary current based on a third signal. The control circuit further includes a third error amplifier. The third error amplifier generates a third error signal based on the difference between the third output voltage and a third reference voltage. When the second signal generation circuit disables the second signal, it simultaneously enables the third signal. The isolation circuit generates the feedback signal based on the first error signal, the second error signal, and the third error signal.

[0012] According to one embodiment of the present invention, the control circuit further includes a current comparator. The current comparator compares the secondary current with a current threshold to generate a current comparison signal. When the secondary current is lower than the current threshold, the second signal generation circuit disables the third signal based on the current comparison signal, thereby turning off the third switch.

[0013] According to another embodiment of the present invention, the control circuit further includes a third comparator and a fourth signal generation circuit. The third comparator compares the third error signal and a third sawtooth wave to generate a third comparison signal. The fourth signal generation circuit disables the third signal based on the third comparison signal. When the third sawtooth wave is not less than the third error signal, the fourth signal generation circuit disables the third signal, thereby turning off the third switch.

[0014] According to one embodiment of the present invention, the power conversion circuit further includes a secondary switch. The secondary switch is connected in series with the secondary coil. When the primary switch is turned on, the secondary switch is turned off. When the primary switch is turned off, the secondary switch is turned on, so that the secondary current supplies power to one of the first output voltage and the second output voltage.

[0015] According to another embodiment of the present invention, the first switch includes a first rectifier transistor and a first blocking transistor. The first rectifier transistor includes a first rectifier gate, a first rectifier drain, and a first rectifier source. The first blocking transistor includes a first blocking gate, a first blocking drain, and a first blocking source. The first rectifier gate receives a first rectified signal, the first rectifier drain is electrically connected to the first blocking drain, and the first rectifier source receives the secondary current. The first blocking gate receives a first blocking signal, and the first blocking source is coupled to the first output voltage.

[0016] According to one embodiment of the present invention, the second switch includes a second rectifier transistor and a second blocking transistor. The second rectifier transistor includes a second rectifier gate, a second rectifier drain, and a second rectifier source. The second blocking transistor includes a second blocking gate, a second blocking drain, and a second blocking source. The second rectifier gate receives a second rectified signal, the second rectifier drain is electrically connected to the second blocking drain, and the second rectifier source receives the secondary current. The second blocking gate receives a second blocking signal, and the second blocking source is coupled to the second output voltage.

[0017] According to one embodiment of the present invention, the conduction time of the first rectifier transistor does not overlap with the conduction time of the second rectifier transistor.

[0018] According to another embodiment of the present invention, in a first period, both the first rectifier transistor and the first blocking transistor are turned on, such that the secondary current supplies power to the first output voltage. In a second period following the first period, the first rectifier transistor is turned off and both the first blocking transistor and the second blocking transistor are turned on, such that the secondary current supplies power to the lower of the first output voltage and the second output voltage. In a third period following the second period, the first blocking transistor is turned off and the second rectifier transistor is turned on, such that the secondary current supplies power to the second output voltage.

[0019] The present invention also proposes a control method for controlling a power conversion circuit to convert an input voltage into a first output voltage and a second output voltage. The power conversion circuit includes a transformer, which includes a primary coil and a secondary coil. The control method includes: magnetizing the primary coil during a magnetization time; supplying power to the first output voltage using the primary current flowing through the secondary coil after the magnetization time; stopping the supply of power to the first output voltage and starting the supply of power to the second output voltage based on the first output voltage; and adjusting the magnetization time based on the first output voltage and the second output voltage.

[0020] According to one embodiment of the present invention, the control method further includes: stopping the supply of power to the second output voltage based on the second output voltage.

[0021] According to another embodiment of the present invention, the control method further includes: stopping the supply of power to the second output voltage based on the secondary current.

[0022] According to one embodiment of the present invention, the step of adjusting the magnetization time based on the first output voltage and the second output voltage further includes: generating a first error signal based on the difference between the first output voltage and a first reference voltage; generating a second error signal based on the difference between the second output voltage and a second reference voltage; and determining the magnetization time based on the first error signal and the second error signal. When the first output voltage is less than the first reference voltage, the magnetization time is extended. When the second output voltage is less than the second reference voltage, the magnetization time is extended.

[0023] According to another embodiment of the present invention, the step of adjusting the magnetization time based on the first output voltage and the second output voltage further includes: determining the output power of the first output voltage and the output power of the second output voltage; extending the magnetization time when the output power of the first output voltage increases; and extending the magnetization time when the output power of the second output voltage increases.

[0024] According to another embodiment of the present invention, the secondary current supplies power to the first output voltage via a first rectifier transistor and a first blocking transistor, and the secondary current supplies power to the second output voltage via a second rectifier transistor and a second blocking transistor. The source terminal of the first rectifier transistor receives the secondary current, the drain terminal of the first rectifier transistor is coupled to the drain terminal of the first blocking transistor, and the source terminal of the first blocking transistor is coupled to the first output voltage. The source terminal of the second rectifier transistor receives the secondary current, the drain terminal of the second rectifier transistor is coupled to the drain terminal of the second blocking transistor, and the source terminal of the second blocking transistor is coupled to the second output voltage.

[0025] According to one embodiment of the present invention, the control method further includes: in a first period, simultaneously turning on the first rectifier transistor and the first blocking transistor, so that the secondary current supplies power to the first output voltage; in a second period after the first period, turning off the first rectifier transistor and turning on the first blocking transistor and the second blocking transistor, so that the secondary current supplies power to the one having a lower voltage value between the first output voltage and the second output voltage; and in a third period after the second period, turning off the first blocking transistor and turning on the second rectifier transistor, so that the secondary current supplies power to the second output voltage. Attached Figure Description

[0026] Figure 1 A schematic diagram of a power conversion circuit according to one embodiment of the present invention is shown;

[0027] Figure 2 A schematic diagram of a power conversion circuit according to another embodiment of the present invention is shown;

[0028] Figure 3 A schematic diagram of a power conversion circuit according to yet another embodiment of the present invention is shown;

[0029] Figure 4 The diagram shows a waveform of a power conversion circuit according to one embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a power conversion circuit according to yet another embodiment of the present invention is shown;

[0031] Figure 6 A schematic diagram of a power conversion circuit according to yet another embodiment of the present invention is shown;

[0032] Figure 7 A schematic diagram of a power conversion circuit according to yet another embodiment of the present invention is shown;

[0033] Figure 8 A schematic diagram of a power conversion circuit according to yet another embodiment of the present invention is shown;

[0034] Figure 9 The diagram shows a waveform of a power conversion circuit according to another embodiment of the present invention.

[0035] Figure 10 A flowchart of a control method according to one embodiment of the present invention is shown.

[0036] Explanation of reference numerals in the attached figures:

[0037] 100, 200, 300, 500, 600, 700, 800: Power conversion circuit

[0038] 110, 610, 710, 810: Control circuit

[0039] 111,811: First control circuit

[0040] 112,812: Second control circuit

[0041] TM: Transformer

[0042] SWP: Primary Switch

[0043] SW1: First switch

[0044] SW2: Second switch

[0045] COUT1: First output capacitor

[0046] COUT2: Second output capacitor

[0047] PS: Primary coil

[0048] SS: Secondary coil

[0049] VIN: Input voltage

[0050] IP: Primary Current

[0051] IS: Secondary current

[0052] IS1: First power supply current

[0053] IS2: Second power supply current

[0054] VREF1: First reference voltage

[0055] VREF2: Second reference voltage

[0056] VOUT1: First output voltage

[0057] VOUT2: Second output voltage

[0058] SEA1: First error signal

[0059] S1: First signal

[0060] S2: Second signal

[0061] SP: Primary control signal

[0062] 211: First signal generation circuit

[0063] 221: Second signal generation circuit

[0064] 222, 622: Isolation circuits

[0065] 223: Third signal generation circuit

[0066] EA1: First error amplifier

[0067] EA2: Second Error Amplifier

[0068] SEA2: Second Error Signal

[0069] CMP1: First comparator

[0070] CMP2: Second comparator

[0071] RMP1: First sawtooth wave

[0072] RMP2: Second sawtooth wave

[0073] SCP1: First Comparison Signal

[0074] SCP2: Second Comparison Signal

[0075] SFB: Feedback Signal

[0076] CMPC: Current Comparator

[0077] ITH: Current Threshold

[0078] SCPC: Current Comparison Signal

[0079] 400, 900: Waveform Diagram

[0080] TSW: Switching Time

[0081] T1: First Time Point

[0082] T2: Second Time Point

[0083] T3: Third Time Point

[0084] T4: Fourth Time Point

[0085] T5: Fifth Time Point

[0086] 621: Second signal generation circuit

[0087] 631: Fourth signal generation circuit

[0088] SW3: Third switch

[0089] IS3: Third supply current

[0090] S3: Third signal

[0091] COUT3: Third output capacitor

[0092] VOUT3: Third output voltage

[0093] VREF3: Third reference voltage

[0094] RMP3: Third Sawtooth Wave

[0095] CMP3: Third Comparator

[0096] SCP3: Third Comparison Signal

[0097] TR1: First rectifier transistor

[0098] TA1: First blocking transistor

[0099] TR2: Second rectifier transistor

[0100] TA2: Second blocking transistor

[0101] GR1: First rectifier gate terminal

[0102] DR1: First rectifier drain end

[0103] SR1: First rectifier source extreme

[0104] GA1: First blocking gate terminal

[0105] DA1: First blocking leak extreme

[0106] SA1: First blocking source extreme

[0107] GR2: Second rectifier gate terminal

[0108] DR2: Second rectifier drain end

[0109] SR2: Second rectifier source extreme

[0110] GA2: Second blocking gate terminal

[0111] DA2: Second blocking leak extreme

[0112] SA2: Second blocking source extreme

[0113] A1: First blocking signal

[0114] A2: Second blocking signal

[0115] R1: First rectified signal

[0116] R2: Second rectified signal

[0117] T6 Sixth Time Point

[0118] T7 Seventh Time Point

[0119] T8 Eighth Time Point

[0120] T9 Ninth Time Point

[0121] T10 Tenth Time Point

[0122] T11 Eleventh Time Point

[0123] T12, the twelfth time point

[0124] S1010~S1050: Procedure Flowchart Detailed Implementation

[0125] The following description is an embodiment of this application. Its purpose is to illustrate the general principles of this application and should not be regarded as a limitation of this application. The scope of this application shall be defined by the claims.

[0126] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this application. The specific element examples and arrangements described below are merely for briefly illustrating the spirit of this application and are not intended to limit its scope. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is solely to provide a simplified and clear explanation and is not intended to limit the relationships between the various embodiments and / or configurations discussed below.

[0127] Furthermore, the description in the following specification of a feature being connected to, coupled to, and / or formed on another feature may actually include multiple different embodiments, including features that are in direct contact, or additional features that are formed between features, such that features are not in direct contact.

[0128] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element depicted on the "lower" side will become the element on the "higher" side.

[0129] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments of this application.

[0130] Some embodiments of this application can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments of this application. It should be understood that the drawings of the embodiments of this application are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of this application. Furthermore, the structures and devices in the drawings are drawn schematically to clearly show the features of the embodiments of this application.

[0131] Here, the terms "about," "approximately," and "roughly" generally indicate within 20%, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%, of a given value or range. The quantities given here are approximate quantities; that is, even without specific mention of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0132] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art as disclosed herein. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this application, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this application.

[0133] In some embodiments of this application, terms such as "connection" and "interconnection" are used to refer to two structures in direct contact, unless otherwise defined. This can also refer to two structures that are not in direct contact, with another structure disposed between them. Furthermore, these terms can also include cases where both structures are movable or both structures are fixed.

[0134] In a diagram, similar elements and / or features may have the same element symbol. Various elements of the same type can be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or similar features.

[0135] Figure 1 A schematic diagram of a power conversion circuit according to one embodiment of the present invention is shown. Figure 1 As shown, the power conversion circuit 100 includes a transformer TM, a primary switch SWP, a first switch SW1, a first output capacitor COUT1, a second switch SW2, a second output capacitor COUT2, and a control circuit 110.

[0136] The transformer TM includes a primary coil PS and a secondary coil SS. One end of the primary coil PS receives an input voltage VIN. A primary switch SWP is coupled between the other end of the primary coil PS and ground. According to one embodiment of the invention, when the primary switch SWP is turned on, the primary coil PS (i.e., the transformer TM) is magnetized, causing the primary current IP to increase. According to another embodiment of the invention, when the primary switch SWP is turned off, the primary coil PS (i.e., the transformer TM) is demagnetized, causing the secondary coil SS to generate a secondary current IS. In one embodiment, the transformer TM has only a single secondary coil SS and no other secondary coil. In other words, the transformer TM has only one secondary coil SS.

[0137] When the transformer TM is demagnetized, the first switch SW1 and the second switch SW2 are turned on in a time-sharing manner, causing the secondary current IS to generate a first supply current IS1 and a second supply current IS2 at different times. These currents are used to charge the first output capacitor COUT1 and the second output capacitor COUT2, respectively, thereby generating the first output voltage VOUT1 and the second output voltage VOUT2. The control circuit 110 generates a first signal S1 based on the first output voltage VOUT1, a second signal S2 based on the second output voltage VOUT2, and a primary control signal SP based on both the first output voltage VOUT1 and the second output voltage VOUT2, thereby controlling the first switch SW1, the second switch SW2, and the primary switch SP, respectively.

[0138] like Figure 1 As shown, the control circuit 110 includes a first control circuit 111 and a second control circuit 112. The first control circuit 111 generates a first signal S1 and a second signal S2 based on a first output voltage VOUT1, and generates a first error signal SEA1 based on the difference between the first output voltage VOUT1 and a first reference voltage VREF1. The second control circuit 112 generates a primary control signal SP based on the first error signal SEA1, a second output voltage VOUT2, and a second reference voltage VREF2, and generates a second signal S2 based on the second output voltage VOUT2.

[0139] According to some embodiments of the present invention, the first control circuit 111 determines the conduction time of the first switch SW1 based on the first output voltage VOUT1, the second control circuit 112 determines the conduction time of the second switch SW2 based on the second output voltage VOUT2, and the second control circuit 112 further determines the conduction time of the primary switch SWP based on the difference between the first output voltage VOUT1 and the first reference voltage VREF1 and the difference between the second output voltage VOUT2 and the second reference voltage VREF2.

[0140] According to one embodiment of the present invention, the power conversion circuit 100 may be a flyback power conversion circuit. For the sake of simplicity, the description here refers to the power conversion circuit 100 generating a first output voltage VOUT1 and a second output voltage VOUT2, and is not intended to limit the description in any way. According to other embodiments of the present invention, the power conversion circuit 100 may also generate any number of output voltages.

[0141] Figure 2 A schematic diagram of a power conversion circuit according to another embodiment of the present invention is shown. The power conversion circuit 200 is connected to... Figure 1 Compared to the power conversion circuit 100, the first control circuit 111 includes a first error amplifier EA1, a first comparator CMP1, and a first signal generation circuit 211.

[0142] The first error amplifier EA1 generates a first error signal SEA1 based on the difference between the first output voltage VOUT1 and the first reference voltage VREF1. According to one embodiment of the invention, when the first output voltage VOUT1 decreases, the first error signal SEA1 increases. According to another embodiment of the invention, when the first output voltage VOUT1 increases, the first error signal SEA1 decreases.

[0143] In other words, the first error amplifier EA1 amplifies the difference between the first output voltage VOUT1 and the first reference voltage VREF1 to generate the first error signal SEA1. The first comparator CMP1 compares the first error signal SEA1 with the first sawtooth wave RMP1 to generate the first comparison signal SCP1. The first signal generation circuit 211 generates the first signal S1 and the second signal S2 based on the first comparison signal SCP1.

[0144] like Figure 2 As shown, the second control circuit 112 includes a second error amplifier EA2, a second comparator CMP2, a second signal generation circuit 221, an isolation circuit 222, and a third signal generation circuit 223. The second error amplifier EA2 generates a second error signal SEA2 based on the difference between the second output voltage VOUT2 and the second reference voltage VREF2.

[0145] The second error amplifier EA2 generates a second error signal SEA2 based on the second output voltage VOUT2 and the second reference voltage VREF2. According to one embodiment of the invention, when the second output voltage VOUT2 decreases, the second error signal SEA2 increases. According to another embodiment of the invention, when the second output voltage VOUT2 increases, the second error signal SEA2 decreases.

[0146] In other words, the second error amplifier EA2 amplifies the difference between the second output voltage VOUT2 and the second reference voltage VREF2 to generate the second error signal SEA2. The second comparator CMP2 compares the second error signal SEA2 with the second sawtooth wave RMP2 to generate the second comparison signal SCP2. The second signal generation circuit 221 generates the second signal S2 based on the second comparison signal SCP2.

[0147] The isolation circuit 222 generates a feedback signal SFB based on the first error signal SEA1 and the second error signal SEA2. According to one embodiment of the invention, the isolation circuit 222 may be an optocoupler. According to another embodiment of the invention, the isolation circuit 222 may be an isolation transformer, wherein the isolation transformer includes an inductive transformer and a capacitive transformer.

[0148] The third signal generation circuit 223 generates a primary control signal SP based on the feedback signal SFB. In other words, the isolation circuit 222 and the third signal generation circuit 223 adjust the on-time of the primary switch SWP based on the difference between the first output voltage VOUT1 and the first reference voltage VREF1 and the difference between the second output voltage VOUT2 and the second reference voltage VREF2, thereby changing the magnetization time.

[0149] Figure 3 A schematic diagram of a power conversion circuit according to another embodiment of the present invention is shown. The power conversion circuit 300 is connected to... Figure 2 Compared to the power conversion circuit 200, the current comparator CMPC is used to replace Figure 2 The second comparator CMP2 and the second signal generation circuit 221.

[0150] like Figure 3 As shown, the current comparator CMPC is used to compare the secondary current IS with the current threshold ITH to generate a current comparison signal SCPC. According to one embodiment of the present invention, when the secondary current IS is lower than the current threshold ITH, the current comparator CMPC enables the current comparison signal SCPC. According to another embodiment of the present invention, when the secondary current IS is not lower than the current threshold ITH, the current comparator CMPC disables the current comparison signal SCPC.

[0151] According to some embodiments of the present invention, after the first signal generation circuit 211 enables the second signal S2 and the secondary current IS is lower than the current threshold ITH, the first signal generation circuit 211 disables the second signal S2 based on the enabled current comparison signal SCPC, thereby turning off the second switch SW2. In other words, when the secondary current IS drops to near zero, the control circuit 110 turns off the second switch SW2, thereby stopping the supply of power to the second output voltage VOUT2. According to some embodiments of the present invention, when the transformer TM finishes demagnetizing, the control circuit 110 immediately turns off the second switch SW2.

[0152] Figure 4 The diagram shows a waveform of a power conversion circuit according to one embodiment of the present invention. The following description of waveform 400 will be accompanied by… Figure 2Power conversion circuit 200 and Figure 3 Power conversion circuit 300, for detailed explanation.

[0153] like Figure 4 As shown, at the first time point T1, the primary control signal SP is enabled, turning on the primary switch SWP and magnetizing the transformer TM. Between the first time point T1 and the second time point T2, the primary current IP increases linearly. At the second time point T2, the primary control signal SP is deactivated, turning off the primary switch SWP and demagnetizing the transformer TM, generating a secondary current IS.

[0154] When the transformer TM begins to demagnetize at the second time point T2 and generates a secondary current IS, the first signal generation circuit 211 enables the first signal S1 and turns on the first switch SW1, so that the secondary current IS charges the first output capacitor COUT1 and generates the first output voltage VOUT1.

[0155] When the first sawtooth wave RMP1 rises to a level not less than the first error signal SEA1 at the third time point T3, the first signal generation circuit 211 disables the first signal S1 based on the disabled first comparison signal SCP1, thereby turning off the first switch SW1. Furthermore, when the first signal generation circuit 211 disables the first signal S1 at the third time point T3, it simultaneously enables the second signal S2, thereby turning on the second switch SW2.

[0156] In other words, when the first sawtooth wave RMP1 is not less than the first error signal SEA1, the first signal generation circuit 211 disables the first signal S1 and enables the second signal S2 based on the disabled first comparison signal SCP1, thereby turning off the first switch SW1 and turning on the second switch SW2, so that the secondary current IS stops supplying power to the first output voltage VOUT1 at the third time point T3 and starts supplying power to the second output voltage VOUT2.

[0157] When the second sawtooth wave RMP2 rises to a level not less than the second error signal SEA2 at the fourth time point T4, the second signal generation circuit 221 disables the second signal S2 based on the disabled second comparison signal SCP2, thereby turning off the second switch SW2. According to some embodiments of the present invention, the control circuit 110 determines the on-time of the first switch SW1 based on the first output voltage VOUT1, and determines the on-time of the second switch SW2 based on the second output voltage VOUT2.

[0158] According to other embodiments of the present invention, since the secondary current IS drops to zero at the fourth time point T4, the first signal generation circuit 211 can disable the second signal S2 based on the secondary current IS dropping to zero (or the secondary current IS dropping below a threshold), thereby turning off the second switch SW2. In other words, in Figure 3 In one embodiment, the control circuit 110 determines the on-time of the first switch SW1 based on the first output voltage VOUT1, and determines the on-time of the second switch SW2 based on the secondary current IS.

[0159] At the fifth time point T5, the isolation circuit 222 and the third signal generation circuit 223 enable the primary control signal SP based on the first error signal SEA1 and the second error signal SEA2, thereby turning on the primary switch SWP. For example... Figure 4 As shown, the switching time TSW is from the first time point T1 to the fifth time point T5. According to some embodiments of the present invention, the isolation circuit 222 and the third signal generation circuit 223 can control the enable time of the primary control signal SP, thereby adjusting the conduction time of the primary switch SWP. According to some embodiments of the present invention, when the third signal generation circuit 223 turns on the primary switch SWP at the fifth time point T5, the isolation circuit 222 and the third signal generation circuit 223 determine the length of the conduction time of the primary switch SWP based on the first error signal SEA1 and the second error signal SEA2.

[0160] For example, the output power of the first output voltage VOUT1 suddenly increases between the third time point T3 and the fourth time point T4, causing the voltage value of the first output voltage VOUT1 to decrease. The isolation circuit 222 and the third signal generation circuit 223 can determine from the first error signal SEA1 that the first output voltage VOUT1 needs more energy and extend the on-time of the primary switch SWP, thereby increasing the maximum value of the primary current IP.

[0161] According to one embodiment of the present invention, the first time point T1 to the second time point T2 is the magnetization time of the transformer TM. According to another embodiment of the present invention, the second time point T2 to the fourth time point T4 is the demagnetization time of the transformer TM.

[0162] Figure 5 A schematic diagram of a power conversion circuit according to another embodiment of the present invention is shown. The power conversion circuit 500 is connected to... Figure 1 Compared to the power conversion circuit 100, the power conversion circuit 500 also includes a secondary switch SWS. For example... Figure 5 As shown, the first switch SW1 and the second switch SW2 are coupled to one end of the secondary coil SS, and the secondary switch SWS is coupled between the other end of the secondary coil SS and the ground terminal.

[0163] When the primary switch SWP is turned on, the primary current IP flows from the input voltage VIN through the primary coil PS to the ground terminal, causing the secondary current IS to flow from either the first switch SW1 or the second switch SW2 to the secondary coil SS. At this time, the secondary switch SWS is turned off, preventing the first output voltage VOUT1 and the second output voltage VOUT2 from discharging through the secondary coil SS.

[0164] When the primary switch SWP is off, the secondary switch SWS is on, allowing the secondary current IS to supply power to the first output voltage VOUT1 and the second output voltage VOUT2. In other words, when the transformer TM is magnetized, the secondary switch SWS is off to prevent the first output voltage VOUT1 and the second output voltage VOUT2 from discharging through the secondary coil SS. When the transformer TM is demagnetized, the secondary switch SWS is on, allowing the secondary current IS to supply power to either the first output voltage VOUT1 or the second output voltage VOUT2. According to some embodiments of the present invention, when the primary switch SWP is on, the secondary switch SWS is off; when the primary switch SWP is off, the secondary switch SWS is on.

[0165] Figure 6 A schematic diagram of a power conversion circuit according to another embodiment of the present invention is shown. The power conversion circuit 600 is connected to... Figure 2 Compared to the power conversion circuit 200, the power conversion circuit 600 also includes a third switch SW3 and a third output capacitor COUT3, and Figure 2 The control circuit 110 is replaced by the control circuit 610.

[0166] like Figure 6 As shown, the third switch SW3, based on the third signal S3, charges the third output capacitor COUT3 with the secondary current IS, thereby generating the third output voltage VOUT3. In other words, the third switch SW3 uses the secondary current IS to generate the third supply current IS3, and the third supply current IS3 is used to charge the third output capacitor COUT3 to generate the third output voltage VOUT3.

[0167] Connect the control circuit 610 and Figure 2 Compared to the control circuit 110, Figure 2 The second signal generation circuit 221 is replaced by the second signal generation circuit 621. According to some embodiments of the present invention, when the second signal generation circuit 621 disables the second signal S2 based on the disabled second comparison signal SCP2, the second signal generation circuit 621 simultaneously enables the third signal S3.

[0168] Compared to Figure 2The control circuit 110 further includes a third error amplifier EA3, a third comparator CMP3, and a fourth signal generation circuit 631. The third error amplifier EA3 generates a third error signal SEA3 based on the difference between the third output voltage VOUT3 and the third reference voltage VREF3. According to one embodiment of the invention, when the third output voltage VOUT3 decreases, the third error signal SEA3 increases. According to another embodiment of the invention, when the third output voltage VOUT3 increases, the third error signal SEA3 decreases.

[0169] In other words, the third error amplifier EA3 amplifies the difference between the third output voltage VOUT3 and the third reference voltage VREF3 to generate the third error signal SEA3. The third comparator CMP3 compares the third error signal SEA3 with the third sawtooth wave RMP3 to generate the third comparison signal SCP3. The fourth signal generation circuit 631 generates the third signal S3 based on the third comparison signal SCP3. According to some embodiments of the present invention, when the third sawtooth wave RMP3 rises to a level less than the third error signal SEA3, the fourth signal generation circuit 631 disables the third signal S3 based on the disabled third comparison signal SCP3, thereby turning off the third switch SW3.

[0170] and Figure 2 Compared to the control circuit 110, the isolation circuit 622 of the control circuit 610 generates a feedback signal SFB based on the first error signal SEA1, the second error signal SEA2, and the third error signal SEA3. Furthermore, the third signal generation circuit 223 generates a primary control signal SP based on the feedback signal SFB generated by the isolation circuit 622. In other words, the isolation circuit 622 and the third signal generation circuit 223 adjust the on-time of the primary switch SWP based on the first error signal SEA1, the second error signal SEA2, and the third error signal SEA3.

[0171] According to some embodiments of the present invention, the first signal generation circuit 211 is used to determine the ratio of the power supply time of the first output voltage VOUT1 to the demagnetization time of the transformer TM, and the demagnetization time minus the power supply time of the first output voltage VOUT1 is used to power the second output voltage VOUT2 and the third output voltage VOUT3. The second signal generation circuit 621 is used to determine the power supply time of the second output voltage VOUT2, and the remaining demagnetization time is used to power the third output voltage VOUT3.

[0172] Furthermore, when the remaining energy of the secondary coil SS is insufficient to power the third output voltage VOUT3, or when the output power of any of the first output voltage VOUT1, the second output voltage VOUT2, and the third output voltage VOUT3 suddenly increases, the third signal generation circuit 223 extends the conduction time of the primary switch SWP, thereby extending the magnetization time of the transformer TM, so that the transformer TM has more energy to power the first output voltage VOUT1, the second output voltage VOUT2, and the third output voltage VOUT3.

[0173] Figure 7 A schematic diagram of a power conversion circuit according to another embodiment of the present invention is shown. The control circuit 710 of the power conversion circuit 700 is connected to... Figure 6 Compared to the control circuit 610, the current comparator CMPC is used to replace Figure 6 The third comparator CMP3 and the fourth signal generation circuit 631.

[0174] like Figure 7 As shown, the current comparator CMPC is used to compare the secondary current IS with the current threshold ITH to generate a current comparison signal SCPC. According to one embodiment of the present invention, when the secondary current IS is lower than the current threshold ITH, the current comparator CMPC enables the current comparison signal SCPC. According to another embodiment of the present invention, when the secondary current IS is not lower than the current threshold ITH, the current comparator CMPC disables the current comparison signal SCPC.

[0175] According to some embodiments of the present invention, after the second signal generation circuit 621 enables the third signal S3 and the secondary current IS is lower than the current threshold ITH, the second signal generation circuit 621 disables the third signal S3 based on the enabled current comparison signal SCPC, thereby turning off the third switch SW3. In other words, when the secondary current IS drops to near zero, the control circuit 710 turns off the third switch SW3, thereby stopping the power supply to the third output voltage VOUT3. According to some embodiments of the present invention, when the transformer TM finishes demagnetizing, the control circuit 710 immediately turns off the third switch SW3.

[0176] Figure 8 This is a schematic diagram showing a power conversion circuit according to another embodiment of the present invention. The power conversion circuit 800 is connected to... Figure 1 Compared to the power conversion circuit 100, Figure 1 The first switch SW1 is replaced with the first rectifier transistor TR1 and the first blocking transistor TA1. Figure 1 The second switch SW2 is replaced by the second rectifier transistor TR2 and the second blocking transistor TA2. Furthermore, Figure 1 The control circuit 110 is replaced with the control circuit 810.

[0177] The first rectifier transistor TR1 includes a first rectifier gate terminal GR1, a first rectifier drain terminal DR1, and a first rectifier source terminal SR1. The first blocking transistor TA1 includes a first blocking gate terminal GA1, a first blocking drain terminal DA1, and a first blocking source terminal SA1. The first rectifier gate terminal GR1 receives a first rectified signal R1. The first rectifier drain terminal DR1 is electrically connected to the first blocking drain terminal DA1. The first rectifier source terminal SR1 receives the secondary current IS. The first blocking gate terminal GA1 receives a first blocking signal A1. The first blocking source terminal SA1 is coupled to the first output voltage VOUT1.

[0178] The second rectifier transistor TR2 includes a second rectifier gate terminal GR2, a second rectifier drain terminal DR2, and a second rectifier source terminal SR2. The second blocking transistor TA2 includes a second blocking gate terminal GA2, a second blocking drain terminal DA2, and a second blocking source terminal SA2. The second rectifier gate terminal GR2 receives the second rectified signal R2. The second rectifier drain terminal DR2 is electrically connected to the second blocking drain terminal DA2. The second rectifier source terminal SR2 receives the secondary current IS. The second blocking gate terminal GA2 receives the second blocking signal A2. The second blocking source terminal SA2 is coupled to the second output voltage VOUT2.

[0179] like Figure 8 As shown, the control circuit 810 includes a first control circuit 811 and a second control circuit 812. The first control circuit 811 generates a first rectified signal R1, a first blocking signal A1, a second rectified signal R2, and a second blocking signal A2 based on a first output voltage VOUT1, and generates a first error signal SEA1 based on the difference between the first output voltage VOUT1 and a first reference voltage VREF1. The second control circuit 812 generates a primary control signal SP based on the first error signal SEA1, a second output voltage VOUT2, and a second reference voltage VREF2, and generates a second rectified signal R2 and a second blocking signal A2 based on the second output voltage VOUT2.

[0180] Figure 9 The diagram shows a waveform of a power conversion circuit according to another embodiment of the present invention. The following description of waveform 900 will be accompanied by… Figure 8 The power conversion circuit 800 is described in detail below.

[0181] like Figure 9As shown, at the sixth time point T6, the primary control signal SP is enabled, turning on the primary switch SWP and magnetizing the transformer TM. Between the sixth time point T6 and the seventh time point T7, the primary current IP increases linearly. At the seventh time point T7, since the primary current IP is not less than the feedback signal SFB, the primary control signal SP is deactivated, turning off the primary switch SWP and demagnetizing the transformer TM, generating a secondary current IS.

[0182] According to some embodiments of the present invention, the power conversion circuit 800 may include a current detection circuit. Figure 8 (Not shown), used to detect the primary current IP to generate a current detection signal. When the current detection signal is not less than the feedback signal SFB, the second control circuit 812 turns off the primary switch SWP at the seventh time point T7. Figure 9 The explanation uses the primary current IP to represent the current detection signal, but is not limited to this in any way.

[0183] When transformer TM begins demagnetization at time point T7, generating secondary current IS, the first rectifier signal R1 is simultaneously enabled, turning on the first rectifier transistor TR1. Combined with the already turned-on first blocking transistor TA1, this causes the secondary current IS to charge the first output capacitor COUT1, generating the first output voltage VOUT1. For example... Figure 8 as well as Figure 9 As shown, between the seventh time point T7 and the eighth time point T8, the secondary current IS passes through the first rectifier transistor TR1 and the first blocking transistor TA1 to generate the first supply current IS1 that charges the first output capacitor COUT1.

[0184] When the first sawtooth wave RMP1 rises to a level not less than the first error signal SEA1 at the eighth time point T8, the first rectifier signal R1 is disabled, the first blocking signal A1 remains enabled, and the second blocking signal A2 is enabled, causing the first rectifier transistor TR1 to turn off, the first blocking transistor TA1 to remain on, and the second blocking transistor TA2 to turn on.

[0185] According to some embodiments of the present invention, since the first rectifier transistor TR1 and the second rectifier transistor TR2 are turned off and the first blocking transistor TA1 and the second blocking transistor TA2 are turned on between the eighth time point T8 and the ninth time point T9, the secondary current IS supplies power to the one with the lowest voltage value among the first output voltage VOUT1 and the second output voltage VOUT2 through the parasitic diode of the first rectifier transistor TR1 or the second rectifier transistor TR2.

[0186] exist Figure 9In this embodiment, the voltage value of the second output voltage VOUT2 is less than the voltage value of the first output voltage VOUT1 for illustration and explanation, but it is not limited to this in any way. Figure 9 As shown in the embodiment, since the second output voltage VOUT2 is less than the first output voltage VOUT1, power is supplied to the second output voltage VOUT2 from the eighth time point T8 to the ninth time point T9. Furthermore, when both the first blocking transistor TA1 and the second blocking transistor TA2 are turned on, the parasitic diodes of the first rectifier transistor TR1 and the second rectifier transistor TR2 are used to prevent the first output voltage VOUT1 and the second output voltage VOUT2 from supplying power to the secondary coil SS, and also to prevent the first output voltage VOUT1 and the second output voltage VOUT2 from supplying power to each other.

[0187] At the ninth time point T9, the second rectifier signal R2 is enabled and the first blocking signal A1 is disabled, causing the second rectifier transistor TR2 to turn on and the first blocking transistor TA1 to turn off. In other words, after the ninth time point T9, the power supply switches to the second output voltage VOUT2. Figure 9 As shown, between the ninth time point T9 and the tenth time point T10, the secondary current IS passes through the second rectifier transistor TR2 and the second blocking transistor TA2 to generate a second supply current IS2 that charges the second output capacitor COUT2.

[0188] According to one embodiment of the present invention, at the tenth time point T10, the second sawtooth wave RMP2 rises to a level not less than the second error signal SEA2, causing the second rectified signal R2 to be disabled and the second rectified transistor TR2 to be turned off. According to another embodiment of the present invention, since the secondary current IS drops to zero at the tenth time point T10, the control circuit 810 can disable the second signal S2 based on the secondary current IS dropping to zero (or the secondary current IS dropping below the current threshold), thereby turning off the second switch SW2. At the eleventh time point T11, the first blocking signal A1 is enabled and the second blocking signal A2 is disabled, causing the first blocking transistor TA1 to be turned on and the second blocking transistor TA2 to be turned off.

[0189] At the twelfth time point T12, the primary control signal SP is enabled, turning on the primary switch SWP, and the on-time of the primary switch SWP is determined based on the first output voltage VOUT1 and the second output voltage VOUT2. According to some embodiments of the present invention, the period from the sixth time point T6 to the twelfth time point T12 is the switching time TSW.

[0190] By Figure 1 The first switch SW1 is replaced with Figure 8 The first rectifier transistor TR1 and the first blocking transistor TA1 and the Figure 1The second switch SW2 is replaced with Figure 8 The second rectifier transistor TR2 and the second blocking transistor TA2 prevent the first output voltage VOUT1 and the second output voltage VOUT2 from supplying power to each other, and also prevent the first output voltage VOUT1 and the second output voltage VOUT2 from discharging to the ground terminal through the secondary coil SS.

[0191] Figure 10 A flowchart of a control method according to one embodiment of the present invention is shown. The following description of the control method 1000 will be accompanied by… Figure 2 Power conversion circuit 200 Figure 3 The power conversion circuit 300 and Figure 4 The waveform diagram 400 is provided for detailed explanation.

[0192] First, during the magnetization time, the transformer TM is magnetized (step S1010). Figure 2 In one embodiment, the primary switch SWP is turned on, causing the input voltage VIN to magnetize the transformer TM (i.e., the primary coil PS). Figure 4 In this embodiment, the magnetization time is between the first time point T1 and the second time point T2, and the demagnetization time is between the second time point T2 and the fourth time point T4. After the magnetization time, the second current IS flowing through the secondary coil SS is used to power the first output voltage VOUT1 (step S1020).

[0193] Based on the first output voltage VOUT1, power supply to the first output voltage VOUT1 is stopped and power supply to the second output voltage VOUT2 is started (step S1030). Figure 2 as well as Figure 4 In one embodiment, when the first sawtooth wave RMP1 rises to a level not less than the first error signal SEA1, the first comparator CMP1 disables the first comparison signal SCP1. The first signal generation circuit 211, based on the disabled first comparison signal SCP1, in... Figure 4 At the third time point T3, the first signal S1 is disabled and the second signal S2 is enabled, thereby stopping the power supply to the first output voltage VOUT1 and starting the power supply to the second output voltage VOUT2.

[0194] According to one embodiment of the present invention, after step S1030, power supply to the second output voltage VOUT2 is stopped based on the second output voltage VOUT2 (step S1041). Figure 2 as well as Figure 4In this embodiment, when the second sawtooth wave RMP2 rises to a level not less than the second error signal SEA2, the second comparator CMP2 disables the second comparison signal SCP2. Based on the disabled second comparison signal SCP2, the second signal generation circuit 221 disables the second signal S2 at the fourth time point T4, thereby stopping the power supply to the second output voltage VOUT2.

[0195] According to another embodiment of the present invention, after step S1030, power supply to the second output voltage VOUT2 is stopped based on the secondary current IS (step S1042). Figure 3 as well as Figure 4 In one embodiment, when the secondary current IS drops to zero at the fourth time point T4 (i.e., the secondary current IS drops below the current threshold ITH), the first signal generation circuit 211 disables the second signal S2, thereby stopping the power supply to the second output voltage VOUT2.

[0196] After step S1041 or step S1042, the magnetization time is adjusted based on the first output voltage VOUT1 and the second output voltage VOUT2 (step S1050), and the process returns to step S1010 for the next switching time TSW. Figure 2 In one embodiment, the isolation circuit 222 and the third signal generation circuit 223 generate a primary control signal SP based on the first error signal SEA1 and the second error signal SEA2 to adjust the conduction time of the primary switch SWP.

[0197] In other words, the isolation circuit 222 and the third signal generation circuit 223 adjust the on-time of the primary switch SWP based on the difference between the first output voltage VOUT1 and the first reference voltage VREF1 and the difference between the second output voltage VOUT2 and the second reference voltage VREF2, thereby adjusting the magnetization time. After step S1050, the circuit returns to step S1010 to continue the next switching time TSW, and magnetizes the transformer TM with the adjusted magnetization time.

[0198] According to other embodiments of the present invention, the isolation circuit 222 and the third signal generation circuit 223 adjust the on-time of the primary switch SWP based on the output power of the first output voltage VOUT1 and the output power of the second output voltage VOUT2. In other words, the on-time of the primary switch SWP is extended when the output power of the first output voltage VOUT1 or the output power of the second output voltage VOUT2 increases.

[0199] This invention proposes a power conversion circuit with multiple output voltages and its control method. Compared to the traditional method of using multiple secondary coils (or multiple transformers) and additional voltage regulators to regulate individual output voltages, the power conversion circuit with multiple output voltages proposed in this invention can use a transformer with a single secondary coil and multiple switches to supply power to multiple output voltages in a time-sharing manner. Because this invention uses a transformer with a single secondary coil and multiple switches, it significantly reduces costs and circuit complexity, while also improving conversion efficiency. Furthermore, the multiple output voltages of the power conversion circuit proposed in this invention can be individually programmed.

[0200] While the embodiments and advantages of this application have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this application. Furthermore, the scope of protection of this application is not limited to the processes, computers, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments herein. Any person skilled in the art can understand, from the disclosure of some embodiments of this application, current or future developed processes, computers, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, they can be used according to some embodiments of this application. Therefore, the scope of protection of this application includes the aforementioned processes, computers, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this application also includes combinations of the various claims and embodiments.

Claims

1. A power conversion circuit, characterized in that, include: A transformer includes a primary coil and a secondary coil, wherein the primary coil receives an input voltage and the secondary coil generates a primary current; A primary switch, based on a primary control signal, electrically connects the primary coil to a ground terminal; A first switch, based on a first signal, supplies power to a first output voltage from the secondary current; A second switch, based on a second signal, supplies power to a second output voltage from the secondary current; as well as A control circuit generates the first signal based on the first output voltage and generates the second signal based on the second output voltage; The control circuit generates the primary control signal based on the first output voltage and the second output voltage.

2. The power conversion circuit as described in claim 1, characterized in that, The control circuit includes: A first error amplifier generates a first error signal based on the difference between the first output voltage and a first reference voltage; A first comparator compares the first error signal with a first sawtooth wave to generate a first comparison signal; and A first signal generation circuit generates the first signal based on the first comparison signal; When the primary switch is turned off, the control circuit enables the first signal to turn on the first switch. When the first sawtooth wave is not less than the first error signal, the first signal generating circuit disables the first signal and simultaneously enables the second signal, causing the first switch to turn off and the second switch to turn on.

3. The power conversion circuit as described in claim 2, characterized in that, The first signal generation circuit disables the second signal based on the secondary current dropping below a current threshold, thereby turning off the second switch.

4. The power conversion circuit as described in claim 2, characterized in that, The control circuit also includes: A second error amplifier generates a second error signal based on the difference between the second output voltage and a second reference voltage; An isolation circuit generates a feedback signal based on the first error signal and the second error signal; and A third signal generation circuit generates the primary control signal based on the feedback signal.

5. The power conversion circuit as described in claim 4, characterized in that, When the first output voltage is less than the first reference voltage or the second output voltage is less than the second reference voltage, the third signal generation circuit extends the enable time of the primary control signal to extend the magnetization time of the primary coil.

6. The power conversion circuit as described in claim 4, characterized in that, The control circuit also includes: A current comparator compares the secondary current with a current threshold to generate a current comparison signal; When the secondary current is lower than the current threshold, the first signal generation circuit disables the second signal based on the current comparison signal, thereby turning off the second switch.

7. The power conversion circuit as described in claim 4, characterized in that, The control circuit also includes: A second comparator compares the second error signal with a second sawtooth wave to generate a second comparison signal; and A second signal generation circuit, based on the second comparison signal, disables the second signal; When the second sawtooth wave is not less than the second error signal, the second signal generating circuit disables the second signal, thereby turning off the second switch.

8. The power conversion circuit as described in claim 7, characterized in that, Also includes: A third switch, based on a third signal, supplies power to a third output voltage from the secondary current; The control circuit further includes: A third error amplifier generates a third error signal based on the difference between the third output voltage and a third reference voltage; When the second signal generation circuit disables the second signal, it simultaneously enables the third signal; The isolation circuit generates the feedback signal based on the first error signal, the second error signal, and the third error signal.

9. The power conversion circuit as described in claim 8, characterized in that, The control circuit also includes: A current comparator compares the secondary current with a current threshold to generate a current comparison signal; When the secondary current is lower than the current threshold, the second signal generation circuit disables the third signal based on the current comparison signal, thereby turning off the third switch.

10. The power conversion circuit as described in claim 8, characterized in that, The control circuit also includes: A third comparator compares the third error signal with a third sawtooth wave to generate a third comparison signal; and A fourth signal generation circuit, based on the third comparison signal, disables the third signal; When the third sawtooth wave is not less than the third error signal, the fourth signal generating circuit disables the third signal, thereby turning off the third switch.

11. The power conversion circuit as described in claim 1, characterized in that, Also includes: A primary switch is connected in series with the secondary coil; When the primary switch is turned on, the secondary switch is turned off; When the primary switch is turned off, the secondary switch is turned on, so that the secondary current supplies power to one of the first output voltage and the second output voltage.

12. The power conversion circuit as described in claim 1, characterized in that, The first switch includes: A first rectifier transistor includes a first rectifier gate terminal, a first rectifier drain terminal, and a first rectifier source terminal; and A first blocking transistor includes a first blocking gate terminal, a first blocking drain terminal, and a first blocking source terminal; The first rectifier gate terminal receives a first rectified signal, the first rectifier drain terminal is electrically connected to the first blocking drain terminal, and the first rectifier source terminal receives the secondary current. The first blocking gate terminal receives a first blocking signal, and the first blocking source terminal is coupled to the first output voltage.

13. The power conversion circuit as described in claim 12, characterized in that, The second switch includes: A second rectifier transistor, including a second rectifier gate terminal, a second rectifier drain terminal, and a second rectifier source terminal; and A second blocking transistor includes a second blocking gate terminal, a second blocking drain terminal, and a second blocking source terminal; The second rectifier gate terminal receives a second rectified signal, the second rectifier drain terminal is electrically connected to the second blocking drain terminal, and the second rectifier source terminal receives the secondary current. The second blocking gate terminal receives a second blocking signal, and the second blocking source terminal is coupled to the second output voltage.

14. The power conversion circuit as described in claim 13, characterized in that, The on-time of the first rectifier transistor does not overlap with the on-time of the second rectifier transistor.

15. The power conversion circuit as described in claim 13, characterized in that, During a first period, both the first rectifier transistor and the first blocking transistor are turned on, so that the secondary current supplies power to the first output voltage; During a second period following the first period, the first rectifier transistor is turned off and both the first blocking transistor and the second blocking transistor are turned on, such that the secondary current supplies power to the lower of the first output voltage and the second output voltage. During a third period following the second period, the first blocking transistor is turned off and the second rectifier transistor is turned on, so that the secondary current supplies power to the second output voltage.

16. A control method for controlling a power conversion circuit to convert an input voltage into a first output voltage and a second output voltage, characterized in that, The power conversion circuit includes a transformer, wherein the transformer includes a primary coil and a secondary coil, and the control method includes: The primary coil is magnetized during a magnetization time; After the magnetization time, the first output voltage is powered by the primary current flowing through the secondary coil; Based on the first output voltage, stop supplying power to the first output voltage and start supplying power to the second output voltage; and The magnetization time is adjusted based on the first output voltage and the second output voltage.

17. The control method as described in claim 16, characterized in that, Also includes: Based on the second output voltage, the power supply to the second output voltage is stopped.

18. The control method as described in claim 16, characterized in that, Also includes: Based on the secondary current, the power supply to the second output voltage is stopped.

19. The control method as described in claim 16, characterized in that, The step of adjusting the magnetization time based on the first output voltage and the second output voltage further includes: A first error signal is generated based on the difference between the first output voltage and a first reference voltage; A second error signal is generated based on the difference between the second output voltage and a second reference voltage; and The magnetization time is determined based on the first error signal and the second error signal. When the first output voltage is less than the first reference voltage, the magnetization time is extended. When the second output voltage is less than the second reference voltage, the magnetization time is extended.

20. The control method as described in claim 16, characterized in that, The step of adjusting the magnetization time based on the first output voltage and the second output voltage further includes: Determine the output power of the first output voltage and the output power of the second output voltage; When the output power of the first output voltage increases, the magnetization time is extended; and When it is determined that the output power of the second output voltage increases, the magnetization time is extended.

21. The control method as described in claim 16, characterized in that, The secondary current supplies power to the first output voltage via a first rectifier transistor and a first blocking transistor, and the secondary current supplies power to the second output voltage via a second rectifier transistor and a second blocking transistor. The source terminal of the first rectifier transistor receives the secondary current, the drain terminal of the first rectifier transistor is coupled to the drain terminal of the first blocking transistor, and the source terminal of the first blocking transistor is coupled to the first output voltage. The source terminal of the second rectifier transistor receives the secondary current, the drain terminal of the second rectifier transistor is coupled to the drain terminal of the second blocking transistor, and the source terminal of the second blocking transistor is coupled to the second output voltage.

22. The control method as described in claim 21, characterized in that, Also includes: During a first period, the first rectifier transistor and the first blocking transistor are simultaneously turned on, so that the secondary current supplies power to the first output voltage; During a second period following the first period, the first rectifier transistor is turned off and the first blocking transistor and the second blocking transistor are turned on, such that the secondary current supplies power to the first output voltage and the second output voltage having a lower voltage value. as well as During a third period following the second period, the first blocking transistor is turned off and the second rectifier transistor is turned on, so that the secondary current supplies power to the second output voltage.

Images