System and method for charging compensator capacitor in dc-dc converter

Abstract

Disclosed herein are DC-DC converters and converter systems, compensator circuits for the DC-DC converters and converter systems, and related methods. In a first example embodiment, a DC-DC converter includes an amplifier circuit, a compensator circuit, and a control circuit. The compensator circuit includes an error amplifier, a comparator, and an intermediate circuit network. The intermediate circuit network includes a first node, at least one first switchable component coupling the first node with a first output of the error amplifier, and a plurality of switched capacitor networks each having a respective capacitor. The control circuit is configured to cause the respective capacitors to reach respective voltages at a first time, and the control circuit is configured to cause the respective capacitors of the respective switched capacitor networks to be coupled to the first node at a second time such that the first node reaches a compensator voltage.

Description

Technical Field

[0001] This disclosure relates to systems and methods associated with DC-DC (“DC-DC”) converters, and more specifically, to systems and methods for charging compensator capacitors in or associated with DC-DC converters, for example, as may be applicable during a transition from light-load operation to heavy-load operation. Background Technology

[0002] This technology relates to systems and methods for controlling DC-DC converters, including, for example, buck converters, boost converters, and buck-boost converters. The term "buck-boost converter" as used herein should be understood to encompass any buck converter, boost converter, and / or buck-boost converter. Summary of the Invention

[0003] This disclosure relates to systems and methods for operating DC-DC converters, including, for example, buck converters, boost converters, and buck-boost converters.

[0004] In a first example embodiment, a DC-DC converter includes an amplifier circuit, a compensator circuit, and a control circuit. The amplifier circuit includes an output power circuit and a feedback circuit, and the compensator circuit is coupled to the amplifier circuit. The compensator circuit includes an error amplifier, a comparator, and an intermediate circuit network. The error amplifier has a first input and a first output, and the comparator has a second input and a second output. The second input is coupled to the first output of the error amplifier, and the second output is coupled to an additional input of the output power circuit. Furthermore, the intermediate circuit network includes a first node, at least one first switchable component, and a plurality of switched capacitor networks. The at least one first switchable component couples the first node to the first output of the error amplifier, and each switched capacitor network has a corresponding capacitor. The control circuit is coupled to each of the switched capacitor networks. Furthermore, the control circuit is configured to cause the corresponding capacitor of the corresponding switched capacitor network to reach a corresponding voltage at a first time, and wherein the control circuit is configured to couple the corresponding capacitor of the corresponding switched capacitor network to the first node at a second time, such that the first node reaches the compensator voltage.

[0005] In one such example embodiment, each of the respective capacitors in the respective switched capacitor networks is coupled to the first node via a respective capacitor connection switch. The control circuit is configured to provide a first control signal to the plurality of switched capacitor networks at a first time to cause the respective capacitor of the respective switched capacitor network to reach a corresponding voltage. The control circuit is configured to provide a second control signal to the plurality of switched capacitor networks at a second time to cause the respective capacitor of the respective switched capacitor network to couple to the first node, causing the first node to reach the compensator voltage. The control circuit is further configured to provide a third control signal to the plurality of switched capacitor networks at a third time to decouple the respective capacitor or the respective capacitor of one or more of the respective switched capacitor networks from the first node, such that the desired compensation capacitance remains coupled to the first node.

[0006] In one such example embodiment, at the first time, the DC-DC converter operates in a first operating mode, which is at least one of a light-load operating mode, a no-load operating mode, or a pulse frequency modulation (PFM) operating mode.

[0007] In one such example embodiment, the second time occurs at or just before the additional time during which the DC-DC converter switches from the first operating mode to the second operating mode, the second operating mode being one of a medium load operating mode, a high load operating mode, a heavy load operating mode, a medium-high load operating mode, a medium-heavy load operating mode, or a pulse width modulation (PWM) operating mode.

[0008] In one such example embodiment, at the third time, the DC-DC converter operates in the second operating mode, and the control circuit operates at least in part based on a digital finite state machine (FSM) or a lookup table (LUT).

[0009] In one such example embodiment, each of the switched capacitor network includes a corresponding internal node, a corresponding first switch, and a corresponding second switch, wherein the corresponding first switch is coupled between the corresponding internal node and a ground node, wherein the corresponding second switch is the corresponding capacitor connection switch of the corresponding switched capacitor network and is coupled between the corresponding internal node and the first node, and wherein each of the corresponding capacitors of the corresponding switched capacitor network is coupled between the corresponding internal node and the ground node.

[0010] In one such example embodiment, with respect to one or more of the switched capacitor networks, the respective switched capacitor network includes a respective third switch, and the respective third switch is coupled between the respective internal node and the power supply node.

[0011] In one such example embodiment, the at least one first switchable component includes a parallel combination of a stabilizing resistor and a transfer switch, wherein each of the stabilizing resistor and the transfer switch is at least indirectly coupled between the first node and the first output, and wherein the DC-DC converter further includes a high-frequency capacitor, which is at least indirectly coupled between the first output and the ground node.

[0012] In one such example embodiment, the DC-DC converter is at least one of a buck converter, a boost converter, or a buck-boost converter, and the control circuitry is included in the compensator circuitry.

[0013] In a second example embodiment, a compensator circuit for a DC-DC converter includes a comparator amplifier and a pulse width modulation (PWM) comparator. The comparator amplifier has a first input and a first output, and the PWM comparator has a second input and a second output, the second input being at least indirectly coupled to the first output of the comparator amplifier. The compensator circuit also includes an intermediate circuit network comprising an integrator node, at least one first switchable component, and a plurality of switched capacitor networks. The at least one first switchable component at least indirectly couples the integrator node to the first output of the comparator amplifier. Each of the switched capacitor networks includes a corresponding capacitor, a corresponding internal node, a corresponding first switch, and a corresponding second switch. Furthermore, each of the corresponding first switches is coupled between the corresponding internal node and a ground node or a corresponding first voltage node, each of the corresponding second switches is coupled between the corresponding internal node and the integrator node, and each of the corresponding capacitors is coupled to the corresponding internal node. Additionally, the corresponding second switch is controlled such that, at a first time, each of the corresponding capacitors is coupled to the integrator node, causing the integrator node to reach a first voltage or a first charge level, and at a second time, at least one of the capacitors remains coupled to the integrator node to function as a compensator capacitor.

[0014] In one such example embodiment, with respect to one or more of the switched capacitor networks, the respective switched capacitor network includes a respective third switch, and the respective third switch is coupled between the respective internal node and the respective additional voltage node.

[0015] In one such example embodiment, each of the respective first switches is coupled between the respective internal node and the ground node, wherein the respective additional voltage node is a power supply node, and wherein each of the respective capacitors of the respective switch capacitor network is coupled between the respective node and the ground node.

[0016] In one such example embodiment, the at least one first switchable component includes a parallel combination of a stabilizing resistor and a transfer switch, wherein each of the stabilizing resistor and the transfer switch is at least indirectly coupled between the integrator node and the first output, and wherein the compensator circuit further includes a high-frequency capacitor, which is at least indirectly coupled between the first output and the ground node.

[0017] In one such example embodiment, the compensator circuit further includes control circuitry that is at least indirectly coupled to the respective first switch, the respective second switch, the respective third switch, and the transfer switch, and is configured to provide control signals to actuate each of the respective first switch, the respective second switch, the respective third switch, and the transfer switch.

[0018] In one such example embodiment, the plurality of switched capacitor networks include at least three and no more than ten said capacitors, and said respective capacitors have corresponding capacitance values ​​associated in a binary manner.

[0019] In a third example embodiment, this disclosure relates to a method for controlling a DC-DC converter having an amplifier circuit coupled to a compensator circuit, the compensator circuit including an integrator node and a plurality of switched capacitor networks, each switched capacitor network having a corresponding capacitor and a corresponding capacitor connection switch, the corresponding capacitor connection switch being at least indirectly located between the corresponding capacitor and the integrator node. The method includes: at a first time when the DC-DC converter is operating in a first operating mode, firstly actuating the corresponding capacitor connection switch of the corresponding switched capacitor network to decouple the corresponding capacitor of the corresponding switched capacitor network from the integrator node, such that the corresponding capacitor can be set to have a corresponding capacitor voltage; furthermore, the method includes: at a second time after the first time, secondly actuating the corresponding capacitor connection switch of the corresponding switched capacitor network, such that all the corresponding capacitors are coupled to the integrator node to establish a compensator voltage at the integrator node. Additionally, the method includes: at a third time after the second time, when the DC-DC converter is operating in a second operating mode, actuating again a first subset of the capacitor connection switches of the plurality of switched capacitor networks such that each capacitor in the first subset of the capacitors of the plurality of switched capacitor networks is decoupled from the integrator node, but each capacitor in the second subset of the capacitors of the plurality of switched capacitor networks remains coupled to the integrator node, such that a compensation capacitor is coupled to the integrator node.

[0020] In one such example embodiment, the first actuation, the second actuation, and the third actuation are triggered by a control signal provided by at least one control circuit.

[0021] In one such example embodiment, at the first time, the at least one control circuit provides a first additional control signal that causes a corresponding additional switch coupled between the corresponding capacitor and the corresponding additional node to close, such that the corresponding additional node is at least indirectly coupled to the corresponding capacitor, and such that the corresponding capacitor is set to have the corresponding capacitor voltage, and at the second time, the at least one control circuit provides a second additional control signal that causes the corresponding additional switch coupled between the corresponding capacitor and the corresponding additional node to open.

[0022] In one such example embodiment, the first operating mode is at least one of a light load operating mode, a no-load operating mode, or a pulse frequency modulation (PFM) operating mode, and the second operating mode is one of a medium load operating mode, a high load operating mode, a heavy load operating mode, a medium-high load operating mode, a medium-heavy load operating mode, or a pulse width modulation (PWM) operating mode, and the second time occurs at or just before the transition time of the DC-DC converter from being in the first operating mode to being in the second operating mode.

[0023] In one such example embodiment, the compensation circuit includes a parallel combination of a stabilizing resistor and a transfer switch, wherein each of the stabilizing resistor and the transfer switch is at least indirectly coupled between the integrator node and a first output of the comparator of the compensation circuit, and the method further includes actuating the transfer switch to short-circuit the stabilizing resistor at least during a first time period between the second time and the third time. Attached Figure Description

[0024] Specific examples have been selected for illustrative and descriptive purposes, and are shown in the accompanying drawings that form part of the specification.

[0025] Figure 1 This is a schematic diagram illustrating an example DC-DC converter (or DC-DC converter circuit) with a compensator (or compensator circuit) according to an example embodiment covered herein;

[0026] Figure 2 It is shown Figure 1 A flowchart illustrating an example operation of a DC-DC converter; and

[0027] Figure 3 It is shown Figure 1 Timing diagram of an example operation mode of a DC-DC converter.

[0028] While the various embodiments discussed herein may be modified and alternatively formed, aspects thereof have been shown by way of example in the accompanying drawings and described in detail herein. However, it should be understood that this disclosure is not limited to the specific embodiments described, but is intended to include all modifications, equivalents, and alternatives falling within the scope of this disclosure. Furthermore, the terms “example” and “embodiment” as used throughout this application are for illustrative purposes only and not for limitation; the drawings are not necessarily drawn to scale, and unless otherwise stated, the same reference numerals are used in different drawings to denote similar or identical items. The term “configured” as used herein with respect to components “being configured” to have certain structural characteristics or perform a particular function in a particular situation means that the component is structurally formed such that the component satisfies said structural characteristics or performs said function in a particular situation without further modification. The term “operably connected” as used herein means that two components are electrically connected directly or indirectly in such a way that the disclosed signal is transmitted from at least one of the components to the other. The term “about” as used herein with respect to any measurement or physical characteristic means approximately and includes the measurement or physical characteristic plus or minus an amount within an acceptable error range or other variance amount that maintains the desired function. Detailed Implementation

[0029] The systems and methods described herein can be applied to any type of DC-DC converter, including any type of DC-DC converter that may undergo transitions from low quiescent, pulse frequency modulation (PFM), light load or no load (or light or zero current) modes or conditions to medium current or high current (or medium load or high load) or pulse width modulation (PWM) modes or conditions.

[0030] Even when operating under light or no-load conditions, DC-DC converters require high efficiency. Under light or no-load conditions, many circuits are shut down or operate under light bias. For example, one circuit ideally to be shut down or lightly biased is the error compensation amplifier.

[0031] Even if it is expected that one or more circuits will be turned off under light or no-load conditions or operate under light bias conditions, it is important to quickly turn on one or more such circuits to prevent a significant drop in output voltage when the output load current suddenly increases.

[0032] Despite these problems, a drawback of many DC-DC circuits is that they continue to draw DC current during light or no-load operation, or cause the compensator capacitor to discharge to an undesirable (e.g., undesirable low) voltage, or employ undesirable and complex active or passive clamping circuitry to maintain the voltage of the compensator capacitor at the desired level.

[0033] For at least one or more of these reasons, or for one or more other reasons, it would be advantageous if new or improved systems could be developed, and / or improved operating or implementation methods could be developed to address any or more of the problems discussed above or to solve one or more other problems or to provide one or more benefits.

[0034] The inventors have recognized the aforementioned problems associated with DC-DC converters. In this regard, the inventors have also recognized that, in order to achieve enhanced performance of the DC-DC converter when transitioning from light-load or no-load conditions to increased-load operating conditions, it is desirable to pre-position the output voltage of the error amplifier to a voltage that allows the DC-DC converter to respond quickly to the increase in load before such a transition. Furthermore, the inventors have recognized that, in at least some DC-DC converters, if compensation components (specifically, capacitors) connected to the output of the error amplifier remain floating during light-load or no-load conditions, these compensation components may leak. Additionally, the inventors have recognized that, in order to achieve enhanced performance of the DC-DC converter, it is desirable to support the capacitor voltage in a certain way.

[0035] In view of these considerations, the inventors have recognized that, in at least some embodiments, an improved DC-DC converter can be implemented by employing a switched capacitor network (or switched capacitor bank, switched capacitor circuit, or switched capacitor architecture) to form a compensation capacitor for the DC-DC converter. In at least some embodiments, the capacitors of the switched capacitor network also serve as (or act as) compensation capacitors. In at least some embodiments, this improved DC-DC converter is used to charge the compensation capacitor of the DC-DC converter before entering medium-heavy load (or medium-high load, or at least medium load) operation. Furthermore, in at least some embodiments, this improved DC-DC converter circuit uses a switched capacitor bank to pre-position the voltage of the compensator capacitor, the switched capacitor bank presets the compensation circuit voltage to a predetermined voltage that allows for a smooth start-up to heavy load operation. Furthermore, in at least some embodiments, the switched capacitors that generate voltage within the improved DC-DC converter also act as compensation capacitors in the improved DC-DC converter.

[0036] By implementing this switched capacitor circuit (or switched capacitor bank, switched capacitor circuit, or switched capacitor architecture) in this improved DC-DC converter, the improved DC-DC converter can be operated according to a method that includes rapidly presetting the voltage of the capacitors in the compensation circuit of the DC-DC converter without any DC bias current requirement. Furthermore, advantageously, the improved DC-DC converter can draw zero DC current (or substantially zero DC current) during light-load or no-load operation (during which zero DC current draw improves efficiency).

[0037] Furthermore, according to embodiments, the improved DC-DC converter can be used as a stand-alone bias circuit or in conjunction with a digital control loop. More specifically, according to embodiments, the switched capacitor network of the improved DC-DC converter can be used as a stand-alone circuit without an external digital control network, or the switched capacitor network can be controlled by an external digital controller. Moreover, in at least some of the embodiments covered herein, the improved DC-DC converter not only uses zero (or substantially zero) DC current during light-load or no-load operation, but also provides the flexibility to charge the capacitors to a desired pre-programmed voltage before entering heavy-load operation. Furthermore, in at least some of such embodiments, the pre-programmed voltage can be programmed by memory or by the digital controller to a wide range of values, which can also be used to improve the performance of the DC-DC converter when entering pulse-width modulation (PWM) operation. In fact, in at least some of the embodiments covered herein, the compensation capacitor value and voltage can be dynamically changed by an external digital controller.

[0038] refer to Figure 1 A schematic diagram is provided to illustrate an example DC-DC converter (or DC-DC converter circuit) 100 according to an exemplary embodiment covered herein. The DC-DC converter 100 includes a compensator (or compensator circuit) 102 combined with an output power circuit (or output power stage) 104 and a feedback circuit 106. In a sense, the DC-DC converter 100 can be considered to have two control loops, a first control loop and a second control loop. The first control loop encompasses an amplifier circuit including the output power circuit 104 and the feedback circuit 106, and the second control loop is formed by the compensator 102 (which can be considered a resistor / capacitor (RC) circuit). Although not shown, the output power circuit 104 may include high-side transistors and low-side transistors, for example, bipolar junction transistors (BJTs) or other transistor devices.

[0039] In this example embodiment, the compensator 102 includes control circuitry (e.g., a controller, microprocessor, or application-specific integrated circuit) 101, an error amplifier 108, a PWM comparator 110, and an intermediate circuit network 112. Although the compensator 102 is described herein as including all these components (108, 110, 112, and 101), it is also suitable to consider the compensator as specifically constituting the intermediate circuit network 112, and to consider the error amplifier 108 and the PWM comparator 110 (and the control circuitry 101) as portions of the DC-DC converter 100 external to the compensator. Furthermore, as Figure 1 As shown, the PWM comparator 110 has an output port 114, which is coupled to an input port 116 of the output power circuit 104. The output power circuit 104 provides an output signal (e.g., output voltage and / or output current) at its output port (or node) 118, which can be provided to a load via an output node 128 (which may be the same electrical node as the output port 118). Additionally, the output port 118 is coupled to an input port 120 of a feedback circuit 106. The output port 122 of the feedback circuit 106 is further coupled to a first input port 124 of an error amplifier 108, which also includes a second input port 126 at which a reference voltage (V0) is received. ref Although control circuitry 101 is included as part of compensator 102 in this example embodiment, in alternative embodiments, control circuitry may be different from compensator but may still constitute part of DC-DC converter 100, or alternatively, may be different from DC-DC converter.

[0040] During operation, amplifier 108 provides a signal to PWM comparator 110 based on the difference between the feedback signal received from feedback circuit 106 at first input port 124 and the reference voltage received at second input port 126. The PWM comparator then provides a control signal to output power circuit 104, thereby managing the output provided at output node 128 (e.g., for reception by a load not shown).

[0041] Further reference Figure 1Within the compensator 102, a node 130 is provided, at which each of the error amplifier 108, the PWM comparator 110, and the intermediate circuit network 112 is coupled. Node 130 can be considered as forming part of the intermediate circuit network 112, and specifically forms the connection between the output port 132 of the error amplifier 108 and the input port 134 of the PWM comparator (and acts as both the output port 132 and the input port 134). Furthermore, the intermediate circuit network 112 additionally includes each of the following: a stabilizing resistor 136 (R_zero), a high-frequency capacitor 138 (C_high_frequency), a switched capacitor network (or switched capacitor bank) 140, and a transfer switch 142 coupled in parallel with the stabilizing resistor 136. The high-frequency capacitor 138 is coupled between node 130 and ground node 144. Stabilizing resistor 136 and transfer switch 142 are coupled in parallel between output node 128 of switched capacitor network 140 and another node 146 (which may also be referred to as capacitor integrator node, integrator node or "vcap_integrator node").

[0042] In addition, such as Figure 1As shown, in this example embodiment, the switched capacitor network 140 includes a plurality of switched (or switchable) capacitor circuit portions 148. Each of the switched capacitor circuit portions 148 can be considered (in some cases) to constitute a capacitor digital-to-analog circuit. More specifically, in this example embodiment, the plurality of switched capacitor circuit portions 148 includes each of a first switched capacitor circuit portion 150, a second switched capacitor circuit portion 152, a third switched capacitor circuit portion 154, a fourth switched capacitor circuit portion 156, and a fifth switched capacitor circuit portion 158 (although, as further mentioned below, any number of switched capacitor circuit portions may be provided in alternative embodiments). Each of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 includes: a corresponding capacitor 160 coupled between the corresponding internal node 162 and the ground node 144, a corresponding first (pchg_lo) switch 164 also coupled between the corresponding internal node 162 and the ground node 144, and a corresponding second switch 166 coupled between the corresponding internal node 162 and another node 146. Additionally, each of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, and the fourth switched capacitor circuit section 156 (but not the fifth switched capacitor circuit section 158) further includes: a corresponding third (pchg_hi) switch 168 coupled between the corresponding internal node 162 and the reference voltage (or power supply, power source, or VDD) node 170. It should be noted that each of the corresponding internal nodes 162 in the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 is a different node that can present different corresponding voltages (although in some operating conditions, two or more internal nodes 162 may share the same voltage, depending on the state of the corresponding first switch 164, the corresponding second switch 166, and the corresponding third switch 168). Furthermore, each of the corresponding first switch 164, the corresponding second switch 166, and the corresponding third switch 168 in the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 is independently controlled and can be independently actuated.

[0043] It should be understood that in this example embodiment, each of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 is identical, except that (a) the fifth switched capacitor circuit section 158 lacks a corresponding third (pchg_hi) switch, through which the corresponding internal node 162 can be coupled to the reference voltage node 170, and (b) each of the corresponding capacitors 160 of the corresponding first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 has a correspondingly different capacitance value. More specifically, in this example embodiment, the corresponding capacitor 160 of the first switched capacitor circuit section 150 has a capacitance value of 64 picofarads (pF), the corresponding capacitor 160 of the second switched capacitor circuit section 152 has a capacitance value of 32 pF, the corresponding capacitor 160 of the third switched capacitor circuit section 154 has a capacitance value of 16 pF, the corresponding capacitor 160 of the fourth switched capacitor circuit section 156 has a capacitance value of 8 pF, and the corresponding capacitor 160 of the fifth switched capacitor circuit section 158 has a capacitance value of 4 pF (however, in another embodiment, this capacitance value may be 2 pF).

[0044] Based on the respective positions of the first switch 164, the second switch 166, and the third switch 168 in each of the switched capacitor circuit sections 148, respectively, the respective internal node 162 and therefore the respective capacitor 160 of each of the respective switched capacitor circuit sections can be coupled to any one of the reference voltage node 170, the ground node 144, or another node 146. Similarly, based on the respective positions of the first switch 164 and the second switch 166 in the fifth switched capacitor circuit section 158, the respective internal node 162 and therefore the respective capacitor 160 of the respective switched capacitor circuit section can be coupled to any one of the ground node 144 or another node 146. More specifically, if the corresponding third switch 168 of any one of the corresponding switching capacitor circuit sections 150, 152, 154, and 156 is closed, but the corresponding second switch 166 and first switch 164 of the corresponding one of the switching capacitor circuit sections are open, then the corresponding internal node 162 of the corresponding one of the switching capacitor circuit sections will be coupled to the reference voltage node 170, and therefore a non-zero potential (voltage difference) will be applied across the corresponding capacitor 160 of the corresponding one of the switching capacitor circuit sections.

[0045] Furthermore, if the corresponding first switch 164 of any one of the switching capacitor circuit sections 150, 152, 154, and 156 is closed, but the corresponding second switch 166 and third switch 168 of that switching capacitor circuit section are open, then the corresponding internal node 162 of that switching capacitor circuit section will be coupled to the ground node 144, and thus a zero potential (voltage difference) will exist across the corresponding capacitor 160 of that switching capacitor circuit section. Similarly, if the corresponding first switch 164 of the fifth switching capacitor circuit section 158 is closed, but the corresponding second switch 166 of the fifth switching capacitor circuit section is open, then the corresponding internal node 162 of the fifth switching capacitor circuit section will be coupled to the ground node 144, and thus a zero potential will exist across the corresponding capacitor of the fifth switching capacitor circuit section. Furthermore, if the corresponding second switch 166 of any one of the switched capacitor circuit sections 150, 152, 154 and 156 is open, and both the corresponding first switch 164 and the corresponding third switch 168 of the corresponding switched capacitor circuit section are open before the corresponding second switch 166 is closed, then the corresponding internal node 162 (and the corresponding capacitor 160) of the corresponding switched capacitor circuit section will be in a floating state.

[0046] Additionally, as described in more detail below, when operating in light-load (or no-load or PFM) mode, the corresponding second switch 166 of the corresponding switched capacitor circuit section can be open, and the corresponding internal node 162 of the corresponding switched capacitor circuit section can be set to zero volts (the voltage at ground node 144) or a reference voltage (the voltage at reference voltage node 170, Vdd) to precharge the corresponding capacitor 160 to zero volts or the reference voltage (Vdd). In any given case, whether the corresponding first switch 164 or the corresponding third switch 168 is opened or closed to set the corresponding capacitor 160 to zero volts or the reference voltage (Vdd) will depend on the predetermined voltage subsequently preset on the compensation capacitor. Typically, during operation, no more than one of the corresponding switches 164, 166, and (if present) 168 coupled to the corresponding capacitor 160 of any given switched capacitor circuit section (e.g., only one or none) is closed at any given time. As will be described in more detail below, the predetermined voltage preset on the compensation capacitor can be calculated, for example, by means of a digital-to-analog converter (DAC) according to equation (1) or (2) provided below.

[0047] Furthermore, if the corresponding second switch 166 of any one of the switching capacitor circuit sections 150, 152, 154, and 156 is closed, but the corresponding first switch 164 and third switch 168 of that switching capacitor circuit section are open, then the corresponding internal node 162 of that switching capacitor circuit section will be coupled to the other node 146, and therefore the voltage (or potential) present at the internal node will be applied to the other node, and / or the voltage at the internal node will be the same as the voltage present at the other node 146. Additionally, when this occurs, the capacitance associated with the corresponding capacitor 160 of that switching capacitor circuit section will be coupled between the other node 146 and the ground node 144. Similarly, if the corresponding first switch 164 of the fifth switched capacitor circuit section 158 is open, but the corresponding second switch 166 of the fifth switched capacitor circuit section is closed, then the corresponding internal node 162 of the fifth switched capacitor circuit section will be coupled to the other node 146, and therefore the voltage (or potential) existing at the internal node will be applied to the other node, and / or the voltage at the internal node will present the voltage existing at the other node 146. Furthermore, when this occurs, the capacitance associated with the corresponding capacitor 160 of the fifth switched capacitor circuit section (e.g., 2 pF in this example) will be coupled between the other node 146 and the ground node 144.

[0048] Furthermore, if the corresponding second switch 166 of more than one of the corresponding switched capacitor circuit sections 148 is closed, and the other corresponding one or more switches of those corresponding switched capacitor circuit sections (both the corresponding first switch 164 and corresponding third switch 168 of any of the switched capacitor circuit sections 150, 152, 154, and 156, or the corresponding first switch 164 in the case of the fifth switched capacitor circuit section 158) are open, then all the corresponding capacitors 160 of these more than one corresponding switched capacitor circuit sections will be coupled in parallel between the additional node 146 and the ground node 144. Therefore, the corresponding capacitance of the corresponding capacitors 160 of these more than one corresponding switched capacitor circuit sections will all be coupled between the additional node 146 and the ground node 144, such that the additional node 146 will experience a total capacitance associated with those corresponding capacitors 160, which is equal to the sum of the corresponding capacitances of those corresponding capacitors.

[0049] For example, regarding Figure 1 In one embodiment, if the corresponding second switches 166 of all the corresponding switched capacitor circuit sections 150, 152, 154, 156, and 158 are closed, and if all the corresponding first switches 164 and third switches 168 of all those corresponding switched capacitor circuit sections are open (there are no corresponding third switches in the fifth switched capacitor circuit section 158), then the additional node 146 will experience a capacitance of 64 pF relative to the ground node 144 due to all the corresponding capacitors 160 of all those switched capacitor circuit sections. Alternatively, also for example regarding Figure 1 In an embodiment, if the corresponding second switches 166 of the first switched capacitor circuit section 150, the third switched capacitor circuit section 154, and the fourth switched capacitor circuit section 156 are closed, if all the corresponding first switches 164 and third switches 168 of all those corresponding first switched capacitor circuit sections, the third switched capacitor circuit section, and the fourth switched capacitor circuit section are open, and if the corresponding second switches 166 of the second switched capacitor circuit section 152 and the fifth switched capacitor circuit section 158 are open, then due to the corresponding capacitors 160 of the first switched capacitor circuit section 150, the third switched capacitor circuit section 154, and the fourth switched capacitor circuit section 156, the additional node 146 will experience a capacitance of 44 pF relative to the ground node 144.

[0050] although Figure 1 A switched capacitor network 140 is illustrated, but this disclosure covers many alternative embodiments of switched capacitor networks. For example, although... Figure 1The switched capacitor network 140 includes five (5) different switched capacitor circuit sections in switched capacitor circuit section 148, and correspondingly includes five (5) different capacitors in capacitor 160. However, other embodiments of the switched capacitor network may include fewer or more than five switched capacitor circuit sections, and correspondingly include fewer than five or more than five capacitors in capacitor 160. In practice, DC-DC converters employing the switched capacitor network covered by this disclosure typically range in number of switched capacitor circuit sections and corresponding capacitors included therein from at least three switched capacitor circuit sections and correspondingly at least three capacitors (with one capacitor provided in each switched capacitor circuit section) to a maximum of ten (10) switched capacitor circuit sections and correspondingly a maximum of ten (10) capacitors (with one capacitor provided in each switched capacitor circuit section). However, this example range of switched capacitor circuit sections and the corresponding range of three to ten capacitors are merely examples. This disclosure covers embodiments of DC-DC converters having any number of switched capacitor circuit sections and / or any number of capacitors, including embodiments having only one or two switched capacitor circuit sections and / or capacitors, and embodiments having more than two (or even more than ten) switched capacitor circuit sections and / or more than two (or even more than ten) capacitors.

[0051] Furthermore, the capacitance values ​​of various capacitors within different switched capacitor circuit sections of different switched capacitor networks can vary depending on the embodiment. For example, although the capacitance values ​​of the corresponding capacitors 160 in the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 do not need to be 32, 16, 8, 4, and 2 pF respectively as described above, they can instead be 64, 32, 16, 8, and 4 pF or other values. In fact, although the above-described capacitance values ​​of the corresponding capacitors 160 are all related by a factor of two, the corresponding capacitance values ​​of different capacitors in the capacitors do not need to be related by a specific factor, but can adopt any arbitrary capacitance value suitable for the embodiment. For example, in some other embodiments, each of the capacitors in consecutive switched capacitor circuit sections in the switched capacitor circuit section can all have the same value (e.g., a series of capacitors with unit capacitance can be used).

[0052] Turn Figure 2Flowchart 200 illustrates an example process of how the DC-DC converter 100, and specifically its compensator 102, can operate during a transition from light-load (or no-load) operation to medium-to-high-load operation in at least one scenario. As shown, it can be assumed that the process represented by flowchart 200 begins at a first step 202, where the DC-DC converter performs light-load (or no-load) operation. In the first step 202, during light-load (or no-load) operation, the corresponding second switch 166 of each of the switched capacitor circuit sections 148 is turned off. Therefore, each of the corresponding capacitors 160 of each of the internal nodes 162 and thus each of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 is disconnected from the other node 146. Given the open state of each of the second switches 166, at the first step 202, each of the corresponding capacitors 160 of each of the internal nodes 162 and therefore each of the switched capacitor circuit portions 148 can be coupled to the reference voltage node 170 or the ground node 144, and thus be charged to the reference (or power supply) voltage (Vdd) or ground.

[0053] More specifically, during this light-load (or no-load) operation, for each of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, and the fourth switched capacitor circuit section 156, one of the first switch 164 and the third switch 168 is open, and the other of the first switch 164 and the third switch 168 is closed. For each of these switched capacitor circuit sections 150, 152, 154, and 156, the selection of the corresponding internal node 162 and therefore whether the corresponding capacitor 160 is coupled to the reference voltage node 170 (VDD) or the ground node 144 depends on the code representing the desired voltage. That is, in this example, in the first step 202, the settings of the first switch 164 and the third switch 168 are programmed (or established in accordance with programming) such that the desired voltage appears at the corresponding internal node 162 of each of the first circuit section 150, the second circuit section 152, the third circuit section 154, and the fourth circuit section 156. Furthermore, during the light-load (or no-load) operation corresponding to the first step 202, the first switch 164 of the fifth switched capacitor circuit section 158 closes, causing the internal node 162 of the fifth switched capacitor circuit section and therefore the capacitor 160 to (always) switch to ground. This state does not consume DC current.

[0054] Although the above-described operation occurs during light load (or no load) operation, if a transition from light load (or no load) operation is imminent, in the second step 204, just before the start of medium-high load (or medium-heavy load, or PWM) operation, all capacitors 160 of all switched capacitor circuit sections 148 are connected to an additional node (also referred to as the vcap_integrator node) 146. When connected in this manner, the various capacitor circuits are effectively integrated, and the voltage at the additional node 146 (or the vcap_integrator voltage) quickly stabilizes to the desired programming voltage. That is, the voltage at the additional node 146 stabilizes substantially immediately to the final capacitor voltage (v_capacitor), which is consistent with all voltages applied to the internal nodes 162 of all first switched capacitor circuit sections 150, second switched capacitor circuit section 152, third switched capacitor circuit section 154, fourth switched capacitor circuit section 156, and fifth switched capacitor circuit section 158 (and thus to the corresponding capacitors 160).

[0055] Typically, for a compensator with n switched capacitor circuit sections, the final capacitor voltage (v_capacitor) can be determined according to equation (1):

[0056] v_capacitor = (C0*(vdd or 0V) + C1*(vdd or 0V) + … Cn*(vdd or 0V)) / Ctotal(1)

[0057] Where v_capacitor is the capacitor voltage, vdd is the circuit supply voltage, Ctotal is the total capacitance in the switched capacitor network, and C0, C1, ..., Cn are distributed capacitors in the same network, which must be charged to vdd or 0 V to achieve the desired voltage. The voltage can be selected by programming the selector line of the switch. Furthermore, for example, regarding... Figure 1 In this example embodiment, the switched capacitor network 140 of the compensator 102 includes five (5) switched capacitor circuit sections 148, each with a corresponding capacitor 160 having the aforementioned capacitance, and assuming that only the internal node 162 of the first switched capacitor circuit section 150 is coupled to the reference voltage node 170, then in this case, the final capacitor voltage (v_capacitor) will be calculated as shown in equation (2):

[0058] v_capacitor = (32pF*1.6V+16pF*0V+8pF*0V+4pF*0V) / 64pF = 0.5*1.6V =0.800V (2)

[0059] Subsequently, in the third step 206, any one or more of the corresponding capacitors 160 of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 that do not require compensation are disconnected (or decoupled) from the other node 146 by re-disconnecting the corresponding second switch 166 of the corresponding one or more switched capacitor circuit sections of the first, second, third, fourth, and fifth switched capacitor circuit sections that include those corresponding capacitors. After this disconnection occurs, those capacitors in the corresponding capacitors 160 of the corresponding switched capacitor circuit section 148 that remain coupled to the other node 146 (because the corresponding one or more switches in the corresponding second switch 166 remain closed) can then act as compensation capacitors for the compensator 102 and the DC-DC converter 100. This allows for tuning of the compensation capacitors, and if tuning of the compensation capacitors is not required, the total capacitance can be divided according to the proposed ratio and connected entirely when switching from PFM to PWM, thus eliminating the need for additional capacitance as compensation capacitors required for operation. Although the above description of the third step 206 assumes that one or more corresponding capacitors 160 will typically be disconnected from the other node 146, in at least some cases (or with respect to some embodiments), it is possible that in the third step 206, no corresponding capacitor 160 will be disconnected, since the expected compensation capacitance is provided by all switched capacitor circuit sections 148.

[0060] Furthermore, in the fourth step 208, after the compensation capacitor has been set in the third step 210, the DC-DC converter 100 can continue to operate at medium to high load.

[0061] Turn Figure 3Additionally, timing diagram 300 is provided to further illustrate how the DC-DC converter 100, and specifically its compensator 102, can operate during the transition between light load (or no load, or PFM) operation and medium-high load (or medium-heavy load, or PWM) operation in at least one condition. Timing diagram 300 specifically includes a first curve 302, a second curve 304, a third curve 306, a fourth curve 308, a fifth curve 310, a sixth curve 312, a seventh curve 314, and an eighth curve 316, which illustrate example variations in the different operations and characteristics of the compensator 102 of the DC-DC converter 100 over time between a first time 318 and a second time 320. The first curve 302 represents the voltage (vcap_integrator voltage or integrator capacitor voltage) at an additional node 146. The second curve 304 shows whether the compensator 102 (or the DC-DC converter 100) operates in a light load (or no load, or PFM) mode or a medium-high load (or PWM) operation mode. A high level or value 322 on the second curve 304 indicates light load (or no load, or PFM) operation, and a low level or value 324 on the second curve indicates medium-high load (or PWM) operation. From the second curve, it should be understood that in this diagram, the compensator 102 operates in medium-high load (or PWM) mode at both the first time 318 and the second time 320, switches from medium-high load mode to light load mode at the third time 326 after the first time 318, and switches back from light load mode to medium-high load mode at the fourth time 328 between the third time 326 and the second time 320.

[0062] The third (discharge_vcap_node) curve 306 represents an internal signal (or state) of the compensator 102. According to this internal signal, when the third curve 306 has a high level 330, it indicates that a certain state has been reached or an action has been taken (e.g., a switch has been opened or closed), causing another node 146 (vcap_integrator voltage) to discharge (i.e., the capacitor node is actively discharged). Although not shown, this discharge can be controlled, for example, by an NMOS (N-type metal-oxide-semiconductor) control. Alternatively, when the third curve 306 has a low level 332, it indicates that there is no state or action that would cause the other node 146 to discharge, and therefore the other node 146 is not discharged at such a time. In this example, the third curve 306 and the second curve 304 transition between low level 332 and high level 330 simultaneously. That is, in this example, the third curve 306 transitions from low level 332 to high level 330 at a third time 326 and from high level 330 to low level 332 at a fourth time 328. Therefore, in this example embodiment, the compensator 102 operates to discharge the additional node 146, especially when the compensator operates in a low-load (or no-load, or PFM) operating mode.

[0063] Curve 308 represents setting (or pre-charging) capacitors 160 of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 to have a particularly desired voltage (voltage potential across the respective capacitor), especially during light-load operation. In this embodiment, this is achieved by actuating the corresponding first (pchg_lo) switches 164 and corresponding third (pchg_hi) switches 168 of the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158, while simultaneously deactivating the corresponding second switches 166 of these respective switched capacitor circuit sections. This actuation of the first (pchg_lo) switches 164 and the third (pchg_hi) switches 168 can be controlled according to the “select_vhold<3.0>” signal, which can be provided by the control circuit 101. When the first switch 164, the second switch 166, and the third switch 168 are actuated (opened or closed) in the manner described above, the corresponding internal nodes 162 of those corresponding switch capacitor circuit portions 148 are set to the voltage of the reference voltage node 170 or the ground voltage of the ground node 144 (e.g., zero volts).

[0064] More specifically, if the corresponding third switches 168 of the corresponding first switched capacitor circuit section 150, second switched capacitor circuit section 152, third switched capacitor circuit section 154, and fourth switched capacitor circuit section 156 are closed, and the corresponding second switches 166 and corresponding first switches 164 of those corresponding switched capacitor circuit sections are open, then the corresponding internal nodes 162 of those corresponding switched capacitor circuit sections are set to the voltage of the reference voltage node 170. Furthermore, if the corresponding first switches 164 of the corresponding first switched capacitor circuit section 150, second switched capacitor circuit section 152, third switched capacitor circuit section 154, fourth switched capacitor circuit section 156, and fifth switched capacitor circuit section 158 are closed, and the corresponding second switches 166 and corresponding third switches 168 of those corresponding switched capacitor circuit sections (especially in the case of the first, second, third, and fourth switched capacitor circuit sections relative to the third switch) are open, then the corresponding internal nodes 162 of those corresponding switched capacitor circuit sections are set to the ground voltage of the ground node 144.

[0065] The specific voltages to which the different capacitors in capacitors 160 of switched capacitor circuit section 148 are set may vary depending on the embodiment or operating environment, or may be determined to be a desired voltage. The fourth curve 308 illustrates in a generalized manner that any one or more of the capacitors 160 in the first switched capacitor circuit section 150, the second switched capacitor circuit section 152, the third switched capacitor circuit section 154, the fourth switched capacitor circuit section 156, and the fifth switched capacitor circuit section 158 may be set to either the reference voltage node 170 voltage (Vdd) or ground (or, with respect to the fifth switched capacitor circuit section 158, the capacitor may or may not be set to ground), accomplished by showing the fourth curve as a split curve comprising both a high curve portion 334 and a low curve portion 336 between a third time 326 at the start of light-load operation and a fifth time 338 occurring shortly after the fourth time 328. In other words, the high curve portion 334 indicates that any one or more of the capacitors 160 in the first switched capacitor circuit portion 150, the second switched capacitor circuit portion 152, the third switched capacitor circuit portion 154, and the fourth switched capacitor circuit portion 156 may present the reference voltage node 170 voltage (Vdd), and the low curve portion 336 indicates that any one or more of the capacitors in those switched capacitor circuit portions and / or the capacitor in the fifth switched capacitor circuit portion 158 may alternatively present the ground voltage.

[0066] As described above, the corresponding first (pchg_lo) switch 164 and the corresponding third (pchg_hi) switch 168 can be actuated (or responded to) by a corresponding first control signal pointing to those corresponding switches, which can be referred to as the “select_vhold<3.0>” signal. In this embodiment, the actuation of switches 164 and 168 can be considered as constituting “programming” of the capacitor in terms of the corresponding charge or voltage of the capacitor (or in terms of the capacitor charging voltage). As shown by the fourth curve 308, this actuation of the first switch 164 and the third switch 168 does not occur when the compensator 102 is in the medium-high load (PWM) operation mode, and therefore the fourth curve 308 has an intermediate level curve portion 340 before the third time 326 and after the fifth time 338. Conversely, during these time periods when the compensator 102 is in the medium-high load (PWM) operation mode, all first switches 164 and third switches 168 are open. Furthermore, curve 308 shows that the actuation of the first (pchg_lo) switch 164 and the corresponding third (pchg_hi) switch 168 is not necessarily instantaneous. Instead, in this embodiment as shown, when the compensator 102 switches from a medium-high load operating mode to a light load (or no load) operating mode at the third time 326, the actuation of switches 164 and 168 is not completed until the sixth time 342, which occurs shortly after the third time (far before the fourth time 328). Similarly, when the compensator 102 switches from a light load (or no load) operating mode to a medium-high load operating mode at the fourth time 328, the deactivation of switches 164 and 168 is not completed until the fifth time 338.

[0067] In contrast to the fourth curve 308, which relates to setting the corresponding capacitor 160 of the corresponding switched capacitor circuit section 148 to the corresponding desired voltage, the fifth curve 310 shows how those corresponding capacitors can then be coupled to another node 146 (vcap_integrator node) shortly before and further at and after the fourth time 328, when the compensator 102 transitions from a light load (or no load, or PFM) operating mode to a medium-high load (PWM) operating mode after being set to the corresponding desired voltage. In this respect, the fifth curve 310 can be viewed as representing a second control signal (or internal signal) pointing to the corresponding second switch 166 of the corresponding switched capacitor circuit section 148, which can be referred to as the "transfer_switches<3.0>" signal. That is, the fifth curve 310 shows a second control signal that can be used in the example embodiment to control the actuation of the second switch 166 of the switched capacitor circuit section 148 (again, such a second control signal can be provided by the control circuit 101). Furthermore, curve 312 further illustrates how charge is transferred to another node 146 due to the coupling of capacitor 160 to another node 146 as indicated by curve 310.

[0068] More specifically, as shown in the figure, shortly before the third time 326 when the compensator 102 switches from a medium-high load (PWM) operation mode to a light load (or no load, or PFM) operation mode, the fifth curve 310 may have a high level 344 (as shown by the dashed line), indicating that one or more of the second switches 166 will be short-circuited, as further described below. Then, at the third time 326, the fifth curve 310 transitions from a high level 344 to a low level 346, indicating that all second switches 166 are commanded to be open. As described above regarding the fourth curve 308, this is consistent with the light load operation mode, in which the switches in the first switch 164 and the third switch 168 are closed to set the voltage of the capacitor 160.

[0069] However, shortly before (and indeed at) the fourth time 328 when the compensator 102 transitions from a light-load operating mode to a medium-high-load operating mode, the fifth curve 310 transitions from a low level 346 to a high level 344. When the fifth curve 310 reaches a high level 344, this indicates that all second switches 166 are closed, causing the voltage of capacitors 160 in all first switched capacitor circuit sections 150, second switched capacitor circuit section 152, third switched capacitor circuit section 154, fourth switched capacitor circuit section 156, and fifth switched capacitor circuit section 158 to be applied to the additional node 146 (vcap_integrator node). Thus, the additional node 146 is set and reaches the desired / programmed compensator voltage, for example, which can be calculated by equation (1) above. Accordingly, at the fourth time 328, the sixth curve 312 also switches from a low level 348 to a high level 350, indicating that the other node 146 is reaching a new (or higher) charging level because capacitor 160 is coupled to it. For this purpose of transferring charge, all capacitors associated with all capacitors 160 in all switched capacitor circuit sections 148 are used (e.g., coupled in parallel between the other node 146 and ground).

[0070] Transferring the voltage (particularly the voltage present at internal node 162) and charge associated with all capacitors 160 in all switched capacitor circuit sections 148 to other nodes 146 takes little time. More specifically, as Figure 3 As shown, the transfer of voltage and charge to the other node 146 and the balancing of all capacitors 160 occur within a T_transfer time 360, which is equal to the difference between the fourth time 328 and the fifth time 338. Therefore, at the fifth time 338, as Figure 3 The solid line portion 352 of the fifth curve 310 shown returns to a low level 346, and the sixth curve also returns to a low level 348.

[0071] However, as already discussed, in this example embodiment, the switched capacitor network 140 of the compensator 102 is used not only to set the additional node (vcap_integrator node) 146 to the desired voltage, but also to provide appropriate compensation capacitance. Therefore, although the fifth curve 310 includes a solid portion 352 at the low level 346 after the fifth time 338, the fifth curve 310 also includes a dashed portion 354 at the high level after the fifth time 338. The dashed portion 354 indicates that one or more of the second switches 166 of the switched capacitor network 140 can remain closed even after the fifth time 338, such that one or more of the capacitors 160 remain coupled to the additional node 146 even after the fifth time 338. In this case where one or more of the capacitors 160 remain coupled to the additional node 146, those capacitors can act as compensation capacitance for the compensator 102.

[0072] Furthermore, the seventh curve 314 represents a signal (which may also be provided by control circuitry 101) provided to transfer switch 142, controlling whether the transfer switch is actuated to close to short-circuit stabilizing resistor 136 or alternatively to open to keep stabilizing resistor 136 active in compensator 102. As shown, in this example embodiment, the seventh curve 314 has a low level 356 shortly before the third time 326 and after the fifth time 338, but a high level 358 between the third time 326 and the fifth time 338. This indicates that between the third time 326 and the fifth time 338, particularly between the fourth time 328 and the fifth time 338, stabilizing resistor 136 is short-circuited, allowing charging of high-frequency capacitor 138 (C_high_frequency).

[0073] Finally, the eighth curve 316 represents programming the compensation capacitor by providing certain signals (i.e., the "Select_compensation<3.0> signal")—signals that do not change between light load (or no load, or PFM) operating mode and medium-high load (or PWM) operating mode, and therefore the eighth curve 316 is shown as constant between the first time 318 and the second time 320. In this example embodiment, from an external source (e.g., Figure 1The external control device (not shown) provides only the following signals: a light load mode signal represented by the second curve 304, a select_vhold<3:0> signal (or selection line) (or selection line) (or selection line) (or selection line) (or selection compensation<3:0> signal ...

[0074] Furthermore, in this example embodiment, the digital finite state machine (FSM) of the DC-DC converter 100 chip, provided by control circuitry 101, can control the on / off states of various blocks of the chip, as well as the sensing and reporting of important telemetry information regarding critical node voltages and currents. Based on the sensed telemetry information regarding Vin (e.g., the voltage applied at the first input port 124), Vout (e.g., the voltage output at output node 128), and Iout (e.g., the current output at output node 128), the FSM can be used to program the select_vhold<3:0> and select_compensation<3:0> signals to ensure minimal output voltage interference. To ensure this, the digital FSM will have a stored set of values ​​in a lookup table (LUT) corresponding to the various operating points of the DC-DC converter 100. For example, in an example scenario where Vin = 12V (12 volts), Vout = 5V, and Iout_pfm threshold = 1A (1 ampere), Select_compensation<3:0> = 8 (e.g., corresponding to a compensation capacitor of arbitrary design of 32 pF), and Select_vhold<3:0> = 8 (e.g., corresponding to the amount of capacitor split required to charge the integrator capacitor node).

[0075] While specific features of particular embodiments have been described above or elsewhere herein, it should be understood that this disclosure covers many other embodiments. For example, although Figure 1The DC-DC converter has been described as having a switched capacitor network 140 having five capacitor circuit sections 148 and five capacitors 160, but this disclosure covers other embodiments having switched capacitor networks and each switched capacitor network having any number of capacitor circuit sections and / or any number of capacitors. For example, some other example embodiments have switched capacitor networks having any number of switched capacitor networks from three (3) to ten (10) and / or any number of capacitors from three (3) to ten (10). As another example, although the corresponding first switched capacitor circuit section 150, second switched capacitor circuit section 152, third switched capacitor circuit section 154, fourth switched capacitor circuit section 156 and fifth switched capacitor circuit section 158 have been described above as having specific corresponding capacitance values, this disclosure contemplates other embodiments with capacitors having other arbitrary capacitance values. While in some embodiments, the respective capacitors of the switched capacitor network have successively increasing or decreasing capacitance values ​​that are binary-dependent (i.e., successively increasing or decreasing capacitance values ​​that are factored by a factor of two, such as successively increasing capacitance values ​​of 4 pF, 8 pF, 16 pF, 32 pF, and 64 pF), in other embodiments, the various respective capacitors do not need to have corresponding values ​​that are binary-dependent. For example, as described above, in some other embodiments, each capacitor in a consecutive switched capacitor network may all have the same value (e.g., a series of capacitors with unit capacitance may be used).

[0076] It should also be understood that while this disclosure envisions embodiments where the switch from PFM mode to PWM mode is due to higher load current, this may not be the only reason for switching from PFM mode to PWM mode, depending on the embodiments. Typically, the embodiments covered herein may perform capacitor pre-charging and coupling shortly before switching to PWM mode (for any reason). However, in practice, in at least some embodiments or cases, the capacitor may be configured to be continuously pre-charged during PFM operation (which will have no effect on the system; no DC current consumption), and coupling (rather than pre-charging and coupling) will necessarily occur shortly before entering PWM operation (or substantially at the time of entering PWM operation).

[0077] Furthermore, this disclosure covers numerous systems and applications employing DC-DC converters (such as the DC-DC converter 100 described above). For example, this disclosure covers power conversion systems and applications, as well as Universal Serial Bus (USB) systems and applications. Additionally, for example, this disclosure includes systems and applications employing DC-DC converters (such as DC-DC converter 100) to perform charging. Furthermore, for example, this disclosure includes systems and applications employing DC-DC converters (such as DC-DC converter 100), such as automotive systems, electric bicycles, and power tools.

[0078] In light of the foregoing discussion, it should be understood that one or more embodiments covered herein are advantageous in one or more respects. For example, at least some embodiments covered herein envision a circuit (e.g., a DC-DC converter 100) that performs at least two operations: (a) charging an integrating capacitor (or another node 146 or a "vcap_integrator node") to a specific voltage, and (b) connecting a certain amount of capacitance to act as a compensator capacitor. As another example, at least some embodiments covered herein relate to DC-DC converter circuits that are advantageous in that, even when operating in a light-load (or no-load, or PFM) operating mode, the DC-DC converter circuit involves reduced current consumption and achieves enhanced efficiency.

[0079] While the principles of the invention have been described above in conjunction with specific devices, it should be clearly understood that this description is by way of example only and not as a limitation on the scope of the invention. In particular, it is desired that the invention is not limited to the embodiments and illustrations included herein, but also includes modifications of those embodiments, including portions of embodiments falling within the scope of the appended claims and combinations of elements from different embodiments.

Claims

1. A DC-DC converter, characterized in that, include: An amplifier circuit, the amplifier circuit including an output power circuit and a feedback circuit; A compensator circuit coupled to the amplifier circuit, wherein the compensator circuit includes an error amplifier, a comparator, and an intermediate circuit network, wherein the error amplifier has a first input and a first output, and wherein the comparator has a second input and a second output. The second input terminal is coupled to the first output terminal of the error amplifier, and the second output terminal is coupled to another input terminal of the output power circuit. The intermediate circuit network includes a first node, at least one first switchable component, and a plurality of switched capacitor networks, wherein the at least one first switchable component couples the first node to the first output terminal of the error amplifier, and each switched capacitor network has a corresponding capacitor. as well as A control circuit coupled to each of the switched capacitor networks, wherein the control circuit is configured to cause the corresponding capacitor of the corresponding switched capacitor network to reach a corresponding voltage at a first time, and wherein the control circuit is configured to cause the corresponding capacitor of the corresponding switched capacitor network to couple to the first node at a second time, such that the first node reaches the compensator voltage.

2. The DC-DC converter according to claim 1, characterized in that, Each of the respective capacitors in the respective switched capacitor networks is coupled to the first node via a respective capacitor connection switch, wherein the control circuit is configured to provide a first control signal to the plurality of switched capacitor networks at a first time to cause the respective capacitor of the respective switched capacitor network to reach a corresponding voltage, wherein the control circuit is configured to provide a second control signal to the plurality of switched capacitor networks at a second time to cause the respective capacitor of the respective switched capacitor network to couple to the first node, causing the first node to reach the compensator voltage, and wherein the control circuit is further configured to provide a third control signal to the plurality of switched capacitor networks at a third time to decouple the respective capacitor or the respective capacitor of one or more of the respective switched capacitor networks from the first node, such that the desired compensation capacitance remains coupled to the first node.

3. The DC-DC converter according to claim 2, characterized in that, During the first time, the DC-DC converter operates in a first operating mode, which is at least one of a light load operating mode, a no-load operating mode, or a pulse frequency modulation (PFM) operating mode.

4. The DC-DC converter according to claim 3, characterized in that, The second time occurs at or just before the additional time during which the DC-DC converter switches from the first operating mode to the second operating mode, the second operating mode being one of the following: medium load operating mode, high load operating mode, heavy load operating mode, medium-high load operating mode, medium-heavy load operating mode, or pulse width modulation (PWM) operating mode.

5. The DC-DC converter according to claim 4, characterized in that, During the third time, the DC-DC converter operates in the second operating mode, and the control circuitry operates at least in part based on a digital finite state machine (FSM) or a lookup table (LUT).

6. The DC-DC converter according to claim 2, characterized in that, Each of the switched capacitor networks includes a corresponding internal node, a corresponding first switch, and a corresponding second switch, wherein the corresponding first switch is coupled between the corresponding internal node and a ground node, wherein the corresponding second switch is the corresponding capacitor connection switch of the corresponding switched capacitor network and is coupled between the corresponding internal node and the first node, and wherein each of the corresponding capacitors of the corresponding switched capacitor network is coupled between the corresponding internal node and the ground node.

7. The DC-DC converter according to claim 6, characterized in that, With respect to one or more of the switched capacitor networks, the respective switched capacitor network includes a respective third switch, and the respective third switch is coupled between the respective internal node and the power supply node.

8. The DC-DC converter according to claim 7, characterized in that, The at least one first switchable component includes a parallel combination of a stabilizing resistor and a transfer switch, wherein each of the stabilizing resistor and the transfer switch is at least indirectly coupled between the first node and the first output, and wherein the DC-DC converter further includes a high-frequency capacitor, which is at least indirectly coupled between the first output and the ground node.

9. A compensator circuit for a DC-DC converter, characterized in that, The compensator circuit includes: An error amplifier having a first input terminal and a first output terminal; A pulse width modulation (PWM) comparator, the PWM comparator having a second input and a second output, the second input being at least indirectly coupled to the first output of the error amplifier; and An intermediate circuit network, comprising an integrator node, at least one first switchable component, and a plurality of switched capacitor networks, wherein the at least one first switchable component at least indirectly couples the integrator node to the first output terminal of the error amplifier. Each of the switched capacitor networks described herein includes a corresponding capacitor, a corresponding internal node, a corresponding first switch, and a corresponding second switch. Each of the respective first switches is coupled between the respective internal node and the ground node or the respective first voltage node, each of the respective second switches is coupled between the respective internal node and the integrator node, and each of the respective capacitors is coupled to the respective internal node. The corresponding second switch is controlled such that, at a first time, each of the corresponding capacitors is coupled to the integrator node, causing the integrator node to reach a first voltage or a first charge level, and at a second time, at least one of the capacitors remains coupled to the integrator node so as to function as a compensator capacitor.

10. A method for controlling a DC-DC converter, characterized in that, The DC-DC converter has an amplifier circuit coupled to a compensator circuit, the compensator circuit including an integrator node and a plurality of switched capacitor networks, each switched capacitor network having a corresponding capacitor and a corresponding capacitor connection switch, the corresponding capacitor connection switch being at least indirectly located between the corresponding capacitor and the integrator node, the method comprising: At the first moment when the DC-DC converter is operating in the first operating mode, the corresponding capacitor connection switch of the corresponding switched capacitor network is first actuated to decouple the corresponding capacitor of the corresponding switched capacitor network from the integrator node, so that the corresponding capacitor can be set to have the corresponding capacitor voltage. At a second time following the first time, the corresponding capacitor connection switches of the corresponding switched capacitor network are then actuated, such that all the corresponding capacitors are coupled to the integrator node to establish a compensator voltage at the integrator node; and At a third time after the second time, when the DC-DC converter is operating in the second operating mode, a first subset of the capacitor connection switches of the plurality of switched capacitor networks is actuated again, such that each capacitor in the first subset of the capacitors of the plurality of switched capacitor networks is decoupled from the integrator node, but each capacitor in the second subset of the capacitors of the plurality of switched capacitor networks remains coupled to the integrator node, such that the compensation capacitor is coupled to the integrator node.

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