Power circuit control method and related device

Abstract

The application provides a power circuit control method and related equipment. The method is applied to a power control unit, the power control unit includes a plurality of EPWM modules, and the plurality of EPWM modules include a first module and a second module. The method includes the following steps: the first module determines a target comparison value corresponding to a phase error comparison register of the first module, the target comparison value corresponding to the phase error comparison register of the first module is obtained based on a period count value in a time base period register of the first module and a target phase error angle corresponding to the first module; in a case where a current count value in a time base counter of the first module is equal to the target comparison value corresponding to the phase error comparison register of the first module, the first module sends a local synchronization signal to the second module; and the second module controls the time base counter of the second module to start counting from a starting count value after being cleared. The technical solution is beneficial to maintaining a target phase error relationship between the plurality of EPWM modules in a frequency modulation or phase adjustment process.

Description

Technical Field

[0001] This application relates to the field of power electronic control technology, and in particular to power circuit control methods and related equipment. Background Technology

[0002] Power circuits regulate power transfer by periodically controlling the switching on and off of switching devices. Power circuits such as resonant converters and dual active bridge converters can use pulse-width modulation (PWM) signals to control multiple bridge arms. In wide input / output range or high-power applications, multiple power conversion branches can also operate in parallel to share power and improve current carrying capacity.

[0003] Power controllers typically configure the period and phase parameters for each pulse width modulation channel separately. To adapt to changes in the operating point, the controller can change the switching frequency or phase. When multiple power conversion branches are connected in parallel, the counting period and phase reference of each channel may change with parameter adjustments, and the original phase interval between channels may deviate from the set state, making it difficult to maintain the phase misalignment relationship. Summary of the Invention

[0004] This application provides a power circuit control method and related equipment to solve the technical problem that the drive signals of multi-parallel power circuits are difficult to maintain a phase mismatch when the switching frequency or phase parameters change.

[0005] In a first aspect, this application provides a power circuit control method applied to a power control unit. The power control unit is connected to a power circuit. The power control unit includes multiple enhanced pulse-width modulation (EPWM) modules. Each EPWM module includes a time-base period register (TBPRD), a phase mismatch register, and a time-base counter. (counter, TBCTR); multiple enhanced pulse width modulation modules form a cascaded link through a local synchronization signal. The multiple enhanced pulse width modulation modules include a first module and a second module. The first module is an enhanced pulse width modulation module that transmits the local synchronization signal, and the second module is an enhanced pulse width modulation module that receives the local synchronization signal. The method includes: the first module determines the target comparison value corresponding to the phase mismatch register of the first module. The target comparison value corresponding to the phase mismatch register of the first module is obtained based on the period count value in the time base period register of the first module and the target phase mismatch angle corresponding to the first module; when the current count value in the time base counter of the first module is equal to the target comparison value corresponding to the phase mismatch register of the first module, the first module sends a local synchronization signal to the second module; in response to the local synchronization signal, the second module controls the time base counter of the second module to start counting from the initial count value after being cleared.

[0006] In this technical solution, multiple EPWM modules in the power control unit form a cascaded link through a local synchronization signal. The EPWM module determines the target comparison value based on the period count value in the TBPRD and the target phase misalignment angle, and sends a local synchronization signal along the cascaded link when the count value of the TBCTR reaches the target comparison value. This allows the EPWM module that receives the local synchronization signal to re-establish the corresponding counting reference, which is beneficial for maintaining the target phase misalignment relationship between multiple EPWM modules during frequency modulation or phase adjustment, thereby suppressing the input current ripple of the multi-parallel power circuit.

[0007] In conjunction with the first aspect, in one possible implementation, each enhanced pulse width modulation module further includes a time-base phase register (TBPHS); the second module controls the second module's time-base counter to start counting from the reset initial count value, including: the second module resets the initial count value in the second module's time-base phase register; the second module controls the second module's time-base counter to read the initial count value from the second module's time-base phase register as the current count value of the second module's time-base counter.

[0008] By clearing TBPHS and loading it into TBCTR, the EPWM module can obtain a definite counting reference after receiving a local synchronization signal, thereby improving the repeatability of cascaded phase-shifting timing.

[0009] In conjunction with the first aspect, in one possible implementation, each enhanced pulse width modulation module further includes a dead-time register; the method further includes: in response to a drive shutdown signal being triggered, reloading the delay count value in the dead-time register of each enhanced pulse width modulation module such that the delay count value in the dead-time register of each enhanced pulse width modulation module is greater than the period count value in the time base period register.

[0010] When the drive signal is turned off, the delay count value in the dead zone register is made greater than the period count value in the period register. The edge delay covering the entire counting cycle can be used to block the drive pulse output, thus achieving drive shutdown without rewriting the original drive level logic.

[0011] In conjunction with the first aspect, in one possible implementation, the delay count in the dead zone register of each enhanced pulse width modulation module after reloading is one plus the period count in the time base period register.

[0012] Setting the delay count value to the period count value in TBPRD plus one allows the entire counting cycle to be covered by a definite value that is immediately adjacent to the upper limit of the period, simplifying the calculation and loading of the drive shutdown parameters.

[0013] In conjunction with the first aspect, in one possible implementation, each enhanced pulse width modulation module further includes a dead-time register; the method further includes: in response to a drive restart signal being triggered, reloading the delay count value in the dead-time register of each enhanced pulse width modulation module, such that the delay count value in the dead-time register of each enhanced pulse width modulation module is a preset dead-time value.

[0014] When restarting the drive signal, reloading the preset dead time value can restore the normal delay relationship between complementary drive edges, allowing the power circuit to resume drive output while meeting the dead time requirements.

[0015] In conjunction with the first aspect, in one possible implementation, the method further includes: in response to a change in the phase shift direction of the plurality of enhanced pulse width modulation modules, after turning off the drive signals of the plurality of enhanced pulse width modulation modules, updating the phase shift parameters in the plurality of enhanced pulse width modulation modules according to the changed phase shift direction, and restarting the drive signals of the plurality of enhanced pulse width modulation modules after the phase shift parameters in the plurality of enhanced pulse width modulation modules have been updated.

[0016] When the phase shift direction changes, the drive signal is turned off first, then the phase shift parameters are updated, and the drive signal is restarted after the parameter update is completed. This can prevent the abnormal duty cycle during the direction switching period from being actually applied to the power circuit, and reduce the risk of abnormal overcurrent and transformer bias.

[0017] In conjunction with the first aspect, in one possible implementation, each enhanced pulse width modulation (PWM) module further includes a shadow register; after the drive signals of multiple PWM modules are turned off, the phase shift parameters in the multiple PWM modules are updated according to the changed phase shift direction, and after the phase shift parameters in the multiple PWM modules are updated, the drive signals of the multiple PWM modules are restarted, including: writing the drive shutdown parameters corresponding to each PWM module into the shadow register of each PWM module, and triggering a first global load event; wherein, the first global load event is used to synchronously load and activate the drive shutdown parameters in the shadow registers of each PWM module to turn off the drive signals of multiple PWM modules; after the drive signals of multiple PWM modules are turned off, each The target phase shift parameters corresponding to each enhanced pulse width modulation (PWM) module are written into the shadow register of each PWM module, triggering a second global load event. The target phase shift parameters are determined based on the changed phase shift direction. The second global load event synchronously loads and activates the target phase shift parameters in the shadow registers of each PWM module, updating the phase shift parameters in multiple PWM modules. After the target phase shift parameters in each PWM module take effect, the drive enable parameters corresponding to each PWM module are written into the shadow registers of each PWM module, triggering a third global load event. The third global load event synchronously loads and activates the drive enable parameters in the shadow registers of each PWM module, restarting the drive signals of multiple PWM modules.

[0018] By synchronizing the driver shutdown parameters, target phase shift parameters, and driver enable parameters through three global load events, the time difference in the effectiveness of parameters of each module caused by the order of program statement execution can be eliminated, and the consistency of the state of multiple drives during the direction switching process can be maintained.

[0019] In conjunction with the first aspect, in one possible implementation, the interval between the triggering time of the second global loading event and the triggering time of the first global loading event is greater than half of the maximum switching period corresponding to the multiple enhanced pulse width modulation modules; the interval between the triggering time of the third global loading event and the triggering time of the second global loading event is greater than half of the maximum switching period.

[0020] The interval between the trigger times of two adjacent global load times is greater than half of the maximum switching cycle, which allows time for drive shutdown propagation and the new phase shift parameters to take effect, reducing the possibility of overlap between the old drive state and the new parameter state.

[0021] In conjunction with the first aspect, in one possible implementation, after the drive signals of multiple enhanced pulse width modulation (PWM) modules are turned off, the target phase shift parameters corresponding to each PWM module are written into the shadow register of each PWM module, and a second global load event is triggered. This includes: after waiting for a maximum switching cycle, writing the target phase shift parameters corresponding to each PWM module into the shadow register of each PWM module, and triggering the second global load event; after the target phase shift parameters in each PWM module take effect, the drive enable parameters corresponding to each PWM module are written into the shadow register of each PWM module, and a third global load event is triggered. This includes: after waiting for a maximum switching cycle, writing the drive enable parameters corresponding to each PWM module into the shadow register of each PWM module, and triggering the third global load event.

[0022] By waiting for a maximum switching cycle before writing the target phase shift parameters and drive enable parameters, it is beneficial to reliably complete the direction switching in the master control sequential execution scenario.

[0023] In conjunction with the first aspect, in one possible implementation, the drive shutdown parameters corresponding to each enhanced pulse width modulation (PWM) module are written into the shadow register of each PWM module, and a first global load event is triggered, including: in response to a first switching frequency interrupt, writing the drive shutdown parameters corresponding to each PWM module into the shadow register of each PWM module, and triggering the first global load event; after the drive signals of multiple PWM modules are turned off, the target phase shift parameters corresponding to each PWM module are written into the shadow register of each PWM module, and a second global load event is triggered, including: in response to a first switching frequency interrupt, writing the drive shutdown parameters corresponding to each PWM module into the shadow register of each PWM module, and triggering the second global load event, including: in response to a first switching frequency interrupt. The second switching frequency interrupt following the frequency interrupt writes the target phase shift parameters corresponding to each enhanced pulse width modulation module into the shadow register of each enhanced pulse width modulation module and triggers the second global load event; after the target phase shift parameters in each enhanced pulse width modulation module take effect, the drive enable parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module and trigger the third global load event, including: in response to the third switching frequency interrupt following the second switching frequency interrupt, writing the drive enable parameters corresponding to each enhanced pulse width modulation module into the shadow register of each enhanced pulse width modulation module and triggering the third global load event.

[0024] By arranging the drive shutdown, phase shift parameter update, and enable in three consecutive switching frequency interrupts, each stage can be synchronized with the switching cycle, thus ensuring timely phase shift direction switching even when the main control cycle is long.

[0025] In conjunction with the first aspect, in one possible implementation, the first switching frequency interrupt, the second switching frequency interrupt, and the third switching frequency interrupt are switching frequency interrupts that respond sequentially through an interrupt nesting method within the control cycle; or, the first switching frequency interrupt, the second switching frequency interrupt, and the third switching frequency interrupt are periodic control interrupts that are triggered sequentially, and the triggering frequency of the periodic control interrupt is the same as the switching frequency of the enhanced pulse width modulation module.

[0026] By configuring the interrupt nesting method or the sequentially triggered periodic control interrupt according to the control cycle, different combinations of master control and switching frequencies can be adapted while maintaining the three-stage timing relationship, thereby improving the deployment flexibility of the control scheme.

[0027] In a second aspect, an electronic device is provided, including a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, and the processor, when executing the one or more computer programs, causing the electronic device to implement the power circuit control method of the first aspect described above.

[0028] Thirdly, a computer-readable storage medium is provided, which stores a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the power circuit control method of the first aspect described above.

[0029] Fourthly, a power control unit is provided, including a plurality of enhanced pulse width modulation modules, the power control unit being used to execute the power circuit control method of the first aspect described above. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the power conversion system architecture provided in the embodiments of this application; Figure 2 A schematic diagram of a power circuit provided in an embodiment of this application; Figure 3 A schematic flowchart of a power circuit control method provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0033] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0034] This application can be applied to multi-channel power conversion control scenarios. A multi-channel power conversion control scenario refers to a scenario where a power control entity needs to provide periodic drive signals to multiple switching arms or multiple parallel power conversion branches, and adjusts power transmission using the frequency and phase relationships between the drive signals. This scenario can include DC / DC conversion, DC / AC conversion, and resonant power conversion with multiple parallel power conversion branches; the embodiments of this application do not limit this to these.

[0035] The following explanation uses a direct current / direct current converter (DC / DC) as an example. A DC / DC converter may include an input terminal, at least one power conversion branch, an output terminal, and a power control unit. The input terminal receives DC power, the power conversion branch changes its switching state under the action of a drive signal, and the output terminal provides converted DC power to the load. The power control unit generates drive signals for each power conversion branch according to the control objective. The above control method can also be used for direct current / alternating current converters (DC / AC). The power conversion branch can be a series resonant dual active bridge (SRDAB) branch. An SRDAB branch may include a primary-side full bridge, a transformer, a resonant inductor, a resonant capacitor, and a secondary-side full bridge. The primary-side full bridge is used to convert the input DC voltage into an alternating voltage, the transformer is used to achieve primary-secondary energy coupling, and the secondary-side full bridge is used to convert the alternating voltage on the secondary side of the transformer into the output voltage. The resonant inductor and resonant capacitor constitute the resonant network in the energy transfer path.

[0036] See Figure 1 , Figure 1 This is a schematic diagram of the power conversion system architecture provided in an embodiment of this application. Figure 1 As shown, the power conversion system 10 includes a power control unit 11 and a power circuit 12, with the power control unit 11 connected to the power circuit 12.

[0037] The power conversion system 10 controls the on / off states of each switching device in the power circuit 12 to transfer electrical energy from the input side to the output side according to a set power transmission mode. During the power conversion process, the power circuit 12 constitutes the main body for the actual power transmission. The power control unit 11 generates drive signals corresponding to each switching device according to the control requirements of the power conversion system 10, and controls the operating state of the power circuit 12 by adjusting the switching period of the drive signals and the phase relationship between different drive signals.

[0038] Specifically, the power control unit 11 is used to generate multiple drive signals, and the power circuit 12 is used to change the conduction state of each switching device in response to the multiple drive signals, so as to form a power transmission path from the input terminal to the output terminal. The power control unit 11 and the power circuit 12 can be directly driven together, or they can be driven together through a driver chip, isolation device, etc. This application does not limit this.

[0039] The power control unit 11 includes multiple EPWM modules, which are used to convert control parameters such as switching period, comparison position, and phase into actual pulse drive signals. Different EPWM modules correspond to different switching devices or pairs of switching devices in the power circuit 12. Multiple EPWM modules work together to form a multi-channel drive waveform that meets the modulation requirements of the power circuit 12.

[0040] Each EPWM module may include hardware functional units such as a time base (TB) submodule, a compare (CC) submodule, an action qualifier (AQ) submodule, a dead band (DB) submodule, and synchronization control-related circuits.

[0041] The TB submodule is used to establish the basic time scale of the EPWM module, including hardware resources such as TBCTR, TBPRD, and TBPHS. TBCTR counts according to a set counting mode (e.g., up-counting mode); TBPRD stores the cycle count value corresponding to one PWM cycle. When TBCTR reaches the cycle count value stored in TBPRD, TBCTR restarts counting, forming a continuous PWM time base. Adjusting the cycle count value in TBPRD changes the switching cycle of the EPWM module, achieving frequency modulation control of the drive signal. TBPHS stores the phase offset of the EPWM module relative to the synchronization reference.

[0042] The CC submodule is used to determine the location of level changes in the EPWM output signal within a switching cycle and includes multiple comparison registers. These comparison registers include, for example, COMPA, COMPB, COMPC, and COMPD. The comparison registers store comparison values. When the TBCTR count value matches the comparison value stored in the comparison register, the comparison register generates a comparison event, which is then passed to the AQ submodule for execution. The comparison registers can also generate synchronization events to trigger synchronization.

[0043] The AQ submodule controls the level changes of the EPWM output port based on time base events, comparison events, etc. Specifically, the CC submodule generates event positions, while the AQ submodule determines when to set the EPWM output high and when to set it low based on these events, thus forming the actual output PWM pulse waveform. The A and B outputs of the EPWM module are typically generated by the action limiting submodule and are used to drive a set of complementary switching devices.

[0044] The DB submodule is used to perform edge delay processing on complementary output signals, including hardware resources such as the dead-band generator rising-edge delay register (DBRED) and the dead-band generator falling-edge delay register (DBFED). DBRED is used to set the delay time (i.e., delay count value) when one output signal transitions from the off state to the on state, and DBFED is used to set the delay time (i.e., delay count value) of the corresponding edge of another complementary output signal, thereby preventing the upper and lower switching devices on the same bridge arm from turning on simultaneously due to drive delay.

[0045] Each EPWM module may also include a shadow register, which is used to cache parameters that need to be loaded into the active register. The active register is used to store parameters that need to participate in hardware operations. The active register includes, but is not limited to, the aforementioned TBPRD, COMPA, COMPB, COMPC, COMPD, DBRED, and DBFED.

[0046] In a specific example, the power circuit 12 can be as follows: Figure 2 As shown. The power circuit 12 includes a first power conversion branch 121 and a second power conversion branch 122 connected in parallel. Both the first power conversion branch 121 and the second power conversion branch 122 can be SRDAB branches. The first power conversion branch 121 includes switches S1 to S8, and the second power conversion branch 122 includes switches S9 to S16.

[0047] In this configuration, switches S1 and S2, S3 and S4, S5 and S6, S7 and S8, S9 and S10, S11 and S12, S13 and S14, and S15 and S16 form complementary drive pairs of switches. These eight pairs of switches can each correspond to one of eight EPWM modules. For example, S1 / S2 to S15 / S16 can sequentially correspond to the A and B outputs of eight EPWM modules, where the A and B outputs are the two outputs of the same EPWM module used to drive a pair of complementary switches.

[0048] When the power conversion system includes only a single power conversion branch, the power conversion state can be changed by adjusting the switching frequency and the phase shift relationship within the branch. In high-power applications, to improve power handling capability, the power circuit 12 includes multiple power conversion branches connected in parallel. In addition to controlling the phase shift relationship within each branch, it is also necessary to control the relative phase relationship between different parallel branches.

[0049] For example, in Figure 2 In the two-way parallel structure shown, phase shift is used to characterize the phase angle difference between similar drive signals in the first power conversion branch 121 and the second power conversion branch 122. By setting the phase shift angle, the current ripples generated by different power conversion branches can be staggered in time, thereby reducing the overall input current ripple of the parallel system. For example, when the two SRDAB branches are shifted by 90°, a better ripple suppression effect can be obtained.

[0050] Therefore, in high-power applications with wide input / output ranges and multiple parallel connections, the power control unit 11 needs to simultaneously meet three modulation requirements: frequency modulation, phase shifting, and phase reversal. Frequency modulation is used to change the switching period of the power conversion branch; phase shifting is used to change the phase relationship between related drive signals within the same power conversion branch; and phase reversal is used to change the relative drive phase between different parallel power conversion branches.

[0051] Since both phase shift angle and phase misalignment angle need to be converted into corresponding time positions within a switching cycle, when frequency modulation causes changes in the switching cycle, the corresponding time positions for phase shift and phase misalignment also need to be adjusted accordingly. Therefore, it is necessary to coordinate and update the period parameters and phase-related parameters of multiple EPWM modules to maintain the set phase shift and phase misalignment relationships during frequency modulation.

[0052] This application achieves frequency modulation by updating TBPRD, phase shift by updating the comparison values ​​in the comparison register COMPA and the comparison register COMPB, and phase misalignment, zero-crossing shutdown and restart are achieved through the power circuit control method described later.

[0053] The power circuit control method of this application is applied to a power control unit. The technical solution of this application is described in detail below.

[0054] See Figure 3 , Figure 3 This is a flowchart illustrating a power circuit control method provided in an embodiment of this application. The method can be applied to a power control unit. Multiple EPWM modules in the power control unit form a cascaded link through a local synchronization signal. The multiple EPWM modules include a first module and a second module. The first module is an EPWM module that sends the local synchronization signal, and the second module is an EPWM module that receives the local synchronization signal. For further details regarding the power control unit, please refer to the foregoing description. Figure 1 The relevant descriptions will not be repeated here. For example... Figure 3 As shown, the method includes the following steps: S201, the first module determines the target comparison value corresponding to the phase error comparison register of the first module.

[0055] A phase error comparison register is a comparison register used to store the comparison values ​​required for phase shifting. For example, the CC submodule of an EPWM module includes COMPA, COMPB, COMPC, and COMPD. COMPA and COMPB are used to store the comparison values ​​required for phase shifting, so the phase error comparison register can be COMPC or COMPD.

[0056] The comparison value stored in the phase mismatch register is used to determine the moment when a local synchronization event occurs within a switching cycle. When the TBPRD of the first module counts to the comparison value stored in the phase mismatch register of the first module, the phase mismatch comparator of the first module can generate a comparison event, triggering the AQ submodule of the first module. Therefore, changing the comparison value in the phase mismatch register can change the generation position of the synchronization signal within a switching cycle, thereby changing the phase mismatch angle between the first module and the second module.

[0057] The target comparison value corresponding to the phase misalignment comparison register of the first module refers to the comparison value that needs to be written into the phase misalignment comparison register to achieve the target phase misalignment angle corresponding to the first module. The target comparison value corresponding to the phase misalignment comparison register of the first module is obtained based on the cycle count value in the TBPRD of the first module and the target phase misalignment angle corresponding to the first module.

[0058] The target phase reversal angle corresponding to the first module is used to characterize the desired phase angle difference between the drive signals of the first module and the second module. This target phase reversal angle can be determined based on the number of parallel power conversion branches, input current ripple suppression requirements, branch current sharing control requirements, etc., or it can be dynamically adjusted according to the control objectives during the operation of the power conversion system.

[0059] Specifically, the power control unit can obtain the cycle count value corresponding to the current switching cycle from the TBPRD of the first module, and obtain the target phase misalignment angle corresponding to the first module from the control parameters of multiple EPWM modules. The target comparison value is determined according to the following relationship:

[0060] in, This indicates the target comparison value corresponding to the phase error comparison register, and P represents the cycle count value stored in the TBPRD of the first module. This indicates the target phase misalignment angle between the first module and the second module.

[0061] For example, in a two-way parallel SRDAB power conversion branch, if the target phase misalignment angle between the first and second branches is 90°, then the target comparison value is one-quarter of the current cycle count value, i.e.: .

[0062] It should be noted that the target phase misalignment angle is not limited to a fixed value. For example, under different operating conditions, the power control unit can dynamically adjust the target phase misalignment angle based on ripple suppression results, current sharing status, or other control objectives.

[0063] After determining the target comparison value, the power control unit can write the target comparison value into the phase mismatch register (such as COMPC) of the first module and wait for the first module to generate a comparison event; the first module reads its own phase mismatch register to determine the target comparison value corresponding to the phase mismatch register of the first module.

[0064] Optionally, before writing the target comparison value into the phase misalignment comparison register, a validity check can be performed on the target phase misalignment angle and the calculated target comparison value. When the target phase misalignment angle and the target comparison value are within a preset allowable range, the target comparison value is written into the phase misalignment comparison register. When the target phase misalignment angle or the calculated target comparison value exceeds the allowable range, the target comparison value can be limited, or the previous valid target comparison value can be retained to avoid the inability to generate a synchronization event normally due to the comparison value exceeding the register's valid range. The above validity processing does not change the fundamental relationship between the target comparison value and the period count value in the period register, which are jointly determined by the target phase misalignment angle.

[0065] S202, when the current count value in the TBCTR of the first module is equal to the target comparison value corresponding to the phase mismatch register of the first module, the first module sends a local synchronization signal to the second module, and the second module receives the local synchronization signal.

[0066] Specifically, the TBCTR of the first module counts in an upward counting mode and updates the current count value at each control clock edge. The first module compares the current count value in the TBCTR with the target comparison value corresponding to the phase mismatch comparator. When the current count value in the TBCTR equals the target comparison value corresponding to the phase mismatch comparator, a comparison event corresponding to the target comparison value is generated. Based on this comparison event, the first module generates a local synchronization signal and sends it to the local synchronization input of the second module through the local synchronization output of the first module. When the current count value in the TBCTR does not equal the target comparison value corresponding to the phase mismatch comparator, the first module continues to count in an upward counting mode until the current count value in the TBCTR reaches the target comparison value corresponding to the phase mismatch comparator.

[0067] For example, the power control unit includes EPWM1 ​​and EPWM2, the phase mismatch register is COMPC, the first module is EPWM1, and the second module is EPWM2. When the current count value in the TBCTR of EPWM1 ​​is equal to the target comparison value in the COMPC of EPWM1, EPWM1 ​​generates a local synchronization signal through the local synchronization output terminal, and EPWM2 receives the local synchronization signal through the local synchronization input terminal.

[0068] S203, in response to the local synchronization signal, the second module controls the TBCTR of the second module to start counting from the initial count value after being cleared.

[0069] The initial count value is the initial value used by the second module to re-establish the counting cycle after responding to the local synchronization signal. A zeroed initial count value indicates that the initial value is zero. After the second module's TBCTR acquires this initial count value, it uses it as the current count value and starts counting from this initial count value in an upward counting mode. In this way, the starting point of the second module's counting cycle can be determined by the time when the first module sends the local synchronization signal.

[0070] In some embodiments, the second module controls the TBCTR of the second module to start counting from the initial count value after being cleared through the following steps A1-A2: A1. Clear the starting count value in the TBPHS of the second module.

[0071] Specifically, after receiving the local synchronization signal sent by the first module, the second module can write zero into the TBPHS of the second module to clear the starting count value in the TBPHS of the second module.

[0072] A2. The second module controls the TBCTR of the second module to read the starting count value from the TBPHS of the second module, and use it as the current count value of the TBCTR of the second module.

[0073] Specifically, the second module can read the starting count value from the second module's TBPHS and write the read starting count value into the second module's TBCTR, thereby using the starting count value as the current count value of the second module's TBCTR.

[0074] In steps A1-A2 above, by clearing TBPHS and loading it into TBCTR, the EPWM module can obtain a definite counting reference after receiving the local synchronization signal, thereby improving the repeatability of the cascaded phase-shifting timing.

[0075] Understandably, the second module maintains its original counting process in the absence of a local synchronization signal.

[0076] It is understandable that when the power control unit contains multiple EPWM modules, local synchronization relationships can be established sequentially between adjacent or synchronous EPWM modules in accordance with the above-mentioned method of the first module sending a local synchronization signal to the second module and the second module responding to the local synchronization signal to re-establish the counting cycle, thereby realizing phase-shift control between multiple EPWM modules.

[0077] In the above Figure 3 In the corresponding technical solution, multiple EPWM modules in the power control unit form a cascaded link through a local synchronization signal. The EPWM module determines the target comparison value based on the period count value in the TBPRD and the target phase misalignment angle, and sends a local synchronization signal along the cascaded link when the count value of the TBCTR reaches the target comparison value. This allows the EPWM module that receives the local synchronization signal to re-establish the corresponding counting reference, which is beneficial for maintaining the target phase misalignment relationship between multiple EPWM modules during frequency modulation or phase adjustment, thereby suppressing the input current ripple of the multi-parallel power circuit.

[0078] The following examples illustrate the frequency modulation, phase shifting, and phase misalignment control of this application.

[0079] For example, power circuits such as Figure 2 As shown, the power control unit includes at least EPWM1 ​​to EPWM8. Each EPWM module can drive a pair of complementary switching transistors through outputs A and B. Assume that switching transistors S1 / S2, S3 / S4, S5 / S6, and S7 / S8 correspond to EPWM1 ​​to EPWM4 respectively, and switching transistors S9 / S10, S11 / S12, S13 / S14, and S15 / S16 correspond to EPWM5 to EPWM8 respectively.

[0080] Among them, EPWM1~EPWM4 are used to drive the first power conversion branch, and EPWM5~EPWM8 are used to drive the second power conversion branch.

[0081] Assuming the control chip's control clock frequency is 120MHz, the target switching frequency is 80kHz, and the control cycle frequency is 20kHz, the first power conversion branch may include a first inner phase shifter D1-1, a second inner phase shifter D3-1, and an outer phase shifter D2-1. The first inner phase shifter D1-1 characterizes the phase shift relationship of EPWM2 relative to EPWM1; the second inner phase shifter D3-1 characterizes the phase shift relationship of EPWM3 relative to EPWM1; and the outer phase shifter D2-1 characterizes the further phase shift relationship of EPWM4 relative to EPWM2. The first inner phase shifter D1-1 in the first power conversion branch is set to 10°, the second inner phase shifter D3-1 is set to 20°, and the outer phase shifter D2-1 is set to 30°. The target phase misalignment angle between the first and second power conversion branches is set to 90°.

[0082] First, the power control unit performs frequency modulation control on the EPWM module according to the target switching frequency. The EPWM module operates in an up-counting mode. The TBCTR starts counting from the initial count value and restarts counting when the count value reaches the period count value in the TBPRD. The period count value in the period register TBPRD is used to determine the switching period of the EPWM module. The period count value in TBPRD can be determined based on the control clock frequency and the target switching frequency.

[0083] P represents the period count value in TBPRD. This indicates the control clock frequency. Indicates the target switching frequency.

[0084] Set the TBPRD of EPWM1 ​​to 1500 to make EPWM1 ​​output the drive signal at a switching frequency of 80kHz. Other EPWM modules can be linked together using the same period parameter, thus ensuring that multiple EPWM modules maintain the same switching period.

[0085] Secondly, the power control unit performs phase-shift control on the EPWM module based on the aforementioned switching cycle. Phase-shift control is achieved by adjusting the comparison values ​​in COMPA and COMPB of the EPWM module. When the current count value in TBCTR reaches the comparison value in COMPA or COMPB, the EPWM module generates a corresponding comparison event and adjusts the edge position of the output drive signal according to the comparison event.

[0086] Specifically, EPWM1 ​​can be used as the reference module for the first power conversion branch, and its comparison register can be set as follows:

[0087]

[0088] Here, Cnt_Rev represents the reference count position, and its value range is a positive integer greater than 0 and less than the period count value in TBPRD. For example, Cnt_Rev is 5%-10% of the period count value in TBPRD. Through the above settings, the A output and B output of EPWM1 ​​can form a complementary driving relationship.

[0089] For the first inner phase shift D1-1, EPWM2 can be offset according to the angle corresponding to the first inner phase shift D1-1, and its comparison value can be set as follows:

[0090]

[0091] Therefore, EPWM2 has a 10° phase shift relative to EPWM1.

[0092] For the second inner phase shift D3-1, EPWM3 can be offset according to the angle corresponding to the second inner phase shift D3-1, and its comparison value can be set as follows:

[0093]

[0094] Therefore, EPWM3 has a 20° phase shift relative to EPWM1.

[0095] For the outer phase shift D2-1, EPWM4 can further increase the phase offset corresponding to the outer phase shift D2-1 based on the comparison position of EPWM2. The comparison value can be set as follows:

[0096]

[0097] Therefore, EPWM4 forms a 30° external phase shift relationship with EPWM2, thereby realizing the overall phase shift control inside the first power conversion branch.

[0098] It should be noted that in the above phase shift control process, each target phase shift angle needs to be converted into a count offset within the corresponding switching cycle. Since one switching cycle corresponds to a 360° phase, the count offset corresponding to any target phase shift angle can be expressed as:

[0099] in, This represents the count offset, where P represents the period count value in the TBPRD. This represents the target phase shift angle. For example, when the period count value P in the TBPRD is 1500, the first inner phase shift D1-1=10° corresponds to approximately 42 count offsets, the second inner phase shift D3-1=20° corresponds to approximately 83 count offsets, and the outer phase shift D2-1=30° corresponds to 125 count offsets. The EPWM module superimposes these count offsets onto the corresponding comparison positions to form a preset phase relationship between the drive signals output by different EPWM modules.

[0100] The second power conversion branch can adopt the control method corresponding to the first power conversion branch. For example, EPWM5 can be linked to EPWM1, EPWM6 can be linked to EPWM2, EPWM7 can be linked to EPWM3, and EPWM8 can be linked to EPWM4, so that the second power conversion branch maintains the phase shift relationship corresponding to the first power conversion branch.

[0101] Furthermore, to achieve phase misalignment control between the two parallel power conversion branches, a synchronization event can be generated using the phase misalignment comparison register of the EPWM module. EPWM1 ​​can be used as the first module, and EPWM5 as the second module, with the target phase misalignment angle between the first and second modules set to 90°.

[0102] The power control unit determines the target comparison value in COMPC based on the cycle count value in TBPRD and the target phase misalignment angle:

[0103] in, This represents the target comparison value in COMPC, and P represents the cycle count value in TBPRD. Indicates the target phase misalignment angle.

[0104] When the cycle count value corresponding to one switching cycle is 1500, and the target phase misalignment angle is 90°:

[0105] Therefore, the COMPC of EPWM1 ​​can be set to 375.

[0106] After EPWM1's TBCTR starts counting, when the current count value in TBCTR reaches 375, EPWM1 ​​generates a synchronization event and sends a partial synchronization signal to EPWM5. EPWM5 responds to the partial synchronization signal by resetting its own TBCTR to the starting count value, for example, by setting TBCTR to count from zero via TBPHS. Since EPWM5 restarts counting when EPWM1 ​​has run for a quarter of a switching cycle, EPWM5 has a 90° time offset relative to EPWM1, thus achieving phase shift control between the two parallel power conversion branches.

[0107] It should be noted that frequency modulation, phase shifting, and phase misalignment control are all implemented based on the same time base of the EPWM module. TBPRD is used to determine the switching period and counting scale of the EPWM module, COMPA and COMPB are used to determine the position of the drive signal within the same power conversion branch, and COMPC is used to determine the position of synchronization events between different power conversion branches. Therefore, when frequency modulation causes a change in the period count value in TBPRD, the comparison values ​​corresponding to the target phase shift angle and the target phase misalignment angle also need to be adjusted synchronously.

[0108] For example, when a change in the switching frequency causes the cycle count value in the TBPRD to change from 1500 to 1800, the COMPC comparison value corresponding to a 90° error needs to be adjusted from 375 to:

[0109] Meanwhile, the COMPA and COMPB comparison values ​​corresponding to phase shift angles of 10°, 20°, and 30° also need to be recalculated based on the new TBPRD. Through this method, the power control unit can maintain the phase shift relationship within the branch and the phase misalignment relationship between parallel branches while adjusting the switching frequency, achieving coordinated control of frequency modulation, phase shifting, and phase misalignment.

[0110] In some embodiments, the power circuit control method described above further includes: responding to a change in the phase shift direction of the plurality of EPWM modules in the power control unit, after turning off the drive signals of the plurality of EPWM modules, updating the phase shift parameters in the plurality of EPWM modules according to the changed phase shift direction, and restarting the drive signals of the plurality of EPWM modules after the phase shift parameters in the plurality of EPWM modules have been updated.

[0111] When the phase shift direction changes, the drive signal is turned off first, then the phase shift parameters are updated, and the drive signal is restarted after the parameter update is completed. This can prevent the abnormal duty cycle during the direction switching period from being actually applied to the power circuit, and reduce the risk of abnormal overcurrent and transformer bias.

[0112] The following steps, B1-B3, can be used to first turn off the drive signal, then update the phase shift parameters, and finally restart the drive signal after the parameter update is complete: B1. Write the driver shutdown parameters corresponding to each EPWM module into the shadow register of each EPWM module and trigger the first global load event.

[0113] Among them, the drive shutdown parameter refers to the parameter that triggers the drive shutdown signal. The drive shutdown parameter can be a delay count value that is greater than the period count value in TBPRD.

[0114] A global load event is an event that triggers the transfer of contents from the shadow registers of multiple EPWM modules to their corresponding active registers and makes them effective. A global load event is triggered once by a software global synchronization signal. The first global load event is used to synchronously load and make effective the drive shutdown parameters in the shadow registers of each EPWM module, thereby shutting down the drive signals of multiple EPWM modules.

[0115] Specifically, the driver shutdown parameters corresponding to each EPWM module can be written into the shadow register corresponding to the dead-time register of each EPWM module, and the first global load event can be triggered. The shadow register corresponding to the dead-time register is used to cache the parameters that need to be loaded into the dead-time register.

[0116] B2. After the drive signals of multiple EPWM modules are turned off, the target phase shift parameters corresponding to each EPWM module are written into the shadow register of each EPWM module, and the second global load event is triggered.

[0117] The target phase shift parameter is determined based on the changed phase shift direction, and the target phase shift parameter may include a period value and a comparison value determined based on the changed phase shift direction.

[0118] The second global load event is used to synchronously load and activate the target phase-shift parameters in the shadow registers of each EPWM module, thereby updating the phase-shift parameters in multiple EPWM modules.

[0119] Specifically, the drive shutdown parameters corresponding to each EPWM module can be written into the shadow register corresponding to the phase-shift comparator register of each EPWM module, triggering a second global load event. The shadow register corresponding to the phase-shift comparator register is used to cache the parameters that need to be loaded into the phase-shift comparator register. The phase-shift comparator register is a comparator register used to store the comparison values ​​required for phase shifting. For example, the CC submodule of the EPWM module includes COMPA, COMPB, COMPC, and COMPD. COMPA and COMPB are used to store the comparison values ​​required for phase shifting, so COMPA and COMPB are phase-shift comparator registers.

[0120] B3. After the target phase shift parameters in each EPWM module take effect, write the corresponding drive enable parameters of each EPWM module into the shadow register of each EPWM module and trigger the third global load event.

[0121] Among them, the driver enable parameter refers to the parameter that triggers the driver start signal or the driver restart signal. The driver enable parameter can be the preset dead zone value mentioned later.

[0122] The third global load event is used to synchronously load and activate the drive enable parameters in the shadow registers of each EPWM module, thereby restarting the drive signals of multiple EPWM modules.

[0123] Specifically, the driver enable parameters corresponding to each EPWM module can be written into the shadow register corresponding to the dead-time register of each EPWM module, and the third global load event can be triggered.

[0124] In steps B1-B3 above, the drive shutdown parameters, target phase shift parameters, and drive enable parameters are synchronized through three global load events, which can eliminate the time difference in the effectiveness of the parameters of each module caused by the order of program statement execution and maintain the consistency of the state of the multi-drive during the direction switching process.

[0125] Specifically, the interval between the triggering times of the second global load event and the first global load event is greater than half the maximum switching period corresponding to the multiple EPWM modules; the interval between the triggering times of the third global load event and the second global load event is also greater than half the maximum switching period. The maximum switching period is the largest of the switching periods that the multiple EPWM modules may currently use. Using the maximum value as the time base can cover the module with the lowest switching frequency and the longest period.

[0126] The interval between the trigger times of two adjacent global load times is greater than half of the maximum switching cycle, which allows time for drive shutdown propagation and the new phase shift parameters to take effect, reducing the possibility of overlap between the old drive state and the new parameter state.

[0127] In one specific implementation, the drive signal can be shut down first, then the phase-shift parameters can be updated, and finally the drive signal can be restarted after the parameter update is complete. Specifically, after triggering the first global load event, after waiting for one maximum switching cycle, the target phase-shift parameters corresponding to each EPWM module can be written into the shadow register of each EPWM module, and a second global load event can be triggered; after triggering the second global load event, after waiting for one maximum switching cycle, the drive enable parameters corresponding to each EPWM module can be written into the shadow register of each EPWM module, and a third global load event can be triggered. In this specific implementation, the control cycle is at least three times the maximum switching cycle.

[0128] By waiting for a maximum switching cycle before writing the target phase shift parameters and drive enable parameters, it is beneficial to reliably complete the direction switching in the master control sequential execution scenario.

[0129] In another specific implementation, the drive signal can be first turned off based on the terminal, then the phase shift parameters can be updated, and finally the drive signal can be restarted after the parameter update is completed. Specifically, in response to a first switching frequency interrupt, the drive shutdown parameters corresponding to each EPWM module can be written into the shadow register of each EPWM module, and a first global load event can be triggered; then, in response to a second switching frequency interrupt following the first switching frequency interrupt, the target phase shift parameters corresponding to each EPWM module can be written into the shadow register of each EPWM module, and a second global load event can be triggered; then, in response to a third switching frequency interrupt following the second switching frequency interrupt, the drive enable parameters corresponding to each EPWM module can be written into the shadow register of each EPWM module, and a third global load event can be triggered. The switching frequency interrupt is an interrupt generated according to the switching cycle of the EPWM module.

[0130] By arranging the drive shutdown, phase shift parameter update, and enable in three consecutive switching frequency interrupts, each stage can be synchronized with the switching cycle, thus ensuring timely phase shift direction switching even when the main control cycle is long.

[0131] Among them, the first switching frequency interrupt, the second switching frequency interrupt, and the third switching frequency interrupt are switching frequency interrupts that respond sequentially in a nested interrupt manner within the control cycle; or, the first switching frequency interrupt, the second switching frequency interrupt, and the third switching frequency interrupt are periodic control interrupts that are triggered sequentially, and the triggering frequency of the periodic control interrupt is the same as the switching frequency of the EPWM module.

[0132] By configuring the interrupt nesting method or the sequentially triggered periodic control interrupt according to the control cycle, different combinations of master control and switching frequencies can be adapted while maintaining the three-stage timing relationship, thereby improving the deployment flexibility of the control scheme.

[0133] In some embodiments, the power circuit control method described above further includes: in response to a drive shutdown signal being triggered, reloading the delay count value in the dead-time register of each EPWM module, such that the delay count value in the dead-time register of each EPWM module is greater than the period count value in the TBPRD.

[0134] The drive shutdown signal is a trigger signal that instructs the power control unit to stop multiple EPWM modules from outputting valid drive pulses to the power circuit. The drive shutdown signal can originate from fault protection logic or system state switching logic; overcurrent, overvoltage, or operating mode switching can all trigger it. For example, the drive shutdown signal is triggered when the phase shift direction of the aforementioned multiple EPWM modules changes.

[0135] Among them, the dead zone registers include the aforementioned DBRED and DBFED.

[0136] Specifically, the power control unit can write a preset delay count value greater than the period count value in TBCTR into the shadow register corresponding to the dead time register (including DBRED and DBFED) in each EPWM module, and trigger loading, so that each EPWM module reads the preset delay count value from its own shadow register corresponding to the dead time register and writes it into its own dead time register, thereby reloading the delay count value in the dead time register of each EPWM module.

[0137] When the drive signal is turned off, the delay count value in the dead zone register is made greater than the period count value in the period register. The edge delay covering the entire counting cycle can be used to block the drive pulse output, thus achieving drive shutdown without rewriting the original drive level logic.

[0138] In some specific implementations, the delay count in the dead-time register of each reloaded EPWM module is one more than the period count in the TBPRD.

[0139] Specifically, the power control unit can read the cycle count value in the TBPRD of each EPWM module and set the preset delay count value corresponding to each EPWM module to the cycle count value in the TBPRD of each EPWM module plus one; write the preset delay count value corresponding to each EPWM module into the shadow register corresponding to the dead time register in each EPWM module, and trigger loading, so that each EPWM module reads the preset delay count value from its own shadow register corresponding to the dead time register and writes it into its own dead time register, so that the delay count value in the dead time register of each EPWM module after reloading is the cycle count value in the TBPRD plus one.

[0140] Setting the delay count value to the period count value in TBPRD plus one allows the entire counting cycle to be covered by a definite value that is immediately adjacent to the upper limit of the period, simplifying the calculation and loading of the drive shutdown parameters.

[0141] In some embodiments, the power circuit control method described above further includes: in response to a drive restart signal being triggered, reloading the delay count value in the dead-time register of each EPWM module, such that the delay count value in the dead-time register of each EPWM module is a preset dead-time value.

[0142] The drive restart signal is a trigger signal that instructs the power control unit to exit the drive shutdown state and resume valid drive pulses. The drive restart signal can be triggered when the fault condition has been cleared or the system state allows for recovery. For example, it can be triggered after the target phase shift parameters in each EPWM module take effect.

[0143] The preset dead zone value is determined based on the turn-off delay time of the switching devices. Specifically, the preset dead zone value should be greater than the turn-off time of the slower-turning device among the switching devices on the same bridge arm. The preset dead zone value can be determined as follows: Dead = (t_off_max + t_margin) × f clk Where t_off_max is the maximum turn-off time of the switching device, t_margin is the safety margin, which is usually taken as 10%-20% of t_off_max, and f clk To control the clock frequency. For example, when the switching device turn-off time is 200ns, the safety margin is 50ns, and the control clock frequency is 120MHz: Dead = (200ns + 50ns) × 120MHz = 30.

[0144] Specifically, the power control unit can write the preset dead time value into the shadow register corresponding to the dead time register in each EPWM module and trigger loading, so that each EPWM module reads the preset dead time value from its own shadow register corresponding to the dead time register and writes it into its own dead time register, thereby reloading the delay count value in the dead time register of each EPWM module, so that the delay count value in the dead time register of each EPWM module is the preset dead time value.

[0145] When restarting the drive signal, reloading the preset dead time value can restore the normal delay relationship between complementary drive edges, allowing the power circuit to resume drive output while meeting the dead time requirements.

[0146] See Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 30 includes a processor 301 and a memory 302. The memory 302 is connected to the processor 301, for example, via a bus.

[0147] The processor 301 can be a central processing unit (CPU), graphics processing unit (GPU), network processor (NP), neural-network processing unit (NPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), complex programmable logic device (CPLD), field-programmable gate array (FPGA), or generic array logic (GAL), etc.

[0148] The memory 302 may include volatile memory (VM), such as random access memory (RAM); the memory 302 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD).

[0149] The memory 302 is used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the power circuit control method in the embodiments of this application. The processor executes various functional applications and data processing of the power circuit control method by running the non-volatile software programs, instructions, and modules stored in the memory, thereby realizing the functions of the power circuit control method provided in the above method embodiments.

[0150] The memory 302 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the power circuit control method. Furthermore, the memory 302 may include high-speed random access memory, and may also include remotely accessible memory connected via a network, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device.

[0151] The one or more modules are stored in the memory, and when executed by the processor, they perform the power circuit control method in any of the above method embodiments.

[0152] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a computer, cause the computer to perform the method described in the foregoing embodiments.

[0153] This application also provides a power control unit, including a plurality of enhanced pulse width modulation modules, which is used to execute the power circuit control method in the foregoing method embodiments.

[0154] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The computer-readable storage medium can be a disk, optical disk, read-only memory, random access memory, flash memory, hard disk, solid-state drive, or a combination of the above media.

[0155] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with this application still fall within the scope of this application.

Claims

1. A power circuit control method, characterized in that, This invention is applied to a power control unit connected to a power circuit. The power control unit includes multiple enhanced pulse width modulation (PWM) modules, each of which includes a time base period register, a phase mismatch register, and a time base counter. The multiple PWM modules form a cascaded link through a local synchronization signal. The multiple PWM modules include a first module and a second module, where the first module is an PWM module that transmits the local synchronization signal, and the second module is an PWM module that receives the local synchronization signal. The method includes: The first module determines the target comparison value corresponding to the phase mismatch comparison register of the first module. The target comparison value corresponding to the phase mismatch comparison register of the first module is obtained based on the period count value in the time base period register of the first module and the target phase mismatch angle corresponding to the first module. When the current count value in the time base counter of the first module is equal to the target comparison value corresponding to the phase mismatch register of the first module, the first module sends a local synchronization signal to the second module. In response to the local synchronization signal, the second module controls the time base counter of the second module to start counting from the initial count value after being cleared.

2. The method according to claim 1, characterized in that, Each enhanced pulse width modulation module also includes a time base phase register; The second module controls its time base counter to start counting from the reset initial count value, including: The second module clears the initial count value in the time base phase register of the second module; The second module controls its time base counter to read the starting count value from the time base phase register of the second module, and uses it as the current count value of the time base counter of the second module.

3. The method according to claim 1, characterized in that, Each enhanced pulse width modulation module also includes a dead-time register; The method further includes: In response to the drive shutdown signal being triggered, the delay count value in the dead time register of each enhanced pulse width modulation module is reloaded, such that the delay count value in the dead time register of each enhanced pulse width modulation module is greater than the period count value in the time base period register.

4. The method according to claim 3, characterized in that, After reloading, the delay count in the dead zone register of each enhanced pulse width modulation module is increased by one from the period count in the time base period register.

5. The method according to claim 1, characterized in that, Each enhanced pulse width modulation module also includes a dead-time register; The method further includes: In response to the drive restart signal being triggered, the delay count value in the dead zone register of each enhanced pulse width modulation module is reloaded, so that the delay count value in the dead zone register of each enhanced pulse width modulation module is a preset dead zone value.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: In response to a change in the phase shift direction of the plurality of enhanced pulse width modulation modules, after the drive signals of the plurality of enhanced pulse width modulation modules are turned off, the phase shift parameters in the plurality of enhanced pulse width modulation modules are updated according to the changed phase shift direction, and after the phase shift parameters in the plurality of enhanced pulse width modulation modules are updated, the drive signals of the plurality of enhanced pulse width modulation modules are restarted.

7. The method according to claim 6, characterized in that, Each enhanced pulse width modulation module also includes a shadow register; After turning off the drive signals of the plurality of enhanced pulse width modulation modules, the phase shift parameters in the plurality of enhanced pulse width modulation modules are updated according to the changed phase shift direction, and the drive signals of the plurality of enhanced pulse width modulation modules are restarted after the phase shift parameters in the plurality of enhanced pulse width modulation modules are updated, including: Write the drive shutdown parameters corresponding to each enhanced pulse width modulation module into the shadow register of each enhanced pulse width modulation module, and trigger a first global load event; wherein, the first global load event is used to load and activate the drive shutdown parameters in the shadow registers of each enhanced pulse width modulation module synchronously, so as to shut down the drive signals of the multiple enhanced pulse width modulation modules. After the drive signals of the plurality of enhanced pulse width modulation modules are turned off, the target phase shift parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a second global load event is triggered; wherein, the target phase shift parameters are determined based on the changed phase shift direction, and the second global load event is used to synchronously load and activate the target phase shift parameters in the shadow registers of each enhanced pulse width modulation module, so as to update the phase shift parameters in the plurality of enhanced pulse width modulation modules; After the target phase shift parameters in each enhanced pulse width modulation module take effect, the drive enable parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a third global load event is triggered; wherein, the third global load event is used to load and take effect the drive enable parameters in the shadow registers of each enhanced pulse width modulation module synchronously, so as to restart the drive signals of the multiple enhanced pulse width modulation modules.

8. The method according to claim 7, characterized in that, The interval between the triggering time of the second global loading event and the triggering time of the first global loading event is greater than half of the maximum switching period corresponding to the plurality of enhanced pulse width modulation modules; the interval between the triggering time of the third global loading event and the triggering time of the second global loading event is greater than half of the maximum switching period.

9. The method according to claim 8, characterized in that, After the drive signals of the plurality of enhanced pulse width modulation modules are turned off, the target phase shift parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a second global load event is triggered, including: After waiting for a maximum switching cycle, the target phase shift parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a second global load event is triggered. After the target phase shift parameters in each enhanced pulse width modulation module take effect, the drive enable parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a third global load event is triggered, including: After waiting for a maximum switching cycle, the drive enable parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a third global load event is triggered.

10. The method according to claim 8, characterized in that, The step of writing the drive shutdown parameters corresponding to each enhanced pulse width modulation module into the shadow register of each enhanced pulse width modulation module and triggering the first global load event includes: In response to the first switching frequency interruption, the drive shutdown parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and the first global load event is triggered. After the drive signals of the plurality of enhanced pulse width modulation modules are turned off, the target phase shift parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a second global load event is triggered, including: In response to a second switching frequency interrupt following the first switching frequency interrupt, the target phase shift parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a second global load event is triggered. After the target phase shift parameters in each enhanced pulse width modulation module take effect, the drive enable parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a third global load event is triggered, including: In response to the third switching frequency interrupt following the second switching frequency interrupt, the drive enable parameters corresponding to each enhanced pulse width modulation module are written into the shadow register of each enhanced pulse width modulation module, and a third global load event is triggered.

11. The method according to claim 10, characterized in that, The first switching frequency interrupt, the second switching frequency interrupt, and the third switching frequency interrupt are switching frequency interrupts that respond sequentially in a nested interrupt manner within the control cycle; or, the first switching frequency interrupt, the second switching frequency interrupt, and the third switching frequency interrupt are periodic control interrupts that are triggered sequentially, and the triggering frequency of the periodic control interrupt is the same as the switching frequency of the enhanced pulse width modulation module.

12. An electronic device, characterized in that, The device includes a memory and a processor, the memory being connected to the processor, the processor being configured to execute one or more computer programs stored in the memory, the processor causing the electronic device to perform the method as described in any one of claims 1-11 when executing the one or more computer programs.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 1-11.

14. A power control unit, characterized in that, It includes multiple enhanced pulse width modulation modules, and the power control unit is used to perform the method as described in any one of claims 1-11.

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