A high-side energy-conserving always-on high-side power supply circuit and method
Patent Information
- Application Number
- CN202611311010.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-27
- Publication Date
- 2026-10-23
AI Technical Summary
但是，该电路的缺点是电容C_CP为高压电容，难以集成
[0013]上述技术方案能够实现下述技术效果中的至少部分：本申请所述的高侧能常通的高侧供电电路及方法，当高侧电源电压VB低于低侧电源VDD时，VDD通过自举电路对VB充电，当VB高于VDD时，电荷泵电路对VBS（VB-VS）充电，直到VBS电压高于预定值时，关闭电荷泵电路。所述电荷泵电路的电源既可以由VDD通过自举电路供电，又可以由VS通过二极管供电，这样无论在VS处于低压还是高压，电荷泵电路都可以工作。因此，本申请所述的高侧供电电路既能够维持高侧电源VBS长时间稳定，使高侧能100%占空比导通；且系统启动时，不需要控制低侧管，也能使高侧电源VBS升高，使高侧电路正常工作；电路不需要外置高压二极管和高压电容，易于集成。
Smart Images
Figure CN122969347A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a high-side power supply circuit and method with high-side power supply that is always on. Background Technology
[0002] In power electronic systems such as switching power supplies, motor drives, and Class D power amplifiers, the half-bridge power stage is the basic unit for power conversion and driving. In a half-bridge circuit, the source voltage of the high-side power switch is floating, and its potential switches rapidly between the high-voltage bus voltage and ground. To ensure reliable conduction of the high-side switch, a drive signal with a voltage amplitude higher than that of the floating source is required. Therefore, providing a stable, reliable, and performance-compliant supply voltage for the floating high-side drive circuit is a critical problem that urgently needs to be solved in high-side drive technology.
[0003] A traditional high-side circuit, such as Figure 1 As shown, the high-side circuit is charged by a bootstrap diode (DBS), and the voltage is maintained by a capacitor (CBS). This power supply method is simple and effective, and is currently the most widely used structure. However, this traditional topology has inherent technical defects. First, since the capacitor CBS only gets a chance to charge when VS is low, if the high-side switch needs to be continuously turned on for a long time (i.e., the duty cycle is close to 100%), the capacitor CBS cannot receive periodic charge replenishment, causing the capacitor VBS to continuously decrease, eventually leading to undervoltage and causing the power transistor PowerMOS to exit the saturation region, resulting in a sharp increase in conduction losses or even burnout. Second, the initial voltage across the capacitor CBS is zero when the system starts up, requiring the low-side transistor or auxiliary switch to be turned on in advance for initial charging (i.e., pulling VS low), which increases the control timing complexity.
[0004] Another type of high-side circuit, such as Figure 2 As shown, this circuit uses a charge pump circuit to charge VB. The charge pump circuit includes a buffer, capacitor C_CP, diodes D_CP1 and D_CP2, and the input signal is the oscillation clock signal CLK. This circuit allows the high side to conduct for a long time while avoiding system startup problems. However, the disadvantage of this circuit is that capacitor C_CP is a high-voltage capacitor, which is difficult to integrate. Summary of the Invention
[0005] This application provides a high-side power supply circuit and method that is always on on the high side. The technical purpose is to maintain the high-side power supply VBS stable for a long time, enable the high side to conduct with 100% duty cycle, avoid system startup problems, and make the overall circuit easy to integrate.
[0006] The above-mentioned technical objective of this application is achieved through the following technical solution: A high-side power supply circuit that is always on includes a resistor R0, a capacitor C0, a Zener diode Z0, a diode D0, a current source I0, a PLDMOS transistor LDM0, a PLDMOS transistor LDM1, an NLDMOS transistor LDM2, a first bootstrap circuit, a second bootstrap circuit, a first oscillator, a charge pump circuit, a voltage detection circuit, and a level shifting circuit. The input terminals of both the first bootstrap circuit and the second bootstrap circuit are connected to the power supply terminal VDD; the output terminal of the first bootstrap circuit is connected to the high-side floating power supply terminal VB, and is also connected to the high-side power supply terminal of the charge pump circuit, the power supply terminal of the voltage detection circuit, and the high-side power supply terminal of the level shifting circuit. The output terminal of the second bootstrap circuit is connected to one end of the resistor R0, one end of the capacitor C0, the negative terminal of the Zener diode Z0, the power supply terminal of the first oscillator, the negative terminal of the diode D0, and the low-side power supply terminal of the charge pump circuit, with the signal being VDD_CP. The other end of the resistor R0 is connected to the source terminal of the PLDMOS transistor LDM1. The gate terminal of the PLDMOS transistor LDM1 is connected to its drain terminal, the other end of the capacitor C0, the positive terminal of the Zener diode Z0, the gate terminal of the PLDMOS transistor LDM0, and the drain terminal of the NLDMOS transistor LDM2. The source terminal of the NLDMOS transistor LDM2 is connected to the power supply terminal of the current source I0, and the gate terminal is connected to the output terminal of the level shifting circuit. The ground terminal of the current source I0 is connected to ground GND and is also connected to the drain terminal of the PLDMOS transistor LDM0. The source terminal of the PLDMOS transistor LDM0 is connected to the ground terminal of the first oscillator and the low-side ground terminal of the charge pump circuit, and the signal is GND_CP. The output terminal of the first oscillator is connected to the input terminal of the charge pump circuit; The positive terminal of the diode D0 is connected to the high-side floating ground terminal VS, and is also connected to the high-side ground terminal of the charge pump circuit, the ground terminal of the voltage detection circuit, and the high-side ground terminal of the level shifting circuit. The output terminal of the voltage detection circuit is connected to the input terminal of the level shifting circuit; The low-side power supply terminal of the level shifting circuit is connected to the power supply terminal VDD, and the low-side ground terminal is connected to the ground terminal GND.
[0007] Preferably, the charge pump circuit includes n signal processing units, n capacitors, and n+1 diodes. The n signal processing units are composed of n1 buffers and n2 inverters, where n1+n2=n, and n1 and n2 are both non-negative integers. All the diodes are connected in series, and a capacitor is connected in parallel between any two adjacent diodes. The output terminal of each buffer or each inverter is connected to one end of a capacitor, and the other end of the capacitor is connected to two adjacent diodes. When n=1, n1=1 and n2=0 or n1=0 and n2=1, the charge pump circuit includes a buffer BUF1 or an inverter INV1, a capacitor C1, a diode D1, and a diode D2. The input terminal of the buffer BUF1 or the inverter INV1 serves as the input terminal of the charge pump circuit, and the signal is clk. The power supply terminal of the buffer BUF1 or the inverter INV1 serves as the low-side power supply terminal VDD_CP of the charge pump circuit. The ground terminal of the buffer BUF1 or the inverter INV1 serves as the low-side ground terminal GND_CP of the charge pump circuit. The output terminal of the buffer BUF1 or the inverter INV1 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the positive terminal of the diode D1 and the negative terminal of the diode D2. The negative terminal of the diode D1 is connected to the high-side floating power supply terminal VB, serving as the high-side power supply terminal of the charge pump circuit. The positive terminal of the diode D2 is connected to the high-side floating ground terminal VS, serving as the high-side ground terminal of the charge pump circuit. When n≥2, if n is even, then n1=n2; if n is odd, then n1=n2+1 or n1=n2-1. The clock signal of the adjacent capacitors is an inverted signal. The adjacent signal processing units are buffers and inverters, respectively. The input terminals of each signal processing unit are connected in parallel as the input terminals of the charge pump circuit, and the signal is clk. The power supply terminal of the first signal processing unit is the low-side power supply terminal VDD_CP of the charge pump circuit. The negative terminal of the first diode is connected to the high-side floating power supply terminal VB, which is the high-side power supply terminal of the charge pump circuit. The ground terminal of the last signal processing unit is the low-side ground terminal GND_CP of the charge pump circuit. The positive terminal of the last diode is connected to the high-side floating ground terminal VS, which is the high-side ground terminal of the charge pump circuit.
[0008] Preferably, the charge pump circuit includes at least one charge pump unit, which includes a buffer BUF1, an inverter INV1, an inverter INV2, an inverter INV3, a capacitor C1, and a capacitor C2. The clock signals of capacitors C1 and C2 are inverted signals. The input terminal of the buffer BUF1 is connected to the input terminal of the inverter INV1, serving as the input terminal of the charge pump unit, and the signal is clk. The output terminal of the buffer BUF1 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the input terminal of the inverter INV2 and the output terminal of the inverter INV3. The output terminals are connected as follows: the output terminal of inverter INV1 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to the output terminal of inverter INV2 and the input terminal of inverter INV3; the power supply terminals of buffer BUF1 and inverter INV1 are connected to the low-side power supply terminal VDD_CP, and the ground terminals of buffer BUF1 and inverter INV1 are connected to the low-side ground GND_CP; the power supply terminals of inverter INV2 and inverter INV3 are connected to the high-side floating power supply terminal VB, and the ground terminals of inverter INV2 and inverter INV3 are connected to the high-side floating ground terminal VS; When the charge pump circuit includes only one charge pump unit: the input terminal of the charge pump unit serves as the input terminal of the charge pump circuit, the power supply terminals of the buffer BUF1 and the inverter INV1 serve as the low-side power supply terminals of the charge pump circuit, the ground terminals of the buffer BUF1 and the inverter INV1 serve as the low-side ground terminals of the charge pump circuit, the power supply terminals of the inverter INV2 and the inverter INV3 serve as the high-side power supply terminals of the charge pump circuit, and the ground terminals of the inverter INV2 and the inverter INV3 serve as the high-side ground terminals of the charge pump circuit; When the charge pump circuit includes two or more charge pump units: the ground terminals of inverters INV2 and INV3 in the previous charge pump unit are connected to the power supply terminals of inverters INV2 and INV3 in the next charge pump unit; the power supply terminals of inverters INV2 and INV3 in the first charge pump unit are connected to the high-side floating power supply terminal VB, and serve as the high-side power supply terminal of the charge pump circuit; the ground terminals of inverters INV2 and INV3 in the last charge pump unit are connected to the high-side floating ground terminal VS, and serve as the high-side ground terminal of the charge pump circuit; the input terminals of each charge pump unit are connected in parallel as the input terminals of the charge pump circuit; the power supply terminals of buffer BUF1 and inverter INV1 in each charge pump unit are connected in parallel as the low-side power supply terminal of the charge pump circuit, and the ground terminals of buffer BUF1 and inverter INV1 in each charge pump unit are connected in parallel as the low-side ground terminal of the charge pump circuit.
[0009] Preferably, both the first bootstrap circuit and the second bootstrap circuit include any one of the following three types of bootstrap circuits: Bootstrap circuit a includes diode D4; the positive terminal of diode D4 is the input terminal of bootstrap circuit a, and the negative terminal is the output terminal of bootstrap circuit a. Bootstrap circuit b includes diode D5 and junction field-effect transistor J0; the positive terminal of diode D5 is the input terminal of bootstrap circuit b, and the negative terminal is connected to the source terminal of junction field-effect transistor J0; the gate terminal of junction field-effect transistor J0 is grounded, and the drain terminal is the output terminal of bootstrap circuit b. The bootstrap circuit c includes a second oscillator, a buffer BUF2, a capacitor C3, diodes D6, D7, and D8, and an NLDMOS transistor LDM3. The power supply terminal of the second oscillator serves as the input terminal of the bootstrap circuit c, connected to the power supply VDD, and connected to the power supply terminal of the buffer BUF2, the positive terminal of diode D6, and the positive terminal of diode D7. The output terminal of the second oscillator is connected to the input terminal of the buffer BUF2. The ground terminal of the second oscillator is connected to GND and to the ground terminal of the buffer BUF2. The output terminal of the buffer BUF2 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the negative terminal of diode D7 and the positive terminal of diode D8, the negative terminal of diode D6 is connected to the source terminal of the NLDMOS transistor LDM3, and the gate terminal of the NLDMOS transistor LDM3 is connected to the negative terminal of diode D8. The drain terminal of the NLDMOS transistor LDM3 is the output terminal of the bootstrap circuit c.
[0010] Preferably, the voltage detection circuit includes resistor R1, resistor R2, a reference circuit, and a comparator; One end of resistor R1 is connected to the high-side floating power supply VB, serving as the power supply terminal of the voltage detection circuit, and is also connected to the power supply terminal of the reference circuit and the power supply terminal of the comparator; the other end of resistor R1 is connected to one end of resistor R2 and the non-inverting input terminal of the comparator. The other end of the resistor R2 is connected to the high-side floating ground VS, serving as the ground terminal of the voltage detection circuit, and is also connected to the ground terminal of the reference circuit and the ground terminal of the comparator. The output terminal of the reference circuit is connected to the inverting input terminal of the comparator, and the signal is the reference signal Vref. The output terminal of the comparator is the output terminal of the voltage detection circuit.
[0011] Preferably, the level shifting circuit includes PLDMOS transistor LDM4, PLDMOS transistor LDM5, NLDMOS transistor LDM6, NLDMOS transistor LDM7, NMOS transistor M0, NMOS transistor M1, inverter INV4, resistor R3, and buffer BUF3; The source terminal of the PLDMOS transistor LDM4 is connected to the high-side floating power supply VB, and is also connected to the power supply terminal of the inverter INV4 and the source terminal of the PLDMOS transistor LDM5, serving as the high-side power supply terminal of the level shifting circuit; the gate terminal is connected to the output terminal of the inverter INV4; and the drain terminal is connected to the drain terminal of the NLDMOS transistor LDM6. The input terminal of the inverter INV4 is connected to the gate terminal of the PLDMOS transistor LDM5, serving as the input terminal of the level shifting circuit; the ground terminal is connected to the high-side floating ground terminal VS, serving as the high-side ground terminal of the level shifting circuit. The drain terminal of the PLDMOS transistor LDM5 is connected to the drain terminal of the NLDMOS transistor LDM7. The gate terminal of the NLDMOS transistor LDM6 is connected to the power supply VDD, and is also connected to the gate terminal of the NLDMOS transistor LDM7, one end of the resistor R3, and the power supply terminal of the buffer BUF3, serving as the low-side power supply terminal of the level shifting circuit; the source terminal is connected to the drain terminal of the NMOS transistor M0 and the gate terminal of the NMOS transistor M1. The source terminal of the NLDMOS transistor LDM7 is connected to the gate terminal of the NMOS transistor M0, the drain terminal of the NMOS transistor M1, the other end of the resistor R3, and the input terminal of the buffer BUF3. The source terminal of the NMOS transistor M0 is connected to GND, and is also connected to the source terminal of the NMOS transistor M1 and the ground terminal of the buffer BUF3, serving as the low-side ground terminal of the level shifting circuit. The output of the buffer BUF3 serves as the output of the level shifting circuit.
[0012] A high-side power supply method with constant high-side power supply, wherein the high-side power supply method realizes high-side power supply through the high-side power supply circuit.
[0013] The above technical solution can achieve at least some of the following technical effects: The high-side power supply circuit and method described in this application, where the high-side power supply voltage VB is lower than the low-side power supply VDD, charges VB through a bootstrap circuit. When VB is higher than VDD, the charge pump circuit charges VBS (VB-VS) until the VBS voltage exceeds a predetermined value, at which point the charge pump circuit is turned off. The power supply for the charge pump circuit can be either supplied by VDD through the bootstrap circuit or by VS through a diode, allowing the charge pump circuit to operate regardless of whether VS is at a low or high voltage. Therefore, the high-side power supply circuit described in this application can maintain the high-side power supply VBS stable for a long time, enabling 100% duty cycle conduction on the high-side; and during system startup, it does not require controlling the low-side transistor to raise the high-side power supply VBS, allowing the high-side circuit to operate normally; the circuit does not require external high-voltage diodes and high-voltage capacitors, making it easy to integrate. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0015] Figure 1 A schematic diagram of a traditional high-side circuit structure; Figure 2 This is a schematic diagram of an existing high-side circuit structure; Figure 3 This is a schematic diagram of a high-side power supply circuit structure that is always on on the high side, according to an embodiment of this application. Figure 4 This is a schematic diagram of the charge pump circuit example 1 in the embodiments of this application; Figure 5 This is a schematic diagram of the charge pump circuit in Example 2 of the embodiments of this application; Figure 6 This is a schematic diagram of the charge pump circuit in Example 3 of the embodiments of this application; Figure 7 This is a schematic diagram of the charge pump circuit in Example 4 of the embodiments of this application; Figure 8 This is a schematic diagram of the charge pump circuit in Example 5 of the embodiments of this application; Figure 9 This is a schematic diagram of the charge pump circuit example six in the embodiments of this application; Figure 10 This is a schematic diagram of the bootstrap circuit example 1 in the embodiments of this application; Figure 11 This is a schematic diagram of the bootstrap circuit example two in the embodiments of this application; Figure 12 This is a schematic diagram of the bootstrap circuit example three in the embodiments of this application; Figure 13 This is a schematic diagram of the voltage detection circuit in an embodiment of this application; Figure 14 This is a schematic diagram of the level shifting circuit in an embodiment of this application. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings.
[0017] The high-side power supply circuit described in this application, which is always on the high-side, is as follows: Figure 3 As shown, it includes resistor R0, capacitor C0, Zener diode Z0, diode D0, current source I0, PLDMOS transistor LDM0, PLDMOS transistor LDM1, NLDMOS transistor LDM2, first bootstrap circuit, second bootstrap circuit, first oscillator, charge pump circuit, voltage detection circuit and level shifting circuit.
[0018] The high-side power supply circuit operates as follows: When the high-side power supply VB is lower than the low-side power supply VDD, VDD primarily charges VB through the bootstrap circuit. When VB is higher than VDD, the bootstrap circuit cannot charge VB. The charge pump circuit's operating state is independent of the VB voltage, depending only on VBS (the voltage difference between VB and VS, VB-VS). When the VBS voltage is lower than a predetermined value, the voltage detection circuit outputs a low level (high voltage), the level shifting circuit outputs a high level (low voltage), the NLDMOS transistor LDM0 is turned on, and the charge pump circuit is in operation. When the VBS voltage is higher than the predetermined value, the voltage detection circuit outputs a high level (high voltage), the level shifting circuit outputs a low level (low voltage), LDM0 is turned off, and the charge pump circuit is turned off. This maintains a stable VBS voltage, preventing excessive voltage and reducing power consumption.
[0019] The power supply system for the first oscillator and charge pump circuit includes a bootstrap current source I0, an NLDMOS transistor LDM2, a resistor R0, a capacitor C0, a Zener diode Z0, a PLDMOS transistor LDM0, and a diode D0. Its voltage is determined by the current source I0 and the resistor R0, and is expressed as: .
[0020] When the VS voltage is low (typically when the PowerMOS transistor is off), the first oscillator and charge pump circuit are powered by VDD through the bootstrap circuit. When the VS voltage increases (typically when the PowerMOS transistor is on), the first oscillator and charge pump circuit are powered by VS through diode D0. The first oscillator provides the clock signal for the charge pump circuit. Therefore, the charge pump circuit can operate regardless of whether the VS voltage is high or low. This allows the high-side PowerMOS transistor to be on for an extended period, keeping VS / VB high for a prolonged time. It also avoids system startup problems, where VS and VB are at the same potential as VDD during startup, making it impossible to power the circuit through the bootstrap circuit; instead, the charge pump circuit can provide power.
[0021] The charge pump circuit can be Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 Any one of them.
[0022] In one embodiment of the charge pump circuit, the charge pump circuit includes n signal processing units, n capacitors, and n+1 diodes. The n signal processing units consist of n1 buffers and n2 inverters, where n1+n2=n, and n1 and n2 are both non-negative integers. The number of capacitors and diodes can be set according to the VBS voltage requirements. The diodes are connected end-to-end in series. One end of a capacitor is connected to the junction of two diodes, and the other end of the capacitor is connected to the clock signal. The clock signals between adjacent capacitors are inverted signals.
[0023] like Figure 4 As shown, the charge pump circuit includes a buffer BUF1, a capacitor C1, and two diodes D1 and D2. In this embodiment, the buffer can also be replaced with an inverter. The output voltage (VB-VS) of this structure can reach the following under no-load conditions: ; VF represents the forward voltage drop of the diode.
[0024] like Figure 5 As shown, this charge pump circuit includes two capacitors, correspondingly requiring three diodes and two signal processing units. One signal processing unit is a buffer, and the other is an inverter. Specifically: one buffer BUF1, one inverter INV1, two capacitors C1 and C2, and three diodes D1, D2, and D3. This structure can achieve the following output voltage (VB-VS) under no-load conditions: .
[0025] like Figure 6 As shown, the charge pump circuit contains n capacitors and n+1 diodes, with corresponding n1 buffers and n2 inverters. The output voltage (VB-VS) of this structure can reach the following under no-load conditions: .
[0026] In another embodiment of the charge pump circuit, the charge pump circuit includes at least one charge pump unit, which includes a buffer, three inverters and two capacitors.
[0027] like Figure 7 As shown, this charge pump circuit includes only one charge pump unit, namely, buffer BUF1, inverter INV1, inverter INV2, inverter INV3, capacitor C1, and capacitor C2. This structure has no diode voltage drop, allowing for higher voltages. The no-load output voltage (VB-VS) is: .
[0028] A charge pump circuit can also be like this Figure 8 The structure shown consists of two identical Figure 7 The structure is configured such that the output voltage (VB-VS) under no-load conditions is: .
[0029] A charge pump circuit can also be like this Figure 9 The structure shown consists of n identical Figure 7 The structure is configured such that the output voltage (VB-VS) under no-load conditions is: .
[0030] Both the first bootstrap circuit and the second bootstrap circuit include three structures, and the first bootstrap circuit and the second bootstrap circuit can choose any one of the three structures.
[0031] The first type of bootstrap circuit structure is as follows: Figure 10 As shown, the bootstrap circuit a includes a high-voltage diode D4, which serves to conduct in the forward direction and withstand high voltage in the reverse direction.
[0032] The second type of bootstrap circuit structure is as follows: Figure 11 As shown, the bootstrap circuit b includes a diode D5 and a high-voltage JFET device J0. Diode D5 and J0 are connected in series. J0 serves to withstand high voltage, and diode D5 prevents the VB current from flowing in reverse to VDD.
[0033] The third type of bootstrap circuit structure is as follows: Figure 12As shown, the bootstrap circuit c works as follows: the second oscillator, buffer BUF2, capacitor C3, diode D6, and diode D7 supply power to the gate of NLDMOS transistor LDM3, keeping it in the on state. When the drain voltage of NLDMOS transistor LDM3 is lower than VDD by one diode voltage, VDD charges the drain through diode D6 and NLDMOS transistor LDM3. When the drain voltage of NLDMOS transistor LDM3 becomes higher, this current path is cut off.
[0034] Voltage detection circuit such as Figure 13 As shown, this circuit detects the voltage difference VBS between VB and VS. When VBS exceeds a certain threshold, the output is high; otherwise, the output is low. This threshold (VTH_BS) is: .
[0035] Level shifting circuits such as Figure 14 As shown, this circuit can convert high-voltage domain (VB / VS) signals into low-voltage domain (VDD / GND) signals, providing switching control signals for the charge pump circuit.
[0036] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
[0037] The above description is not intended to limit the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.
Claims
1. A high-side power supply circuit that is always on on the high side, characterized in that, It includes resistor R0, capacitor C0, Zener diode Z0, diode D0, current source I0, PLDMOS transistor LDM0, PLDMOS transistor LDM1, NLDMOS transistor LDM2, first bootstrap circuit, second bootstrap circuit, first oscillator, charge pump circuit, voltage detection circuit and level shifting circuit. The input terminals of both the first bootstrap circuit and the second bootstrap circuit are connected to the power supply terminal VDD; the output terminal of the first bootstrap circuit is connected to the high-side floating power supply terminal VB, and is also connected to the high-side power supply terminal of the charge pump circuit, the power supply terminal of the voltage detection circuit, and the high-side power supply terminal of the level shifting circuit. The output terminal of the second bootstrap circuit is connected to one end of the resistor R0, one end of the capacitor C0, the negative terminal of the Zener diode Z0, the power supply terminal of the first oscillator, the negative terminal of the diode D0, and the low-side power supply terminal of the charge pump circuit, with the signal being VDD_CP. The other end of the resistor R0 is connected to the source terminal of the PLDMOS transistor LDM1. The gate terminal of the PLDMOS transistor LDM1 is connected to its drain terminal, the other end of the capacitor C0, the positive terminal of the Zener diode Z0, the gate terminal of the PLDMOS transistor LDM0, and the drain terminal of the NLDMOS transistor LDM2. The source terminal of the NLDMOS transistor LDM2 is connected to the power supply terminal of the current source I0, and the gate terminal is connected to the output terminal of the level shifting circuit. The ground terminal of the current source I0 is connected to ground GND and is also connected to the drain terminal of the PLDMOS transistor LDM0. The source terminal of the PLDMOS transistor LDM0 is connected to the ground terminal of the first oscillator and the low-side ground terminal of the charge pump circuit, and the signal is GND_CP. The output terminal of the first oscillator is connected to the input terminal of the charge pump circuit; The positive terminal of the diode D0 is connected to the high-side floating ground terminal VS, and is also connected to the high-side ground terminal of the charge pump circuit, the ground terminal of the voltage detection circuit, and the high-side ground terminal of the level shifting circuit. The output terminal of the voltage detection circuit is connected to the input terminal of the level shifting circuit; The low-side power supply terminal of the level shifting circuit is connected to the power supply terminal VDD, and the low-side ground terminal is connected to the ground terminal GND.
2. The high-side power supply circuit as described in claim 1, characterized in that, The charge pump circuit includes n signal processing units, n capacitors, and n+1 diodes. The n signal processing units are composed of n1 buffers and n2 inverters, where n1+n2=n, and n1 and n2 are both non-negative integers. All the diodes are connected in series, and a capacitor is connected in parallel between any two adjacent diodes. The output of each buffer or each inverter is connected to one end of a capacitor, and the other end of the capacitor is connected to the two adjacent diodes. When n=1, n1=1 and n2=0 or n1=0 and n2=1, the charge pump circuit includes a buffer BUF1 or an inverter INV1, a capacitor C1, a diode D1, and a diode D2. The input terminal of the buffer BUF1 or the inverter INV1 serves as the input terminal of the charge pump circuit, and the signal is clk. The power supply terminal of the buffer BUF1 or the inverter INV1 serves as the low-side power supply terminal VDD_CP of the charge pump circuit. The ground terminal of the buffer BUF1 or the inverter INV1 serves as the low-side ground terminal GND_CP of the charge pump circuit. The output terminal of the buffer BUF1 or the inverter INV1 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the positive terminal of the diode D1 and the negative terminal of the diode D2. The negative terminal of the diode D1 is connected to the high-side floating power supply terminal VB, serving as the high-side power supply terminal of the charge pump circuit. The positive terminal of the diode D2 is connected to the high-side floating ground terminal VS, serving as the high-side ground terminal of the charge pump circuit. When n≥2, if n is even, then n1=n2; if n is odd, then n1=n2+1 or n1=n2-1. The clock signal of the adjacent capacitors is an inverted signal. The adjacent signal processing units are buffers and inverters, respectively. The input terminals of each signal processing unit are connected in parallel as the input terminals of the charge pump circuit, and the signal is clk. The power supply terminal of the first signal processing unit is the low-side power supply terminal VDD_CP of the charge pump circuit. The negative terminal of the first diode is connected to the high-side floating power supply terminal VB, which is the high-side power supply terminal of the charge pump circuit. The ground terminal of the last signal processing unit is the low-side ground terminal GND_CP of the charge pump circuit. The positive terminal of the last diode is connected to the high-side floating ground terminal VS, which is the high-side ground terminal of the charge pump circuit.
3. The high-side power supply circuit as described in claim 1, characterized in that, The charge pump circuit includes at least one charge pump unit, which includes a buffer BUF1, an inverter INV1, an inverter INV2, an inverter INV3, a capacitor C1, and a capacitor C2. The clock signals of capacitors C1 and C2 are inverted signals. The input terminal of the buffer BUF1 is connected to the input terminal of the inverter INV1, serving as the input terminal of the charge pump unit, and the signal is clk. The output terminal of the buffer BUF1 is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the input terminal of inverter INV2 and the output terminal of inverter INV3. Connections: The output terminal of inverter INV1 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to the output terminal of inverter INV2 and the input terminal of inverter INV3; the power supply terminals of buffer BUF1 and inverter INV1 are connected to the low-side power supply terminal VDD_CP, and the ground terminals of buffer BUF1 and inverter INV1 are connected to the low-side ground GND_CP; the power supply terminals of inverter INV2 and inverter INV3 are connected to the high-side floating power supply terminal VB, and the ground terminals of inverter INV2 and inverter INV3 are connected to the high-side floating ground terminal VS; When the charge pump circuit includes only one charge pump unit: the input terminal of the charge pump unit serves as the input terminal of the charge pump circuit, the power supply terminals of the buffer BUF1 and the inverter INV1 serve as the low-side power supply terminals of the charge pump circuit, the ground terminals of the buffer BUF1 and the inverter INV1 serve as the low-side ground terminals of the charge pump circuit, the power supply terminals of the inverter INV2 and the inverter INV3 serve as the high-side power supply terminals of the charge pump circuit, and the ground terminals of the inverter INV2 and the inverter INV3 serve as the high-side ground terminals of the charge pump circuit; When the charge pump circuit includes two or more charge pump units: the ground terminals of inverters INV2 and INV3 in the previous charge pump unit are connected to the power supply terminals of inverters INV2 and INV3 in the next charge pump unit; The power supply terminals of inverters INV2 and INV3 in the first charge pump unit are connected to the high-side floating power supply terminal VB, serving as the high-side power supply terminal of the charge pump circuit; the ground terminals of inverters INV2 and INV3 in the last charge pump unit are connected to the high-side floating ground terminal VS, serving as the high-side ground terminal of the charge pump circuit; the input terminals of each charge pump unit are connected in parallel as the input terminals of the charge pump circuit; the power supply terminals of buffer BUF1 and inverter INV1 in each charge pump unit are connected in parallel as the low-side power supply terminal of the charge pump circuit, and the ground terminals of buffer BUF1 and inverter INV1 in each charge pump unit are connected in parallel as the low-side ground terminal of the charge pump circuit.
4. The high-side power supply circuit as described in claim 1, characterized in that, Both the first bootstrap circuit and the second bootstrap circuit include any one of the following three types of bootstrap circuits: Bootstrap circuit a includes diode D4; the positive terminal of diode D4 is the input terminal of bootstrap circuit a, and the negative terminal is the output terminal of bootstrap circuit a. Bootstrap circuit b includes diode D5 and junction field-effect transistor J0; the positive terminal of diode D5 is the input terminal of bootstrap circuit b, and the negative terminal is connected to the source terminal of junction field-effect transistor J0; the gate terminal of junction field-effect transistor J0 is grounded, and the drain terminal is the output terminal of bootstrap circuit b. The bootstrap circuit c includes a second oscillator, a buffer BUF2, a capacitor C3, a diode D6, a diode D7, a diode D8, and an NLDMOS transistor LDM3; The power supply terminal of the second oscillator serves as the input terminal of the bootstrap circuit c, connected to the power supply VDD, and connected to the power supply terminal of the buffer BUF2, the positive terminal of the diode D6, and the positive terminal of the diode D7; the output terminal of the second oscillator is connected to the input terminal of the buffer BUF2; the ground terminal of the second oscillator is connected to GND, and connected to the ground terminal of the buffer BUF2. The output terminal of the buffer BUF2 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the negative terminal of the diode D7 and the positive terminal of the diode D8, the negative terminal of the diode D6 is connected to the source terminal of the NLDMOS transistor LDM3, and the gate terminal of the NLDMOS transistor LDM3 is connected to the negative terminal of the diode D8; the drain terminal of the NLDMOS transistor LDM3 is the output terminal of the bootstrap circuit c.
5. The high-side power supply circuit as described in claim 1, characterized in that, The voltage detection circuit includes resistor R1, resistor R2, a reference circuit, and a comparator; One end of resistor R1 is connected to the high-side floating power supply VB, serving as the power supply terminal of the voltage detection circuit, and is also connected to the power supply terminal of the reference circuit and the power supply terminal of the comparator; the other end of resistor R1 is connected to one end of resistor R2 and the non-inverting input terminal of the comparator. The other end of the resistor R2 is connected to the high-side floating ground VS, serving as the ground terminal of the voltage detection circuit, and is also connected to the ground terminal of the reference circuit and the ground terminal of the comparator. The output terminal of the reference circuit is connected to the inverting input terminal of the comparator, and the signal is the reference signal Vref. The output terminal of the comparator is the output terminal of the voltage detection circuit.
6. The high-side power supply circuit as described in claim 1, characterized in that, The level shifting circuit includes PLDMOS transistors LDM4, LLDMOS transistors LDM5, NLDMOS transistors LDM6, NLDMOS transistors LDM7, NMOS transistors M0 and M1, inverter INV4, resistor R3, and buffer BUF3. The source terminal of the PLDMOS transistor LDM4 is connected to the high-side floating power supply VB, and is also connected to the power supply terminal of the inverter INV4 and the source terminal of the PLDMOS transistor LDM5, serving as the high-side power supply terminal of the level shifting circuit; the gate terminal is connected to the output terminal of the inverter INV4; and the drain terminal is connected to the drain terminal of the NLDMOS transistor LDM6. The input terminal of the inverter INV4 is connected to the gate terminal of the PLDMOS transistor LDM5, serving as the input terminal of the level shifting circuit; the ground terminal is connected to the high-side floating ground terminal VS, serving as the high-side ground terminal of the level shifting circuit. The drain terminal of the PLDMOS transistor LDM5 is connected to the drain terminal of the NLDMOS transistor LDM7. The gate terminal of the NLDMOS transistor LDM6 is connected to the power supply VDD, and is also connected to the gate terminal of the NLDMOS transistor LDM7, one end of the resistor R3, and the power supply terminal of the buffer BUF3, serving as the low-side power supply terminal of the level shifting circuit; the source terminal is connected to the drain terminal of the NMOS transistor M0 and the gate terminal of the NMOS transistor M1. The source terminal of the NLDMOS transistor LDM7 is connected to the gate terminal of the NMOS transistor M0, the drain terminal of the NMOS transistor M1, the other end of the resistor R3, and the input terminal of the buffer BUF3. The source terminal of the NMOS transistor M0 is connected to GND, and is also connected to the source terminal of the NMOS transistor M1 and the ground terminal of the buffer BUF3, serving as the low-side ground terminal of the level shifting circuit. The output of the buffer BUF3 serves as the output of the level shifting circuit.
7. A high-side power supply method with constant high-side power supply, characterized in that, The high-side power supply method achieves high-side power supply through any one of the high-side power supply circuits described in claims 1-6.