A driving control method and system for parallel switching speed dynamic adjustment of a power device, and a power conversion device

Abstract

The application discloses a kind of power device parallel switch speed dynamic adjustment driving control method, system and power conversion device, it is related to power electronics technical field.The method is by obtaining the current signal of each parallel power device in switching process, the relative switching delay time between each device is extracted, the driving capacity adjustment signal corresponding to each device is generated accordingly, and then the number of driving resistance accessed by each device, the number of enabled driver and / or driving voltage amplitude are changed, to differentiate the switching speed of each device, reduce the relative switching delay time.The application also provides a corresponding driving control system and power conversion device.The application can effectively eliminate the residual dynamic switching imbalance that conventional parallel current sharing measures cannot solve through current detection→delay statistics→driving capacity quantitative fine-tuning closed-loop control, with the advantages of reliable adjustment, wide adaptability.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a drive control method, system, and power conversion device for dynamically adjusting the parallel switching speed of power devices. Background Technology

[0002] In the field of power electronic converters, the current-carrying capacity of a single power semiconductor device (such as an insulated-gate bipolar transistor (IGBT), a silicon carbide metal-oxide-semiconductor field-effect transistor (SiCMOSFET), or a gallium nitride high electron mobility transistor (GaN HEMT)) is often insufficient to meet the demands of high-power applications. Therefore, multiple power devices are typically connected in parallel to increase the current rating. Such parallel structures are widely used in medium- and high-voltage static var generators (SVG), direct-connected energy storage converters, solid-state transformers (SST), DC transmission and distribution converters, new energy vehicle motor controllers, and rail transit traction converters. Specifically, in cascaded H-bridge (CHB) topologies, multiple transistors are often connected in parallel within each power module to improve current carrying capacity. Similarly, in dual active bridge (DAB) and LLC / CLLC resonant converters, the primary and secondary arms of the high-frequency transformer also require parallel current sharing. In these scenarios, the unbalanced switching of parallel devices not only affects the reliability of individual modules but also, through the cascaded structure, exacerbates the uneven loss and thermal stress concentration of the entire system.

[0003] Currently, conventional measures to address current imbalance in parallel device switching mainly include: device parameter selection and matching (selecting devices with similar threshold voltage, transconductance, input capacitance, etc.), symmetrical power circuit layout (ensuring consistent parasitic inductance in each parallel branch), symmetrical drive circuit design (equal gate trace length and impedance matching), derating, and heat dissipation and temperature equalization design. However, even after implementing all these conventional measures, residual dynamic switching imbalance still exists in actual operation. The root cause is that: temperature gradients cannot be completely eliminated, leading to inconsistent threshold voltage and transconductance drift with temperature for each device; aging drift is time-varying, with different degradation rates for each device; unavoidable slight differences exist between batches, which can still produce significant current imbalance under high-speed switching (especially in SiCMOSFET and GaN HEMT applications); furthermore, dynamic changes in operating conditions such as bus voltage, load current, and switching frequency can alter the degree and direction of residual imbalance, while the aforementioned conventional measures are all static or passive and cannot be adjusted accordingly.

[0004] A search revealed existing patent literature containing parallel current sharing technologies. For example, Chinese patent CN120729265A employs a main-auxiliary dual-branch drive structure, dynamically adjusting the timing of the dual-branch enable using a proportional-integral (PI) algorithm. Another example is Chinese patent CN114362487A, which adjusts the gate drive signal delay by sensing the current difference between the parallel devices at the moment of turn-on. Chinese patent CN117792040A, on the other hand, collects static parameters of the devices and uses a delay controller to generate independent delayed turn-on / turn-off signals. However, these solutions all focus on adjusting the timing delay of the drive signal or continuously changing the gate resistance value, failing to address the issue from the perspective of discrete quantization adjustment of the drive capability. Summary of the Invention

[0005] To address this, embodiments of the present invention provide a drive control method, system, and power conversion device for dynamic adjustment of the parallel switching speed of power devices. This addresses the problems that conventional parallel current sharing measures in the prior art cannot eliminate residual dynamic switching imbalances caused by temperature drift, aging degradation, and changes in operating conditions during operation, as well as the failure of existing active drive schemes to achieve closed-loop adaptive fine-tuning from the perspective of discrete quantitative adjustment of drive capability.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a drive control method for dynamically adjusting the parallel switching speed of power devices, comprising: Acquire the current signal of each power device in a series of power devices connected in parallel during the switching process; Based on the current signals of each power device, the relative switching delay time between each power device is extracted; Based on the relative switching delay time, a drive capability adjustment signal corresponding to each power device is generated; According to the drive capability adjustment signal of each power device, the drive configuration of the power device is changed to adjust the switching speed of the power device, thereby reducing the relative switching delay time between the power devices. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

[0007] Preferably, acquiring the current signal of each power device in the parallel-connected power devices during the switching process includes: The edge of the pulse width modulation signal is used as the trigger signal to collect the current signal of each power device within the time window of the switching transient. The current signal is obtained by at least one of the following methods: a combination of a shunt resistor and an isolation operational amplifier or an isolation ΔΣ modulator, a Rogowski coil, a current transformer, a current detection unit integrated inside the power device, and a di / dt detection method for detecting the voltage across the parasitic inductance of the power circuit.

[0008] Preferably, the extraction of the relative switching delay time between each power device includes: A current threshold is set for the current signal of each power device, and the timestamp of the current signal of each power device crossing the current threshold is recorded. The relative switching delay time of each power device is calculated based on the median of the timestamps or based on the timestamp of a preset reference power device. Alternatively, a current waveform window near the switching transient can be selected, and cross-correlation calculations can be performed on the current waveforms of each power device within the window. The relative switching delay time can be determined based on the peak offset of the cross-correlation function. Alternatively, the derivative of the current signal of each power device can be calculated, and the peak time or zero-crossing time of the derivative can be used as the switching timestamp of each power device. The relative switching delay time can be calculated based on each of the switching timestamps.

[0009] Preferably, it further includes: performing a moving average or low-pass filtering on the relative switching delay time extracted from multiple switching cycles; When the absolute value of the relative switching delay time is less than the preset adjustment threshold, the current driving capability adjustment signal remains unchanged.

[0010] Preferably, the change in the drive configuration of the power device is performed in at least one of the following ways: Method 1: By controlling the on / off state of the controlled switches in multiple parallel resistor branches, the number of connected drive resistors is changed, thereby changing the equivalent gate resistance; the resistance values ​​in the multiple resistor branches are equal, or increase according to binary weights. Method 2: Change the number of enabled drivers by controlling the enable state of multiple drivers connected in parallel; Method 3: The amplitude of the driving voltage applied to the gate of the power device is changed by switching between multiple preset discrete driving voltage levels.

[0011] Preferably, the current distribution of each power device during the conduction steady state is adjusted by changing the amplitude of the driving voltage, and the current distribution of each power device during the switching transient state is adjusted by changing the number of driving resistors and / or the number of drivers. And / or, the switching speed is preferentially adjusted by changing the number of drive resistors and / or the number of drivers, and when the adjustment has reached its limit and the relative switching delay time still exceeds a preset threshold, the amplitude of the drive voltage is further changed.

[0012] This invention also provides a drive control system for dynamically adjusting the parallel switching speed of power devices, comprising: The current detection unit is used to acquire the current signal of each power device in a series of power devices connected in parallel during the switching process. The delay extraction unit, connected to the current detection unit, is used to extract the relative switching delay time between each power device based on the current signal of each power device. A control unit, connected to the delay extraction unit, is used to generate a drive capability adjustment signal for each power device based on the relative switching delay time. A configurable drive unit, connected to the control unit, is used to change the drive configuration of each power device according to the drive capability adjustment signal of each power device, so as to adjust the switching speed of the power device and thereby reduce the relative switching delay time between each power device. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

[0013] Preferably, the configurable drive unit includes: Multiple resistor branches are connected in parallel. Each resistor branch consists of a resistor and a controlled switch connected in series. One end of each resistor branch is connected to the output terminal of the driver, and the other end is connected to the gate of the corresponding power device. The control unit changes the number of connected drive resistors by controlling the on and off of each controlled switch. And / or, multiple drivers connected in parallel, each driver having an independent enable terminal, and the output terminals of all drivers being connected to the gate of the corresponding power device; the control unit changes the number of enabled drivers by controlling the enable state of each driver; And / or a programmable voltage source or a multiplexer, wherein the programmable voltage source provides an adjustable supply voltage to the drivers of each power device, and the multiplexer has multiple preset voltage inputs and a voltage output, the voltage output being connected to the power supply terminal of the corresponding driver for each power device; the control unit changes the amplitude of the drive voltage applied to the gate of the corresponding power device by controlling the output voltage of the programmable voltage source or by controlling the multiplexer to switch between multiple discrete voltage levels.

[0014] This invention also provides a power conversion device, comprising: Multiple power devices connected in parallel; And a drive control system for dynamically adjusting the parallel switching speed of power devices as described above, wherein the drive control system for dynamically adjusting the parallel switching speed of power devices is connected to the gate of each of the power devices and is used to differentiate the switching speed of each of the power devices.

[0015] Preferably, the power conversion device is any one of a static var generator, a direct-connected energy storage converter, a solid-state transformer, a DC power transmission and distribution converter, a frequency converter, a motor controller, an LLC resonant converter, a CLLC resonant converter, an on-board charger, a charging pile, or a photovoltaic inverter. The power device is any one of an insulated gate bipolar transistor, a silicon carbide metal oxide semiconductor field-effect transistor, or a gallium nitride high electron mobility transistor. The plurality of power devices constitute at least one bridge arm of any of the following topologies: cascaded H-bridge topology, dual active bridge topology, LLC resonant converter topology, CLLC resonant converter topology, half-bridge topology, full-bridge topology, three-phase bridge topology, or multi-level topology.

[0016] As can be seen from the above technical solutions, this invention application has the following beneficial effects: This invention detects the current signals of each parallel power device in real time and extracts the relative switching delay time, forming a closed-loop control system of current detection → delay statistics → quantitative fine-tuning of drive capability. This system can automatically adjust the drive capability of each device in response to temperature drift, aging degradation, and changes in operating conditions, effectively eliminating residual dynamic switching imbalances that cannot be resolved by conventional static current sharing measures. Simultaneously, it employs a discrete quantitative adjustment method by increasing or decreasing the number of drive resistors, increasing or decreasing the number of drivers, and / or switching discrete drive voltage levels, avoiding the reliability and temperature drift issues of continuously adjustable schemes, making it more suitable for digital control implementation. Furthermore, this invention complements rather than replaces existing technologies, has a low implementation threshold, a wide range of applications, and can be equipped with device aging trend monitoring functions, improving the long-term reliability and intelligent operation and maintenance level of the system. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Referring to the drawings will make the features and advantages of the present invention clearer. The drawings are illustrative and should not be construed as limiting the present invention in any way. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart of a drive control method for dynamically adjusting the parallel switching speed of power devices provided in an embodiment of the present invention; Figure 2 This is a block diagram of a drive control system for dynamically adjusting the parallel switching speed of power devices, provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that the "power devices" mentioned in the various embodiments of the present invention include, but are not limited to, insulated-gate bipolar transistors (IGBTs), silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), and gallium nitride high electron mobility transistors (GaN HEMTs). The "power conversion devices" include, but are not limited to, static var generators (SVG), direct-connected energy storage converters, solid-state transformers (SSTs), DC transmission and distribution converters, frequency converters, motor controllers, LLC resonant converters, CLLC resonant converters, on-board chargers, charging piles, and photovoltaic inverters. Those skilled in the art should understand that the drive control method and system proposed in this invention are applicable to various power electronic application scenarios requiring parallel operation of power devices.

[0020] The "conventional parallel current sharing measures" described in this invention serve as the first equalization layer, including but not limited to: device parameter screening and matching (selecting devices with similar threshold voltage, transconductance, input capacitance, etc.), symmetrical power circuit layout (ensuring consistent parasitic inductance in each parallel branch), symmetrical drive circuit design (equal gate trace length and impedance matching), derating, and heat dissipation and temperature equalization design. The drive control method and system proposed in this invention serve as the second equalization layer, superimposed on the first equalization layer, to eliminate residual dynamic switching imbalances that the first equalization layer cannot resolve.

[0021] Example 1: To address the shortcomings of conventional parallel current sharing measures in existing technologies, which fail to eliminate residual dynamic switching imbalances caused by temperature drift, aging degradation, and changes in operating conditions during operation, and the limitations of existing active drive schemes in achieving closed-loop adaptive fine-tuning from the perspective of discrete quantization adjustment of drive capability, this invention proposes a drive control method for dynamically adjusting the parallel switching speed of power devices. Figure 1 As shown, the method includes the following steps: S1: Acquire the current signal of each power device in the parallel connection during the switching process; S2: Extract the relative switching delay time between each power device based on the current signal of each power device; S3: Generate driving capability adjustment signals for each power device based on the relative switching delay time; S4: Adjust the drive configuration of each power device according to the drive capability adjustment signal of each power device to adjust the switching speed of the power device, thereby reducing the relative switching delay time between each power device. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

[0022] As can be seen from the above technical solution, this invention proposes a drive control method for dynamically adjusting the switching speed of parallel power devices. First, by acquiring the current signals of each parallel power device during the switching process, a real-time and accurate raw data foundation is provided for subsequent delay analysis, thereby capturing the behavioral differences of each device in the switching transient. Then, based on the current signals of each device, the relative switching delay time between them is extracted, and the raw current waveform is transformed into a delay deviation index that quantitatively characterizes the degree of asynchronous switching of each device, providing a direct basis for differentiated adjustment. Next, based on the extracted relative switching delay time, a corresponding drive capability adjustment signal for each device is generated, clarifying whether each device needs to accelerate or decelerate and the required adjustment direction and magnitude, thereby achieving targeted control command output. Finally, based on the drive capability adjustment signal of each device, the number of drive resistors connected to the device, the number of enabled drivers, and / or the drive voltage amplitude, etc., are changed to differentiate the switching speed of each device in a discrete quantization manner, forming a complete closed loop from detection to execution, thereby effectively eliminating the relative switching delay time between each parallel power device and achieving synchronous optimization of the switching transient.

[0023] Further, in step S1, the current signal of each power device in the multiple power devices connected in parallel during the switching process is acquired.

[0024] Specifically, each parallel power device is configured with an independent current detection channel to acquire the current signal of each power device during the switching process. The switching process includes the turn-on transient and / or turn-off transient of the power devices.

[0025] Regarding the selection of detection timing, this invention uses the edge of a pulse width modulation (PWM) signal as a trigger signal to acquire the current signal of each power device within the time window of the switching transient. Specifically, the rising edge of the PWM signal is used as the trigger signal for the turn-on transient, and high-speed analog-to-digital converter (ADC) sampling is initiated within a preset time window after the rising edge; the falling edge of the PWM signal is used as the trigger signal for the turn-off transient, and high-speed ADC sampling is initiated within a preset time window after the falling edge. The duration of the time window is preset according to the switching speed of the power device. For example, for SiC MOSFET devices, the switching transient is typically in the range of tens to hundreds of nanoseconds, so the acquisition window can be set to 100ns~500ns; for IGBT devices, the acquisition window can be set to 500ns~2μs. By adopting a trigger-based acquisition method, high-speed sampling is performed only during the switching transient, avoiding the problems of large data volume and heavy processing burden caused by continuous high-speed sampling.

[0026] Regarding the detection method of current signal, the present invention can adopt various implementation schemes, including but not limited to the following: Method 1: Combination of shunt resistors with isolated operational amplifiers or isolated ΔΣ modulators. A shunt resistor is connected in series in the power circuit of each power device (e.g., at the emitter or source). After converting the current signal into a voltage signal, it is conditioned and isolated by an isolated operational amplifier or isolated ΔΣ modulator before being sent to the control unit for sampling. This method offers advantages such as high accuracy and low cost, and is particularly suitable for applications with small to medium power ratings (≤ tens of kW).

[0027] Method 2: Rogowski Coil. A Rogowski coil is placed in the power circuit of each power device. The rate of change of current, di / dt, is measured using the Rogowski coil, and then converted back to a current signal via an integrator. This method offers advantages such as non-invasiveness and good high-frequency response, making it particularly suitable for medium to high power applications and high-frequency switching scenarios.

[0028] Method 3: Current Transformer (CT). Current transformers are installed in the power circuits of each power device to obtain current signals using the principle of mutual inductance. This method offers good isolation performance and is suitable for medium-power, medium-frequency applications.

[0029] Method 4: Current sensing unit integrated within the power device. This method utilizes a SenseFET or current mirror structure integrated within the power device to directly obtain the current sensing signal from within the device. It offers advantages such as high integration and fast response, making it particularly suitable for scenarios involving integration within power modules, especially SiC MOSFET and GaN HEMT modules.

[0030] Method 5: Detection of the di / dt voltage across the parasitic inductance in the power circuit. This method utilizes the parasitic inductance present in the power circuit of the power device to detect the voltage across the parasitic inductance (V=L·di / dt), thereby obtaining a signal reflecting the rate of change of current. This method has the advantages of being non-invasive and having zero additional loss, making it suitable for compact layouts and high-frequency applications.

[0031] Furthermore, in step S2, the relative switching delay time between each power device is extracted based on the current signal of each power device.

[0032] Specifically, the relative switching delay time is extracted from the current waveforms of each power device obtained in step S1. This invention provides various delay extraction algorithms, including but not limited to the following: Method 1: Current Threshold Crossover Method. A current threshold is set for the current signal of each power device. (For example, 5% to 10% of the rated current), record the timestamps of the current signals of each power device crossing this current threshold. Specifically, for the turn-on transient, the current in each transistor is recorded as it rises from zero and crosses... At the moment of shutdown; for the turn-off transient, record the current drop and its crossing of each transistor. The time is determined. Then, using the median of the timestamps or a preset reference power device timestamp as a reference, the relative switching delay time of each power device is calculated: (in (This can be the median timestamp or a preset reference device timestamp). The advantage of using the median as the reference is that it avoids the impact of a certain extreme delay value on the overall reference, thus exhibiting better robustness.

[0033] Method 2: Cross-Correlation. A current waveform window near the switching transient is selected (e.g., a window of 100ns to 500ns before and after the PWM edge). Cross-correlation is performed on the current waveforms of each power device within this window. Specifically, the current waveform of one power device is used as a reference waveform. Cross-correlation is performed on the current waveforms of other power devices against the reference waveform. The offset corresponding to the peak value of the cross-correlation function is the relative delay time of that power device relative to the reference device. Cross-correlation effectively suppresses noise interference and has higher accuracy when the signal-to-noise ratio of the current waveform is low.

[0034] Method 3: di / dt zero-crossing or extreme value detection method. Calculate the derivative di / dt of the current signal for each power device. In the switching transient, the peak value or zero-crossing moment of di / dt corresponds to the moment of fastest switching speed. Specifically, for the turn-on transient, the peak value of di / dt corresponds to the moment of greatest current change rate, i.e., the moment the device is fully turned on; for the turn-off transient, the zero-crossing moment of di / dt corresponds to the moment the current begins to decrease. Use this moment as the switching timestamp for each power device, and calculate the relative switching delay time based on each switching timestamp.

[0035] Method 4: Integral Energy Method. Integrate the current of each power device within the switching transient window to obtain the electrical charge passing through each device during the switching process. The switching delay is indirectly reflected by comparing the integral values ​​of each device. A larger integral value usually means that the device turns on earlier or turns off later. This method is insensitive to high-frequency noise in the current waveform and has a good smoothing effect.

[0036] To further improve the accuracy and stability of delay extraction, this invention also performs moving average or low-pass filtering on the relative switching delay times extracted from multiple switching cycles. For example, the sliding window length can be set to N switching cycles (N can be set to 8, 16, or 32 according to actual needs), and the delay data within the window can be arithmetically averaged or weighted averaged to suppress single-cycle measurement noise and random interference.

[0037] Furthermore, this invention incorporates a dead time delay. When the absolute value of the relative switching delay time of a power device is less than a preset adjustment threshold (e.g., a delay deviation of less than 2ns to 5ns), the current drive capability adjustment signal remains unchanged, and no adjustment action is triggered. The dead time delay prevents the system from frequently switching drive configurations under minute fluctuations, avoiding unnecessary switching actions that could lead to additional losses and electromagnetic interference.

[0038] Furthermore, in step S3, a drive capability adjustment signal corresponding to each power device is generated based on the relative switching delay time.

[0039] Specifically, based on the relative switching delay times of each power device obtained in step S2, a drive capability adjustment signal corresponding to each power device is generated according to a preset control logic. The core control logic is as follows: For each parallel device i: like If the value is greater than +Threshold (indicating that the switching of device i lags behind the reference), an adjustment signal is generated to enhance the driving capability of device i and accelerate its switching. like < Threshold (indicating that the switching of device i is ahead of the reference) generates an adjustment signal to reduce the driving capability of device i, thereby slowing down its switching. like If the value is less than or equal to Threshold (indicating that the switching synchronization of device i has met the requirements), then the current configuration will remain unchanged and no new adjustment signal will be generated.

[0040] Regarding the control of the adjustment step size, this invention changes only one driving resistor, one driver, or one driving voltage level each time. After waiting for a preset number of switching cycles (e.g., 8-16 switching cycles), it determines whether to perform the next adjustment based on the updated relative switching delay time. This small-step, multi-step adjustment strategy avoids over-adjustment and system oscillation caused by excessively large one-time adjustments.

[0041] Regarding the control of adjustment priorities, this invention can simultaneously adjust the device with the largest delay and the device with the smallest delay (one is accelerated and the other is decelerated) to reduce the overall imbalance as quickly as possible. The convergence speed of this bidirectional adjustment strategy is significantly better than that of the unidirectional strategy of adjusting only the worst device.

[0042] Furthermore, this invention supports multi-objective optimization adjustment. In addition to delay deviation, it can also comprehensively consider the junction temperature information of each power device (if a temperature detection unit is present), prioritizing the protection of the device with the highest temperature. Specifically, when the junction temperature of a certain power device is significantly higher than that of other devices, the control algorithm can appropriately relax the switching delay requirement for that device, or even actively allow it to lag slightly to reduce its switching losses, thereby achieving thermal-electric joint optimization.

[0043] When the driving capability of a power device has been adjusted to the maximum or minimum limit, but the relative switching delay time still exceeds the preset threshold, the control unit reports an abnormal alarm signal, indicating that the device may be damaged or aging beyond the limit, so that maintenance personnel can handle it in a timely manner.

[0044] Furthermore, in step S4, the drive configuration of each power device is changed according to the drive capability adjustment signal of each power device to adjust the switching speed of the power device, thereby reducing the relative switching delay time between each power device.

[0045] Specifically, the drive configuration of each power device is adjusted differently based on the drive capability adjustment signal generated in step S3. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

[0046] This invention provides the following three independent adjustment methods, which can be used individually or in any combination: Method 1: By controlling the on / off state of the controlled switches in multiple parallel resistor branches, the number of connected drive resistors is changed, thereby changing the equivalent gate resistance.

[0047] Specifically, multiple resistor branches are connected in parallel between the output of the driver and the gate of the power device. Each resistor branch consists of a resistor and a controlled switch connected in series. One end of each resistor branch is connected to the output of the driver, and the other end is connected to the gate of the corresponding power device. The controlled switch can be implemented using a small-signal MOSFET or an analog switch, and its on / off state is controlled by a switch control signal output from the control unit.

[0048] When the control unit closes the controlled switches in more resistor branches, the number of resistor branches connected in parallel increases, and the equivalent gate resistance decreases (in the case of equivalent resistance, Req=Rg / ,in The number of closed resistive branches increases the driving capability and speeds up the switching process. Conversely, when the control unit closes the controlled switches in fewer resistive branches, the number of parallel-connected resistive branches decreases, the equivalent gate resistance increases, the driving capability weakens, and the switching speed slows down.

[0049] Regarding the selection of values ​​for multiple resistor branches, the present invention can adopt the following two schemes: (1) The resistance values ​​in each resistor branch are equal, which results in good linearity of adjustment and the equivalent resistance is inversely proportional to the number of connected resistors; (2) The resistance values ​​in each resistor branch are increased according to binary weight (e.g., R, 2R, 4R, 8R...), which allows for more equivalent resistance levels to be achieved with fewer switches, which helps to reduce hardware costs and PCB area.

[0050] Method 2: Change the number of enabled drivers by controlling the enable state of multiple drivers connected in parallel.

[0051] Specifically, multiple drivers are configured in parallel for each power device, each driver having an independent enable terminal (EN), and the output terminals of all drivers are connected to the gate of the corresponding power device. The control unit controls the enable state of each driver through its enable terminal.

[0052] When the control unit enables more drivers, the number of enabled drivers increases, which not only reduces the equivalent gate resistance (due to the parallel connection of the internal output resistances of each driver) but also increases the peak drive current capability, making it particularly effective for driving high-power devices. Conversely, when the control unit disables some drivers, the number of enabled drivers decreases, and the driving capability weakens.

[0053] Method 2 can be used in combination with Method 1, meaning that a resistor network can still be configured at the output of each driver to achieve a wider range of drive capability adjustment.

[0054] Method 3: The amplitude of the driving voltage applied to the gate of the power device is changed by switching between multiple preset discrete driving voltage levels.

[0055] Specifically, the driver's supply voltage can be switched between multiple discrete drive voltage levels via a programmable voltage source or a multiplexer. For example, for SiC MOSFET devices, three voltage levels can be set: 15V, 12V, and 9V; for IGBT devices, three voltage levels can be set: 20V, 17V, and 15V.

[0056] The adjustment logic is as follows: Increasing the drive voltage amplitude increases the gate charging / discharging current, accelerates the gate voltage rise / fall rate, and speeds up the switching speed; simultaneously, it reduces the on-resistance Rdson during conduction, which helps improve static current sharing. Decreasing the drive voltage amplitude decreases the gate charging / discharging current, slows down the gate voltage rise / fall rate, and slows down the switching speed; simultaneously, it increases the on-resistance Rdson during conduction.

[0057] The adjustment of the driving voltage affects both dynamic current sharing (current distribution during switching transients) and static current sharing (current distribution during conduction steady state), making it particularly suitable for power module scenarios that are on for extended periods (such as CHB cascaded power modules).

[0058] When the three methods are used in combination, the present invention also provides the following synergistic strategy: Voltage-resistor division of labor strategy. The current distribution among power devices during the steady-state conduction period is adjusted by changing the amplitude of the drive voltage (static current sharing), while the current distribution among power devices during the transient switching period is adjusted by changing the number of drive resistors and / or drivers (dynamic current sharing). Both work together to achieve optimized current sharing throughout the entire time period.

[0059] Prioritization strategy. The switching speed is initially adjusted by changing the number of drive resistors and / or drivers. When the adjustment reaches its limit (e.g., all resistor branches are on or all drivers are enabled, but the relative switching delay time still exceeds a preset threshold), the magnitude of the drive voltage is further changed. This prioritization strategy allows the drive voltage to be used as a last resort, avoiding the potential impact of frequent drive voltage adjustments on the reliability of the device's gate oxide layer.

[0060] As can be seen from the above technical solutions, this invention proposes a drive control method for dynamically adjusting the switching speed of parallel power devices. This method detects the current signal of each parallel power device in real time, extracts the switching delay time, and dynamically adjusts the driving capability of each device through discrete quantization (increasing or decreasing the number of drive resistors, increasing or decreasing the number of drivers, and switching the drive voltage level). This forms a closed-loop control of current detection → delay statistics → quantitative fine-tuning of driving capability, effectively eliminating residual dynamic switching imbalances that cannot be resolved by conventional parallel current sharing measures.

[0061] Example 2: This embodiment provides a drive control system for dynamically adjusting the speed of parallel switching of power devices. For example... Figure 2 As shown, the system is used to implement the drive control method for dynamic adjustment of the parallel switching speed of power devices as described in Embodiment 1, and specifically includes: a current detection unit, a delay extraction unit, a control unit, and a configurable drive unit.

[0062] The current sensing unit is used to acquire the current signal of each of the multiple power devices connected in parallel during the switching process. Each parallel power device is configured with an independent current sensing channel. Each channel can employ one or more of the following methods: a combination of shunt resistor and isolation operational amplifier or isolated ΔΣ modulator, Rogowski coil, current transformer, current sensing unit integrated within the power device (SenseFET or current mirror), and di / dt detection method that detects the voltage across the parasitic inductance of the power circuit. The current sensing unit uses the edge of the PWM signal as a trigger signal to perform high-speed sampling within the switching transient time window and transmits the sampled current signal to the delay extraction unit.

[0063] The delay extraction unit, connected to the current detection unit, is used to extract the relative switching delay time between each power device based on the current signal of each power device. The delay extraction unit can be implemented using a field-programmable gate array (FPGA) or a digital signal processor (DSP), and integrates a delay extraction algorithm module. The delay extraction unit can use any one or more combinations of the following methods to extract the relative switching delay time: current threshold crossing method, cross-correlation method, di / dt zero-crossing or extreme value detection method, and integral energy method. The delay extraction unit also performs moving average or low-pass filtering on the relative switching delay times extracted over multiple switching cycles, and transmits the processed delay time data to the control unit.

[0064] The control unit, connected to the delay extraction unit, generates drive capability adjustment signals for each power device based on the relative switching delay time. The control unit can be implemented using at least one of an FPGA, DSP, microcontroller (MCU), or application-specific integrated circuit (ASIC). The control unit integrates a control algorithm module, whose core control logic is as follows: for each parallel device, when the relative switching delay time exceeds a preset positive threshold, an adjustment signal to enhance drive capability is generated; when the relative switching delay time is below a preset negative threshold, an adjustment signal to weaken drive capability is generated; when the relative switching delay time is within the dead zone, the current configuration remains unchanged. The control unit also features adjustment step size limits and adjustment priority management functions, and transmits the generated drive capability adjustment signals to the configurable drive unit.

[0065] Optionally, the system in this embodiment may further include a temperature detection unit for acquiring junction temperature information of each power device. The temperature detection unit may be implemented using an NTC thermistor, a PTC thermistor, or a temperature-sensing diode. The temperature detection unit transmits the junction temperature information of each power device to the control unit, and the control unit generates a drive capability adjustment signal based on the junction temperature information and the relative switching delay time, thereby achieving thermal-electric joint optimization.

[0066] A configurable drive unit, connected to a control unit, is used to adjust the drive configuration of each power device according to the drive capability adjustment signal of each power device, thereby adjusting the switching speed of the power device and reducing the relative switching delay time between the power devices. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

[0067] The configurable drive unit specifically includes at least one of the following structures: (1) Switchable parallel resistor network. This includes multiple resistor branches connected in parallel, each consisting of a resistor and a controlled switch connected in series. One end of each resistor branch is connected to the output of the driver, and the other end is connected to the gate of the corresponding power device. The control unit changes the number of connected drive resistors by controlling the on / off state of each controlled switch, thereby changing the equivalent gate resistance. The resistance values ​​in the multiple resistor branches can be equal or increase according to binary weights.

[0068] (2) Selectively Enabled Parallel Driver Array. This includes multiple drivers connected in parallel, each driver having an independent enable terminal, and the output terminals of all drivers being connected to the gate of the corresponding power device. The control unit changes the number of enabled drivers by controlling the enable state of each driver.

[0069] (3) Adjustable drive voltage source. This includes a programmable voltage source or a multiplexer. The programmable voltage source provides an adjustable supply voltage to the drivers of each power device; the multiplexer has multiple preset voltage inputs and one voltage output, which is connected to the power supply terminal of the corresponding driver for each power device. The control unit changes the amplitude of the drive voltage applied to the gate of the corresponding power device by controlling the output voltage of the programmable voltage source or by controlling the multiplexer to switch between multiple discrete voltage levels.

[0070] Preferably, the configurable drive unit includes all three structures mentioned above to achieve flexible combination and synergistic optimization of the three adjustment dimensions.

[0071] This embodiment provides a drive control system for dynamically adjusting the parallel switching speed of power devices, used to implement the aforementioned drive control method for dynamically adjusting the parallel switching speed of power devices. Therefore, the specific implementation of the drive control system for dynamically adjusting the parallel switching speed of power devices can be found in the embodiment section of the drive control method for dynamically adjusting the parallel switching speed of power devices above. To avoid redundancy, it will not be repeated here.

[0072] Example 3: This embodiment provides a power conversion device, including: multiple power devices connected in parallel, and a drive control system for dynamically adjusting the parallel switching speed of the power devices as described in Embodiment 2. The drive control system is connected to the gate of each power device and is used to differentiate the switching speed of each power device.

[0073] Specifically, multiple power devices are connected in parallel to form a power switching unit for at least one bridge arm of the power conversion device. The gate of each power device is connected to the corresponding output terminal of the configurable drive unit of the drive control system, and a corresponding detection channel of the current detection unit is provided in the power circuit of each power device.

[0074] The power conversion device can be any of the following: static var generator (SVG), direct-connected energy storage converter, solid-state transformer (SST), DC power transmission and distribution converter, frequency converter, motor controller, LLC resonant converter, CLLC resonant converter, on-board charger, charging pile, or photovoltaic inverter.

[0075] The power device can be any of the following: insulated gate bipolar transistor (IGBT), silicon carbide metal oxide semiconductor field-effect transistor (SiC MOSFET), or gallium nitride high electron mobility transistor (GaN HEMT).

[0076] The plurality of power devices can form at least one bridge arm of any of the following topologies: cascaded H-bridge (CHB) topology, dual active bridge (DAB) topology, LLC resonant converter topology, CLLC resonant converter topology, half-bridge topology, full-bridge topology, three-phase bridge topology, or multi-level topology.

[0077] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A drive control method for dynamically adjusting the parallel switching speed of power devices, characterized in that, include: Acquire the current signal of each power device in a series of power devices connected in parallel during the switching process; Based on the current signals of each power device, the relative switching delay time between each power device is extracted; Based on the relative switching delay time, a drive capability adjustment signal corresponding to each power device is generated; According to the drive capability adjustment signal of each power device, the drive configuration of the power device is changed to adjust the switching speed of the power device, thereby reducing the relative switching delay time between the power devices. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

2. The drive control method for dynamically adjusting the parallel switching speed of power devices according to claim 1, characterized in that, The acquisition of the current signal of each power device in the parallel-connected power devices during the switching process includes: The edge of the pulse width modulation signal is used as the trigger signal to collect the current signal of each power device within the time window of the switching transient. The current signal is obtained by at least one of the following methods: a combination of a shunt resistor and an isolation operational amplifier or an isolation ΔΣ modulator, a Rogowski coil, a current transformer, a current detection unit integrated inside the power device, and a di / dt detection method for detecting the voltage across the parasitic inductance of the power circuit.

3. The drive control method for dynamically adjusting the parallel switching speed of power devices according to claim 1, characterized in that, The extraction of the relative switching delay time between each power device includes: A current threshold is set for the current signal of each power device, and the timestamp of the current signal of each power device crossing the current threshold is recorded. The relative switching delay time of each power device is calculated based on the median of the timestamps or based on the timestamp of a preset reference power device. Alternatively, a current waveform window near the switching transient can be selected, and cross-correlation calculations can be performed on the current waveforms of each power device within the window. The relative switching delay time can be determined based on the peak offset of the cross-correlation function. Alternatively, the derivative of the current signal of each power device can be calculated, and the peak time or zero-crossing time of the derivative can be used as the switching timestamp of each power device. The relative switching delay time can be calculated based on each of the switching timestamps.

4. The drive control method for dynamically adjusting the parallel switching speed of power devices according to claim 1, characterized in that, Also includes: The relative switching delay time extracted from multiple switching cycles is subjected to moving average or low-pass filtering. When the absolute value of the relative switching delay time is less than the preset adjustment threshold, the current driving capability adjustment signal remains unchanged.

5. The drive control method for dynamically adjusting the parallel switching speed of power devices according to claim 1, characterized in that, The change in the drive configuration of the power device is made in at least one of the following ways: Method 1: By controlling the on / off state of the controlled switches in multiple parallel resistor branches, the number of connected drive resistors is changed, thereby changing the equivalent gate resistance; the resistance values ​​in the multiple resistor branches are equal, or increase according to binary weights. Method 2: Change the number of enabled drivers by controlling the enable state of multiple drivers connected in parallel; Method 3: The amplitude of the driving voltage applied to the gate of the power device is changed by switching between multiple preset discrete driving voltage levels.

6. The drive control method for dynamically adjusting the parallel switching speed of power devices according to claim 1, characterized in that, The current distribution of each power device during the conduction steady state is adjusted by changing the magnitude of the drive voltage, and the current distribution of each power device during the switching transient state is adjusted by changing the number of drive resistors and / or the number of drivers. And / or, the switching speed is preferentially adjusted by changing the number of drive resistors and / or the number of drivers, and when the adjustment has reached its limit and the relative switching delay time still exceeds a preset threshold, the amplitude of the drive voltage is further changed.

7. A drive control system for dynamically adjusting the speed of parallel switching of power devices, characterized in that, include: The current detection unit is used to acquire the current signal of each power device in a series of power devices connected in parallel during the switching process. The delay extraction unit, connected to the current detection unit, is used to extract the relative switching delay time between each power device based on the current signal of each power device. A control unit, connected to the delay extraction unit, is used to generate a drive capability adjustment signal for each power device based on the relative switching delay time. A configurable drive unit, connected to the control unit, is used to change the drive configuration of each power device according to the drive capability adjustment signal of each power device, so as to adjust the switching speed of the power device and thereby reduce the relative switching delay time between each power device. The drive configuration includes at least one of the following: the number of drive resistors connected to the power device, the number of drivers enabled by the power device, and the amplitude of the drive voltage applied to the gate of the power device.

8. The drive control system for dynamic adjustment of parallel switching speed of power devices according to claim 7, characterized in that, The configurable drive unit includes: Multiple resistor branches are connected in parallel. Each resistor branch consists of a resistor and a controlled switch connected in series. One end of each resistor branch is connected to the output terminal of the driver, and the other end is connected to the gate of the corresponding power device. The control unit changes the number of connected drive resistors by controlling the on and off of each controlled switch. And / or, multiple drivers connected in parallel, each driver having an independent enable terminal, and the output terminals of all drivers being connected to the gate of the corresponding power device; the control unit changes the number of enabled drivers by controlling the enable state of each driver; And / or a programmable voltage source or a multiplexer, wherein the programmable voltage source provides an adjustable supply voltage to the drivers of each power device, and the multiplexer has multiple preset voltage inputs and a voltage output, the voltage output being connected to the power supply terminal of the corresponding driver for each power device; the control unit changes the amplitude of the drive voltage applied to the gate of the corresponding power device by controlling the output voltage of the programmable voltage source or by controlling the multiplexer to switch between multiple discrete voltage levels.

9. A power conversion device, characterized in that, include: Multiple power devices connected in parallel; And a drive control system for dynamically adjusting the parallel switching speed of power devices as described in claim 7 or 8, wherein the drive control system for dynamically adjusting the parallel switching speed of power devices is connected to the gate of each of the power devices and is used to differentiate the switching speed of each of the power devices.

10. The power conversion device according to claim 9, characterized in that, The power conversion device is any one of the following: static var generator, direct-connected energy storage converter, solid-state transformer, DC power transmission and distribution converter, frequency converter, motor controller, LLC resonant converter, CLLC resonant converter, on-board charger, charging pile, or photovoltaic inverter. The power device is any one of an insulated gate bipolar transistor, a silicon carbide metal oxide semiconductor field-effect transistor, or a gallium nitride high electron mobility transistor. The plurality of power devices constitute at least one bridge arm of any of the following topologies: cascaded H-bridge topology, dual active bridge topology, LLC resonant converter topology, CLLC resonant converter topology, half-bridge topology, full-bridge topology, three-phase bridge topology, or multi-level topology.

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