A ripple generating circuit and a switching converter

Abstract

Embodiments of the present application provide a ripple generation circuit and a switching converter. The circuit includes a switching module, an energy storage filter module and a level lifting module. The switching module outputs a first voltage in response to an inverted control signal output by an RS flip-flop, and a high level of the first voltage is equal to an output voltage of the switching converter; the energy storage filter module charges and filters the first voltage at a high level to output a second voltage, and discharges the first voltage at a low level to make the second voltage drop; and the level lifting module outputs a third voltage which is a sum of the second voltage and a threshold voltage, and sends the third voltage to a comparator for comparison with an error signal. In this way, the present application can obtain a ripple signal for determining a turn-off time without sampling an inductor current, the ripple signal is not restricted by the inductor current, and the ripple signal can continue to drop when the inductor current is discontinuous, so that the main loop can continue to extend the turn-off time of a power switch.

Description

Technical Field

[0001] This application relates to the field of voltage conversion technology, and in particular to a ripple generation circuit and a switching converter. Background Technology

[0002] Switching converters typically employ constant on-time control, where the on-time of the power switch remains constant, and the output voltage is adjusted by regulating the off-time. This control method relies on a sufficiently large ripple in the output voltage to maintain loop stability; in early designs, this ripple was generated by the equivalent series resistance of the output capacitor. However, with the increasing demand for miniaturization in switching converters, ceramic capacitors with very low equivalent series resistance are widely used, making it impossible for them to generate sufficient ripple at the output to maintain loop stability.

[0003] To maintain loop stability under low equivalent series resistance conditions, existing technologies employ a constant on-time control topology based on valley current mode. This involves sampling the inductor current through a current sampling circuit to obtain a sampling voltage carrying inductor current information. The sampling voltage is then compared with the error signal output by the constant voltage loop. When the sampling voltage drops to the error signal level, the power switch is turned on, thereby achieving closed-loop control of the power switch's off-time.

[0004] The main problem with the above topology is that the sampled voltage is obtained by sampling the inductor current, and its decrease is limited by the inductor current. When the load decreases and the inductor current drops to zero, and the switching converter enters an intermittent inductor current operating state, the inductor current cannot continue to decrease, and the sampled voltage also cannot continue to decrease. Therefore, it is impossible to further extend the turn-off time of the power switch by extending the time required for the sampled voltage to drop to the error signal. The main loop loses its ability to continue to reduce the duty cycle, and the output voltage is raised. To address this, existing technologies have to introduce an additional pulse frequency modulation loop to manage the frequency regulation under light load conditions. This not only occupies additional circuit area but also causes output voltage jumps due to the switching of operating modes, and leads to a significant increase in output voltage ripple when the load is further reduced. Summary of the Invention

[0005] This application aims to solve the problem in the prior art that the sampling voltage is limited by the inductor current and cannot continue to decrease when the inductor current is discontinuous.

[0006] In a first aspect, this application provides a ripple generation circuit for a switching converter including a constant voltage loop, a comparator, and an RS flip-flop. The RS flip-flop outputs a control signal and an inverted control signal that is opposite to the control signal. The output terminal of the constant voltage loop outputs an error signal. The non-inverting input terminal of the comparator is connected to the output terminal of the constant voltage loop. The output terminal of the comparator outputs a set signal and is connected to the set terminal of the RS flip-flop. The ripple generation circuit includes a switching module, an energy storage and filtering module, and a level boosting module. The switching module is configured to output a first voltage in response to the inverting control signal; when the inverting control signal is low, the first voltage is high, and the high-level first voltage is equal to the output voltage of the switching converter; when the inverting control signal is high, the first voltage is low. The input terminal of the energy storage filter module is connected to the output terminal of the switching module. The energy storage filter module is configured to charge and filter in response to a high-level first voltage and output a second voltage; and to discharge in response to a low-level first voltage to cause the second voltage to drop. The input terminal of the level-up module is connected to the output terminal of the energy storage filter module, and the output terminal of the level-up module is connected to the inverting input terminal of the comparator. The level-up module is configured to output a third voltage in response to the second voltage; the third voltage is the sum of the second voltage and the threshold voltage.

[0007] Optionally, the switching module includes a first switching transistor and a second switching transistor; The gate of the first switch receives the inverted control signal, the source of the first switch is connected to the output terminal of the switching converter, and the drain of the first switch serves as the output terminal of the switching module. The gate of the second switch receives the inverted control signal, the source of the second switch is grounded, and the drain of the second switch is connected to the drain of the first switch.

[0008] Optionally, the first switching transistor is a P-channel MOSFET, and the second switching transistor is an N-channel MOSFET.

[0009] Optionally, the energy storage and filtering module includes a voltage divider unit and an energy storage and filtering unit; The input terminal of the voltage divider unit is connected to the output terminal of the switching module, and the voltage divider unit is configured to output a divided voltage in response to the first voltage; The input terminal of the energy storage filter unit is connected to the output terminal of the voltage divider unit, and the output terminal of the energy storage filter unit is connected to the input terminal of the level rise module. The energy storage filter unit is configured to charge and filter in response to a high-level voltage divider voltage to output the second voltage; and to discharge in response to a low-level voltage divider voltage to cause the second voltage to drop.

[0010] Optionally, the voltage divider unit includes a first voltage divider resistor and a second voltage divider resistor; The first end of the first voltage divider resistor is connected to the output end of the switching module, the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor and the input end of the energy storage filter unit, and the second end of the second voltage divider resistor is grounded.

[0011] Optionally, the energy storage filter unit includes a filter resistor and a filter capacitor; The first end of the filter resistor is connected to the second end of the first voltage divider resistor, the second end of the filter resistor is connected to the first end of the filter capacitor and the input end of the level boosting module, and the second end of the filter capacitor is grounded.

[0012] Optionally, the resistance of the filter resistor is greater than the resistance of the first voltage divider resistor, and the resistance of the filter resistor is greater than the resistance of the second voltage divider resistor.

[0013] Optionally, the average value of the second voltage is equal to the product of the duty cycle of the control signal, the output voltage of the switching converter, and the ratio of the resistance of the second voltage divider resistor to the sum of the resistances of the first voltage divider resistor and the second voltage divider resistor.

[0014] Optionally, the level-up module includes a follower transistor and a bias current source; The follower transistor is a P-channel field-effect transistor. The gate of the follower transistor serves as the input terminal of the level-up module, the drain of the follower transistor is grounded, and the source of the follower transistor serves as the output terminal of the level-up module. One end of the bias current source is connected to the power supply, and the other end of the bias current source is connected to the source and substrate of the follower transistor. The third voltage is the sum of the second voltage and the threshold voltage of the follower transistor.

[0015] In a second aspect, this application also provides a switching converter, including an inductor, a first power switch, a second power switch, a constant voltage loop, a comparator, an RS flip-flop, an on-time control module, a drive module, and a ripple generation circuit as described in the first aspect; The first end of the inductor is connected to the input power supply; The first power switch is connected between the second terminal of the inductor and ground, and the source of the second power switch is connected to the second terminal of the inductor. The source of the second power switch serves as the output terminal of the switching converter. The input terminal of the constant voltage loop is connected to the output terminal of the switching converter, the output terminal of the constant voltage loop outputs an error signal, and the output terminal of the constant voltage loop is connected to the non-inverting input terminal of the comparator. The first input terminal of the ripple generation circuit is connected to the inverted output terminal of the RS flip-flop, the second input terminal of the ripple generation circuit is connected to the output terminal of the switching converter, and the output terminal of the ripple generation circuit is connected to the inverted input terminal of the comparator. The comparator outputs a set signal, and the output of the comparator is connected to the set terminal of the RS flip-flop. The output of the on-time control module is connected to the reset terminal of the RS flip-flop. The RS flip-flop outputs a control signal, and its inverted output outputs an inverted control signal that is opposite to the control signal. The output of the RS flip-flop is connected to the input of the drive module, and the output of the drive module is connected to the control terminals of the first power switch and the second power switch.

[0016] At least one advantage of the ripple generation circuit and switching converter provided in this application embodiment is that: the output voltage of the switching converter is chopped into a first voltage by the switching module, a second voltage is obtained by the energy storage filter module through charging and discharging filtering, and a third voltage is obtained by the level rise module after raising the threshold voltage and sending it to the comparator. Thus, a ripple signal for determining the turn-off time of the power switch is obtained without sampling the inductor current. Since the third voltage is derived from the output voltage rather than the inductor current, its decrease is not constrained by the inductor current. After the switching converter enters the intermittent inductor current operating state, it can continue to decrease with the decrease of the error signal, so that the main loop can continue to extend the turn-off time of the power switch without introducing an additional pulse frequency modulation loop. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 is a circuit diagram of a switching converter with constant on-time control of valley current mode in the prior art; Figure 2 shows the operating waveforms of the switching converter shown in Figure 1 in continuous conduction mode; Figure 3 is a schematic diagram of a ripple generation circuit provided in an embodiment of this application; Figure 4 is a structural schematic diagram of an energy storage and filtering module provided in an embodiment of this application; Figure 5 is a circuit diagram of a ripple generation circuit provided in an embodiment of this application; Figure 6 is a circuit schematic diagram of a switching converter provided in an embodiment of this application; Figure 7 shows the operating waveforms of the switching converter shown in Figure 6 in continuous conduction mode; Figure 8 shows the operating waveforms of the switching converter shown in Figure 6 in discontinuous conduction mode; Figure 9 shows the working waveform of the switching converter shown in Figure 6 under pulse frequency modulation mode under no-load conditions. Detailed Implementation

[0019] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0021] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0022] Figure 1 The circuit schematic for a switching converter with constant on-time control of valley current mode in the prior art is shown below. Figure 1The power stage of this switching converter includes an inductor L, power switches Q1 and Q2, and an output capacitor Cout. One end of the inductor L is connected to the input power supply Vin, and the other end of the inductor L is connected to the switching node LX. Power switch Q1 is connected between the switching node LX and ground, and power switch Q2 is connected between the switching node LX and the output terminal. The output capacitor Cout and its equivalent series resistance ESR are connected in series and then connected between the output terminal and ground. The load Rout is connected between the output terminal and ground. The inductor current flowing through the inductor L is denoted as Iin, and the output voltage at the output terminal is denoted as Vout.

[0023] The control stage of the switching converter includes feedback resistors Rfb1 and Rfb2, error amplifier EA, current sampling circuit, comparator CMP, RS flip-flop, timer and drive circuit. Feedback resistors Rfb1 and Rfb2 are connected in series between the output terminal and ground, and the connection point of the two outputs the feedback voltage Vfb. The inverting input of the error amplifier EA receives the feedback voltage Vfb, the non-inverting input receives the reference voltage Vref, and the output terminal outputs the error signal Vea. The current sampling circuit samples the inductor current flowing through the power switch Q2 and outputs a sampling voltage Vsen carrying the inductor current information. The non-inverting input of the comparator CMP receives the error signal Vea, the inverting input receives the sampling voltage Vsen, and the output terminal outputs the signal PWMON. The output terminal of the comparator CMP is connected to the set terminal S of the RS flip-flop, and the output terminal of the timer is connected to the reset terminal R of the RS flip-flop. The output terminal Q of the RS flip-flop outputs the signal NMOSON, and the inverting output terminal QB outputs the signal NMOSONB. The output terminal Q of the RS flip-flop is connected to the input terminal of the drive circuit, and the output terminal of the drive circuit is connected to the gate of the power switch Q1 and the power switch Q2 respectively.

[0024] The operation of the aforementioned switching converter is as follows: When the PWMON signal goes high, the RS flip-flop is set, and the NMOSON signal goes high, thus turning on the power switch Q1. Simultaneously, the timer starts counting. After one conduction time, the timer output resets the RS flip-flop, the NMOSON signal goes low, and the power switch Q1 turns off. Therefore, the conduction time of the power switch Q1 is determined by the timer and remains constant, while the turn-off time is determined by when the PWMON signal goes high again. To maintain a stable switching frequency during continuous operation with the inductor current Iin, the timer also receives the input voltage Vin and the output voltage Vout, adjusting the conduction time according to changes in Vin and Vout.

[0025] Figure 2 for Figure 1 The waveform diagram of the switching converter in continuous conduction mode shown is available in [reference]. Figure 2In continuous conduction mode, the inductor current Iin rises during the on-state of power switch Q1 and falls during the off-state. Since the sampling voltage Vsen is obtained by sampling the inductor current, it rises and falls synchronously with the inductor current Iin. When the sampling voltage Vsen drops to the error signal Vea, the comparator CMP flips, causing the signal PWMON to go high, and power switch Q1 turns on again, entering the next switching cycle.

[0026] During the above process, the output voltage Vout fluctuates slightly during each switching cycle as the power switch Q1 is turned on and off, and is maintained near the level determined by the voltage division ratio of the reference voltage Vref and the feedback resistors Rfb1 and Rfb2 under the action of closed-loop control.

[0027] Figure 1 The closed-loop regulation process of the circuit structure shown is as follows: When the load decreases and the output voltage Vout increases, the feedback voltage Vfb increases accordingly, the error signal Vea decreases, and the sampling voltage Vsen takes longer to drop to the error signal Vea. Consequently, the low-level duration of the NMOSON signal is prolonged, the turn-off time of the power switch Q1 is extended, the duty cycle of the switching converter decreases, and the output voltage Vout falls back. When the load increases and the output voltage Vout decreases, the regulation process is reversed. This achieves closed-loop control of the turn-off time of the power switch Q1.

[0028] However, the sampling voltage Vsen is obtained by sampling the inductor current, and its level drop is limited by the inductor current Iin. See also Figure 2 The valley of the sampling voltage Vsen corresponds to the valley of the inductor current Iin. When the load continues to decrease, causing the inductor current Iin to drop to zero and the switching converter to enter discontinuous conduction mode, the inductor current Iin can no longer decrease, and the sampling voltage Vsen can no longer decrease. Therefore, it is impossible to further extend the turn-off time of the power switch Q1 by extending the time required for the sampling voltage Vsen to drop to the error signal Vea. The main loop loses the ability to continue to reduce the duty cycle, and the output voltage Vout will be raised.

[0029] To address these issues, existing technologies typically introduce an additional pulse frequency modulation loop, which handles frequency regulation in discontinuous conduction mode. This approach requires additional circuit space; furthermore, to ensure stability during mode switching, the constant voltage value in pulse frequency modulation mode is usually slightly higher than that in pulse width modulation mode, causing output voltage jumps during mode switching. When the load decreases further, the pulse frequency modulation loop also lacks the ability to operate at extremely low frequencies, requiring a switch to a pulse skipping cycle mode controlled by an overvoltage comparator with hysteresis to stabilize the output voltage, resulting in a further increase in output voltage ripple under no-load conditions.

[0030] Figure 3 A schematic diagram of the ripple generation circuit provided in the embodiments of this application is shown below. Figure 3 The ripple generation circuit 200 provided in this application embodiment is applied to a switching converter, which includes a constant voltage loop 130, a comparator 140, and an RS flip-flop 110. The RS flip-flop 110 outputs a control signal and an inverted control signal that is the opposite phase of the control signal, wherein the control signal is... Figure 1 The NMOSON signal in the diagram is the inverting control signal. Figure 1 The signal NMOSONB in ​​the middle.

[0031] The input terminal of constant voltage loop 130 is connected to the output terminal of the switching converter to sample and amplify the output voltage Vout. The output terminal of constant voltage loop 130 outputs an error signal Vea. The non-inverting input terminal of comparator 140 is connected to the output terminal of constant voltage loop 130. The output terminal of comparator 140 outputs a set signal, which is the... Figure 1 The signal PWMON in the comparator 140 is connected to the set terminal of the RS flip-flop 110.

[0032] The ripple generation circuit 200 includes a switching module 210, an energy storage and filtering module 220, and a level boosting module 230.

[0033] One input terminal of the switching module 210 is connected to the inverting output terminal of the RS flip-flop 110 to receive the inverting control signal. The other input terminal of the switching module 210 is connected to the output terminal of the switching converter to receive the output voltage Vout. The output terminal of the switching module 210 outputs a first voltage. The input terminal of the energy storage filter module 220 is connected to the output terminal of the switching module 210, and the output terminal of the energy storage filter module 220 outputs a second voltage. The input terminal of the level-up module 230 is connected to the output terminal of the energy storage filter module 220, and the output terminal of the level-up module 230 is connected to the inverting input terminal of the comparator 140. The output terminal of the level-up module 230 outputs a third voltage.

[0034] The switching module 210 is configured to output a first voltage in response to an inverting control signal. When the inverting control signal is low, the first voltage is high, and the high-level first voltage is equal to the output voltage Vout of the switching converter; when the inverting control signal is high, the first voltage is low. Since the inverting control signal is inverted from the control signal, and the control signal is used to drive the power switch of the switching converter, the first voltage is high during the on-state of the power switch and low during the off-state of the power switch. That is, the duty cycle of the first voltage is the same as the duty cycle of the control signal, and the amplitude of the high-level first voltage is determined by the output voltage Vout. Thus, the first voltage simultaneously carries the output voltage information and switching timing information of the switching converter.

[0035] The energy storage filter module 220 is configured to charge and filter in response to a high-level first voltage, outputting a second voltage; and to discharge in response to a low-level first voltage, causing the second voltage to decrease. That is, during the conduction period of the power switch, the first voltage is high, the energy storage filter module 220 is charged, and the second voltage rises; during the turn-off period of the power switch, the first voltage is low, the energy storage filter module 220 discharges, and the second voltage decreases. The energy storage filter module 220 filters the first voltage while charging and discharging, making the ripple of the second voltage smaller than the ripple of the first voltage, thus changing the square wave shape of the first voltage to a shape that rises and falls smoothly with the charging and discharging process.

[0036] The level-up module 230 is configured to output a third voltage in response to the second voltage, the third voltage being the sum of the second voltage and a threshold voltage. That is, the level-up module 230 raises the second voltage by a threshold voltage before outputting it, while keeping the change pattern of the second voltage unchanged.

[0037] As can be seen from the above process, the third voltage rises and falls synchronously with the second voltage, while the second voltage charges and discharges according to the high and low levels of the first voltage. Therefore, the third voltage rises during the conduction period of the power switch and falls during the turn-off period of the power switch, which is consistent with the direction of change of the inductor current of the switching converter. The third voltage is sent to the inverting input of comparator 140 and compared with the error signal Vea output from constant voltage loop 130 to the non-inverting input of comparator 140. When the third voltage drops to the error signal Vea, comparator 140 flips to make the set signal high, which makes the control signal high through RS flip-flop 110, and the power switch turns on again, thereby realizing closed-loop control of the turn-off time of the power switch.

[0038] and Figure 1Compared to the prior art, in this embodiment, the signal sent to the comparator is changed from the sampling voltage Vsen to a third voltage. This third voltage is not obtained by sampling the inductor current, but rather by the output voltage Vout of the switching converter after being chopped by the switching module 210, charged and discharged by the energy storage filter module 220, and raised by the level-up module 230. Therefore, the decrease in the third voltage is not constrained by the inductor current. When the switching converter enters discontinuous conduction mode and the inductor current drops to zero, the third voltage can continue to decrease as the error signal Vea decreases. The main loop does not need an additional pulse frequency modulation loop to continue extending the turn-off time of the power switch.

[0039] Furthermore, since the amplitude of the first high-level voltage is equal to the output voltage Vout, when the load decreases and causes the output voltage Vout to rise, the second voltage also increases, and the third voltage also increases, requiring a longer time to drop to the error signal Vea. Simultaneously, the increase in output voltage Vout causes the error signal Vea to decrease. These two factors combined extend the turn-off time of the power switch, reduce the duty cycle of the switching converter, and cause the output voltage Vout to fall back down.

[0040] Figure 4 A schematic diagram of the energy storage and filtering module provided in the embodiments of this application is shown below. Figure 4 In some embodiments, the energy storage filter module 220 includes a voltage divider unit 221 and an energy storage filter unit 222.

[0041] The input terminal of voltage divider unit 221 is connected to the output terminal of switch module 210, and the output terminal of voltage divider unit 221 is connected to the input terminal of energy storage filter unit 222. The output terminal of energy storage filter unit 222 is connected to the input terminal of level boosting module 230.

[0042] Voltage divider unit 221 is configured to output a divided voltage in response to a first voltage. Voltage divider unit 221 divides the first voltage according to a predetermined ratio, so that the divided voltage is consistent with the high and low level states of the first voltage: when the first voltage is high, the divided voltage is high, and the high-level divided voltage is equal to the product of the output voltage Vout and the division ratio; when the first voltage is low, the divided voltage is low.

[0043] The purpose of the voltage divider unit 221 is that the amplitude of the first high-level voltage is equal to the output voltage Vout of the switching converter, which may be relatively high. If it is directly fed into the subsequent stage, it is not convenient to compare it with the error signal Vea within the same voltage range. After being divided by the voltage divider unit 221, the amplitude of the divided voltage is proportionally reduced to a range suitable for subsequent processing. At the same time, since the voltage division ratio is fixed, the divided voltage is still proportional to the output voltage Vout, and the output voltage information carried by the first voltage is thus preserved.

[0044] The energy storage filter unit 222 is configured to charge and filter in response to a high-level voltage divider voltage to output a second voltage; and to discharge in response to a low-level voltage divider voltage to cause the second voltage to decrease. Specifically, during the on-state of the power switch, the voltage divider voltage is high, the energy storage filter unit 222 is charged, and the second voltage rises; during the off-state of the power switch, the voltage divider voltage is low, the energy storage filter unit 222 discharges, and the second voltage decreases. The energy storage filter unit 222 filters the voltage divider voltage during charging and discharging, ensuring that the ripple of the second voltage is less than the ripple of the voltage divider voltage.

[0045] Therefore, the average value of the second voltage is equal to the average value of the voltage divider, while its ripple is reduced due to the filtering effect. The second voltage changes from the square wave shape of the voltage divider to a shape that rises and falls gently during the charging and discharging process.

[0046] It should be noted that the division between the voltage divider unit 221 and the energy storage filter unit 222 is based on function. In some other embodiments, the energy storage filter module 220 may not be divided into the two units mentioned above, but may be implemented by a network that simultaneously has voltage divider, energy storage and filtering functions, as long as the network can charge when the first voltage is high level, discharge when the first voltage is low level, and make the ripple of the output second voltage less than the ripple of the first voltage.

[0047] Figure 5 For the circuit schematic diagram of the ripple generation circuit provided in the embodiments of this application, please refer to... Figure 5 In some embodiments, the switching module 210 includes a first switching transistor MP1 and a second switching transistor MN1, wherein the first switching transistor MP1 is a P-channel field-effect transistor and the second switching transistor MN1 is an N-channel field-effect transistor.

[0048] The gate of the first switch MP1 receives the inverting control signal NMOSONB. The source of the first switch MP1 is connected to the output terminal of the switching converter to receive the output voltage Vout. The drain of the first switch MP1 serves as the output terminal of the switching module 210, and the voltage at this output terminal is the first voltage V0. The gate of the second switch MN1 receives the inverting control signal NMOSONB. The source of the second switch MN1 is grounded, and the drain of the second switch MN1 is connected to the drain of the first switch MP1. The substrates of the first switch MP1 and the second switch MN1 are respectively connected to their respective sources. That is, the substrate of the first switch MP1 is connected to the output voltage Vout, and the substrate of the second switch MN1 is grounded to avoid the influence of substrate bias on the conduction state of the switch.

[0049] Since the first switch MP1 is a P-channel MOSFET and the second switch MN1 is an N-channel MOSFET, they conduct alternately under the control of the same inverting control signal NMOSONB. When the inverting control signal NMOSONB is low, the first switch MP1 is turned on and the second switch MN1 is turned off, and the first voltage V0 is pulled up to the output voltage Vout through the first switch MP1. When the inverting control signal NMOSONB is high, the first switch MP1 is turned off and the second switch MN1 is turned on, and the first voltage V0 is pulled down to ground through the second switch MN1. Therefore, the first voltage V0 is a square wave voltage with a high level equal to the output voltage Vout, a low level equal to ground potential, and a duty cycle the same as the control signal NMOSONB.

[0050] In some embodiments, the second switch MN1 may be omitted from the switching module 210. In this case, during the turn-off period of the first switch MP1, the node containing the first voltage V0 discharges to ground through the resistor path of the subsequent stage, and the voltage can also drop. The purpose of setting the second switch MN1 is to clamp the node containing the first voltage V0 to ground potential during the turn-off period of the first switch MP1, so as to prevent the node from being in a floating state and causing the low level of the first voltage V0 to drift.

[0051] See Figure 5 In some embodiments, the voltage divider unit 221 includes a first voltage divider resistor R1 and a second voltage divider resistor R2. The first end of the first voltage divider resistor R1 is connected to the output terminal of the switch module 210 to receive the first voltage V0. The second end of the first voltage divider resistor R1 is connected to the first end of the second voltage divider resistor R2. The connection point of the two is the output terminal of the voltage divider unit 221, and the voltage at the output terminal is the divided voltage V1. The second end of the second voltage divider resistor R2 is grounded.

[0052] Therefore, the voltage divider V1 is determined by the voltage division ratio of the first voltage divider resistor R1 and the second voltage divider resistor R2. When the first voltage V0 is high, the voltage divider V1 is equal to the product of the output voltage Vout and this voltage division ratio, which is the ratio of the resistance of the second voltage divider resistor R2 to the sum of the resistances of the first voltage divider resistor R1 and the second voltage divider resistor R2. When the first voltage V0 is low, the voltage divider V1 is at ground potential. Therefore, the average value of the voltage divider V1 is equal to the product of the duty cycle of the control signal NMOSON, the output voltage Vout, and the aforementioned voltage division ratio.

[0053] See Figure 5In some embodiments, the energy storage filter unit 222 includes a filter resistor R0 and a filter capacitor C0. The first end of the filter resistor R0 is connected to the second end of the first voltage divider resistor R1 to receive the divided voltage V1. The second end of the filter resistor R0 is connected to the first end of the filter capacitor C0. The connection point of the two serves as the output terminal of the energy storage filter unit 222, and the voltage at this output terminal is the second voltage V2. The second end of the filter capacitor C0 is grounded.

[0054] In some embodiments, the resistance of the filter resistor R0 is greater than the resistance of the first voltage divider resistor R1, and the resistance of the filter resistor R0 is greater than the resistance of the second voltage divider resistor R2. With this configuration, the current flowing through the filter resistor R0 is much smaller than the current flowing through the first voltage divider resistor R1 and the second voltage divider resistor R2. The influence of the branch containing the filter resistor R0 on the voltage division ratio of the voltage divider unit 221 can be ignored, thus ensuring that the amplitude of the divided voltage V1 is determined solely by the first voltage divider resistor R1 and the second voltage divider resistor R2.

[0055] Furthermore, in some embodiments, the resistance values ​​of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are both much smaller than the resistance value of the filter resistor R0. With this configuration, the influence of the branch containing the filter resistor R0 on the voltage division ratio of the voltage divider unit 221 can be further ignored. Simultaneously, during the discharge of the filter capacitor C0, the filter resistor R0 becomes the dominant resistor in the discharge path, and the rate of decrease of the second voltage V2 is mainly determined by the filter resistor R0 and the filter capacitor C0.

[0056] The working process of the energy storage filter unit 222 is as follows: When the voltage divider V1 is high, the output voltage Vout charges the filter capacitor C0 through the first voltage divider resistor R1 and the filter resistor R0, and the second voltage V2 rises; when the voltage divider V1 is low, the charge on the filter capacitor C0 discharges to ground through the path formed by the filter resistor R0, the first voltage divider resistor R1, and the second voltage divider resistor R2, and the second voltage divider V2 falls. Since the filter resistor R0 and the filter capacitor C0 form a low-pass filter network, the ripple of the second voltage V2 is smaller than the ripple of the voltage divider V1. The second voltage V2 changes from the square wave shape of the voltage divider V1 to a shape that rises and falls smoothly with the charging and discharging process. The average value of the second voltage V2 is the same as the average value of the voltage divider V1, that is, equal to the product of the duty cycle of the control signal NMOSON, the output voltage Vout, and the aforementioned voltage division ratio.

[0057] In some embodiments, the product of the resistance of the filter resistor R0 and the capacitance of the filter capacitor C0 is greater than the period of the control signal NMOSON. With this configuration, the charging and discharging amplitude of the filter capacitor C0 within a single switching cycle is relatively small, the second voltage V2 rises and falls approximately linearly, and the ripple amplitude of the second voltage V2 can be set by the resistance of the filter resistor R0 and the capacitance of the filter capacitor C0, thereby meeting the ripple requirements for loop stability while avoiding excessive ripple.

[0058] See Figure 5 In some embodiments, the level-up module 230 includes a follower transistor MP2 and a bias current source IB, wherein the follower transistor MP2 is a P-channel MOSFET.

[0059] The gate of follower transistor MP2 serves as the input terminal of level-up module 230, connected to the second terminal of filter resistor R0 to receive the second voltage V2; the drain of follower transistor MP2 is grounded; the source of follower transistor MP2 serves as the output terminal of level-up module 230, outputting the third voltage Vramp. One end of bias current source IB is connected to power supply SVCC, and the other end of bias current source IB is connected to the source and substrate of follower transistor MP2. The substrate of follower transistor MP2 is connected to its source to eliminate the influence of substrate bias on the threshold voltage of follower transistor MP2.

[0060] The follower transistor MP2 and the bias current source IB form a source follower. Under the bias current provided by the bias current source IB, the gate-source voltage of the follower transistor MP2 remains constant. Therefore, the third voltage Vramp is equal to the sum of the second voltage V2 and the threshold voltage of the follower transistor MP2. That is, while keeping the change pattern of the second voltage V2 unchanged, the third voltage Vramp is raised by a threshold voltage relative to the second voltage V2.

[0061] The purpose of setting up the level-up module 230 is as follows: When the switching converter operates under extremely light load or no-load conditions, the duty cycle of the control signal NMOSON is extremely low, and the second voltage V2 will drop to near zero. If the second voltage V2 is directly fed into the comparator CMP, this voltage may be lower than the common operating voltage range of the comparator CMP and the error amplifier EA, making comparison impossible. After being boosted by a threshold voltage, the third voltage Vramp is still equal to a threshold voltage when the second voltage V2 approaches zero, thus falling within the voltage range that can be compared with the error signal Vea. In addition, the gate of the follower transistor MP2 is a high-impedance input terminal, so the node where the second voltage V2 is located will not be pulled off due to the input current of the comparator CMP, and the voltage on the filter capacitor C0 can be accurately transmitted to the subsequent stage.

[0062] In some embodiments, the voltage of the power supply SVCC is greater than the sum of the maximum value of the third voltage Vramp and the voltage drop required for the bias current source IB to operate normally. This configuration ensures that the bias current source IB provides a constant bias current even when the third voltage Vramp is at its maximum value, preventing the third voltage Vramp from being limited due to the bias current source IB losing its operating margin.

[0063] In other embodiments, the level-up module 230 may also be implemented by other circuits capable of achieving a fixed level-up, such as a diode and a bias current source, or a resistor and a bias current source, as long as it can raise the second voltage V2 by a predetermined voltage while keeping the change pattern of the second voltage V2 unchanged.

[0064] Figure 6 For the circuit schematic diagram of the switching converter provided in the embodiments of this application, please refer to [link / reference]. Figure 6 The switching converter provided in this application includes an inductor L, a power switch Q1, a power switch Q2, an output capacitor Cout, a constant voltage loop 130, a comparator CMP, an RS flip-flop 110, an on-time control module 150, a drive module 120, and a ripple generation circuit 200 in any of the above embodiments.

[0065] The first terminal of inductor L is connected to the input power supply Vin, and the second terminal of inductor L is connected to the switching node LX. The inductor current flowing through inductor L is denoted as Iin. Power switch Q1 is connected between the switching node LX and ground. The source of power switch Q2 is connected to the switching node LX, and the drain of power switch Q2 serves as the output terminal of the switching converter. The output voltage at the output terminal is denoted as Vout. The output capacitor Cout and its equivalent series resistance ESR are connected in series between the output terminal and ground. The load Rout is connected between the output terminal and ground.

[0066] The constant voltage loop 130 includes feedback resistors Rfb1 and Rfb2 and an error amplifier EA. Feedback resistors Rfb1 and Rfb2 are connected in series between the output terminal and ground, and the connection point outputs a feedback voltage Vfb. The inverting input of the error amplifier EA receives the feedback voltage Vfb, the non-inverting input receives the reference voltage Vref, and the output outputs an error signal Vea. Therefore, the input of the constant voltage loop 130 is connected to the output of the switching converter, and the output of the constant voltage loop 130, the error signal Vea, is connected to the non-inverting input of the comparator CMP.

[0067] The first input terminal of the ripple generation circuit 200 is connected to the inverted output terminal QB of the RS flip-flop 110 to receive the inverted control signal NMOSONB; the second input terminal of the ripple generation circuit 200 is connected to the output terminal of the switching converter to receive the output voltage Vout; the output terminal of the ripple generation circuit 200 outputs a third voltage Vramp and is connected to the inverted input terminal of the comparator CMP.

[0068] The comparator CMP outputs a set signal PWMON, and the output of the comparator CMP is connected to the set terminal S of the RS flip-flop 110; the output of the conduction time control module 150 is connected to the reset terminal R of the RS flip-flop 110.

[0069] The output terminal Q of RS flip-flop 110 outputs the control signal NMOSON, and the inverted output terminal QB of RS flip-flop 110 outputs the inverted control signal NMOSONB, which is the inverse of the control signal NMOSON. The output terminal Q of RS flip-flop 110 is connected to the input terminal of drive module 120, and the output terminal of drive module 120 is connected to the gate of power switch Q1 and the gate of power switch Q2, respectively.

[0070] contrast Figure 6 and Figure 1 It can be seen that the main difference between the two lies in: Figure 1 The voltage Vsen, obtained by sampling the inductor current through the current sampling circuit, is sent to the inverting input of the comparator CMP. Figure 6 The voltage Vramp output from the ripple generation circuit 200 is sent to the inverting input of the comparator CMP. In other words, this embodiment replaces the ripple generation circuit 200 with the... Figure 1 The current sampling circuit in the circuit replaces the sampling voltage Vsen with a third voltage Vramp; otherwise, the structure is the same. Figure 1 The same applies. Since the third voltage Vramp is obtained by chopping, charging and discharging filtering and level boosting of the output voltage Vout, the switching converter does not need to set up a current sampling circuit, nor does it need to introduce a sampling element in the branch of the power switch Q2.

[0071] Since the third voltage Vramp sent to the comparator CMP is obtained by processing the output voltage Vout, the control loop of the switching converter no longer introduces inductor current information, but instead simultaneously introduces the DC component of the output voltage Vout and the ripple component obtained by chopping the output voltage Vout. Accordingly, the control structure of the switching converter is changed from... Figure 1 The constant on-time control structure of the valley current mode shown is transformed into a constant on-time control structure with the output voltage as the only sampled quantity.

[0072] The switching converter operates as follows: When the set signal PWMON goes high, the RS flip-flop 110 is set, the control signal NMOSON goes high, and the drive module 120 turns on the power switch Q1 accordingly. Simultaneously, the on-time control module 150 starts timing. After one on-time period, the on-time control module 150 resets the RS flip-flop 110, the control signal NMOSON goes low, and the power switch Q1 turns off. Therefore, the on-time of the power switch Q1 is determined by the on-time control module 150, while the off-time is determined by the moment when the third voltage Vramp drops to the error signal Vea.

[0073] In some embodiments, the on-time control module 150 also receives the input voltage Vin and the output voltage Vout, and adjusts the on-time generated by it according to the changes in the input voltage Vin and the output voltage Vout, thereby keeping the switching frequency of the switching converter constant in the continuous operation state of the inductor current Iin.

[0074] In some embodiments, the power switch Q2 is a synchronous rectifier, which is turned on by the drive module 120 during the off-state of the power switch Q1 to carry the freewheeling current Iin from the inductor to the output. When the switching converter operates in a state where the inductor current Iin is discontinuous, the switching converter may further include a zero-crossing detection module. This zero-crossing detection module detects the inductor current Iin and turns off the power switch Q2 via the drive module 120 when the inductor current Iin drops to zero, in order to prevent current from flowing back from the output to the inductor L through the power switch Q2.

[0075] Figure 7 for Figure 6 The waveform diagram of the switching converter in continuous conduction mode shown is available in [reference]. Figure 6 and Figure 7 In continuous conduction mode, one switching cycle of the switching converter includes the following process.

[0076] When the control signal NMOSON is high, power switch Q1 is turned on. When the inverting control signal NMOSONB is low, the first switch MP1 is turned on while the second switch MN1 is turned off. The first voltage V0 quickly rises to the output voltage Vout. The voltage divider V1 is determined by the voltage division ratio of the first voltage divider resistor R1 and the second voltage divider resistor R2. The output voltage Vout charges the filter capacitor C0 through the first voltage divider resistor R1 and the filter resistor R0, causing the second voltage V2 to rise. The third voltage Vramp is obtained by boosting the second voltage V2 by a threshold voltage using the follower transistor MP2, and therefore rises synchronously with the second voltage V2. During this period, the inductor current Iin also rises as power switch Q1 is turned on, meaning the third voltage Vramp rises synchronously with the inductor current Iin.

[0077] After the conduction time control module 150 completes its timing, the control signal NMOSON goes low, power switch Q1 turns off, and the inverting control signal NMOSONB goes high, turning off the first switch MP1 and turning on the second switch MN1. The first voltage V0 is quickly pulled down to ground. The charge on the filter capacitor C0 discharges to ground through the path formed by the filter resistor R0 and the first and second voltage divider resistors R1 and R2, causing the second voltage V2 to drop. The third voltage Vramp drops synchronously with the second voltage V2. During this period, the inductor current Iin also drops as the power switch Q1 turns off, meaning the third voltage Vramp drops synchronously with the inductor current Iin.

[0078] When the third voltage Vramp drops to the error signal Vea, the comparator CMP flips, causing the set signal PWMON to go high. This, in turn, triggers the RS flip-flop 110 to make the control signal NMOSON go high again, turning on the power switch Q1 and starting the next switching cycle. This achieves closed-loop control of the turn-off time of the power switch Q1.

[0079] See Figure 7 In continuous conduction mode, the inductor current Iin rises and falls continuously in each switching cycle without falling to zero. The third voltage Vramp rises and falls synchronously with the inductor current Iin, while the output voltage Vout fluctuates slightly and remains stable in each switching cycle.

[0080] The closed-loop control process described above is as follows: When the load decreases and causes the output voltage Vout to rise, the feedback voltage Vfb rises, and the error signal Vea decreases. Simultaneously, assuming the duty cycle of the current switching converter has not yet had time to decrease, the rise in output voltage Vout will increase the second voltage V2, thereby increasing the third voltage Vramp. Therefore, the third voltage Vramp takes longer to drop to the error signal Vea, extending the turn-off time of power switch Q1, reducing the duty cycle of the switching converter, and causing the output voltage Vout to fall back. When the load increases and causes the output voltage Vout to decrease, the adjustment process is reversed.

[0081] Figure 8 for Figure 6 The waveform diagram of the switching converter in discontinuous conduction mode shown is available in [reference]. Figure 6 and Figure 8When the load continues to decrease, causing the inductor current Iin to drop to zero and the switching converter to enter discontinuous conduction mode, the third voltage Vramp is not obtained by sampling the inductor current. Instead, it is obtained by chopping the output voltage Vout through the first switch MP1 and the second switch MN1, filtering it through the charging and discharging of the filter resistor R0 and the filter capacitor C0, and then boosting it through the follower transistor MP2. Therefore, the level of the third voltage Vramp will not be as... Figure 1 and Figure 2 The sampling voltage Vsen shown is also limited by the inductor current crossing zero and cannot continue to decrease. At this point, as long as the error signal Vea continues to decrease, the third voltage Vramp can continue to decrease to the error signal Vea, thereby obtaining a longer turn-off time for the power switch Q1.

[0082] See Figure 8 In discontinuous conduction mode, the inductor current Iin drops to zero after the power switch Q1 is turned off and remains zero until the start of the next switching cycle; that is, the inductor current Iin has a discontinuous segment within each switching cycle. Meanwhile, the third voltage Vramp continues to decrease during this discontinuous segment until it reaches the error signal Vea. Figure 7 In contrast, the turn-off time of the power switch Q1 is extended, the switching frequency of the switching converter is reduced accordingly, and the output voltage Vout remains stable.

[0083] Therefore, in the discontinuous conduction mode, the switching converter of this application embodiment does not need to introduce an additional pulse frequency modulation loop. It can continue to reduce the switching frequency and stabilize the output voltage Vout by relying solely on the main loop, thereby avoiding the circuit area required by introducing an additional loop and also avoiding the output voltage jump caused by the switching of the working mode.

[0084] Figure 9 for Figure 6 The waveform diagram of the switching converter in pulse frequency modulation mode under no-load is shown below. Figure 6 and Figure 9 When the load is further reduced, causing the switching converter to enter a very light load or even no-load condition, due to the extremely low duty cycle of the control signal NMOSON, the power switch Q1 is in the off state for most of the time, the second voltage V2 has dropped to close to zero, and the third voltage Vramp is equal to a threshold voltage.

[0085] Under this operating condition, the process of one switching cycle is as follows. After one switching cycle, the output voltage Vout increases, the feedback voltage Vfb increases accordingly, and the error signal Vea initially decreases. As time progresses, the output voltage Vout decreases slowly due to the presence of the load, the feedback voltage Vfb decreases accordingly, and the error signal Vea begins to rise again. When the error signal Vea rises again to the third voltage Vramp, the comparator CMP flips, causing the set signal PWMON to go high. This triggers a new switching cycle via the RS flip-flop 110, pulling the output voltage Vout high again.

[0086] Therefore, under no-load conditions, the error signal Vea changes with the output voltage Vout, replacing the change in the third voltage Vramp, thus realizing the flipping of the set signal PWMON, thereby achieving ultra-low frequency modulation under no-load conditions.

[0087] Furthermore, after a new switching cycle begins, the inverting control signal NMOSONB immediately goes low, the first voltage V0 immediately jumps to the output voltage Vout, and the second voltage V2 and the third voltage Vramp are subsequently rapidly raised away from the error signal Vea, thus resetting the comparator CMP. In other words, the third voltage Vramp itself provides an equivalent hysteresis effect, preventing the set signal PWMON from being repeatedly triggered after one switching cycle begins. Therefore, the switching converter in this embodiment does not need to switch to the pulse-jumping cycle mode controlled by the hysteretic overvoltage comparator under no-load conditions, and can still rely on the main loop to stabilize the output voltage Vout.

[0088] Furthermore, under no-load conditions, the output voltage ripple of the switching converter depends on the energy injected into the output terminal during a single switching cycle, which is determined by the peak inductor current resulting from the on-time of the power switch Q1. Therefore, by designing the on-time of the power switch Q1, the energy level of a single switching cycle can be set, thereby controlling the output voltage ripple under no-load conditions within the expected range. In contrast, the output voltage ripple in the pulse-skipping cycle mode controlled by an overvoltage comparator with hysteresis is determined by the hysteresis window of the comparator and is typically much larger than the aforementioned ripple.

[0089] It should be noted that, Figures 7 to 9 The continuous conduction mode referred to in the text is the continuous operating state of the inductor current Iin, while the discontinuous conduction mode is the intermittent operating state of the inductor current Iin.

[0090] In summary, the ripple generation circuit and switching converter provided in this application replace the sampling voltage obtained by sampling the inductor current in the valley current mode structure with a third voltage Vramp generated on-chip and related to the output voltage and duty cycle. This ensures loop stability while enabling the main loop to stably control the output voltage even after the switching converter enters discontinuous conduction mode, eliminating the need for an additional pulse frequency modulation loop. Furthermore, under no-load conditions, the output voltage can be stabilized using the main loop instead of an overvoltage comparator with hysteresis. This simplifies loop design, avoids the problem of a slight increase in output voltage after switching to pulse frequency modulation mode, and improves output voltage ripple under no-load conditions.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A ripple generation circuit for a switching converter including a constant voltage loop, a comparator, and an RS flip-flop, wherein the RS flip-flop outputs a control signal and an inverted control signal opposite to the control signal, the output of the constant voltage loop outputs an error signal, the non-inverting input of the comparator is connected to the output of the constant voltage loop, the output of the comparator outputs a set signal, and the output of the comparator is connected to the set input of the RS flip-flop; characterized in that, Includes a switching module, an energy storage and filtering module, and a level boosting module; The switching module is configured to output a first voltage in response to the inverting control signal; when the inverting control signal is low, the first voltage is high, and the high-level first voltage is equal to the output voltage of the switching converter; when the inverting control signal is high, the first voltage is low. The input terminal of the energy storage filter module is connected to the output terminal of the switch module. The energy storage filter module is configured to charge and filter in response to a high-level first voltage and output a second voltage. And in response to a low-level first voltage, discharge is performed to cause the second voltage to drop; The input terminal of the level-up module is connected to the output terminal of the energy storage filter module, and the output terminal of the level-up module is connected to the inverting input terminal of the comparator. The level-up module is configured to output a third voltage in response to the second voltage. The third voltage is the sum of the second voltage and the threshold voltage.

2. The circuit according to claim 1, characterized in that, The switching module includes a first switching transistor and a second switching transistor; The gate of the first switch receives the inverted control signal, the source of the first switch is connected to the output terminal of the switching converter, and the drain of the first switch serves as the output terminal of the switching module. The gate of the second switch receives the inverted control signal, the source of the second switch is grounded, and the drain of the second switch is connected to the drain of the first switch.

3. The circuit according to claim 2, characterized in that, The first switching transistor is a P-channel MOSFET, and the second switching transistor is an N-channel MOSFET.

4. The circuit according to claim 1, characterized in that, The energy storage and filtering module includes a voltage divider unit and an energy storage and filtering unit; The input terminal of the voltage divider unit is connected to the output terminal of the switching module, and the voltage divider unit is configured to output a divided voltage in response to the first voltage; The input terminal of the energy storage filter unit is connected to the output terminal of the voltage divider unit, and the output terminal of the energy storage filter unit is connected to the input terminal of the level boosting module. The energy storage filter unit is configured to charge and filter in response to the high-level voltage divider voltage and output the second voltage. And discharge in response to the low-level voltage divider to cause the second voltage to drop.

5. The circuit according to claim 4, characterized in that, The voltage divider unit includes a first voltage divider resistor and a second voltage divider resistor; The first end of the first voltage divider resistor is connected to the output end of the switching module, the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor and the input end of the energy storage filter unit, and the second end of the second voltage divider resistor is grounded.

6. The circuit according to claim 5, characterized in that, The energy storage filter unit includes a filter resistor and a filter capacitor; The first end of the filter resistor is connected to the second end of the first voltage divider resistor, the second end of the filter resistor is connected to the first end of the filter capacitor and the input end of the level boosting module, and the second end of the filter capacitor is grounded.

7. The circuit according to claim 6, characterized in that, The resistance of the filter resistor is greater than the resistance of the first voltage divider resistor, and the resistance of the filter resistor is greater than the resistance of the second voltage divider resistor.

8. The circuit according to claim 6, characterized in that, The average value of the second voltage is equal to the product of the duty cycle of the control signal, the output voltage of the switching converter, and the ratio of the resistance of the second voltage divider resistor to the sum of the resistances of the first voltage divider resistor and the second voltage divider resistor.

9. The circuit according to claim 1, characterized in that, The level-up module includes a follower transistor and a bias current source; The follower transistor is a P-channel field-effect transistor. The gate of the follower transistor serves as the input terminal of the level-up module, the drain of the follower transistor is grounded, and the source of the follower transistor serves as the output terminal of the level-up module. One end of the bias current source is connected to the power supply, and the other end of the bias current source is connected to the source and substrate of the follower transistor. The third voltage is the sum of the second voltage and the threshold voltage of the follower transistor.

10. A switching converter, characterized in that, It includes an inductor, a first power switch, a second power switch, a constant voltage loop, a comparator, an RS flip-flop, an on-time control module, a drive module, and a ripple generation circuit as described in any one of claims 1 to 9; The first end of the inductor is connected to the input power supply; The first power switch is connected between the second terminal of the inductor and ground, and the source of the second power switch is connected to the second terminal of the inductor. The source of the second power switch serves as the output terminal of the switching converter. The input terminal of the constant voltage loop is connected to the output terminal of the switching converter, the output terminal of the constant voltage loop outputs an error signal, and the output terminal of the constant voltage loop is connected to the non-inverting input terminal of the comparator. The first input terminal of the ripple generation circuit is connected to the inverted output terminal of the RS flip-flop, the second input terminal of the ripple generation circuit is connected to the output terminal of the switching converter, and the output terminal of the ripple generation circuit is connected to the inverted input terminal of the comparator. The comparator outputs a set signal, and the output of the comparator is connected to the set terminal of the RS flip-flop. The output of the on-time control module is connected to the reset terminal of the RS flip-flop. The RS flip-flop outputs a control signal, and its inverted output outputs an inverted control signal that is opposite to the control signal. The output of the RS flip-flop is connected to the input of the drive module, and the output of the drive module is connected to the control terminals of the first power switch and the second power switch.

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