Power converter and control method, device and power supply equipment thereof

Abstract

The application provides a power converter and a control method, device and power supply equipment thereof. The method comprises the following steps: obtaining a reference voltage vector and a given value of a direct current side current of the power converter; determining a plurality of groups of alternative space vector combinations according to the reference voltage vector; for each group of alternative space vector combinations, calculating a deviation evaluation result based on a plurality of direct current instantaneous values corresponding to the group of alternative space vector combinations and the given value of the direct current side current, and selecting an alternative space vector combination with the minimum deviation evaluation result as a target space vector combination; and generating a driving signal for controlling a switch tube in the power converter based on the target space vector combination. According to the application, the direct current side current waveform is as close as possible to the given value, so that the several instantaneous levels of the direct current side current closely change around the given value in one switching cycle, and the high-frequency fluctuation of the direct current side current is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and in particular to a power converter and its control method, device, and power supply equipment. Background Technology

[0002] Power converters, as core devices for power conversion and control, are widely used in key areas such as new energy power generation, motor drives, uninterruptible power supplies (UPS), and power quality management of power grids. Among them, three-phase voltage source power converters have become the mainstream choice for medium and high power applications due to their advantages such as simple topology, flexible control, and ability to achieve bidirectional energy flow. In this type of converter, the DC bus capacitor plays a crucial role in buffering instantaneous power differences between the AC and DC sides and suppressing DC voltage fluctuations. Its reliability and lifespan directly determine the long-term operational stability of the entire system. However, engineering practice shows that the DC bus capacitor is usually one of the weakest links in a power converter, and the internal heating caused by the high-frequency ripple current flowing through the capacitor is the core factor leading to capacitor performance degradation and shortened lifespan.

[0003] Currently, Space Vector Pulse Width Modulation (SVPWM) is commonly used to synthesize the desired AC-side voltage for power converters. In traditional SVPWM, to obtain a symmetrical switching sequence and reduce output harmonics, the zero vector is typically concentrated in the middle of the switching cycle or symmetrically distributed on both sides, forming a space vector sequence such as P (high level) in the middle and N (low level) on both sides, or vice versa. This type of modulation strategy results in a very high effective value of the current ripple injected into the DC bus capacitor within one switching cycle. Large capacitor ripple current will exacerbate dielectric losses and heat generation inside the capacitor, accelerate electrolyte evaporation or film aging under long-term operation, significantly shorten capacitor lifespan, and reduce the overall reliability of the system. Summary of the Invention

[0004] This invention provides a power converter and its control method, apparatus, and power supply equipment to solve the problem of large capacitor ripple caused by the modulation method of existing power converters.

[0005] In a first aspect, embodiments of the present invention provide a control method for a power converter, comprising: Obtain the reference voltage vector and DC-side current setpoint of the power converter; Based on the reference voltage vector, multiple sets of candidate space vector combinations are determined; each set of candidate space vector combinations corresponds to multiple instantaneous DC current values. For each set of candidate space vector combinations, based on the multiple instantaneous DC current values ​​corresponding to the set of candidate space vector combinations and the given DC current value, the deviation evaluation result is calculated, and the candidate space vector combination with the smallest deviation evaluation result is selected as the target space vector combination. The drive signals for controlling the switching transistors in the power converter are generated based on the combination of target space vectors.

[0006] In a second aspect, embodiments of the present invention provide a control device for a power converter, comprising: The parameter acquisition module is used to acquire the reference voltage vector and DC-side current setpoint of the power converter; The space vector determination module is used to determine multiple sets of candidate space vector combinations based on the reference voltage vector; each set of candidate space vector combinations corresponds to multiple instantaneous DC current values; The target space vector combination selection module is used to calculate the deviation evaluation result for each group of candidate space vector combinations based on the multiple instantaneous DC current values ​​corresponding to the group of candidate space vector combinations and the given DC current value, and select the candidate space vector combination with the smallest deviation evaluation result as the target space vector combination. The drive signal generation module is used to generate drive signals for controlling the switching transistors in the power converter based on the combination of target space vectors.

[0007] Thirdly, embodiments of this application provide a power converter including a controller, the controller including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the control method of the power converter as described in any possible implementation of the first aspect above.

[0008] Fourthly, embodiments of this application provide a power supply device that includes the power converter as described in the third aspect.

[0009] This invention provides a power converter and its control method, apparatus, and power supply device. The method iterates through multiple vector combinations corresponding to the same reference voltage vector and selects the optimal one based on minimizing DC-side current ripple. This ensures that several instantaneous levels of the DC-side current closely vary around a given value within a switching cycle, significantly reducing high-frequency fluctuations in the DC-side current. Since the ripple current borne by the DC bus capacitor is equal to the difference between the instantaneous DC-side current and the given value, reduced current fluctuations mean a lower effective value of the capacitor ripple current. This significantly reduces dielectric losses and heat generation within the capacitor, delays electrolyte evaporation or film aging, and extends the capacitor's lifespan. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the power converter provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the implementation of the control method for the power converter provided in this embodiment of the invention. Figure 3 This is a schematic diagram of the spatial vector hexagon provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a three-phase switch sequence provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the control device for the power converter provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the controller provided in an embodiment of the present invention. Detailed Implementation

[0012] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0013] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0014] Figure 1 The circuit diagram of the power converter provided in the embodiment of the present invention is shown below. Figure 1 For this type of power converter, Space Vector Pulse Width Modulation (SVPWM) is commonly used to synthesize the desired AC-side voltage. In traditional SVPWM, to obtain a symmetrical switching sequence and reduce output line voltage harmonics, the zero vectors are typically concentrated in the middle of the switching cycle or symmetrically distributed on both sides, forming a space vector arrangement such as P (high level) in the middle and N (low level) on both sides, or vice versa. Taking a three-phase voltage source power converter as an example, the DC-side input current... i dc Directly determined by the switch state and AC side current, it can be expressed as ,in For the three-phase bridge arm switching function, This is a three-phase alternating current. During the zero vector (NNN or PPP) period, regardless of the AC side current, i dcAll are forced to zero; only during the action of non-zero vectors, i dc This is equal to the AC current of the corresponding phase or a combination thereof. Traditional seven-segment SVPWM concentrates the two zero vectors at the ends and the very middle of the switching cycle, causing... i dc Within each switching cycle, a waveform alternating between long zero intervals and short pulses is formed, characterized by "zero current - pulse current - zero current - pulse current - zero current". This waveform exhibits a high peak-to-average power ratio and high harmonic content. Because the DC bus capacitor needs to be bypassed... i dc The high-frequency ripple component in the capacitor is used to maintain a stable DC voltage. The magnitude of the ripple current flowing through the capacitor is almost equal to the intensity of that fluctuating component in the total DC bus current. The existence of long zero intervals means that reactive current only flows through the capacitor and the switching transistor, further increasing the charging and discharging burden on the capacitor. Therefore, traditional centralized zero vector sorting inevitably leads to the DC bus capacitor bearing a large value of high-frequency ripple current. Large capacitor ripple current will aggravate the dielectric loss and heat generation inside the capacitor, accelerate electrolyte evaporation or film aging under long-term operation, significantly shorten the capacitor's lifespan, and reduce the overall reliability of the system.

[0015] To address the aforementioned issues, this application selects a spatial vector combination with the smallest deviation between the instantaneous DC current value and the given value. This effectively suppresses DC-side current ripple, significantly reduces ripple current stress on the bus capacitor, reduces capacitor heating, thereby extending capacitor life and improving system reliability.

[0016] See Figure 2 This document illustrates a flowchart of the implementation of a control method for a power converter provided in an embodiment of the present invention. This method can be applied to applications such as... Figure 1 The three-phase rectifier described above can also be applied to other power converters such as inverters. This embodiment takes a three-phase rectifier as an example and describes the control method of the power converter in detail below: S101: Obtain the reference voltage vector and DC-side current setpoint of the power converter.

[0017] In this embodiment, the reference voltage vector is the desired AC-side synthesized voltage vector calculated according to the system control objective, and it serves as the reference for space vector modulation.

[0018] The DC-side current setpoint is the system's desired average DC-side current value, output from the DC voltage outer loop, used to balance the power between the AC and DC sides.

[0019] The calculation process for the reference voltage vector is as follows: First, calculate the amplitude of the AC side current setpoint based on the DC side current setpoint. The specific formula is as follows: ,in, This indicates the magnitude of the AC side current setpoint. This indicates the DC-side current setpoint. This represents the voltage across the DC-side capacitor. This indicates the phase voltage amplitude of the power grid.

[0020] Secondly, the phase of the grid voltage is obtained through a phase-locked loop. Determine the instantaneous setpoint of the three-phase current ( The specific calculation formula is as follows: ; The instantaneous setpoint of the three-phase current ( The current setpoint on the d-axis is obtained by transforming the abc coordinate system into the dq-axis coordinate system. and q-axis current setpoint And further calculate the d-axis voltage setpoint. and q-axis voltage setpoint The calculation formula is as follows: ; in, This indicates the proportional gain of the current loop. This represents the integral gain of the current loop. This represents the actual value of the d-axis current. This represents the actual value of the q-axis current. e d and e q This represents the components of the grid voltage in the dq rotating coordinate system. This indicates a decoupling term.

[0021] The calculated d-axis voltage setpoint and q-axis voltage setpoint Perform an inverse coordinate transformation, converting from the dq-axis coordinate system to... Using the axial coordinate system, the reference voltage vector in the stationary coordinate system is obtained. and Reference voltage vector based on stationary coordinate system and Then, alternative spatial vector combinations are selected.

[0022] S102: Based on the reference voltage vector, determine multiple sets of candidate space vector combinations; each set of candidate space vector combinations corresponds to multiple instantaneous DC current values.

[0023] In this embodiment, for a three-phase two-level rectifier, multiple sets of candidate space vector combinations are determined based on the sectors within the space vector hexagon where the reference voltage vector falls. The reference voltage vector can be synthesized from the three basic voltage vectors in the space vector hexagon. The space vector hexagon is a complex plane region divided by the basic voltage vectors. A traditional two-level converter is divided into six space vector sectors, each sector being enclosed by two adjacent non-zero basic voltage vectors and a zero vector.

[0024] In one possible implementation, the specific implementation process of S102 includes: Determine the space vector sector where the reference voltage vector is located, and use it as the target sector; Based on the target sector corresponding to the reference voltage vector, a variety of alternative space vector combinations are determined.

[0025] The instantaneous value of DC current is the instantaneous value of the DC-side current of the power converter when a certain basic voltage vector is applied.

[0026] Specifically, will Reference voltage vector in axial coordinate system and Substitute into the formula Determine the reference voltage vector V ref The phase. It can also be... Reference voltage vector in axial coordinate system and Substitute into the formula The magnitude of the reference voltage vector is obtained.

[0027] refer to Figure 3 The phase angle of the reference voltage The magnitude and value of the reference voltage vector are used to determine the sector of the space vector hexagon that the reference voltage vector falls into. Finally, based on the sector where the reference voltage vector lies, multiple candidate space vector combinations are determined. Each space vector combination includes three basic voltage vectors, each corresponding to an instantaneous DC current value. For example... Figure 3 The reference voltage vector falls into the second sector of the space vector hexagon. Based on the magnitude of this reference voltage vector, the first candidate space vector combination can be determined as NPN, PPN, and PPP; the second candidate space vector combination can be NPP, NPN, and PPN; and the third candidate space vector combination can be NPN, PPN, and PNN. Here, P represents level 1, and N represents level 0. For the first candidate space vector combination, NPN represents a three-phase level of 010, i.e. Figure 1In the first bridge arm, the upper switch Q31 is turned off and the lower switch Q32 is turned on; in the second bridge arm, the upper switch Q33 is turned on and the lower switch Q34 is turned off; in the third bridge arm, the upper switch Q35 is turned off and the lower switch Q36 is turned on. The instantaneous DC current corresponding to this space vector is... i b If PPN represents a three-phase level of 110, then the instantaneous value of the DC current corresponding to this space vector is - i c If PPP represents a three-phase level of 111, then the instantaneous value of the DC current corresponding to the space vector is 0.

[0028] S103: For each group of candidate space vector combinations, calculate the deviation evaluation result based on the multiple instantaneous DC current values ​​corresponding to the group of candidate space vector combinations and the given DC current value, and select the candidate space vector combination with the smallest deviation evaluation result as the target space vector combination.

[0029] In this embodiment, the deviation evaluation result is a scalar index reflecting the overall degree of deviation between the instantaneous DC current value sequence under the action of the candidate space vector combination and the DC side current setpoint. The smaller the deviation evaluation result, the closer the instantaneous DC current value corresponding to the candidate space vector combination is to the DC side current setpoint; the larger the deviation evaluation result, the greater the difference between the instantaneous DC current value corresponding to the candidate space vector combination and the DC side current setpoint.

[0030] Since capacitor ripple current is essentially a DC-side pulse current i dc The difference between the DC-side current and the given DC-side current is used to iterate through all possible spatial vector combinations generated by the same reference voltage vector, and the spatial vector combination with the smallest deviation evaluation result is selected. Essentially, from all feasible switching sequences, the sequence that makes the DC-side current waveform closest to the given DC-side current, with the smallest ripple amplitude and zero current range is chosen. This sequence significantly reduces the high-frequency ripple component flowing into the DC-side capacitor by making the instantaneous value of the DC-side current fluctuate closely around the given DC-side current, thereby reducing the ripple current stress and internal heat loss of the DC-side capacitor from the source.

[0031] S104: Generate drive signals to control the switching transistors in the power converter based on the combination of target space vectors.

[0032] In this embodiment, the controller inputs the target space vector combination into the modulation module to generate a drive signal for controlling the switching transistors in the power converter. This drive signal can be a PWM (Pulse Width Modulation) signal. The modulation method in the modulation module can be SVPWM (Space Vector Pulse Width Modulation) or CBPWM (Carrier Based Pulse Width Modulation).

[0033] As can be seen from the above embodiments, this embodiment obtains a reference voltage vector and a DC-side current setpoint, and then determines multiple sets of candidate space vector combinations that can synthesize the reference voltage vector. Each set of combinations corresponds to a different sequence of instantaneous DC current values. Subsequently, based on the deviation evaluation results, the combination with the smallest deviation between the instantaneous value and the setpoint is selected as the target space vector combination, and a drive signal is generated accordingly. This process ensures that within one switching cycle, multiple instantaneous levels of the DC-side current fluctuate slightly around the DC-side current setpoint, fundamentally avoiding the large-amplitude pulsations caused by the concentrated arrangement of zero vectors in traditional seven-segment SVPWM, which cause the current to periodically drop to zero. Since the ripple current borne by the DC bus capacitor is equal to the difference between the DC-side pulse current and the DC-side current setpoint, the reduction in current fluctuation directly means a significant reduction in the effective value of the ripple current flowing through the capacitor. According to Joule's law, the heat loss on the equivalent series resistance inside the capacitor is proportional to the square of the effective value of the ripple current. Therefore, this method can effectively suppress the capacitor temperature rise, slow down the electrolyte evaporation or metallization film aging process, thereby significantly extending the capacitor's service life and improving the overall reliability of the power conversion system. At the same time, this method is implemented only through software algorithms, without the need for additional hardware costs, and has strong versatility.

[0034] In one possible implementation, the specific implementation process of S103 includes: Calculate the difference between the instantaneous value of the DC current and the given value of the DC side current in each of the first candidate space vector combinations; the first candidate space vector combination is any candidate space vector combination; The deviation evaluation result of the first candidate space vector combination is calculated based on the difference between the instantaneous value of the DC current and the given value of the DC side current in each of the first candidate space vector combinations.

[0035] In this embodiment, the controller can calculate the difference between the instantaneous value of the DC current corresponding to each basic voltage vector in any candidate space vector combination and the given value of the DC side current, and then obtain the deviation evaluation result based on the current difference corresponding to each basic voltage vector.

[0036] Specifically, in this embodiment, the three instantaneous DC current values ​​can be subtracted from the given DC current value, and the three differences can be summed to obtain the deviation evaluation result. For example, taking the first alternative space vector combination NPN, PPN, and PPP as an example, then... Based on the deviation evaluation results J The size determines the final target space vector combination.

[0037] As can be seen from the above embodiments, since the difference directly reflects the magnitude and direction of the DC-side current deviating from the target value during the action of each basic voltage vector, and these instantaneous deviations are superimposed to form the complete waveform of the capacitor ripple current, the evaluation function constructed based on the difference can accurately quantify the ripple intensity generated by different combinations of space vectors, ensuring strict consistency between the optimal target and the capacitor stress. Ultimately, by accurately evaluating and selecting the candidate space vector combination with the smallest deviation, the high-frequency ripple current borne by the DC bus capacitor is effectively suppressed, the internal heating of the capacitor is significantly reduced, and the long-term operational reliability is improved.

[0038] In one possible implementation, the specific implementation process of calculating the deviation evaluation result of the first candidate space vector combination based on the difference between the instantaneous value of the DC current and the given value of the DC side current in S103 above includes: Based on formula Calculate the deviation evaluation result between the group of candidate space vector combinations and the given DC side current value; Among them, the These are the instantaneous DC current values ​​corresponding to the three voltage vectors, respectively; This represents the DC-side current setpoint. J This indicates the deviation evaluation result.

[0039] Understandably, in this embodiment, the sum of the absolute values ​​of the differences between each instantaneous DC current value and the given DC current value can also be used as the deviation calculation result; alternatively, it can be based on the formula. or Calculate the deviation evaluation results.

[0040] As can be seen from the above embodiments, within a switching cycle, the square of the effective value of the ripple current flowing through the DC bus capacitor is exactly equal to the weighted average of the squares of the current deviations of each segment with respect to their respective durations. When the weights are equal or the duty cycle differences are negligible, this sum of squares is directly proportional to the ripple energy within that cycle. Therefore, minimizing this sum of squares essentially means selecting the combination that minimizes the total energy of the capacitor ripple current among all candidate space vector combinations that can synthesize the same reference voltage vector. Furthermore, the square operation has an amplifying effect on large deviations, making the deviation evaluation results particularly sensitive to extreme deviations such as the current dropping to zero due to the zero vector. This effectively rejects combinations with traditional concentrated zero vector arrangements, tending to select sequences where each level is close to the given value of the DC side current. Consequently, the effective value of the capacitor ripple current decreases significantly, the heat loss on its internal equivalent series resistance decreases by a square factor, the capacitor temperature rise is effectively suppressed, and the aging process is significantly delayed.

[0041] In one possible implementation, the multiple sets of alternative spatial vector combinations include a first type of vector combination and / or a second type of vector combination; The first type of vector combination includes two non-zero basic voltage vectors and a zero vector corresponding to the target sector; The second type of vector combination includes three basic voltage vectors, and at least one of the three basic voltage vectors does not belong to the target sector.

[0042] This embodiment explicitly divides the candidate space vector combinations into a first type of vector combination and a second type of vector combination. The first type of vector combination is the "two non-zero vectors + zero vector" combination used in traditional SVPWM, while the second type of vector combination is a three-vector combination that includes basic voltage vectors across sectors. This combination breaks the limitations of traditional sector boundaries, enabling the acquisition of more DC-side current waveforms, thereby finding a solution with smaller ripple.

[0043] Specifically, the non-zero basic voltage vectors in the space vector hexagon correspond to the vectors in the power converter switching state where the three-phase bridge arms are neither fully on nor fully off. There are a total of 6 vectors with equal amplitudes and phases that differ by 60°. The zero vector corresponds to the vectors in the three-phase bridge arms that are fully on (PPP) or fully off (NNN). There are a total of 2 vectors with an amplitude of 0.

[0044] The first type of vector combination can be formed by two adjacent non-zero vectors and a zero vector of the target sector, for example, Figure 3 In sector II, the corresponding first-type vector combinations are NPN, PPP, and PPN. The first-type vector combination ensures reliable synthesis of the reference voltage vector at any modulation ratio and inherits the mature performance of traditional modulation in terms of switching losses and output harmonics.

[0045] The second type of vector combination consists of three basic voltage vectors, and at least one of the basic voltage vectors does not belong to the target sector. If there are two basic voltage vectors that belong to the target sector, then the two basic voltage vectors can be two non-zero basic voltage vectors corresponding to the target sector, or a zero vector and a non-zero basic voltage vector corresponding to the target sector. The other basic voltage vector can be a non-zero basic voltage vector in an adjacent sector of the target sector. The specific selection method of the vector can be determined by combining the phase and amplitude of the reference voltage vector.

[0046] The second type of vector combination breaks the dependence of vector synthesis on sector boundaries and zero vectors, enabling the construction of switching sequences without zero vectors. Throughout the switching cycle, the second type of vector combination avoids the extreme deviation state where the DC-side current is forced to zero during the action of the zero vector, ensuring that the DC current fluctuates slightly around the given value of the DC-side current, greatly reducing the peak-to-average power ratio and effective value of the current ripple. Therefore, the high-frequency ripple current flowing through the DC bus capacitor is significantly reduced at its source, and the capacitor heating is correspondingly reduced. At the same time, the introduction of non-adjacent vectors enriches the combination form of the instantaneous value of the DC current, enhancing the algorithm's adaptability to ripple suppression under different power factor angles. The hybrid alternative of the two types of combinations ensures both the feasibility and robustness of voltage synthesis, while providing a breakthrough optimization space for minimizing ripple, achieving the optimal balance between ripple suppression and operational reliability.

[0047] In one possible implementation, the specific implementation process of S104 includes: The duty cycle of the three phases is determined based on the target space vector combination, and the comparison value of each phase is determined according to the duty cycle of the duty cycle of each phase. The basic voltage vectors in the target space vector combination are arranged into a three-corresponding switching sequence using a centrally symmetric method; If the target space vector combination is a second type of vector combination, then the carriers of the two phases with opposite center levels will be phase-shifted. ; The phase in the switching sequence that maintains the level at the target level is designated as the specified phase, and the corresponding PWM signal is clamped to the target level; and for the remaining phases other than the specified phase, a PWM signal is generated according to the corresponding carrier signal and comparison value. The target level is either high or low.

[0048] Specifically, the detailed implementation process for determining the three-phase conduction time duty cycle based on the target space vector combination includes: Based on the target space vector combination, the reference voltage vector, and the volt-second balance principle, determine the duration of action of each space vector in the target space vector combination; Based on the action time of each spatial vector, the basic voltage vectors in the target spatial vector combination are arranged into a three-corresponding switching sequence using a centrally symmetric method. The duty cycle of each phase is determined based on the duration of action of each space vector.

[0049] In this embodiment, taking the target space vector combination as PNN, PPN, and NPN as an example, with action times of T1, T2, and T3 respectively, the switch sequence generated based on the centrosymmetric method is as follows: By traversing this sequence, the total conduction time of each phase's upper tube can be obtained: Phase a conduction period: ; Phase b conduction period: ; Phase c conduction period: No conduction throughout, which is 0.

[0050] Then the duty cycles d1, d2, and d3 of the three basic voltage vectors are converted into the conduction duty cycles of the three-phase upper transistors. D a , D b and D c ,and , , .

[0051] Next, for each phase, according to the formula Calculate the comparison value.

[0052] After determining the comparison value, this embodiment uses a triangular carrier as the carrier signal. For each phase, the counter increments and is less than... cmp x When the count value is greater than 1, the upper transistor outputs a low level; when the count value is greater than 1, the upper cmp x When the timer reaches its peak, the upper transistor outputs a high level. After the counter reaches its peak value, it decrements, and the comparison is repeated. This naturally generates a PWM wave that is symmetrical about the period center.

[0053] Specifically, for the second type of vector combination, after arranging the basic voltage vectors in a centrally symmetrical manner, the generated switching sequence will result in one phase maintaining a high or low level throughout the entire cycle (i.e., clamping), while the other two phases require switching actions. (Reference) Figure 4 Based on the second type of vector combination NPP, PPN, and NPN, the generated three-phase switching sequence is as follows: Figure 4As shown, phase B is at a low level throughout the entire switching cycle, while phases A and C perform switching actions. At this time, the PWM signal of phase B is directly clamped to 0. Simultaneously, for phases A and C, since their center levels are opposite (phase A's center level is P, and phase C's center level is N), if these two phases still use carrier signals of the same phase, based on the requirement that the pulse sequence be mirror-symmetrical at the midpoint of the cycle according to the central symmetry arrangement, the switching action of one phase will not be synchronized with the other. Specifically, when phase A's carrier matches its own comparison value, phase C needs to wait for a carrier with a 180-degree phase difference to be completely opposite to phase A's carrier before it can match the comparison value to generate a PWM signal with a center level opposite to that of phase A's PWM signal within one switching cycle. This not only disrupts the central symmetry timing structure but may also lead to output pulse misalignment, line voltage distortion, or even the clamped phase being forced to participate in unnecessary switching.

[0054] To address this issue, this embodiment shifts the two carrier phases with opposite center levels by 180 degrees. After the phase shift, the rising and falling edges of the two carrier phases within the cycle are precisely staggered, allowing their respective comparison values ​​to intersect with their respective carrier signals simultaneously without additional waiting. This ensures the precise timing and central symmetry of the switching actions of the remaining two phases while keeping the clamped phase inactive. This method enables the second type of vector combination to correctly and reliably generate PWM waveforms while achieving low capacitance ripple characteristics. It avoids the delay problem caused by the synchronous carrier while ensuring fewer switching operations, and also eliminates the full-cycle switching loss of the specified phase through clamping.

[0055] In one possible implementation, the method provided in this embodiment further includes: If the target space vector combination is a first type of vector combination, then the corresponding PWM signal is generated by comparing the synchronous carrier signal with the comparison value of each phase.

[0056] This embodiment focuses on the generation of drive signals for the first type of vector combination, using the traditional carrier comparison method. Since the first type of vector combination includes a zero vector, its switching sequence is compatible with traditional SVPWM, eliminating the need for additional carrier phase shifting and clamping operations, thus ensuring the compatibility and simplicity of the control method.

[0057] The controller compares the comparison value with the carrier signal. When the comparison value is greater than the carrier signal, it outputs a high level; otherwise, it outputs a low level, thereby generating a PWM signal.

[0058] The control method for the power converter proposed in this application is not limited to three-phase two-level power converters, but is also applicable to three-level and other arbitrary multi-level power conversion circuits. The core control logic framework of this application remains completely unchanged, and only needs to be adapted and adjusted for different level topologies, such as the basic voltage vector set, the space vector sector division rules, and the calculation method of the instantaneous DC current value corresponding to each basic voltage vector.

[0059] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0060] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0061] Figure 5 A schematic diagram of the control device for a power converter provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: like Figure 5 As shown, the control device 100 of the power converter includes: Parameter acquisition module 110 is used to acquire the reference voltage vector and DC side current setpoint of the power converter; The space vector determination module 120 is used to determine multiple sets of candidate space vector combinations based on the reference voltage vector; each set of candidate space vector combinations corresponds to multiple instantaneous DC current values; The target space vector combination selection module 130 is used to calculate the deviation evaluation result for each group of candidate space vector combinations based on the multiple instantaneous values ​​of DC current corresponding to the group of candidate space vector combinations and the given value of DC side current, and select the candidate space vector combination with the smallest deviation evaluation result as the target space vector combination. The drive signal generation module 140 is used to generate drive signals for controlling the switching transistors in the power converter based on the combination of target space vectors.

[0062] In one possible implementation, the target space vector combination selection module 130 includes: Calculate the difference between the instantaneous value of the DC current and the given value of the DC side current in each of the first candidate space vector combinations; the first candidate space vector combination is any candidate space vector combination; The deviation evaluation result of the first candidate space vector combination is calculated based on the difference between the instantaneous value of the DC current and the given value of the DC side current in each of the first candidate space vector combinations.

[0063] In one possible implementation, the target space vector combination selection module 130 is specifically used for: Based on formula Calculate the deviation evaluation result between the group of candidate space vector combinations and the given DC side current value; Among them, the These are the instantaneous DC current values ​​corresponding to the three voltage vectors, respectively; This represents the DC-side current setpoint. J This indicates the deviation evaluation result.

[0064] In one possible implementation, the space vector determination module 120 includes: Determine the space vector sector where the reference voltage vector is located, and use it as the target sector; Based on the target sector corresponding to the reference voltage vector, a variety of alternative space vector combinations are determined.

[0065] In one possible implementation, the multiple sets of alternative spatial vector combinations include a first type of vector combination and / or a second type of vector combination; The first type of vector combination includes two non-zero basic voltage vectors and a zero vector corresponding to the target sector; The second type of vector combination includes three basic voltage vectors, and at least one of the three basic voltage vectors does not belong to the target sector.

[0066] In one possible implementation, the drive signal is a PWM signal; the drive signal generation module 140 is specifically used for: The duty cycle of the three phases is determined based on the target space vector combination, and the comparison value of each phase is determined according to the duty cycle of the duty cycle of each phase. The basic voltage vectors in the target space vector combination are arranged into a three-corresponding switching sequence using a centrally symmetric method; If the target space vector combination is a second type of vector combination, then the carriers of the two phases with opposite center levels will be phase-shifted. ; The phase in the switching sequence that maintains the level at the target level is designated as the specified phase, and the corresponding PWM signal is clamped to the target level; and for the remaining phases other than the specified phase, a PWM signal is generated according to the corresponding carrier signal and comparison value. The target level is either high or low.

[0067] In one possible implementation, the drive signal generation module 140 is further configured to: If the target space vector combination is a first type of vector combination, then the corresponding PWM signal is generated by comparing the synchronous carrier signal with the comparison value of each phase.

[0068] Figure 6 This is a schematic diagram of the controller provided in an embodiment of the present invention. Figure 6 As shown, the controller 6 in this embodiment includes a processor 60, a memory 61, and a computer program 62 stored in the memory 61 and executable on the processor 60. When the processor 60 executes the computer program 62, it implements the steps in the control method embodiments of the various power converters described above, for example... Figure 2 Steps S101 to S104 are shown. Alternatively, when the processor 60 executes the computer program 62, it implements the functions of each module / unit in the above-described device embodiments.

[0069] For example, the computer program 62 can be divided into one or more modules / units, which are stored in the memory 61 and executed by the processor 60 to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 62 in the controller 6. For example, the computer program 62 can be divided into... Figure 5 Modules 110 to 140 are shown.

[0070] The controller 6 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The controller 6 may include, but is not limited to, a processor 60 and a memory 61. Those skilled in the art will understand that... Figure 6 This is merely an example of controller 6 and does not constitute a limitation on controller 6. It may include more or fewer components than shown, or combine certain components, or different components. For example, the controller may also include input / output devices, network access devices, buses, etc.

[0071] The processor 60 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0072] The memory 61 can be an internal storage unit of the controller 6, such as a hard disk or memory of the controller 6. The memory 61 can also be an external storage device of the controller 6, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the controller 6. Furthermore, the memory 61 can include both internal storage units and external storage devices of the controller 6. The memory 61 is used to store the computer program and other programs and data required by the controller. The memory 61 can also be used to temporarily store data that has been output or will be output.

[0073] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0074] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0075] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0076] In the embodiments provided by this invention, it should be understood that the disclosed devices / controllers and methods can be implemented in other ways. For example, the device / controller embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0079] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the control method embodiments of the various power converters described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0080] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A control method for a power converter, characterized in that, include: Obtain the reference voltage vector and DC-side current setpoint of the power converter; Based on the reference voltage vector, multiple sets of alternative space vector combinations are determined; Each set of candidate space vector combinations corresponds to multiple instantaneous DC current values; For each set of candidate space vector combinations, based on the multiple instantaneous DC current values ​​corresponding to the set of candidate space vector combinations and the given DC current value, the deviation evaluation result is calculated, and the candidate space vector combination with the smallest deviation evaluation result is selected as the target space vector combination. The drive signals for controlling the switching transistors in the power converter are generated based on the combination of target space vectors.

2. The control method for the power converter according to claim 1, characterized in that, The deviation evaluation result is calculated based on the multiple instantaneous DC current values ​​corresponding to the set of candidate space vector combinations and the given DC current value, including: Calculate the difference between the instantaneous value of the DC current and the given value of the DC side current in each of the first candidate space vector combinations; the first candidate space vector combination is any candidate space vector combination; The deviation evaluation result of the first candidate space vector combination is calculated based on the difference between the instantaneous value of the DC current and the given value of the DC side current in each of the first candidate space vector combinations.

3. The control method for the power converter according to claim 2, characterized in that, The step of calculating the deviation evaluation result of the first candidate space vector combination based on the difference between the instantaneous value of the DC current and the given value of the DC side current in each candidate space vector combination includes: Based on formula Calculate the deviation evaluation result between the group of candidate space vector combinations and the given DC side current value; Among them, the These are the instantaneous DC current values ​​corresponding to the three voltage vectors, respectively; This represents the DC-side current setpoint. J This indicates the deviation evaluation result.

4. The control method for the power converter according to claim 1, characterized in that, The step of determining multiple sets of candidate space vector combinations based on the reference voltage vector includes: Determine the space vector sector where the reference voltage vector is located, and use it as the target sector; Based on the target sector corresponding to the reference voltage vector, a variety of alternative space vector combinations are determined.

5. The control method for the power converter according to claim 4, characterized in that, The multiple sets of alternative spatial vector combinations include a first type of vector combination and / or a second type of vector combination; The first type of vector combination includes two non-zero basic voltage vectors and a zero vector corresponding to the target sector; The second type of vector combination includes three basic voltage vectors, and at least one of the three basic voltage vectors does not belong to the target sector.

6. The control method for the power converter according to claim 5, characterized in that, The driving signal is a PWM signal; the generation of the driving signal for controlling the switching transistors in the power converter based on the target space vector combination includes: The duty cycle of the three phases is determined based on the target space vector combination, and the comparison value of each phase is determined according to the duty cycle of the duty cycle of each phase. The basic voltage vectors in the target space vector combination are arranged into a three-corresponding switching sequence using a centrally symmetric method; If the target space vector combination is a second type of vector combination, then the carriers of the two phases with opposite center levels will be phase-shifted. ; The phase in the switching sequence that maintains the level at the target level is designated as the specified phase, and the corresponding PWM signal is clamped to the target level; and for the remaining phases other than the specified phase, a PWM signal is generated according to the corresponding carrier signal and comparison value. The target level is either high or low.

7. The control method for the power converter according to claim 6, characterized in that, The method further includes: If the target space vector combination is a first type of vector combination, then the corresponding PWM signal is generated by comparing the synchronous carrier signal with the comparison value of each phase.

8. A control device for a power converter, characterized in that, include: The parameter acquisition module is used to acquire the reference voltage vector and DC-side current setpoint of the power converter; The space vector determination module is used to determine multiple sets of candidate space vector combinations based on the reference voltage vector; each set of candidate space vector combinations corresponds to multiple instantaneous DC current values; The target space vector combination selection module is used to calculate the deviation evaluation result for each group of candidate space vector combinations based on the multiple instantaneous DC current values ​​corresponding to the group of candidate space vector combinations and the given DC current value, and select the candidate space vector combination with the smallest deviation evaluation result as the target space vector combination. The drive signal generation module is used to generate drive signals for controlling the switching transistors in the power converter based on the combination of target space vectors.

9. A power converter, comprising a controller, the controller including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the control method for the power converter as described in any one of claims 1 to 6.

10. A power supply device, characterized in that, include: The power converter as described in claim 9.

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