Voltage generating device and charge pump circuit thereof

Abstract

The present application provides a voltage generating device and a charge pump circuit thereof. The charge pump circuit includes a plurality of serially coupled charge pump units, a first capacitor and a voltage divider capacitor. The charge pump units include a first charge pump unit configured to generate a first pumped voltage and a second charge pump unit configured to generate a second pumped voltage. The first capacitor is coupled between the first pumped voltage and a first clock signal. The voltage divider capacitor is coupled between the second pumped voltage and a second clock signal and receives a bias voltage, wherein the bias voltage is less than the second pumped voltage and greater than a reference ground voltage.

Description

Technical Field

[0001] This invention relates to a voltage generating device and its charge pump circuit, and more particularly to a more sustainable internal voltage generating device and its charge pump circuit. Background Technology

[0002] In electronic devices, an internal voltage generation device is typically required to generate an internal voltage. For example, in flash memory, an internal voltage generation device with a charge pump circuit is usually provided to generate a programming voltage higher than the operating voltage.

[0003] Known voltage generating devices include multi-stage charge pump units paired with capacitors at the output, which can generate a boosted voltage by pumping up a reference voltage. As the voltage pumping operation continues, subsequent charge pump units can generate higher boosted voltages. When the voltage pumping operation of a charge pump unit stops, one end of the capacitor corresponding to the subsequent charge pump unit can receive a higher boosted voltage, while the other end of the capacitor may receive a lower reference voltage or reference ground voltage. This results in a high voltage difference across the capacitor, leading to a reduction in capacitor lifespan, and consequently affecting the lifespan of the voltage generating device and the overall system. Summary of the Invention

[0004] This invention relates to a voltage generating device and its charge pump circuit, which can prevent the capacitor in the charge pump unit from being subjected to a high voltage difference.

[0005] According to an embodiment of the present invention, a charge pump circuit includes a plurality of series-coupled charge pump units, a first capacitor, and a voltage divider capacitor. The charge pump units include a first charge pump unit and a second charge pump unit, the first charge pump unit being configured to generate a first pump-up voltage, and the second charge pump unit being configured to generate a second pump-up voltage. The first capacitor is coupled between the first pump-up voltage and a first clock signal. The voltage divider capacitor is coupled between the second pump-up voltage and the second clock signal, and receives a bias voltage, wherein the bias voltage is less than the second pump-up voltage and greater than a reference ground voltage.

[0006] According to an embodiment of the present invention, the voltage generating device includes a charge pump circuit as described above and an enable signal generator. The charge pump circuit provides an output pump-up voltage. The enable signal generator is coupled to the voltage generating device to generate an enable signal for disabling or enabling the charge pump circuit based on a comparison between the output pump-up voltage and a reference voltage.

[0007] Based on the above, in the charge pump circuit of the present invention, the output terminals of one or more charge pump units are coupled to a voltage divider capacitor. Furthermore, the voltage divider capacitor receives a bias voltage that is less than the second pump-up voltage but greater than the reference ground voltage. This avoids a high voltage difference across the capacitor, effectively extending its lifespan and meeting the requirements of green semiconductors. Attached Figure Description

[0008] Figure 1 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown;

[0009] Figure 2 A schematic diagram of a clock signal generator according to an embodiment of the present invention is shown;

[0010] Figure 3A as well as Figure 3B The diagram shows the operating waveform of the charge pump circuit according to an embodiment of the present invention.

[0011] Figure 4A , Figure 4B as well as Figure 4C Schematic diagrams of a charge pump circuit according to another embodiment of the present invention are shown respectively;

[0012] Figure 5A as well as Figure 5B Schematic diagrams of voltage generating devices according to different embodiments of the present invention are shown. Detailed Implementation

[0013] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0014] Please refer to Figure 1 The charge pump circuit 100 of this embodiment includes multiple charge pump units 111-11N, multiple capacitors C1-CM, and a voltage divider capacitor 120. The voltage divider capacitor 120 may include a capacitor string CS1 and a bias generator 130. These charge pump units 111-11N are connected in series. The first-stage charge pump unit 111 receives a reference voltage VCC and performs a charge pump operation on the reference voltage VCC to generate a pumped voltage V1. The second-stage charge pump unit 112 receives the pumped voltage V1 and increases the pumped voltage V1 to generate a pumped voltage V2. And so on, the charge pump units 111-11N can perform a step-by-step charge pump operation on the reference voltage VCC to generate sequentially increasing pumped voltages V1-VN respectively. In this embodiment, the number of charge pump units 111-11N can be N, where N can be a positive integer greater than 1. The reference voltage VCC can be the power supply voltage.

[0015] In this embodiment, the number of capacitors C1 to CM can be M, where M is less than N. For example, NM=1, but this invention is not limited to this. The first terminal of each capacitor C1 to CM is coupled to the output terminal of the corresponding charge pump unit 111 to 11N, excluding charge pump unit 11J. The second terminal of each capacitor C1 to CM receives clock signal CK or clock signal CKB. The clock signal CK and clock signal CKB can be periodic signals with opposite phases.

[0016] The first end of capacitor string CS1 is coupled to the output of the corresponding J-th stage charge pump unit 11J to receive the pump-up voltage VJ. The second end of capacitor string CS1 receives a clock signal CLKB or CLK. The clock signals CLK and CLKB can be periodic signals with opposite phases or signals with different voltage values. Capacitor string CS1 may include capacitors CA1 and CA2 connected in series. The first end of capacitor CA1 is the first end of capacitor string CS1, and the second end of capacitor CA2 is the second end of capacitor string CS1. Capacitor string CS1 may have a bias node ME located between the second end of capacitor CA1 and the first end of capacitor CA2. In this embodiment, the number of capacitor strings CS1 may be one (i.e., equal to NM), but this is not a limitation of the invention.

[0017] On the other hand, bias generator 130 is coupled to capacitor string CS1 and configured to provide a bias voltage VQ to bias node ME of capacitor string CS1. In this embodiment, bias generator 130 may include a level shifter (LS) 131 and a transistor MN. The control terminal of transistor MN is coupled to level shifter 131 to receive a control voltage Vpreq. The first terminal of transistor MN receives a second input voltage less than the pump-up voltage VJ-1, such as a reference voltage VCC or a first pre-stage pump-up voltage VA. The second terminal of transistor MN is coupled to bias node ME of capacitor string CS1 to provide bias voltage VQ. The first pre-stage pump-up voltage VA may be the pump-up voltage generated by charge pump unit 11A of stage A, and A is a positive integer less than J-1, such as V1.

[0018] Voltage shifter 131 can receive a first input voltage that is greater than the second input voltage received at the first terminal of transistor MN and less than the pump-up voltage VJ. For example, when the second input voltage is the reference voltage VCC, the first input voltage can be the pump-up voltage V2. When the second input voltage is the first pre-stage pump-up voltage VA, the first input voltage can be the second pre-stage pump-up voltage VA+1. The second pre-stage pump-up voltage VA+1 can be generated by the charge pump unit 11A+1 of stage A+1. Specifically, voltage shifter 131 can receive a clock signal CLK and, based on the received input voltage (pump-up voltage V2 or second pre-stage pump-up voltage VA+1), perform a voltage shift operation on the clock signal CLK to generate a control voltage Vpreq. Transistor MN can provide the reference voltage VCC or the first pre-stage pump-up voltage VA according to the control voltage Vpreq to generate a bias voltage VQ.

[0019] Please note that in this embodiment, by providing a bias voltage VQ to the bias node ME of the capacitor string CS1 through the bias generator 130, the voltage difference across capacitor CA1 can be made equal to VJ – VQ, and the maximum voltage difference across capacitor CA2 can be made equal to VQ – VSS, where VSS is the reference ground voltage. In this way, the voltage difference between the two ends of each capacitor CA1 and CA2 can be less than VJ, which helps to improve the lifespan of capacitors CA1 and CA2 and extend the lifespan of the charge pump circuit 100. Incidentally, in this embodiment, the equivalent capacitance of the capacitor string CS1 can be equal to C. CA1 C CA2 / (C CA1 +C CA2 ), where C CA1 Let C be the capacitance value of capacitor CA1, and C CA2 This is the capacitance value of capacitor CA2.

[0020] The charge pump circuit of this embodiment may further include a clock signal generator 200 for generating clock signals CLK / CLKB. For example... Figure 2 As shown, the clock signal generator 200 may include an oscillator 210 and logic circuitry 220. The oscillator 210 is coupled to the output of an inverter INV0. The input of the inverter INV0 receives and inverts an enable signal ENB to generate an inverted enable signal EN. The enable signal ENB can be a low-logic-value active signal, while the inverted enable signal EN can be a high-logic-value active signal.

[0021] Oscillator 210 is configured to receive an inverting enable signal EN and, when the inverting enable signal EN is a high logic value, generate clock signals CK and CKB, which are periodic signals with opposite phases. In this embodiment, when the inverting enable signal EN is a low logic value, oscillator 210 can stop the clock signals CK and CKB from oscillating and maintain them at different logic values.

[0022] Logic circuit 220 is coupled to oscillator 210. Logic circuit 220 performs logical operations on enable signal ENB and clock signals CK and CKB respectively, generating clock signals CLK and CLKB respectively. In this embodiment, logic circuit 220 includes NOR gate NO2, NAND gate NA2, and inverters INV1 and INV2. NOR gate NO2 receives enable signal ENB and clock signal CK, and its output is coupled to the input of inverter INV1. NOR gate NO2 and inverter INV1 generate clock signal CLK based on the result of the logical OR operation of enable signal ENB and clock signal CK. Furthermore, NAND gate NA2 receives the inverted enable signal EN and clock signal CKB, and its output is coupled to the input of inverter INV2. NAND gate NA2 and inverter INV2 generate clock signal CLKB based on the result of the logical AND operation of inverted enable signal EN and clock signal CKB.

[0023] According to this embodiment, the logic circuit 220 is configured such that when the enable signal ENB is a low logic value, the clock signals CLK and CLKB can be periodic signals with opposite phases; when the enable signal ENB is a high logic value, the clock signal CLK can be maintained at a high logic value voltage, while the clock signal CLKB can be maintained at a high logic value voltage or a low logic value voltage.

[0024] Please refer to the following as well. Figure 1 , Figure 2 , Figure 3A as well as Figure 3B ,in Figure 3A as well as Figure 3B The diagram shows the operating waveforms of a voltage generating device according to an embodiment of the present invention. Figure 3AAs shown, when the charge pump circuit is enabled, the enable signal ENB can be a low logic value. In response, the logic circuit 220 of the clock signal generator 200 can generate clock signals CLK and CLKB, which are periodic signals with opposite phases. In response, the voltage offset unit 131 in the bias generator 130 can correspondingly generate a control voltage Vpreq, which is also a periodic signal, and can oscillate synchronously with the clock signal CLK between the second pre-stage pump-up voltage VA+1 (or pump-up voltage V2) and the reference ground voltage VSS. In response, the pump-up voltage VJ oscillates synchronously with the clock signal CLKB between the pump-up voltage VJ and the reference voltage VCC.

[0025] Here, we take the example of capacitor CA2 receiving the clock signal CLKB at its second terminal and transistor MN receiving the reference voltage VCC at its first terminal. During time points T1 to T2, based on the high logic value of the clock signal CLK, the control voltage Vpreq is at a high voltage value (e.g., the second pre-amplifier voltage VA+1), the clock signal CLKB is at a low voltage value, transistor MN can be turned on, and capacitor CA2 is charged so that the bias voltage VQ rises to equal the reference voltage VCC. Then, during time points T2 to T3, based on the low logic value of the clock signal CLK, the control voltage Vpreq is at a low voltage value (e.g., the reference ground voltage VSS), transistor MN is turned off, but based on the charged capacitor CA2, the clock signal CLKB can rise to a high voltage value, and the bias voltage VQ can be pumped up to a high voltage value greater than the reference voltage VCC.

[0026] According to this embodiment, during the generation of the pump-up voltage VN by the charge pump circuit 100, the bias voltage VQ can oscillate between the reference voltage VCC and a high voltage value greater than the reference voltage VCC, following the corresponding pump-up voltage VJ. Therefore, the voltage difference across capacitor CA1 can be less than the pump-up voltage VJ. Furthermore, the bias voltage VQ can oscillate synchronously with the voltage of the clock signal CLKB. Therefore, the voltage difference across capacitor CA2 can also be less than the pump-up voltage VJ. In other words, the bias voltage VQ can be less than the pump-up voltage VJ and greater than the reference ground voltage VSS. Thus, during the enabling period of the charge pump circuit 100, capacitors CA1 and CA2 do not need to withstand a high voltage difference, which helps to improve the service life of capacitors CA1 and CA2.

[0027] like Figure 3BAs shown, in this embodiment, when the charge pump circuit 100 is disabled, the enable signal ENB can be a high logic value. In response (e.g., at time T4), the clock signal CLK can be maintained at a high logic value, while the clock signal CLKB can be maintained at a low logic value. In response, the voltage offset unit 131 can correspondingly generate a control voltage Vpreq that maintains the second pre-stage pump-up voltage VA+1, and by turning on the transistor MN, reduce the bias voltage VQ to be equal to the reference voltage VCC. In response, the pump-up voltage is maintained at a voltage greater than the reference voltage VCC. At this time, the two ends of capacitor CA1 receive the pump-up voltage VJ and the bias voltage VQ, respectively. The two ends of capacitor CA2 receive the bias voltage VQ and the reference ground voltage VSS, respectively. That is, during the disabled period of the charge pump circuit 100, capacitors CA1 and CA2 do not need to withstand a high voltage difference, which helps to improve the service life of capacitors CA1 and CA2.

[0028] Furthermore, in another embodiment not shown, the logic circuit 220 may be configured to generate a clock signal CLKB that is maintained at a high logic value when the charge pump circuit 100 is disabled.

[0029] It should be noted that this invention does not limit the number of voltage-dividing capacitors. The following combinations... Figure 4A , Figure 4B as well as Figure 4C The present invention describes a charge pump circuit 400 according to another embodiment. The charge pump circuit 400 includes multiple stages of charge pump units (this embodiment uses six stages, i.e., charge pump units 411-416, but the invention is not limited thereto), multiple capacitors C1, C2, C3, C5, a first voltage divider capacitor 421, and a second voltage divider capacitor 422. The charge pump units 411-416 are connected in series sequentially and generate sequentially increasing pump voltages V1-V6 by performing charge pump operations. Capacitors C1, C2, C3, and C5 are respectively coupled to the output terminals of charge pump units 411, 412, 413, and 415 to receive pump voltages V1, V2, V3, and V5, respectively. The first voltage divider capacitor 421 and the second voltage divider capacitor 422 are respectively coupled to the output terminals of charge pump units 414 and 416 to receive pump voltages V4 and V6, respectively.

[0030] like Figure 4BAs shown, the first voltage divider capacitor 421 includes a voltage shifter 4211, a transistor MN1, and a capacitor string CS1 consisting of capacitors CA1 and CA2. In this embodiment, the voltage received by the voltage shifter 4211 is greater than the voltage received by the first terminal of the transistor MN1. For example, the voltage shifter 4211 generates a control voltage Vpreq1 based on the pump-up voltage V3 by shifting the voltage value of the clock signal CLKB. The voltage shifter 4211 provides the control voltage Vpreq1 to the control terminal of the transistor MN1. The first terminal of the transistor MN1 receives a reference voltage VCC. It should be noted that the voltages received by the voltage shifter 4211 and the first terminal of the transistor MN1 described above are merely examples, and the invention is not limited thereto. For example, in some embodiments not shown, when the first terminal of the transistor MN1 is configured to receive the reference voltage VCC, the voltage shifter 4211 may be configured to generate the control voltage Vpreq1 based on the pump-up voltage V2. In other embodiments, when the first terminal of transistor MN1 is configured to receive pump-up voltage V2, voltage shifter 4211 may be configured to generate control voltage Vpreq1 based on pump-up voltage V3.

[0031] In this embodiment, the first terminal of capacitor CA1 receives the pump-up voltage V4, while the second terminal of capacitor CA1 receives the bias voltage VQ1. The two terminals of capacitor CA2 receive the bias voltage VQ1 and the clock signal CLK, respectively. Transistor MN1 can generate the bias voltage VQ1 according to the control voltage Vpreq1, thereby making the voltage difference between the two terminals of capacitors CA1 and CA2 less than the pump-up voltage V4, thus improving the lifespan of capacitors CA1 and CA2.

[0032] like Figure 4C As shown, the second voltage divider capacitor 422 includes a voltage shifter 4221, a transistor MN2, and a capacitor string CS2 consisting of capacitors CB1 and CB2. The voltage received by the voltage shifter 4221 is greater than the voltage received by the first terminal of the transistor MN2. For example, in this embodiment, the voltage shifter 4221 generates a control voltage Vpreq2 based on the pump-up voltage V3 by shifting the voltage value of the clock signal CLKB. The voltage shifter 4221 provides the control voltage Vpreq2 to the control terminal of the transistor MN2. The first terminal of the transistor MN2 receives the reference voltage VCC.

[0033] Furthermore, the first terminal of capacitor CB1 receives the pump-up voltage V6, while the second terminal of capacitor CB1 receives the bias voltage VQ2. The two terminals of capacitor CB2 receive the bias voltage VQ2 and the clock signal CLK, respectively. Transistor MN2 can generate the bias voltage VQ2 according to the control voltage Vpreq2, thereby reducing the voltage difference between the two terminals of capacitors CB1 and CB2 and effectively improving their lifespan. However, in some embodiments not shown, the bias voltage VQ2 may be greater than the bias voltage VQ1.

[0034] It is worth mentioning that, in a preferred embodiment, the front-stage capacitor (e.g., capacitor C1) in the charge pump circuits 100 and 400 can be a low-voltage-tolerance transistor capacitor or a silicon oxide-silicon nitride-silicon oxide (ONO) capacitor. The intermediate-stage capacitors in the charge pump circuits 100 and 400 (e.g....) Figure 1 capacitor C2 or Figure 4A The capacitors C2 and C3 in the charge pump circuit can be ONO capacitors. The subsequent charge pump units in the charge pump circuits 100 and 400 (e.g., any one of 11J, 414-416, or any combination thereof) can be coupled to a voltage divider capacitor composed of low-voltage-resistance transistor capacitors, ONO capacitors, high-voltage-resistance transistor capacitors, or combinations thereof. Therefore, compared to using high-voltage-resistance transistors throughout the capacitors of the charge pump circuit, this embodiment can have a smaller size, which is beneficial for the miniaturization of the charge pump circuit.

[0035] For example, regarding capacitor string CS1, capacitor CA1 can be an ONO capacitor, and capacitor CA2 can be a low-voltage-tolerance transistor capacitor or an ONO capacitor. Regarding capacitor string CS2, since capacitor string CS2 receives a pump-up voltage V6 with a relatively high voltage value, capacitor CB1 can be a high-voltage-tolerance transistor capacitor, and capacitor CB2 can be an ONO capacitor.

[0036] Please refer to the following: Figure 5A as well as Figure 5B , Figure 5A as well as Figure 5B Schematic diagrams of voltage generating devices according to different embodiments of the present invention are shown. Figure 5A In this embodiment, voltage generating device 501 can be used to generate a programmed voltage VREG to perform programmed operations on memory cells, such as those in flash memory. Voltage generating device 501 includes a charge pump circuit 510 and a voltage regulator 530. The charge pump circuit 510 can generate multiple pump-up voltages and can provide the highest of these pump-up voltages to generate an output pump-up voltage VPDCHG. Details regarding the charge pump circuit 510 have been mentioned in the foregoing embodiments and will not be repeated here. In this embodiment, voltage regulator 530 may include an enable signal generator 520 and a transistor MP1.

[0037] The control terminal of transistor MP1 receives the enable signal ENB, the first terminal of transistor MP1 receives the output pump-up voltage VPDCHG, and the second terminal of transistor MP1 is used to provide the programmed voltage VREG. The enable signal generator 520 may include a voltage divider 521 and a comparator 522. The voltage divider 521 is used to divide the programmed voltage VREG to generate a divided voltage dVREG. The comparator 522 is used to compare the divided voltage dVREG with the reference voltage VREF and generate the enable signal ENB based on the comparison result.

[0038] In detail, when the voltage divider 521 generates a voltage divider voltage dVREG greater than or equal to the reference voltage VREF, comparator 522 generates an enable signal ENB with a logic value of 1, turning off transistor MP1 and disabling the charge pump circuit 510. When the voltage divider voltage dVREG is less than the reference voltage VREF, comparator 522 generates an enable signal ENB with a logic value of 0, turning on transistor MP1 and enabling the charge pump circuit 510.

[0039] and Figure 5A The difference between the embodiments is that, Figure 5B The voltage regulator 530' in the voltage generating device 502 shown does not have a transistor MP1. The output pump-up voltage (e.g., the maximum pump-up voltage) generated by the charge pump circuit 510 can be directly used as the programmed voltage VREG.

[0040] In summary, the voltage generating device and its charge pump circuit of the present invention couple the output terminal of a portion (preferably a later stage) of the charge pump unit to a voltage divider capacitor and apply a specific bias voltage to the voltage divider capacitor. In this way, the voltage difference between the two terminals of each capacitor in the voltage divider capacitor can be effectively reduced, avoiding the reduction in lifespan caused by prolonged exposure to high voltage differences across the capacitors. Thus, the lifespan of the voltage generating device and its charge pump circuit can be improved, meeting the requirements of green semiconductors.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A charge pump circuit, comprising: Multiple charge pump units coupled in series, including a first charge pump unit and a second charge pump unit, wherein the first charge pump unit is configured to generate a first pump-up voltage and the second charge pump unit is configured to generate a second pump-up voltage; A first capacitor is coupled between the first pump-up voltage and the first clock signal; and A voltage divider capacitor is coupled between the second pump-up voltage and the second clock signal, and receives a bias voltage, wherein the bias voltage is less than the second pump-up voltage and greater than the reference ground voltage.

2. The charge pump circuit according to claim 1, wherein the voltage divider capacitor comprises: The capacitor string includes a second capacitor and a third capacitor connected in series, wherein the second capacitor is coupled between the second pump-up voltage and the bias voltage, and the third capacitor is coupled between the bias voltage and the second clock signal.

3. The charge pump circuit according to claim 2, wherein the voltage divider capacitor further comprises: A bias generator is coupled to a bias node between the second capacitor and the third capacitor, and the bias generator is configured to provide the bias voltage to the bias node.

4. The charge pump circuit according to claim 2, wherein the second capacitor is a silicon oxide-silicon nitride-silicon oxide capacitor or a high voltage withstand transistor capacitor, and the third capacitor is a low voltage withstand transistor capacitor or a silicon oxide-silicon nitride-silicon oxide capacitor.

5. The charge pump circuit according to claim 3, wherein the bias generator comprises: A voltage shifter receives a second clock signal and a first input voltage, and performs a voltage shift operation on a third clock signal based on the first input voltage to generate a control voltage; as well as A transistor, wherein the control terminal of the transistor is coupled to the voltage shifter to receive the control voltage, the first terminal of the transistor receives a second input voltage greater than or equal to a reference voltage, and the second terminal of the transistor is coupled to the bias node to provide the bias voltage, wherein the first input voltage is greater than the second input voltage and less than the second pump-up voltage.

6. The charge pump circuit according to claim 1, comprising M first charge pump units and NM second charge pump units, and comprising M first capacitors and NM voltage divider capacitors, wherein N is a positive integer greater than or equal to 2, and M is a positive integer less than N.

7. The charge pump circuit according to claim 6, wherein M is greater than NM.

8. The charge pump circuit according to claim 1, wherein the first pump-up voltage is less than the second pump-up voltage.

9. The charge pump circuit according to claim 1, further comprising: A clock signal generator is configured to generate the first clock signal and generate the second clock signal based on an enable signal and the first clock signal, wherein the enable signal is used to disable or enable the charge pump circuit.

10. The charge pump circuit of claim 9, wherein the clock signal generator comprises: An oscillator for generating the first clock signal and the inverted first clock signal; as well as A logic circuit, coupled to the oscillator, performs a logical operation between the enable signal and the first clock signal and the inverted first clock signal to generate the second clock signal and the inverted second clock signal.

11. The charge pump circuit of claim 10, wherein in response to the enable signal for disabling the charge pump circuit, the logic circuit is configured to maintain the second clock signal and the inverted second clock signal at a first logic value and a second logic value, respectively.

12. The charge pump circuit of claim 10, wherein in response to the enable signal for enabling the charge pump circuit, the logic circuit is configured such that the second clock signal and the inverted second clock signal are two-periodic signals with opposite phases.

13. A voltage generating device, comprising: The charge pump circuit as described in any one of claims 1 to 8 is used to provide an output pump-up voltage; as well as An enable signal generator, coupled to the charge pump circuit, is used to generate an enable signal to disable or enable the charge pump circuit based on a comparison between the output pump voltage and a reference voltage.

14. The voltage generating device according to claim 13, wherein the charge pump circuit further comprises: A clock signal generator is configured to generate the first clock signal and to generate the second clock signal based on the enable signal and the first clock signal.

15. The voltage generating apparatus of claim 14, wherein the clock signal generator comprises: An oscillator for generating the first clock signal and the inverted first clock signal; as well as A logic circuit, coupled to the oscillator, performs a logical operation between the enable signal and the first clock signal and the inverted first clock signal to generate the second clock signal and the inverted second clock signal.

16. The voltage generating apparatus of claim 15, wherein in response to the enable signal for disabling the charge pump circuit, the logic circuit is configured to maintain the second clock signal and the inverted second clock signal at a first logic value and a second logic value, respectively.

17. The voltage generating apparatus of claim 15, wherein, in response to the enable signal for enabling the charge pump circuit, the logic circuit is configured to make the second clock signal and the inverted second clock signal bi-periodic signals with opposite phases.

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