A method for active thermal equalization control of a three-level inverter

Abstract

The application discloses an active thermal balance control method of a three-level inverter, relates to the technical field of power electronics, and solves the serious problem of thermal stress imbalance among devices of an existing silicon / silicon carbide hybrid topology under a high-frequency high-power density working condition; the application comprises the following steps: step 1, calculating real-time power loss vectors of an inverter topology inner tube and an inverter topology outer tube; step 2, based on the real-time power loss vectors, estimating the junction temperature T 内 of the inverter topology inner tube and the junction temperature T 外 of the inverter topology outer tube through a Foster thermal network; and step 3, setting a junction temperature difference threshold as a trigger condition for mode switching, comparing the junction temperature difference between the inverter topology inner tube and the inverter topology outer tube with the junction temperature difference threshold ΔT th to determine a commutation mode; and the application enables a medium-cost hybrid scheme to achieve a performance close to that of a full SiC scheme.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to an active thermal equalization control method for a three-level inverter. Background Technology

[0002] With the rapid development of electrified transportation, electric drive systems have placed more stringent demands on the power density and conversion efficiency of inverters. Among them, the three-level active neutral clamp (3L-ANPC) inverter has become one of the preferred solutions in the medium- and high-voltage high-power drive field due to its significant advantages such as high output waveform quality and low device voltage stress.

[0003] While wide-bandgap semiconductor devices (such as SiC MOSFETs) can significantly reduce switching losses, the extremely high hardware cost of all-SiC solutions limits their large-scale commercial application. Therefore, the Si / SiC hybrid 3L-ANPC inverter, combining traditional Si IGBTs and SiC MOSFETs, has emerged. This hybrid topology can significantly improve system switching frequency and operating efficiency while effectively controlling hardware costs, making it a highly promising cutting-edge electric drive solution.

[0004] However, the high-frequency operation of hybrid devices also presents two serious challenges. First, the extremely fast switching speed of SiC modules generates very large di / dt and dv / dt during switching transients. In high-power inverters without strict stray inductance control, the complex commutation circuit can easily induce severe voltage overshoot, thus threatening the safe operation of the devices. Second, due to the inherent physical differences in the conduction and switching characteristics of Si and SiC devices, traditional fixed modulation schemes inevitably lead to severe uneven power loss distribution. This localized heat concentration not only accelerates device aging but also significantly shortens the overall lifespan of the inverter.

[0005] Existing optimization methods often have limitations: pure software-level modulation strategy optimization (such as dynamically adjusting redundant zero states or hybrid switching frequencies) often leads to negative effects such as increased switching frequency, drastic junction temperature fluctuations, or worsened output current harmonics. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention provides an active thermal equalization control method for a three-level inverter, which solves the serious problem of thermal stress imbalance between devices in existing silicon / silicon carbide hybrid topologies under high-frequency and high-power-density operating conditions.

[0007] An active thermal equalization control method for a three-level inverter, applicable to three-level inverters employing long-short commutation modes, includes:

[0008] Step 1: Calculate the real-time power loss vectors of the inverter topology inner and outer transistors;

[0009] Step 2: Based on the real-time power loss vector, estimate the junction temperature T of the inner tubes of phase A using a Foster thermal network. 内 The junction temperature T of the outer tube of the topology 外 ;

[0010] Step 3: Set the junction temperature difference threshold as the trigger condition for mode switching, and compare the junction temperature difference between the inner and outer tubes of the topology with the junction temperature difference threshold ΔT. th The converter mode was determined through comparison.

[0011] Furthermore, the real-time power loss vector mentioned in step 1 includes: the conduction loss P of the switching device. con Switching loss P sw The conduction loss P of the anti-parallel / body diode Dcon and reverse recovery loss P rr ;

[0012] The conduction loss P con This refers to the instantaneous energy loss of a device during conduction caused by its saturation voltage drop or on-resistance, determined by the corresponding device type, which includes Si-IGBT devices and SiC MOSFET devices.

[0013] The switching loss P sw The turn-on energy E of the device on and shut-off energy E off sum;

[0014] The conduction loss P of the anti-parallel / body diode Dcon This refers to the losses generated when an anti-parallel diode or MOSFET body diode is conducting freewheeling.

[0015] The reverse recovery loss P rr This refers to the transient spike loss that occurs when a diode switches from forward conduction to reverse cutoff due to minority carrier recombination. This phenomenon is unique to Si-IGBT devices.

[0016] Further, step 2 includes: constructing the system thermal impedance matrix Z. total This matrix integrates self-heating resistance and coupled thermal resistance:

[0017]

[0018] In the formula, the diagonal element Z th_jc(Si) The off-diagonal element Z represents the self-thermal resistance of each device. thc(i,j) The thermal coupling resistance R represents the thermal coupling impedance from device j to device i. thc(i,j)The size decreases exponentially with increasing chip pitch.

[0019] Junction temperature T j By using real-time power loss vector Mapped to the system thermal impedance matrix, and then superimposed with the thermal impedance Z from the heat sink to the environment. th_ha and ambient temperature T a To obtain:

[0020]

[0022] Furthermore, the self-thermal impedance of each device is defined, and the transient thermal characteristics of each power device from junction to case are equivalent to a fourth-order Foster-type RC network, thus determining the self-thermal impedance Z. th_jc(Si) for:

[0023]

[0024] Where R (i)th_k and τ (i)th_k These represent the k-th order thermal resistance and thermal time constant corresponding to the i-th device, respectively, and are obtained by fitting the transient thermal impedance curve from the junction to the case side provided in the device datasheet.

[0025] Furthermore, the thermal coupling impedance Z thc(i,j) Used to quantify the thermal interaction between devices, defined as the power loss P of adjacent device j. loss_j The resulting increase in junction temperature of target device i is expressed as follows:

[0026]

[0027] Where T j(i T is the junction temperature of device i caused solely by the power loss of device j. a It refers to the ambient temperature.

[0028] Furthermore, the threshold temperature difference ΔT between the junction and the junction temperature is... th The comparison and determination of the converter modes include:

[0029] When T 外 -T 内 >ΔT th When switching to long converter mode, the high-frequency switching action and its corresponding high-frequency switching loss are transferred from the outer tube of the topology to the inner tube of the topology.

[0030] When T 内 -T 外 >ΔT th When switching to short commutation mode, the high-frequency switching action and its corresponding high-frequency switching loss are transferred from the inner tube of the topology to the outer tube of the topology.

[0031] When |T 内 -T 外 |≤ΔT th If so, the current converter mode will remain unchanged.

[0032] Furthermore, the junction temperature difference threshold ΔT th The lower limit must be greater than the steady-state estimation error of the thermal network model and the signal sampling noise; ΔT th The upper limit is constrained by the combined limitations of the safe operating area of ​​power devices (maximum junction temperature limit), the thermal fatigue life of the module (junction temperature fluctuation range limit), and the overall efficiency degradation of the inverter. Under heavy load conditions, the value of ΔTth must ensure that the peak junction temperature of both the inner and outer transistors of the topology does not exceed the preset safe derating boundary, and that the junction temperature fluctuation range is within the fatigue life allowable range of the packaging material.

[0033] The beneficial effects of this invention include:

[0034] For the first time in Si / SiC hybrid inverter design, an active thermal control strategy can dynamically adjust according to the real-time junction temperature, adapting to changes in load, ambient temperature, and other factors to achieve active thermal management. While achieving significant thermal balance, it maximizes the maintenance of system conversion efficiency and output waveform quality without sacrificing core electrical performance, enabling a mid-cost 4SiC hybrid solution to perform close to that of an all-SiC solution. Attached Figure Description

[0035] Figure 1 The voltage state switching in the hybrid ANPC topology involved in the embodiments of this application is shown in the following: (a) long commutation mode and (b) corresponding to short commutation mode.

[0036] Figure 2 This is a flowchart of an active thermal equalization control method for a three-level inverter according to an embodiment of this application.

[0037] Figure 3 This is a thermal network model of the power switching device involved in the embodiments of this application.

[0038] Figure 4 These are the temperature distribution and power loss distribution results of the devices involved in the embodiments of this application, (a) short commutation mode, (b) long commutation mode, and (c) hybrid commutation mode.

[0039] Figure 5 This refers to the thermal equilibrium performance under dynamic load in the embodiments of this application.

[0040] Figure 6 The following are experimental results for different converter modes involved in the embodiments of this application: (a) is a comparison of total harmonic distortion (THD), and (b) is a comparison of efficiency.

[0041] Figure 7 The following are the steady-state experimental results of the resistive-inductive load (power factor PF=0.9) involved in the embodiments of this application: (a) is the short commutation mode, (b) is the long commutation mode, and (c) is the hybrid commutation mode. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] Example 1

[0044] The following is in conjunction with the appendix Figure 1 Specific embodiments of the present invention will be described in detail;

[0045] An active thermal equalization control method for a three-level inverter, applicable to three-level inverters employing long-short commutation modes, includes:

[0046] Step 1: Calculate the real-time power loss of the inverter topology inner and outer transistors;

[0047] Step 2: Based on real-time power loss, estimate the junction temperature of the inner and outer tubes of phase A using the Foster thermal network;

[0048] Step 3: Set the junction temperature difference threshold as the trigger condition for mode switching, and compare the junction temperature difference between the inner tube and the outer tube of the topology with the junction temperature difference threshold to determine the commutation mode.

[0049] When T 外 -T 内 >ΔT th When switching to long converter mode, the high-frequency switching action and its corresponding high-frequency switching loss are transferred from the outer tube of the topology to the inner tube of the topology.

[0050] When T 内 -T 外 >ΔT th When switching to short commutation mode, the high-frequency switching action and its corresponding high-frequency switching loss are transferred from the inner tube of the topology to the outer tube of the topology.

[0051] When |T 内 -T 外 |≤ΔT thIf so, the current converter mode will remain unchanged.

[0052] like Figure 1 As shown, the three-level inverter involved in this embodiment is a Si / SiC hybrid 3L-ANPC inverter, operating in two commutation modes: long-loop mode and short-loop mode. In the diagram, red indicates that current flows through the device, and arrows indicate the direction of current flow. The Si / SiC hybrid 3L-ANPC inverter includes external transistors S1–S4 and internal transistors S5–S6. The long-loop commutation mode is as follows... Figure 1 As shown in (a), high-frequency switching stress is concentrated on the inner diodes S5 and S6. During the transition from the [P] state to the redundant zero state [OL1], S5, as the main switching device, bears most of the switching losses and part of the conduction losses. When S5 is turned off, the inductive load current is commutated through the anti-parallel diode of the clamping switch S3 during the dead time, and finally flows to the neutral point O through S6. Since the current flows through its body diode before S6 is controlled to turn on, S6 achieves zero-voltage switching, thereby eliminating its turn-on and turn-off losses; therefore, its losses are limited to conduction losses and the body diode reverse recovery losses during the dead-time transition. In contrast, the short commutation mode is as follows: Figure 1 As shown in (b), high-frequency switching is achieved using external transistors S1–S4, while S5 and S6 operate at the fundamental frequency. By employing a specific zero-state, switching losses are concentrated and transferred to the external transistor S1, which possesses high-frequency characteristics. During the transition between the [P] and [OU2] states, S1 bears the majority of the switching losses, while S2 achieves zero-voltage switching (ZVS) after its body diode begins to conduct. Furthermore, the short commutation mode is characterized by dual current paths in the zero state, where S3 and S5 share the conduction current. Compared to the long commutation mode, this configuration effectively reduces the total conduction loss of the system.

[0053] Power loss distribution in different commutation processes is analyzed based on the positive half-cycle.

[0054] The losses during commutation include switching losses, body diode reverse recovery losses, conduction losses, and body diode conduction losses. Table 1 summarizes the loss distribution for different commutation modes during the positive half-cycle. The loss distribution during the negative half-cycle can be analyzed in a similar manner.

[0055] Table 1. Distribution of loss types under different commutation processes

[0056]

[0057] The loss type distribution shown in Table 1 is strictly based on the positive half-cycle operation. During this specific half-cycle, since the output current is positive, the state switching and load current of the three-level ANPC inverter are mainly handled by the upper arm switches (such as S1) and the midpoint clamp. S4, as the outermost device of the lower arm, remains completely off during the positive half-cycle, and no reverse current flows through its body diode. Therefore, no losses are generated during the two positive half-cycle commutation processes in Table 1. However, according to the basic principle of symmetrical inverter operation, the loss characteristics of the outer switches S1 and S4 are completely symmetrical in both the positive and negative half-cycles. When the system operates in the negative half-cycle, S4 will replace S1 as the main switch and fully bear the high-frequency hard switching losses and part of the conduction losses similar to those of S1 in the positive half-cycle. It is evident that, in different commutation modes, power loss distribution is mainly concentrated on the inner tube (S5 / S6) and outer tube (S1 / S4) devices.

[0058] Due to its inherent circuit characteristics, clamping device S2 achieves ZVS during its operation, with significantly lower losses compared to inner and outer tube devices that undergo hard switching.

[0059] Therefore, this embodiment analyzes the loss balance between the inner and outer transistors of the Si / SiC hybrid 3L-ANPC inverter. Furthermore, the loss distribution of the outer transistor switches (S1 / S4) and the inner transistor switches (S5 / S6) is symmetrical in both the positive and negative half-cycles. Since the loss characteristics of S1 are similar to those of S4, and S5 and S6 are also essentially similar, evaluating the loss difference between S1 and S5 is sufficient to reflect the overall loss imbalance among key components.

[0060] Based on the above analysis, it is known that there are significant differences in loss distribution between long and short commutation modes, and thermal stress is concentrated on different devices, resulting in a large steady-state junction temperature difference under fixed modulation. To address the serious problems of large stray inductance and thermal stress imbalance between devices in existing silicon / silicon carbide hybrid topologies under high-frequency, high-power-density conditions, this embodiment proposes an active thermal equalization control method for a three-level inverter, employing a hybrid commutation active thermal control strategy, such as... Figure 2 As shown. By dynamically adjusting the ratio of the two commutation modes, switching losses are redistributed to actively balance the junction temperatures of devices S1 and S5. Correspondingly, an active thermal balance control method for a three-level inverter includes:

[0061] Step 1: The controller calculates the real-time power loss of devices S1 and S5;

[0062] Step 2: Estimate the junction temperature T corresponding to devices S1 and S5 using a Foster thermal network. j1 Tj5 ;

[0063] Step 3: Set the junction temperature difference threshold ΔT th As the trigger condition for mode switching; the junction temperature T corresponding to devices S1 and S5 j1 T j5 The junction temperature difference and the junction temperature difference threshold ΔT th Compare and determine the converter mode;

[0064] When T j1 >T j5 +ΔT th When the system switches to long-term switching mode, the high-frequency switching action and its corresponding high-frequency switching loss will be transferred from the outer switching device S1 to the switching device S5.

[0065] When T j5 >T j1 +ΔT th At that time, a short-circuit converter mode is adopted.

[0066] If T j1 and T j5 The temperature difference between them is less than ΔT th If so, the current converter mode will be maintained.

[0067] The junction temperature difference threshold ΔT th The lower limit must be greater than the steady-state estimation error of the thermal network model and the signal sampling noise. If the threshold is set too low, the system is prone to frequent false triggering switching between long and short commutation modes, which not only increases the computational burden on the controller but may also introduce transient distortion caused by high-frequency mode switching. If the threshold is set too high, the control strategy will exhibit hysteresis, rendering active thermal equalization meaningless and unable to effectively eliminate severe temperature differences between devices. A threshold of 2-5℃ should be set according to the specific circumstances.

[0068] The upper limit of ΔTth is constrained by the combined limitations of the safe operating area of ​​power devices (maximum junction temperature limit), the thermal fatigue life of the module (junction temperature fluctuation range limit), and the overall efficiency degradation of the inverter. Under heavy load conditions, the value of ΔTth must ensure that the peak junction temperature of both the inner and outer transistors of the topology does not exceed the preset safe derating boundary, and that the junction temperature fluctuation range is within the fatigue life allowable range of the packaging material.

[0069] This strategy improves the thermal reliability of the inverter by calculating losses and estimating junction temperature in real time using a thermal model, and then dynamically coordinating the commutation mode based on real-time heat distribution.

[0070] Real-time power loss in step 1 Including: the conduction loss P of the switching device con Switching loss P swThe conduction loss P of the anti-parallel / body diode Dcon and reverse recovery loss P rr The conduction loss P con The calculation formula is determined based on the corresponding device type, which includes Si-IGBT devices and SiC MOSFET devices. The reverse recovery loss P of the SiC MOSFET device is... rr The conduction loss P is negligible. con This refers to the instantaneous energy loss of a device during conduction caused by its saturation voltage drop or on-resistance. The devices in question are classified as Si-IGBT devices and SiC MOSFET devices.

[0071] The output characteristics of the Si-IGBT device are typically determined by its threshold voltage V. ce and slope resistance r ce In combination, both are significantly affected by the junction temperature T. j Influence.

[0072] The linear relationship between its average conduction loss formula and temperature correction coefficient can be expressed as follows:

[0073]

[0074] Where T0 represents the fundamental period of the output current, d(t) is the duty cycle at time t, and i L(t) It is the instantaneous load current, T j It is the junction temperature of the device, V ce(Tj) and r ce(Tj) These are the junction temperatures T j Threshold voltage and slope resistance, V ce_25°C and r ce_25°C These are the threshold voltage and slope resistance at 25°C, K. v and K r These are their temperature coefficients.

[0075] The SiC MOSFET device exhibits purely resistive characteristics in the on-state, and its drain-source on-resistance R ds(on) It increases with increasing junction temperature Tj.

[0076] R must be considered when modeling. ds(on) Due to the temperature nonlinearity, the average conduction loss of SiC during the switching cycle can be calculated using the following formula:

[0077]

[0078] Where R ds(Tj) It depends on the junction temperature T j The changing drain-source on-resistance.

[0079] The switching loss Psw Energy E on and shut-off energy E off Composition. An accurate model for calculating switching losses must be based on the actual operating voltage V. dc Load current I L and real-time junction temperature T j Calibration is performed. The specific switching loss power is expressed as follows:

[0080]

[0081]

[0082]

[0083] Where f sw E represents the switching frequency. on It is the energy loss of a device during a single turn-on, E off This represents the energy loss during a single turn-off. A, B, and C are the fitted energy values ​​as a function of the load current i. L The changing binomial coefficient, V dc It is the real-time DC bus voltage, V ref This is the reference DC voltage in the test data, α is the voltage dependence index, and T ref It is the reference junction temperature in the test data, and β is the temperature dependence index.

[0084] The conduction loss P of the anti-parallel / body diode Dcon This represents the conduction loss of a diode. It refers to the loss generated when an anti-parallel diode or the body diode of a MOSFET is conducting freewheeling current.

[0085]

[0086] Where V f(Tj) Indicates the real-time junction temperature T j The forward conduction threshold voltage of the diode, r D(Tj) It is the real-time junction temperature T j The slope resistance of the lower diode, V f_25°C K is the initial forward voltage drop of the diode at 25°C. Vf It is the temperature correction factor for the forward voltage drop of the diode, r D_25°C It is the initial resistance of the diode at 25°C, K. rD It is the temperature correction factor for the diode resistor.

[0087] The reverse recovery loss P rrThis represents the reverse recovery loss (Erec) of a diode. It refers to the transient spike loss caused by minority carrier recombination when the diode switches from forward conduction to reverse cutoff. Only Si-IGBTs have this loss; SiC's loss is negligible.

[0088]

[0089]

[0090] Where A3, B3, and C3 are the coefficients of a quadratic polynomial fitted to the diode's reverse recovery energy as a function of load current using test data, and V dc It is the real-time DC bus voltage, V ref This is the reference DC voltage in the test data, α is the voltage dependence index, and T ref It is the reference junction temperature in the test data, and β is the temperature dependence index.

[0091] Step 2 includes defining the self-thermal impedance of each device, where the transient thermal characteristics of each power device (e.g., IGBT or diode) from junction to case are equivalent to a fourth-order Foster-type RC network. Its transient thermal impedance Z... th_jc(Si) Defined as:

[0092]

[0093] Where R (i)th_k and τ (i)th_k These represent the k-th order thermal resistance and thermal time constant corresponding to the i-th device, respectively, obtained by fitting the transient thermal impedance curve from the junction to the case side provided in the device datasheet.

[0094] In the loss analysis of three-level ANPC inverters, given the significant temperature dependence of the physical parameters of semiconductor devices, establishing a loss model that includes the electrothermal coupling effect is crucial for achieving accurate junction temperature control.

[0095] To perform effective thermal analysis of power semiconductor devices, an equivalent thermal path model based on a Foster-type RC network is adopted. This model uses a fourth-order RC network to characterize the internal transient thermal impedance from the chip junction temperature to the device case temperature. The RC parameters are lumped values, primarily used for behavioral modeling, and do not correspond to specific physical structures.

[0096] According to the thermal resistance R of each order given in the device datasheet i and the corresponding time constant τ i Calculate the corresponding heat capacity C i Heat capacity:

[0097]

[0098] In the complete system-level model, an additional thermal impedance element is introduced to describe the interfacial thermal resistance between the device case and the heat sink, primarily influenced by the material properties of the thermal interface between the package and the heat sink. For co-packaged power modules, the anti-parallel diodes and the main switching device share the same package case, thus using the same case-to-heat sink thermal impedance path. Finally, heat flow is transferred from the heat sink to the environment. The transient response of a single device is characterized by a fourth-order Foster RC network, such as... Figure 3 As shown in the figure. Key temperature nodes. These represent the case temperature of the power device, the heatsink temperature, and the ultimate reference ambient temperature for the entire system's heat dissipation, respectively. Regarding the input of the loss source, This represents the total losses generated by the main switching chip (i.e., SiC MOSFET or Si IGBT) in a single-phase bridge arm within one control cycle. This represents the sum of the conduction loss and reverse recovery loss generated by its anti-parallel freewheeling diode or body diode.

[0099] Since multiple chips are integrated on a common substrate, significant lateral thermal diffusion occurs in the shared layer when heat is dissipated to the heat sink, making the thermal coupling effect between devices non-negligible.

[0100] To quantify the thermal interactions between devices, a transient equivalent thermal coupling impedance Z is introduced. thc(i,j) , defined as the power loss P of adjacent device j loss_j The resulting increase in junction temperature of target device i:

[0101]

[0102] Where T j(i T is the junction temperature of device i caused solely by the power loss of device j. a It refers to the ambient temperature.

[0103] Based on the above definitions, a complete system thermal impedance matrix Z containing six devices was constructed. total This matrix integrates self-heating resistance and coupled thermal resistance.

[0104]

[0105] The diagonal elements Z of the matrix th_jc(Si) This represents the self-thermal resistance of each device. Off-diagonal element Z. thc(i,j) This represents the thermal coupling impedance from device j to device i. The coupling thermal resistance R thc(i,j)The magnitude of the coupling effect decreases exponentially with increasing chip spacing. Therefore, in the described layout, the thermal coupling is most significant between devices belonging to the same half-bridge due to their closest proximity; while the coupling effect between devices belonging to different half-bridges weakens with increasing spacing. System junction temperature T j By vectorizing power loss Mapped to this thermal impedance matrix, the mapping refers to matrix Z total With the column vector P containing all device losses loss Perform a dot product, then add the thermal resistance Z from the heatsink to the environment. th_ha and ambient temperature T a To obtain.

[0106]

[0107] Z th_ch It is a shared thermal resistance from the shell to the heat sink.

[0108] This model explicitly characterizes the thermal coupling path between devices S1 and S6, thus enabling accurate prediction of junction temperature distribution during operation.

[0109] Since power loss is related to junction temperature, a bidirectional coupled iterative algorithm is employed. This algorithm continuously corrects the conduction and switching loss parameters, minimizing steady-state calculation errors, thereby providing high-fidelity feedback for the active thermal balance control strategy.

[0110] To capture thermal stress migration during dynamic commutation in real time, a complete electrothermal coupling model is established for the six power devices (S1–S6) under layout scheme (A) based on a multi-chip parallel module thermal analysis method. This model (electrical parameters cause losses, losses are input to the thermal network to calculate junction temperature, and junction temperature is fed back to electrical parameters to change on-resistance / voltage drop) is then used. By explicitly characterizing thermal diffusion along the common thermal path, this model can more accurately assess junction temperature distribution and system reliability, avoiding estimation biases introduced by neglecting thermal coupling.

[0111] To accurately capture the thermal response, PT100 platinum resistance temperature sensors were used. These sensors were precisely mounted at case temperature measurement points on three key power devices (S1, S2, and S5)—points located near the chip package surface. High thermal conductivity silicone grease was applied to ensure reliable thermal contact, and copper foil was used for fixation. Additionally, independent PT100 sensors were installed at specific critical locations on the heatsink to monitor the ambient reference temperature. To clearly illustrate dynamic temperature trends, valid data points were extracted every 3 minutes for curve plotting in subsequent analyses.

[0112] The output power of the 4-SiC hybrid 3L-ANPC inverter was set to 10 kW and operated under natural convection cooling. The changes in junction temperature distribution over time under different commutation modes are shown below. Figure 4 As shown. From Figure 4 It can be seen that the temperature curves of the inverter heat sink are highly consistent, indicating that the experiment was conducted under uniform heat dissipation conditions. Figure 4 (a) shows that, in short-commutation mode, the steady-state junction temperature of device S1 reaches 65.3°C, and the steady-state junction temperature of device S5 reaches 60.5°C. Figure 4 In (b), under long commutation mode, the steady-state junction temperature of device S1 is 60.8°C, and the steady-state junction temperature of device S5 is 65.9°C. Figure 4 In (c), when the hybrid commutation mode is used, the steady-state junction temperature of device S1 reaches 62.4°C, and the steady-state junction temperature of device S5 reaches 63.2°C. The experimental results show that the hybrid commutation mode can significantly reduce the junction temperature difference between devices S1 and S5 from 5°C to 0.8°C, while also reducing the highest device temperature.

[0113] To verify the dynamic adaptability and robustness of the proposed active junction temperature control strategy, this paper studies the thermal response of the system under a step load change, such as... Figure 5 As shown. During the initial 8 kW steady-state operation phase, the steady-state junction temperatures of both the outer device S1 and the inner device S5 converged to approximately 54.5 ℃, keeping the temperature difference ΔTj within 1 ℃. At t=60 min, the output power jumped to 12 kW, resulting in a significant increase in the total power loss of the devices. By switching the appropriate commutation mode in real time, dynamic distribution of device losses was achieved. By t=110 min, the system reached a new thermal equilibrium. Although the absolute junction temperatures of S1 and S5 both rose to approximately 71.8 ℃, their temperature difference ΔTj was still strictly controlled within 1 ℃.

[0114] Figure 6 (a) The system conversion efficiency comparison results for the three commutation modes are shown across the entire modulation ratio range. The efficiency curves indicate that the conversion efficiency of the hybrid commutation mode is consistently higher than that of the long commutation mode, but slightly lower than that of the short commutation mode. Figure 6 (b) Shows the comparison results of total current THD across the entire modulation ratio range. Experimental data show that the THD level of the hybrid commutation mode is significantly lower than that of the long commutation mode, exhibiting low THD characteristics close to those of the short commutation mode.

[0115] Figure 7 The steady-state experimental waveforms of short, long, and hybrid commutation modes are shown under an RL load with a power factor of 0.9. These experimental results visually verify that the hybrid commutation mode maintains high-quality output waveforms while effectively balancing thermal stress between devices.

[0116] Experiments show that the proposed active thermal control strategy can reduce the steady-state junction temperature difference between key internal and external transistor components (such as S1 and S5) from over 5°C under fixed modulation to less than 1°C. Infrared thermography tests show that the temperature deviation between phases is small, effectively eliminating local hot spots, significantly alleviating thermomechanical stress, and thus significantly extending the inverter's service life and reliability.

[0117] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

Claims

1. An active thermal equalization control method for a three-level inverter, characterized in that, Suitable for three-level inverters employing long-short commutation modes, including: Step 1: Calculate the real-time power loss vectors of the inverter topology inner and outer transistors; Step 2: Based on the real-time power loss vector, estimate the junction temperature T of the inner tubes of phase A using a Foster thermal network. 内 The junction temperature T of the outer tube of the topology 外 ; Step 3: Set the junction temperature difference threshold as the trigger condition for mode switching, and compare the junction temperature difference between the inner and outer tubes of the topology with the junction temperature difference threshold ΔT. th The converter mode was determined through comparison.

2. The active thermal equalization control method for a three-level inverter according to claim 1, characterized in that, The real-time power loss vector mentioned in step 1 includes: the conduction loss P of the switching device. con Switching loss P sw The conduction loss P of the anti-parallel / body diode Dcon and reverse recovery loss P rr ; The conduction loss P con This refers to the instantaneous energy loss of a device during conduction caused by its saturation voltage drop or on-resistance, which is determined by the corresponding device type, including Si-IGBT devices and SiC MOSFET devices; The switching loss P sw The turn-on energy E of the device on and shut-off energy E off sum; The conduction loss P of the anti-parallel / body diode Dcon This refers to the loss generated when an anti-parallel diode or MOSFET body diode is in freewheeling conduction. The reverse recovery loss P rr This refers to the transient spike loss that occurs when a diode switches from forward conduction to reverse cutoff due to minority carrier recombination. This phenomenon is unique to Si-IGBT devices.

3. The active thermal equalization control method for a three-level inverter according to claim 1, characterized in that, Step 2 includes: constructing the system thermal impedance matrix Z. total This matrix integrates self-heating resistance and coupled thermal resistance: In the formula, the diagonal element Z th_jc(Si) The off-diagonal element Z represents the self-thermal resistance of each device. thc(i,j) The thermal coupling resistance R represents the thermal coupling impedance from device j to device i. thc(i,j) The size decreases exponentially with increasing chip pitch; Junction temperature T j By using real-time power loss vector Mapped to the system thermal impedance matrix, and then superimposed with the thermal impedance Z from the heat sink to the environment. th_ha and ambient temperature T a To obtain: In the formula, This is the thermal resistance from the heat sink to the environment.

4. The active thermal equalization control method for a three-level inverter according to claim 3, characterized in that, Define the self-thermal impedance of each device, and represent the transient thermal characteristics of each power device from junction to case as an equivalent fourth-order Foster-type RC network to determine the self-thermal impedance Z. th_jc(Si) for: Where R (i)th_k and τ (i)th_k These represent the k-th order thermal resistance and thermal time constant corresponding to the i-th device, respectively, obtained by fitting the transient thermal impedance curve from the junction to the case side provided in the device datasheet.

5. The active thermal equalization control method for a three-level inverter according to claim 3, characterized in that, The thermal coupling impedance Z thc(i,j) Used to quantify the thermal interaction between devices, defined as the power loss P of adjacent device j. loss_j The resulting increase in junction temperature of target device i is expressed as follows: Where T j(i T is the junction temperature of device i caused solely by the power loss of device j. a It refers to the ambient temperature.

6. The active thermal equalization control method for a three-level inverter according to claim 1, characterized in that, The junction temperature difference threshold ΔT th The comparison and determination of the converter modes include: When T 外 -T 内 >ΔT th When switching to long converter mode, the high-frequency switching action and its corresponding high-frequency switching loss are transferred from the outer tube of the topology to the inner tube of the topology. When T 内 -T 外 >ΔT th When switching to short commutation mode, the high-frequency switching action and its corresponding high-frequency switching loss are transferred from the inner tube of the topology to the outer tube of the topology. When |T 内 -T 外 |≤ΔT th If so, the current converter mode will remain unchanged.

7. The active thermal equalization control method for a three-level inverter according to claim 1, characterized in that, The junction temperature difference threshold ΔT th The lower limit must be greater than the steady-state estimation error of the thermal network model and the signal sampling noise; ΔT th The upper limit is limited by the combined constraints of the safe operating area of ​​power devices, the thermal fatigue life of modules, and the overall efficiency reduction of inverters.

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