Data collector, signal transmission method and photovoltaic system

Abstract

The application provides a data collector, a signal sending method and a photovoltaic system, and belongs to the technical field of PLC. The data collector is connected with a power converter through a power line. The data collector can obtain a low-noise time slot of the power converter in each power frequency cycle according to the phase or amplitude of the electric signal obtained from the power line, and send a signal to the power converter in the low-noise time slot. Since the energy of the noise generated by the switching tube in the power converter in the low-noise time slot in each power frequency cycle is relatively low, the data collector can send a signal in the low-noise time slot, so that the signal-to-noise ratio of the signal received by the power converter is high. Therefore, the reliability of PLC communication is effectively improved.

Description

Technical Field

[0001] This application relates to the field of PLC technology, and in particular to a data acquisition device, a signal transmission method, and a photovoltaic system. Background Technology

[0002] A photovoltaic (PV) power generation system typically includes photovoltaic panels, power converters (such as inverters), box-type transformers (referred to as box-type transformers), and data acquisition devices. The power converter transforms the direct current (DC) output from the photovoltaic panels into alternating current (AC). The box-type transformer performs voltage conversion on the AC output from the inverter. The data acquisition device collects power and status information from the power converter and performs power dispatch control based on the collected data.

[0003] Data acquisition units and power converters typically communicate via power line communication (PLC) technology. Because the distance between the data acquisition unit and the power converter is usually quite large, the signal emitted by the data acquisition unit experiences significant energy attenuation after long-distance transmission over the power line. Furthermore, the power conversion circuitry within the power converter generates substantial noise during operation, resulting in a low signal-to-noise ratio for the signal received by the power converter, thus affecting the reliability of PLC communication. Summary of the Invention

[0004] This application provides a data acquisition device, a signal transmission method, and a photovoltaic system, which can solve the technical problem that the signal-to-noise ratio of the signal received by the power converter is low, affecting the reliability of PLC communication.

[0005] Firstly, a data acquisition device is provided for connecting a power converter via a power line. The data acquisition device includes an analog front end (AFE) circuit, a time slot detection circuit, and a PLC circuit. The AFE circuit connects to the power line and acquires an electrical signal, either a voltage or current signal, from the power line. The time slot detection circuit determines the low-noise time slot of the power converter in each power frequency cycle based on the phase or amplitude of the electrical signal. The PLC circuit transmits a signal to the power converter via the power line during the low-noise time slot. Within each power frequency cycle, the energy of the noise generated by the switching transistors in the power converter during the low-noise time slot is lower than the energy of the noise generated during switching in other time slots. These other time slots are the time slots within the power frequency cycle other than the low-noise time slot.

[0006] Because the energy of noise generated by the switching transistors in the power converter is relatively low during the low-noise time slots of each power frequency cycle, the data acquisition unit can ensure a high signal-to-noise ratio for the signal received by the power converter by sending signals during these low-noise time slots. This effectively improves the reliability of PLC communication.

[0007] Optionally, the time slot detection circuit can pre-store the correspondence between the phase or amplitude of the electrical signal and the energy of the noise generated by the switching transistors in the power converter. For example, this correspondence can record the changing trend of the phase or amplitude of the electrical signal and the corresponding changing trend of the noise energy within each power frequency cycle. Accordingly, after detecting the phase or amplitude of the electrical signal on the power line, the time slot detection circuit can obtain the energy level of the noise generated by the switching transistors in the power converter, thereby obtaining a low-noise time slot.

[0008] Optionally, each power frequency cycle includes at least two low-noise time slots. For example, each power frequency cycle includes two low-noise time slots. The power frequency can be 50 Hz, and the corresponding power frequency cycle is 0.02 seconds. Since each power frequency cycle includes at least two low-noise time slots, it can be ensured that the PLC circuit in the data acquisition unit can send signals to the power converter in a timely and effective manner through these at least two low-noise time slots.

[0009] Optionally, the duration of the low-noise time slot is greater than or equal to 1 / 6 of the power frequency cycle. For example, assuming the power frequency cycle is 0.02 seconds, the duration of the low-noise time slot is approximately 3.3 milliseconds (ms). Of course, the duration of the low-noise time slot can also be slightly longer than 1 / 6 of the power frequency cycle, for example, 4 ms to 5 ms, to ensure that the PLC circuit can complete the transmission of a downlink frame within one low-noise time slot.

[0010] Optionally, the time slot detection circuit is used to obtain the switching timing of the switching transistors in the power converter in each power frequency cycle according to the phase or amplitude of the electrical signal, and to obtain the low-noise time slot based on the correspondence between the switching timing and the energy of the noise.

[0011] It is understandable that the noise in a power converter is mainly generated by the switching action of the switching transistors within the converter. Therefore, the energy distribution of the noise in the time domain within each power frequency cycle is related to the switching timing of the transistors. Furthermore, since the power converter adjusts the amplitude and phase of the AC power output to the power line based on the switching action of the transistors, the amplitude or phase of the electrical signal on the power line can reflect the switching timing of the transistors in the power converter within each power frequency cycle.

[0012] Based on the above analysis, it can be seen that the time slot detection circuit can accurately obtain the switching sequence of the switching transistors in the power converter in each power frequency cycle according to the amplitude or phase of the electrical signal on the power line. Furthermore, it can accurately obtain the energy distribution of the noise generated by the power converter in each power frequency cycle based on this switching sequence. Then, based on this noise energy distribution, the time slot detection circuit can accurately obtain the low-noise time slots in each power frequency cycle.

[0013] It is also understandable that, since the switching timing of the transistors in the power converter is usually fixed and periodically repeating, the position of the aforementioned low-noise time slot within each power frequency cycle is also fixed; that is, the low-noise time slot will periodically repeat at fixed intervals. Accordingly, the data acquisition unit can detect the low-noise time slot information once during idle periods (i.e., periods when no signal transmission is required) based on the amplitude or phase of the electrical signal on the power line (e.g., an electrical signal for at least two power frequency cycles), i.e., detect the position of the low-noise time slot within one power frequency cycle. Afterward, the data acquisition unit can directly obtain the low-noise time slot in the current power frequency cycle based on the pre-detected time slot information when signal transmission is required, without needing to detect the low-noise time slot in real time using the amplitude or phase of the electrical signal on the power line. The signal can then be transmitted within that low-noise time slot.

[0014] Optionally, the data acquisition unit is used to connect a power converter via a first phase line and a second phase line in the power line. The power converter includes a first bridge arm and a second bridge arm, wherein the first bridge arm is connected to the first phase line and the second bridge arm is connected to the second phase line. Furthermore, during a low-noise time slot, the switching state of the switch in the first bridge arm is the same as the switching state of the switch in the second bridge arm.

[0015] The switching states of the transistors can include on, off, and high-frequency switching states. Since each of the first and second bridge arms can include multiple transistors, the identical switching states of the transistors in the two bridge arms can mean that the transistors located at the same position in both bridge arms have the same switching state. It is understood that the phase and amplitude of the electrical signal on the power line are related to the switching timing of the transistors in each bridge arm of the power converter. Furthermore, since the low-noise time slots have the aforementioned correspondence with the switching states of the transistors in the two bridge arms, the data acquisition unit can obtain the switching timing of the transistors in each bridge arm by measuring the phase or amplitude of the electrical signal on the power line, and thus obtain the low-noise time slots.

[0016] Optionally, the AFE circuit includes a coupling circuit for coupling an electrical signal from the power line, wherein the coupled electrical signal is a power frequency signal, i.e., a fundamental wave or a power frequency sine wave. The time slot detection circuit includes a phase detector and a signal processing circuit. The phase detector is used to detect the phase of the electrical signal. The signal processing circuit is used to obtain the low-noise time slot of the power converter in each power frequency cycle based on the correspondence between the phase of the electrical signal and the energy of the noise generated by the switching transistors in the power converter.

[0017] It is understandable that the phase of the power frequency signal (such as power frequency voltage) on the power line determines the phase of the output voltage of the power converter, and thus determines the switching timing of the switching transistors in the power converter. Furthermore, as mentioned earlier, the switching timing of the switching transistors in the power converter determines the energy distribution of noise. Therefore, there is a correspondence between the phase of the electrical signal and the energy of the noise in the power converter. Accordingly, the time slot detection circuit can detect the phase of the electrical signal on the power line and accurately obtain the low-noise time slot based on the above correspondence.

[0018] It is also understood that the above-mentioned AFE circuit may also include a filter circuit, which can be used to filter the signal coupled to the coupling circuit to obtain the power frequency signal, i.e., the fundamental wave or the power frequency sine wave.

[0019] Optionally, the AFE circuit includes a coupling circuit and an analog-to-digital converter (ADC). The coupling circuit couples the power line signal from the power line and removes the fundamental frequency and DC component from the power line signal to obtain a noise signal. The ADC converts this noise signal from an analog signal to a digital signal to obtain an electrical signal. That is, the electrical signal obtained by the AFE circuit from the power line is a noise signal after removing the fundamental frequency and DC component and undergoing analog-to-digital conversion. The signal processing circuit obtains the low-noise time slot of the power converter in each power frequency cycle based on the amplitude variation pattern of the noise signal after conversion to a digital signal.

[0020] The fundamental frequency (FFM) refers to the core frequency component of electrical energy transmission on the power line (i.e., the power frequency). The signal after removing the fundamental frequency and DC component is the noise signal. The AFE may also include a filter used to filter the signal output from the coupling circuit to further remove the fundamental frequency and / or DC component, and / or to filter the signal output from the coupling circuit into the PLC's communication frequency band. Since the aforementioned noise signal is mainly generated by the switching of the switching transistors in the power converter, the low-noise time slot within each power frequency cycle can be accurately obtained based on the amplitude variation pattern of this noise signal.

[0021] It is understandable that the PLC circuit in this data acquisition unit may also include a coupling circuit. This coupling circuit is connected to the power line and is used to couple signals sent to the power converter via the power line, as well as to couple signals from the power converter via the power line. The coupling circuit used to couple power line signals from the power line can be the same coupling circuit as the coupling circuit in the PLC circuit. That is, the data acquisition unit can reuse the coupling circuit in the PLC circuit to couple power line signals and detect low-noise time slots, thereby reducing the structural complexity and hardware cost of the data acquisition unit.

[0022] Optionally, the signal processing circuit in the time slot detection circuit can be integrated into the PLC circuit, for example, into the PLC chip of the PLC circuit. This further reduces the structural complexity and hardware cost of the data acquisition device.

[0023] Optionally, the above-mentioned AFE circuit can be implemented by discrete devices or integrated circuits, or a combination of discrete devices and integrated circuits.

[0024] Secondly, a signal transmission method is provided, which is applied to the data acquisition device provided in the first aspect above, the data acquisition device being used to connect a power converter via a power line. The signal transmission method includes: first, acquiring an electrical signal from the power line, the electrical signal being a voltage signal or a current signal; then, obtaining a low-noise time slot of the power converter in each power frequency cycle based on the amplitude or phase of the electrical signal; and then, transmitting a signal to the power converter via the power line within the low-noise time slot. Wherein, within each power frequency cycle, the energy of the noise generated by the switching transistors in the power converter switching within the low-noise time slot is lower than the energy of the noise generated by switching in other time slots, which are time slots within the power frequency cycle other than the low-noise time slot.

[0025] Optionally, each power frequency cycle includes at least two low-noise time slots. The duration of each low-noise time slot is greater than or equal to 1 / 6 of the duration of the power frequency cycle.

[0026] Optionally, the process of obtaining the low-noise time slot of the power converter in each power frequency cycle based on the amplitude or phase of the electrical signal may include: first obtaining the switching timing of the switching transistors in the power converter in each power frequency cycle based on the phase or amplitude of the electrical signal, and then obtaining the low-noise time slot based on the correspondence between the switching timing and the energy of the noise.

[0027] Thirdly, a data acquisition device is provided for connecting a power converter via a power line. This data acquisition device includes an AFE circuit and a timing detection circuit. The AFE circuit connects to the power line and acquires an electrical signal, which is either a voltage signal or a current signal, from the power line. The timing detection circuit determines the switching timing of the switching transistors in the power converter based on the phase or amplitude of the electrical signal.

[0028] Optionally, the AFE circuit obtains a power frequency signal from the power line. This timing detection circuit is used to obtain the switching timing of the switching transistors in the power converter based on the phase of the electrical signal. Since the phase of the electrical signal on the power line determines the output phase of the power converter, and the power converter adjusts its output phase through the switching timing of the switching transistors, the timing detection circuit can accurately detect the switching timing of the switching transistors in the power converter based on the phase of the electrical signal.

[0029] Optionally, the electrical signal obtained from the power line by the AFE circuit is a noise signal after removing the fundamental frequency and DC component. The timing detection circuit is used to analyze the characteristics (such as amplitude) of the noise signal to obtain the switching timing of the switching transistors in the power converter.

[0030] Fourthly, a photovoltaic system is provided, comprising: a data acquisition unit as provided in the first or third aspect above, and at least one power converter. The data acquisition unit and the at least one power converter are connected via power lines and are used to exchange signals via the power lines.

[0031] Fifthly, a chip is provided that includes programmable logic circuitry and / or program instructions, or includes an application-specific integrated circuit (ASIC) and / or program instructions. When the chip operates, it performs some or all of the steps in the signal transmission method provided in the second aspect above.

[0032] In summary, this application provides a data acquisition device, a signal transmission method, and a photovoltaic system. The data acquisition device provided in this application connects to a power converter via a power line. Furthermore, the data acquisition device can obtain the low-noise time slot of the power converter in each power frequency cycle based on the phase or amplitude of the electrical signal acquired from the power line, and transmit a signal to the power converter during this low-noise time slot. Since the energy of the noise generated by the switching transistors in the power converter during this low-noise time slot is relatively low in each power frequency cycle, transmitting a signal during this low-noise time slot ensures a high signal-to-noise ratio for the signal received by the power converter. This effectively improves the reliability of PLC communication. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a photovoltaic power generation system provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of the structure of a photovoltaic system in related technologies;

[0035] Figure 3 This is a schematic diagram of another photovoltaic system provided in an embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the structure of a data acquisition device provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of another data acquisition device provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of a power conversion circuit provided in an embodiment of this application;

[0039] Figure 7 This is a schematic diagram illustrating the correspondence between the switching timing of the switching transistors, the phase of the electrical signal, and the energy of noise in a power converter provided in this application embodiment;

[0040] Figure 8 This is a schematic diagram of the structure of another data acquisition device provided in the embodiments of this application;

[0041] Figure 9 This is a schematic diagram of the time-domain waveform of noise generated by a power converter according to an embodiment of this application;

[0042] Figure 10 This is a schematic diagram of the power spectral density of noise generated by a power converter according to an embodiment of this application;

[0043] Figure 11 This is a flowchart of a signal transmission method provided in an embodiment of this application. Detailed Implementation

[0044] The data acquisition device, signal transmission method, and photovoltaic system provided in the embodiments of this application are described in detail below with reference to the accompanying drawings. First, the key terms involved in the embodiments of this application are introduced.

[0045] PLC: also known as power line carrier communication, is a communication method that uses power lines to transmit data.

[0046] Photovoltaic modules: also known as photovoltaic panels or PV modules, are used to convert solar energy into electrical energy.

[0047] Inverter: A power converter and a DC-to-AC power source used to convert the direct current (DC) from photovoltaic panels into alternating current (AC).

[0048] Box-type transformer: a type of transformer that contains a low-voltage distribution cabinet and a transformer, used to convert the AC output of the inverter.

[0049] AC combiner box: Used to combine the AC output from multiple inverters, reducing the number of connecting cables to the grid or load and reducing line losses.

[0050] Data acquisition unit: A controller device used to collect data and control the inverter. It can communicate with the inverter via a PLC and exchange information with management systems (such as network administrators) via mobile communication technology or Fast Ethernet (FE). The mobile communication technology can be fourth-generation mobile communication technology (4G) or 5G, etc.

[0051] Figure 1 This is a schematic diagram of a photovoltaic system provided in an embodiment of this application. The photovoltaic system may include a photovoltaic power station, such as a ground-mounted power station, an industrial / commercial power station, or a residential power station. Figure 1 As shown, the photovoltaic system may include a data acquisition unit and multiple power converters. Each power converter can be an inverter, with its DC terminal connected to the photovoltaic modules and its AC terminal connected to the power grid. For example, the AC terminals of these multiple power converters can be connected to the power grid via an AC combiner box and a transformer substation. The power converter converts the DC power output from the photovoltaic modules into AC power before outputting it. The AC combiner box combines the AC power outputs from the multiple power converters and outputs it to the transformer substation. The transformer substation performs voltage conversion on the received AC power before outputting it to the power grid.

[0052] In photovoltaic (PV) power generation systems, for ease of management, the multiple power converters and PV modules connected to each transformer substation can be collectively referred to as a PV subarray. To obtain power information from the power converters and perform power dispatch control, each PV subarray requires a data acquisition device for centralized management of its power converters. This data acquisition device can also be called a subarray controller. Furthermore, this data acquisition device serves as the control center of the PV subarray, such as... Figure 1 As shown, it is typically placed next to the transformer substation. This data acquisition device can establish a communication connection and exchange information with the management system (such as the network administrator). For example, refer to... Figure 1The data acquisition unit and management system can exchange information via a fiber optic ring network. Furthermore, for cost and reliability considerations, the data acquisition unit and power converter typically communicate via PLC technology, i.e., through power lines. The data acquisition unit can be the master unit of the PLC system, also known as the central coordinator (CCO), while the power converter can be the slave unit of the PLC system, also known as a station (STA). Communication between the data acquisition unit and the power converter can occur via any two phase wires of the power line.

[0053] Optionally, the data acquisition unit can send data query commands and scheduling control commands to the power converter via the power line. The data query command is used to instruct the user to query the operating status data of a specified power converter, such as voltage, current, power, and / or internal status. The scheduling control command is used to adjust the operating status of a specified power converter, such as adjusting the voltage, current, and / or power of power converter 20. The power converter can send its operating status data to the data acquisition unit via the power line.

[0054] In a typical photovoltaic power plant scenario, during downlink transmission, the data acquisition unit (CA) acts as the control operator (CCO) in the PLC system, sending signals to the power converter (STA). The signal transmitted by the CA concentrator experiences significant energy attenuation after traveling a long distance via power lines. Furthermore, the power conversion circuitry within the power converter generates substantial noise during operation, resulting in a low signal-to-noise ratio (SNR) of the received signal and consequently reducing the reliability of PLC communication.

[0055] In power systems using PLC technology for communication, to reduce the impact of noise on PLC communication quality, the signal receiving end (such as a power converter) employs time-domain and frequency-domain noise cancellation schemes to process the noise. For example, ... Figure 2 As shown, the PLC transmitter in the data acquisition unit (or simply data acquisition unit) acts as the CCO (Concurrent Control Operator) and sends PLC signals, i.e., downlink signals. The PLC receiver in the power converter (or inverter) acts as the STA (Stationary Receiver) and receives these downlink signals. Because the downlink signal has traveled a long distance via the power line, the signal energy reaching the PLC receiver is relatively low, while the noise energy generated locally by the power converter is relatively high, resulting in a low signal-to-noise ratio (SNR) for the received signal.

[0056] To improve the signal-to-noise ratio (SNR) of the received signal and ensure signal quality and transmission reliability, it is usually necessary to process either the useful signal or the noise. Techniques for processing the useful signal mainly include increasing the transmit power of the PLC transmitter and employing modulation / demodulation techniques and channel encoding / decoding techniques. Noise processing techniques mainly include analog filtering, digital filtering, impulse noise suppression, and narrowband interference suppression. For example, refer to... Figure 2A PLC transmitter may include an analog front end (AFE) and a PLC chip. The PLC chip is used to modulate and encode the baseband signal. The AFE processes the signal output from the PLC chip, which may include digital-to-analog conversion, power amplification, and filtering. A PLC receiver may include an AFE, a noise processing module, and a PLC chip. The AFE couples the analog signal from the power lines (e.g., A-phase and B-phase lines) and converts it into a digital signal. The noise processing module applies the aforementioned noise processing techniques to the signal output from the AFE to improve the signal-to-noise ratio (SNR) of the received signal. The PLC chip demodulates and decodes the processed signal. However, this approach of enhancing the useful signal and suppressing noise to improve the SNR of the received signal is costly, and its performance improvement has essentially reached a bottleneck.

[0057] This application proposes a system-level solution for power systems, such as photovoltaic power generation systems, that optimizes the communication subsystem by combining a power subsystem. The power subsystem refers to the power conversion circuit in a power converter, and the communication subsystem refers to a PLC system. In the solution provided by this application, the PLC transmitter (i.e., the data acquisition unit) can acquire the noise energy distribution characteristics of the PLC receiver (i.e., the power converter) and, using these characteristics, actively avoid high-noise-energy time slots and select low-noise-energy time slots for PLC communication. The noise at the receiver refers to the noise caused by the operation of the power conversion circuit, which is the main source of noise at the receiver. The solution provided by this application can overcome the performance bottleneck of PLC systems applied in power systems, effectively improving the received signal-to-noise ratio at a lower cost, thereby significantly enhancing the reliability of long-distance communication.

[0058] Figure 3 This is a schematic diagram of the structure of a photovoltaic system provided in an embodiment of this application. This photovoltaic system can be applied to, for example... Figure 1 In the scenario shown. For example... Figure 3 As shown, the photovoltaic system includes a data acquisition unit 10 and a power converter 20. The data acquisition unit 10 includes a PLC transmitter. The power converter 20 can be an inverter, which includes a PLC receiver. The PLC transmitter and receiver can form a PLC system, where the PLC transmitter can be the CCO (Concurrent Control Operator) of the PLC system, and the PLC receiver can be the STA (Signal Controller) of the PLC system. The data acquisition unit 10 and the power converter 20 are connected via power lines. For example, Figure 3 In the photovoltaic system shown, the power lines include phase A, phase B, and phase C, and the data acquisition unit 10 and the power converter 20 are connected via phase A and phase B.

[0059] Continue to refer to Figure 3 The data acquisition unit 10 includes an AFE circuit 11, a time slot detection circuit 12, and a PLC circuit 13. The AFE circuit 11 is used to connect to the power line and to acquire electrical signals from the power line. These electrical signals can be voltage or current signals. The AFE circuit 11 may include a coupling circuit, which may include coupling devices such as capacitors, inductors, signal transformers, and / or magnetic rings.

[0060] The time slot detection circuit 12 is used to obtain the low-noise time slot of the power converter 20 in each power frequency cycle based on the phase or amplitude of the electrical signal. The PLC circuit 13 is used to send a signal to the power converter 20 via the power line during the low-noise time slot. Specifically, within each power frequency cycle, the energy of the noise generated by the switching transistors in the power converter 20 during the low-noise time slot is lower than the energy of the noise generated during switching in other time slots, which are the time slots other than the low-noise time slot in each power frequency cycle. The noise energy is obtained based on the noise amplitude; for example, the noise energy is proportional to the time integral of the square of the amplitude.

[0061] It is understood that the power converter 20 includes a power conversion circuit, namely a DC / AC conversion circuit (also called an inverter circuit), which includes at least one switching transistor. Within each power frequency cycle, this at least one switching transistor operates according to a fixed switching sequence. The power frequency can be 50Hz, and the power frequency cycle can be 0.02 seconds, or 20ms. The switching transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT), etc. During the switching process, i.e., the instants of conduction and turn-off, the switching transistor generates very high voltage and current change rates in the power conversion circuit. These voltage and current transients cause oscillations in parasitic inductance and capacitance, thus generating high-frequency noise. Furthermore, the frequent switching of the switching transistor generates alternating electric and magnetic fields, which can couple into surrounding circuits or devices through conduction or radiation, forming electromagnetic noise. Furthermore, when the switching transistor is turned on, the freewheeling diode connected in parallel with it undergoes a reverse recovery process. During this process, the diode briefly conducts reverse current, causing a sudden current change and generating noise. Based on the above analysis, it can be seen that the switching transistor in the power conversion circuit generates significant noise during the switching process, which severely affects the signal-to-noise ratio of the signal received by the power converter 20.

[0062] It is also understandable that, since the aforementioned noise is generated by the switching action of the switching transistors in the power converter 20, the energy distribution of the noise in the time domain within each power frequency cycle is related to the switching timing of the switching transistors. That is, the switching timing of the switching transistors within each power frequency cycle can reflect the energy distribution of the noise within that cycle. Furthermore, since the power converter 20 adjusts the amplitude and phase of the AC power output to the power line based on the switching action of the switching transistors, the amplitude or phase of the electrical signal on the power line can reflect the switching timing of the switching transistors in the power converter 20 within each power frequency cycle.

[0063] Based on the above analysis, it can be seen that the amplitude or phase of the electrical signal on the power line can reflect the switching timing of the switching transistors in the power converter 20 in each power frequency cycle, and the switching timing can reflect the energy distribution of noise within that power frequency cycle. Therefore, based on the amplitude or phase of the electrical signal on the power line, the energy distribution of noise generated by the switching transistors in the power converter 20 within each power frequency cycle can be obtained, thereby obtaining the low-noise time slot of the power converter 20 in each power frequency cycle. Since the energy of the noise generated by the switching transistors in the power converter 20 is relatively small during this low-noise time slot, the PLC circuit 13 in the data acquisition unit 10 can send signals to the power converter 20 during this low-noise time slot, ensuring a high signal-to-noise ratio for the signal received by the power converter 20. This effectively improves the reliability of PLC communication.

[0064] It is understood that the PLC circuit 13 also includes a coupling circuit, which is connected to the power line and used to couple signals sent to the power converter 20 (i.e., downlink signals, also called downlink frames) to the power line, and signals from the power converter 20 (i.e., uplink signals, also called uplink frames) to the power line. The coupling circuit in the AFE circuit 11 and the coupling circuit in the PLC circuit 13 can be two independent coupling circuits, or they can be the same coupling circuit. By multiplexing the coupling circuit in the PLC circuit 13 to couple electrical signals and detect low-noise time slots, the structural complexity and hardware cost of the data acquisition unit can be effectively reduced.

[0065] Optionally, the time slot detection circuit 12 is used to obtain the switching timing of the switching transistors in the power converter 20 in each power frequency cycle according to the phase or amplitude of the electrical signal, and to obtain the low-noise time slot based on the correspondence between the switching timing and the energy of the noise.

[0066] As mentioned earlier, the amplitude or phase of the electrical signal on the power line can reflect the switching timing of the switching transistors in the power converter 20 in each power frequency cycle, and this switching timing can reflect the energy distribution of noise within that power frequency cycle. Therefore, the time slot detection circuit 12 can first accurately obtain the switching timing of the switching transistors in the power converter 20 in each power frequency cycle based on the phase or amplitude of the electrical signal, and then accurately obtain the low-noise time slot based on the correspondence between the switching timing and the energy of the noise.

[0067] For example, the time slot detection circuit 12 can pre-store a first correspondence between the phase or amplitude of the electrical signal and the switching timing of the switching transistors in the power converter 20 in each power frequency cycle, and can also store a second correspondence between the switching timing of the switching transistors in the power converter 20 in each power frequency cycle and the energy of the noise. The time slot detection circuit 12 can obtain the switching timing of the switching transistors in the power converter 20 in each power frequency cycle based on the phase or amplitude of the electrical signal actually obtained from the power line by the AFE circuit 11, and the aforementioned first correspondence. Furthermore, based on the aforementioned second correspondence, it can obtain the energy distribution of the noise generated by the switching transistors in the power converter 20 in each power frequency cycle, and obtain the low-noise time slot for each power frequency cycle.

[0068] Optionally, both the first and second correspondences mentioned above can be obtained using machine learning methods. For example, both the first and second correspondences can be machine learning models, and these models can be trained on offline data. For instance, the machine learning model for the first correspondence can be trained on the following offline data: the switching timing of the switching transistors in the power converter 20 in each power frequency cycle, and the amplitude or phase of the electrical signal on the power line. The machine learning model for the second correspondence can be trained on the following offline data: the switching timing of the switching transistors in the power converter 20 in each power frequency cycle, and the time-domain distribution of the noise energy generated by the switching transistors in the power converter 20 in each power frequency cycle. The switching timing of the switching transistors can be characterized based on the timing of the driving signal of the switching transistors, which can be a pulse width modulation (PWM) signal.

[0069] It is understandable that the time slot detection circuit 12 can also directly obtain the low-noise time slot of the power converter 20 in each power frequency cycle based on the phase or amplitude of the electrical signal obtained by the AFE circuit 11.

[0070] For example, the time slot detection circuit 12 can pre-store a third correspondence between the phase or amplitude of the electrical signal and the energy of the noise generated by the switching transistor in the power converter 20 in each power frequency cycle. This third correspondence can be obtained based on the first and second correspondences mentioned above. For example, the third correspondence can record the changing trend of the phase or amplitude of the electrical signal and the corresponding changing trend of the noise energy within each power frequency cycle. Accordingly, the time slot detection circuit 12 can directly obtain the energy distribution of the noise generated by the switching transistor in the power converter 20 in each power frequency cycle based on the phase or amplitude of the electrical signal actually obtained from the power line by the AFE circuit 11 and the aforementioned third correspondence, and obtain the low-noise time slot for each power frequency cycle. Alternatively, the third correspondence can be a machine learning model, and the machine learning model can be trained based on the following offline data: the amplitude or phase of the electrical signal on the power line, and the energy distribution of the noise generated by the switching transistor in the power converter 20 in each power frequency cycle.

[0071] It is also understood that the time slot detection circuit 12 can obtain the low-noise time slot of the power converter 20 in each power frequency cycle based on the phase and amplitude of the electrical signal obtained by the AFE circuit 11. Alternatively, it can first obtain the switching timing of the switching transistors in the power converter 20 based on the phase and amplitude of the electrical signal, and then obtain the low-noise time slot for each power frequency cycle based on the switching timing. For example, the time slot detection circuit 12 can pre-store a fourth correspondence between the phase and amplitude of the electrical signal and the noise energy of the switching transistors in the power converter 20 in each power frequency cycle. This fourth correspondence can record the changing trend of the phase and amplitude of the electrical signal and the corresponding changing trend of the noise energy within each power frequency cycle. Accordingly, the time slot detection circuit 12 can directly obtain the energy distribution of the noise generated by the switching transistors in the power converter 20 in each power frequency cycle based on the phase and amplitude of the electrical signal actually obtained by the AFE circuit 11 from the power line and the aforementioned fourth correspondence, and obtain the low-noise time slot for each power frequency cycle. Alternatively, the fourth correspondence can be a machine learning model, which can be trained based on offline data such as the amplitude and phase of the electrical signal on the power line, and the energy distribution of noise generated by the switching transistors in the power converter 20 in each power frequency cycle. The aforementioned electrical signal can be an electrical signal after removing the fundamental frequency and DC component, or it can be a power frequency electrical signal, i.e., a power frequency sine wave.

[0072] Optionally, such as Figure 4As shown, the aforementioned time slot detection circuit 12 may include a noise slot detector 121 and an auxiliary logic module 122. The noise slot detector 121 is capable of detecting low-noise time slots with small energy (amplitude) within the communication frequency band in the time domain, amidst the noise generated by the power conversion circuit in the power converter 20. Furthermore, the noise slot detector 121 can generate interaction signals with the auxiliary logic module 122 to provide the necessary time slot information to the auxiliary logic module 122. The noise slot detector 121 can be implemented using discrete devices or integrated circuits.

[0073] The auxiliary logic module 122 interacts with the noise time slot detection module 121 and the PLC circuit 13, and analyzes the time slot information obtained by the noise time slot detection module 121 (such as information indicating low-noise time slots) to allocate transmission time slots for the PLC downlink frames. For example, the auxiliary logic module 122 can identify and schedule downlink frames that can be transmitted using the low-noise time slots, and generate an interactive signal to control the PLC circuit 13. This interactive signal can be an enable signal or an interrupt signal, and the PLC circuit 13 can send a signal to the power converter 20 via the power line under the control of this interactive signal, i.e., transmit the downlink frame.

[0074] For example, the auxiliary logic module 122 can schedule downlink frames that meet the frame length and service requirements to be transmitted in the low-noise time slot. Since the duration of the low-noise time slot is relatively short, short frames can be scheduled for transmission in this low-noise time slot. Furthermore, since low-noise time slots typically occur at regular intervals, downlink frames with lower service urgency can be scheduled for transmission in this low-noise time slot. A short frame can refer to a downlink frame that can be transmitted within one low-noise time slot according to the data transmission rate corresponding to the PLC communication frequency band. That is, a short frame can refer to a downlink frame with a frame length less than or equal to a frame length threshold, where the frame length threshold is equal to the product of the data transmission rate and the duration of one low-noise time slot.

[0075] It is understood that the auxiliary logic module 122 can be implemented using digital circuits, such as logic circuits, or it can be implemented using discrete components or integrated circuits. Furthermore, the auxiliary logic module 122 can be set up independently of the PLC circuit 13. Alternatively, as... Figure 5 As shown, the auxiliary logic module 122 can also be integrated into the PLC circuit 13 to avoid increasing the structural complexity and hardware cost of the data acquisition unit.

[0076] As a first optional implementation of AFE circuit 11 and time slot detection circuit 12, such as Figure 5As shown, the AFE circuit 11 includes a coupling circuit 11a, and the time slot detection circuit 12 includes a phase detector 121a and a signal processing circuit 121b. For example, see reference... Figure 4 and Figure 5 The noise time slot detection module 121 in the time slot detection circuit 12 includes a phase detector 121a and a signal processing circuit 121b.

[0077] The coupling circuit 11a is used to couple an electrical signal from the power line, and the electrical signal coupled by the coupling circuit 11a is a power frequency signal, i.e., a fundamental wave or a power frequency sine wave. The phase detector 121a is used to detect the phase of the electrical signal. The signal processing circuit 121b is used to obtain the low-noise time slot of the power converter 20 in each power frequency cycle based on the phase of the electrical signal. For example, the signal processing circuit 121b can identify the low-noise time slot with low noise energy in the time domain within the communication band of the PLC system based on the correlation between the phase of the electrical signal, the switching timing of the switching transistors in the power converter 20, and the distribution of noise energy. The signal processing circuit 121b can also be called a logic processing module. The signal processing circuit 121b can be implemented by discrete devices or integrated circuits, and the signal processing circuit 121b can be set independently of the PLC circuit 13, or it can be integrated into the PLC circuit 13.

[0078] It is understandable that the phase of the power frequency signal (such as the grid power frequency voltage) on the power line determines the phase of the three-phase output voltage of the power converter 20, and thus determines the switching timing of the switching transistors in the power converter 20. Furthermore, when multiple power converters 20 are connected to the grid, their phases must remain synchronized. Therefore, in this implementation, the time slot detection circuit 12 can use the phase of the electrical signal on the power line as a feature that can be directly obtained on the power line and is correlated with the switching timing of the switching transistors in the power converter 20, and obtain a low-noise time slot based on this feature. In the scenario where multiple power converters 20 are connected to the grid, the aforementioned power line can refer to the power line after the multiple power converters 20 are connected.

[0079] It is also understood that, in this first implementation, the electrical signal coupled from the power line by the coupling circuit 11a can be either power frequency voltage or power frequency current. The power frequency voltage can be the line voltage of a high-voltage power frequency sinusoidal wave (…). Figure 5Taking the line voltage between phases A and B as an example, or phase voltage; the power frequency current can be the line current or phase current of a high-voltage power frequency sine wave. Furthermore, the coupling circuit 11a can also process the electrical signal on the power line into a power frequency sine wave that meets the input requirements of the subsequent circuit (such as phase detector 121a), so that the phase detector 121a can detect the phase of the power frequency sine wave. The input requirements of the phase detector 121a refer to the requirements for the amplitude of the input signal. For example, assuming that the phase detector 121a requires the amplitude of the input power frequency sine wave to be 5 volts (V), then the coupling circuit 11a can process the electrical signal on the power line to ensure that the amplitude of the power frequency sine wave input to the phase detector 121a is within 5V.

[0080] It is also understood that, since the phases of the electrical signals on each phase line in the power line have a specific phase relationship, i.e., the phase difference between any two phase lines is 120°, in the first implementation described above, the phase line connected to the coupling circuit 11a can be different from the phase line connected to the PLC circuit 13. Furthermore, the coupling circuit 11a can also connect only one phase line. Correspondingly, after the time slot detection circuit 12 detects the phase of the electrical signal on the phase line connected to the coupling circuit 11a, it can infer the phase of the electrical signal on the phase line connected to the PLC circuit 13 based on this phase, and thus detect the low-noise time slot. For example, assuming the PLC circuit 13 is connected to phase lines A and B respectively, the coupling circuit 11a can connect phase lines A and C, or phase lines B and C, or it can connect only phase lines A, B, or C. This application embodiment does not limit the phase line connected to the coupling circuit 11a.

[0081] It is also understandable that the coupling circuit 11a also serves as a high-voltage isolation device. Furthermore, as... Figure 5 As shown, in this first implementation, the AFE circuit 11 may further include a filter 11b. The filter 11b can be used to filter the signal coupled to the coupling circuit 11a to further filter out harmonic components and obtain a power frequency sine wave.

[0082] The following section uses the power conversion circuit in power converter 20 as an example, specifically a neutral point clamped (NPC) three-level circuit, to explain the relationship between the switching timing of the switching transistors, the phase of the electrical signal, and the energy of noise in this power conversion circuit. Figure 6 As shown, the NPC three-level circuit includes phase A, phase B, and phase C. Each phase arm includes four switching transistors T1 to T4 connected in series between the positive (+) and negative (-) terminals of the DC circuit, as well as diodes D1 and D2 connected in series. Diodes D1 and D2 are connected in parallel across switching transistors T2 and T3. The series connection point between switching transistors T2 and T3 in each phase arm is the output terminal.

[0083] Figure 7 The diagram illustrates the correspondence between the switching timing of the transistors, the phase of the electrical signal, and the energy of the noise in the power converter 20. Specifically, Figure 7 The diagram shows the waveforms of the PWM signals of the four switching transistors T1 to T4 in the A-phase bridge arm, the waveforms of the PWM signals of the four switching transistors T1 to T4 in the B-phase bridge arm, the waveforms of the A-phase voltages after removing the base wave, the waveform of the A-phase voltage, and the waveform of the A-line current. Figure 7 The horizontal axis represents time T, and its unit is 1e-1 (representing 1×10⁻¹). -1 (i.e., 0.1) seconds. The PWM signal for each switching transistor is used to control the switching of that transistor; therefore, the timing of the PWM signal can characterize the switching timing of the transistors. The unit of this PWM signal can be a normalized voltage value. For example... Figure 7 In the diagram, 0 represents a low level, and 1 represents a high level. The switching transistor is turned off when the PWM signal is low and turned on when the PWM signal is high. AB phase voltage refers to the line voltage between phases A and B. The fundamental frequency (FYG) refers to the core frequency component of power transmission on the power line (i.e., the power frequency, e.g., 50Hz). The AB phase voltage after removing the FYG is the harmonic component in the AB phase voltage, which is the amplitude of the noise generated by the switching transistor, and its unit is V. Phase A voltage refers to the voltage between phase A line and the neutral line, and its unit is V. Phase A line current refers to the current flowing through phase A line, and its unit is ampere (A).

[0084] refer to Figure 7 It can be seen that the duration of each power frequency cycle is 0.02 seconds. Within each power frequency cycle, the switching timing of the switching transistors in the power converter 20 (i.e., the timing of the PWM signal) and the electrical signal ( Figure 7 (Taking the A-phase voltage and A-line current as an example for illustration) There is a clear correspondence between the phases of the electrical signal and the energy (i.e., amplitude) of the noise generated by the switching transistor in the power converter 20. For example, refer to... Figure 7 The waveforms of the A and B phase voltages after removing the fundamental frequency (i.e., the waveforms of the noise amplitude) show that there are two low-noise time slots within each power frequency cycle. Specifically, the phase range of the A-phase voltage and A-line current in the first low-noise time slot (time slot 1) is 120° to 180°, and the phase range of the A-phase voltage and A-line current in the second low-noise time slot (time slot 2) is 300° to 360°. Furthermore, within each low-noise time slot, the switches in the power converter 20 maintain specific switching states. For example, in time slot 1, switch T2 in both the A-phase and B-phase bridge arms remains on, switch T4 remains off, and switches T1 and T3 are in a high-frequency switching state. In time slot 2, switch T1 in both the A-phase and B-phase bridge arms remains off, switch T3 remains on, and switches T2 and T4 are in a high-frequency switching state.

[0085] As a second optional implementation of AFE circuit 11 and time slot detection circuit 12, such as Figure 8 As shown, the AFE circuit 11 includes a coupling circuit 11c and an ADC 11d. The coupling circuit 11c couples the power line signal from the power line and removes the fundamental frequency and DC component from the power line signal to obtain a noise signal. The ADC 11d converts the noise signal from an analog signal to a digital signal to obtain the electrical signal described above. That is, the electrical signal obtained by the AFE circuit 11 is a noise signal after removing the fundamental frequency and DC component and undergoing analog-to-digital conversion. The time slot detection circuit 12 obtains the low-noise time slot of the power converter 20 in each power frequency cycle based on the amplitude variation of the noise signal after conversion to a digital signal.

[0086] It is understood that PLC circuit 13 also includes AFE circuit; for example, PLC circuit 13 includes AFE circuit and PLC chip. In this second implementation, some or all of the components in the aforementioned AFE circuit 11 can be reused with the corresponding components in the AFE circuit of PLC circuit 13 to reduce the structural complexity and hardware cost of the data acquisition unit. For example, the coupling circuit 11c in the AFE circuit 11 can reuse the coupling circuit in PLC circuit 13. Furthermore, the coupling circuit 11c can also achieve high-voltage isolation from the power line.

[0087] Optionally, continue to refer to Figure 8 The AFE circuit 11 may also include a filter 11e, which can be used to filter the signal output by the coupling circuit 11c to further remove the fundamental frequency and / or DC component, and / or filter the signal output by the coupling circuit 11c into the communication frequency band of the PLC.

[0088] In this implementation, the time slot detection circuit 12 is a digital circuit capable of detecting noise signals and performing related logic processing. For example, it can identify noise characteristics related to the switching timing of the switching transistors in the power converter 20 using a preset algorithm or machine learning method, and further obtain low-noise time slots within the communication frequency band in the time domain using related logic. The time slot detection circuit 12 can be implemented using discrete components or integrated circuits, and it can be set independently of the PLC circuit 13 or integrated into the PLC circuit 13.

[0089] In one possible example of this second implementation, the time slot detection circuit 12 can detect the variation pattern of the noise signal amplitude within each power frequency cycle and identify time slots with amplitudes below a threshold as low-noise time slots. This threshold can be obtained based on the average amplitude of the noise signal over one power frequency cycle. For example, the threshold can be less than or equal to this average value.

[0090] Example, Figure 9 A schematic diagram of the timing waveform of the noise signal in the power converter is shown. Figure 9 The horizontal axis represents time in seconds, and the vertical axis represents amplitude in millivolts (mV). Furthermore, Figure 9 The amplitude of the noise signal shown is obtained by attenuating it according to a certain ratio. Figure 9 The left side of the image shows the waveform of the noise signal over several power frequency cycles, and the right side is a magnified view of time period T0 within the waveform on the left. Each power frequency cycle is 0.02 seconds long. For example... Figure 9 One power frequency cycle is 0.02 seconds to 0.04 seconds, and another is 0.04 seconds to 0.06 seconds. From Figure 9 It can be seen that there is at least one low-noise time slot in each power frequency cycle, and the amplitude of the noise signal in the low-noise time slot is significantly lower than that in other time slots.

[0091] In another possible example of this second implementation, the time slot detection circuit 12 can detect the variation pattern of the noise signal amplitude within each power frequency cycle and obtain the occurrence period of impulse noise in the noise signal, and then obtain a low-noise time slot based on the occurrence period of the impulse noise. (Reference) Figure 9 It can be seen that the noise signal generated by the power converter 20 contains pulse noise (also known as large pulse noise) that occurs at the power frequency. This pulse noise has a short duration, a pulse-like waveform, and an amplitude much higher than that of other non-pulse noise. From Figure 9 It can also be seen that there is a certain correlation between the occurrence period of impulse noise and the low-noise time slot. For example, a low-noise time slot exists after a certain duration (e.g., 1 / 6 of a power frequency cycle) following the occurrence of each impulse noise. Therefore, the time slot detection circuit 12 can also obtain the low-noise time slot within each power frequency cycle based on the occurrence period of the impulse noise.

[0092] For example, the time slot detection circuit 12 may pre-store a machine learning model trained based on offline data. The time slot detection circuit 12 can input the characteristics of the noise signal (such as amplitude) into the machine learning model to obtain the time slot information of the low-noise time slots output by the machine learning model. The offline data may include the characteristics (such as amplitude) of the noise signal generated in each power frequency cycle during the operation of the power converter 20, as well as the time slot information of the low-noise time slots within each power frequency cycle. The time slot information can be used to indicate the position of the low-noise time slots within each power frequency cycle; for example, the time slot information may include the start and end times of the low-noise time slots within each power frequency cycle.

[0093] Optionally, each power frequency cycle may include at least two low-noise time slots. For example, refer to Figure 7 Each power frequency cycle includes two low-noise time slots, namely time slot 1 and time slot 2. Accordingly, within each power frequency cycle, the PLC circuit 13 in the data acquisition unit can transmit downlink signals through at least two low-noise time slots to ensure timely transmission of downlink signals.

[0094] Optionally, continue to refer to Figure 9 The duration of each low-noise time slot is greater than or equal to 1 / 6 of the power frequency cycle length. For example, assuming the power frequency cycle is 0.02 seconds, the duration of each low-noise time slot can be equal to 1 / 6 of the power frequency cycle length, which is approximately 3.3 ms. This duration of low-noise time slot ensures that the PLC circuit 13 can complete the transmission of a short frame. Alternatively, the duration of the low-noise time slot can be slightly longer than 1 / 6 of the power frequency cycle length to ensure that longer frames can be transmitted within a single low-noise time slot. For example, the duration of each low-noise time slot can also be 4 ms to 5 ms.

[0095] Optionally, the data acquisition unit 10 is used to connect the power converter 20 via a first phase line and a second phase line in the power line. Accordingly, the power converter 20 includes a first arm and a second arm, the first arm being connected to the first phase line and the second arm being connected to the second phase line. For example, refer to... Figures 3 to 6 The first phase line and the second phase line can be phase A and phase B, respectively. The first bridge arm and the second bridge arm can be phase A and phase B, respectively. Based on the above connection method, during the low-noise time slot, the switching state of the switch in the first bridge arm is the same as the switching state of the switch in the second bridge arm.

[0096] It is understandable that the structure of the first bridge arm is the same as that of the second bridge arm. Furthermore, since each of the first and second bridge arms can include multiple switching transistors, the same switching state of the switching transistors in the first and second bridge arms can mean that the switching state of each switching transistor in the first bridge arm is the same as the switching state of the corresponding switching transistor in the second bridge arm. That is, the switching states of the switching transistors at the same positions in both bridge arms are the same. The switching state of each switching transistor can include: on, off, and high-frequency switching states.

[0097] Example, reference Figure 7 In time slot 1, switch T2 in both phase A and phase B bridge arms remains on, switch T4 remains off, and switches T1 and T3 are both in high-frequency switching mode. In time slot 2, switch T1 in both phase A and phase B bridge arms remains off, switch T3 remains on, and switches T2 and T4 are both in high-frequency switching mode.

[0098] It is also understandable that the phase and amplitude of the electrical signal on the power line are related to the switching timing of the transistors in each arm of the power converter. Since the low-noise time slots have the aforementioned correspondence with the switching states of the transistors in the two arms, the data acquisition unit can obtain the switching timing of the transistors in each arm by measuring the phase or amplitude of the electrical signal on the power line, and thus obtain the low-noise time slots. For example, the time slot detection circuit 12 can obtain the switching timing of the transistors in each arm based on the phase or amplitude of the electrical signal, and identify the time slots where the switching states of the transistors in the first and second arms are the same as the low-noise time slots.

[0099] It is also understandable that, since the switching timing of the transistors in the power converter is usually fixed and periodically repeating, the position of the aforementioned low-noise time slot within each power frequency cycle is also fixed; that is, the low-noise time slot will periodically repeat at fixed intervals. Accordingly, the data acquisition unit can detect the low-noise time slot information once during idle periods (i.e., periods when no signal transmission is required) based on the amplitude or phase of the electrical signal on the power line. For example, it can detect the low-noise time slot information once based on the amplitude or phase of the electrical signal for at least two power frequency cycles. Afterward, the data acquisition unit can directly obtain the low-noise time slot in the current power frequency cycle based on the pre-detected time slot information when a signal transmission is needed, without needing to detect the low-noise time slot in real time using the amplitude or phase of the electrical signal on the power line. The signal can then be transmitted within that low-noise time slot.

[0100] In addition, to ensure the accuracy of the obtained low-noise time slots, the data acquisition unit can also reacquire electrical signals from the power line at regular intervals, and reacquire the low-noise time slots in each power frequency cycle based on the amplitude or phase of the acquired electrical signals, so as to achieve periodic updates of the low-noise time slots.

[0101] For example, the data acquisition unit can update the low-noise time slot after each power-on startup and subsequent stable operation of the power converter. Alternatively, the data acquisition unit can update the low-noise time slot when it detects changes in the power converter's operating conditions (such as input / output voltage, current, or power) exceeding a certain threshold. For instance, the low-noise time slot might be updated when the voltage change reaches 10V, the current change reaches 5A, and / or the power change reaches 20W. It is understood that the data acquisition unit can obtain this operating condition information of the power converter through PLC communication. Furthermore, if the power converter's operating conditions are relatively stable, the data acquisition unit can update the low-noise time slot at a fixed period (e.g., half an hour).

[0102] Figure 10 This is a schematic diagram of the in-band power spectral density of noise in a power converter provided in an embodiment of this application, that is, a schematic diagram of the energy of noise in the frequency domain. Figure 10 The horizontal axis represents frequency in megahertz (MHz), and the vertical axis represents power spectral density in decibel-milliwatts per hertz (dBm / Hz). The in-band power spectral density refers to the power spectral density within the communication band of the PLC system, as referenced... Figure 10 The PLC's communication frequency band can include 0.5MHz to 4MHz. Furthermore, Figure 10 Curve 1 in the figure shows the power spectral density of time slots other than the low-noise time slot (i.e., the high-amplitude noise segment), and curve 2 shows the power spectral density of the low-noise time slot (i.e., the low-amplitude noise segment). From Figure 10 As shown in curves 1 and 2, the power spectral density of the noise generated by the switching transistors in power converter 20 during the low-noise time slot is significantly lower compared to other time slots. For example, in other time slots, the total in-band power of the noise generated by the switching transistors in power converter 20 is 23.48 dBm, while in the low-noise time slot, the total in-band power of the noise generated by the switching transistors in power converter 20 is only 17.89 dBm. Because the noise energy is lower in this low-noise time slot, transmitting signals in this low-noise time slot can effectively improve the signal-to-noise ratio and enhance the communication quality of the PLC system.

[0103] It is understood that in this embodiment, the AFE circuit 11, time slot detection circuit 12, and PLC circuit 13 in the data acquisition unit can all be considered as part of the PLC transmitter. As mentioned above, the noise generated by the power converter has the characteristic that the energy distribution in the time domain is related to the switching timing of the switching transistors in the power converter. At the same time, some characteristics exhibited by the electrical signals on the power line, such as the phase of the voltage or current signal, or the amplitude of the noise signal (such as power frequency large pulse noise), or other machine learning-based features, are also related to the switching timing of the switching transistors in the power converter. Therefore, the PLC transmitter can obtain the switching timing of the switching transistors in the power converter from one or more characteristics directly exhibited by the electrical signals on the power line, and thus obtain the time slots with smaller energy in the noise caused by the operation of the switching transistors. That is, the PLC transmitter in this data acquisition unit can make communication transmission decisions based on the energy distribution characteristics of the noise generated by the switching transistors in the receiver equipment (i.e., the power converter), thereby effectively improving the reception signal-to-noise ratio and transmission reliability.

[0104] In summary, this application provides a data acquisition device that connects to a power converter via a power line. Furthermore, the data acquisition device can obtain the low-noise time slot of the power converter in each power frequency cycle based on the phase or amplitude of the electrical signal acquired from the power line, and send a signal to the power converter during this low-noise time slot. Since the energy of the noise generated by the switching transistors in the power converter during this low-noise time slot is relatively low in each power frequency cycle, sending a signal by the data acquisition device during this low-noise time slot ensures a high signal-to-noise ratio for the signal received by the power converter. This effectively improves the reliability of PLC communication.

[0105] Furthermore, this data acquisition unit can obtain the switching timing of the switching transistors in the power conversion circuit by analyzing the phase or noise characteristics of the electrical signals on the power line. This ensures accurate and low-cost acquisition of the switching timing of the switching transistors at the receiver end (i.e., the power converter) at a remote location (i.e., the data acquisition unit), thereby enabling accurate acquisition of low-noise time slots.

[0106] This application also provides a signal transmission method, which can be applied to the data acquisition device provided in the above embodiments. This data acquisition device is used to connect a power converter via a power line. Figure 11 As shown, the method includes:

[0107] Step 101: Obtain an electrical signal from the power line, which can be a voltage signal or a current signal.

[0108] Step 102: Obtain the low-noise time slot of the power converter in each power frequency cycle based on the amplitude or phase of the electrical signal.

[0109] Step 103: Send a signal to the power converter via the power line during the low-noise time slot.

[0110] Within each power frequency cycle, the energy of noise generated by the switching transistors in the power converter during the low-noise time slot is lower than the energy of noise generated during switching in other time slots. Other time slots are the time slots within the power frequency cycle other than the low-noise time slot.

[0111] It is understood that step 101 can be implemented by the AFE circuit in the data acquisition unit, step 102 can be implemented by the time slot detection circuit in the data acquisition unit, and step 103 can be implemented by the PLC circuit in the data acquisition unit. For the implementation process of each of the above steps, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0112] Optionally, each power frequency cycle includes at least two low-noise time slots. The duration of each low-noise time slot can be greater than or equal to 1 / 6 of the duration of the power frequency cycle.

[0113] Optionally, step 102 above may include:

[0114] Step 1021: Based on the phase or amplitude of the electrical signal, obtain the switching timing of the switching transistors in the power converter for each power frequency cycle.

[0115] Step 1022: Based on the correspondence between switching timing and noise energy, obtain low-noise time slots.

[0116] It is also understood that the embodiments of the above signal transmission method have essentially the same implementation methods and technical effects as the embodiments of the aforementioned data acquisition device. Therefore, for the sake of brevity, the implementation methods and technical effects of the signal transmission method will not be described again here.

[0117] This application also provides another data acquisition device for connecting a power converter via a power line. The data acquisition device includes an AFE circuit and a timing detection circuit. The AFE circuit is used to connect to the power line and acquire an electrical signal from the power line, which is a voltage signal or a current signal. The timing detection circuit is used to obtain the switching timing of the switching transistors in the power converter based on the phase or amplitude of the electrical signal.

[0118] As an optional implementation, the AFE circuit obtains a power frequency signal, i.e., a power frequency sine wave, from the power line. This timing detection circuit is used to obtain the switching timing of the transistors in the power converter based on the phase of the electrical signal. Since the phase of the power frequency signal on the power line determines the output phase of the power converter, and the power converter adjusts its output phase through the switching timing of the transistors, the timing detection circuit can accurately detect the switching timing of the transistors in the power converter based on the phase of this electrical signal.

[0119] The AFE circuit may include a coupling circuit capable of coupling a power frequency signal from the power line. The timing detection circuit may include a phase detector and a signal processing circuit. The phase detector detects the phase of the power frequency signal coupled to the coupling circuit. The signal processing circuit obtains the switching timing of the switching transistors in the power converter based on the phase of the electrical signal.

[0120] As an alternative implementation, the AFE circuit obtains a noise signal from the power line after removing the fundamental frequency and DC component. The timing detection circuit is used to analyze the characteristics (such as amplitude) of this noise signal to obtain the switching timing of the switching transistors in the power converter.

[0121] The AFE circuit includes a coupling circuit and an ADC. The coupling circuit couples the power line signal from the power line and removes the fundamental frequency and DC component from the power line signal to obtain a noise signal. The ADC converts the noise signal from an analog signal to a digital signal to obtain an electrical signal. The signal processing circuit obtains the switching timing of the transistors in the power converter based on the amplitude variation of the noise signal after conversion to a digital signal. For example, the signal processing circuit can identify impulse noise in the noise signal based on the amplitude variation of the noise signal and obtain the switching timing of the transistors in the power converter based on the occurrence period of the impulse noise.

[0122] This application also provides a photovoltaic system, such as... Figure 3 As shown, the photovoltaic system includes a data acquisition unit 10 as provided in the above embodiment and at least one power converter 20. The data acquisition unit 10 is connected to the at least one power converter 20 via a power line and is used to exchange signals via the power line.

[0123] Example, reference Figure 1 The photovoltaic system may include multiple power converters. The AC terminals of the multiple power converters are combined through a combiner box and then connected to the data acquisition unit 10 through a power line.

[0124] It is understood that the solutions provided in this application can be applied to power systems that use PLC technology as an inter-device communication subsystem. For example, they can be applied to new energy power plant scenarios, such as photovoltaic power plants or energy storage power plants, and other industrial and commercial scenarios that simultaneously have communication and power conversion systems.

[0125] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" refers to one or more, and "multiple" refers to two or more.

[0126] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0127] The above description is merely an optional implementation of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data acquisition device, characterized in that, The data acquisition unit is used to connect to the power converter via the power line, and the data acquisition unit includes: an analog front-end AFE circuit, a time slot detection circuit, and a power line communication PLC circuit; The AFE circuit is used to connect to the power line and to obtain an electrical signal from the power line, wherein the electrical signal is a voltage signal or a current signal. The time slot detection circuit is used to obtain the low-noise time slot of the power converter in each power frequency cycle based on the phase or amplitude of the electrical signal. The PLC circuit is used to send signals to the power converter via the power line during the low-noise time slot; Wherein, within each power frequency cycle, the energy of the noise generated by the switching transistor in the power converter during the low-noise time slot is lower than the energy of the noise generated during the switching in other time slots, wherein the other time slots are the time slots within the power frequency cycle other than the low-noise time slot.

2. The data acquisition device according to claim 1, characterized in that, Each of the power frequency cycles includes at least two of the low-noise time slots.

3. The data acquisition device according to claim 1 or 2, characterized in that, The duration of the low-noise time slot is greater than or equal to 1 / 6 of the duration of the power frequency cycle.

4. The data acquisition device according to any one of claims 1 to 3, characterized in that, The time slot detection circuit is used to obtain the switching timing of the switching transistor in the power converter in each power frequency cycle according to the phase or amplitude of the electrical signal, and to obtain the low noise time slot based on the correspondence between the switching timing and the energy of the noise.

5. The data acquisition device according to claim 4, characterized in that, The data acquisition unit is used to connect the power converter through the first phase line and the second phase line in the power line, and the power converter includes a first bridge arm and a second bridge arm, the first bridge arm being connected to the first phase line and the second bridge arm being connected to the second phase line; During the low-noise time slot, the switching state of the switch in the first bridge arm is the same as that of the switch in the second bridge arm.

6. The data acquisition device according to any one of claims 1 to 5, characterized in that, The AFE circuit includes a coupling circuit, and the time slot detection circuit includes a phase detector and a signal processing circuit. The electrical signal obtained by the coupling circuit from the power line is a power frequency signal; The phase detector is used to detect the phase of the electrical signal; The signal processing circuit is used to obtain the low-noise time slot of the power converter in each power frequency cycle based on the correspondence between the phase of the electrical signal and the energy of the noise generated by the switching transistor in the power converter.

7. The data acquisition device according to any one of claims 1 to 5, characterized in that, The AFE circuit includes: a coupling circuit and an analog-to-digital conversion circuit; The coupling circuit is used to couple a power line signal from the power line and remove the fundamental frequency and DC component from the power line signal to obtain a noise signal. The analog-to-digital converter circuit is used to convert the noise signal from an analog signal to a digital signal to obtain the electrical signal; The time slot detection circuit is used to obtain the low-noise time slot of the power converter in each power frequency cycle based on the variation law of the amplitude of the noise signal after it is converted into a digital signal.

8. A signal transmission method, characterized in that, Applied to a data acquisition unit for connecting a power converter via a power line, the method includes: An electrical signal is obtained from the power line, wherein the electrical signal is a voltage signal or a current signal; The low-noise time slot of the power converter in each power frequency cycle is obtained based on the amplitude or phase of the electrical signal. During the low-noise time slot, a signal is sent to the power converter via the power line; Wherein, within each power frequency cycle, the energy of the noise generated by the switching transistor in the power converter during the low-noise time slot is lower than the energy of the noise generated during the switching in other time slots, wherein the other time slots are the time slots within the power frequency cycle other than the low-noise time slot.

9. The method according to claim 8, characterized in that, Each of the aforementioned power frequency cycles includes at least two of the aforementioned low-noise time slots.

10. The method according to claim 8 or 9, characterized in that, The duration of the low-noise time slot is greater than or equal to 1 / 6 of the duration of the power frequency cycle.

11. The method according to any one of claims 8 to 10, characterized in that, The step of obtaining the low-noise time slot of the power converter in each power frequency cycle based on the amplitude or phase of the electrical signal includes: Based on the phase or amplitude of the electrical signal, the switching timing of the switching transistors in the power converter in each power frequency cycle is obtained; The low-noise time slot is obtained based on the correspondence between the switching timing and the energy of the noise.

12. A photovoltaic system, characterized in that, The photovoltaic system includes: a data acquisition unit as described in any one of claims 1 to 7 and at least one power converter; The data acquisition unit is connected to the at least one power converter via a power line and is used to exchange signals via the power line.

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