Charge pump, method of driving circuit, display device, and electronic apparatus

Abstract

The application provides a charge pump, a driving circuit method, a display device and an electronic equipment, wherein the charge pump comprises a first driving circuit; the first driving circuit comprises a first control circuit, a second control circuit, a first input circuit, a second input circuit and a first output end; the first input circuit comprises a first transistor, a control electrode of the first transistor is coupled with the first control circuit, a first electrode of the first transistor is coupled with a first power supply end, a second electrode of the first transistor is coupled with a first capacitor, and the first capacitor is coupled with the first output end; the second input circuit comprises a second transistor, a control electrode of the second transistor is coupled with the second control circuit, a first electrode of the second transistor is coupled with a second power supply end, and a second electrode of the second transistor is coupled with the first capacitor; the first control circuit is used for controlling the conduction or turn-off of the first transistor, and the second control circuit is used for controlling the conduction or turn-off of the second transistor. Therefore, the output voltage of the charge pump can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to charge pumps, methods of driving circuits, display devices, and electronic devices. Background Technology

[0002] As micro-electro-mechanical system (MEMS) devices are applied to sensors, optical communication components, displays and other devices, there is an increasing demand for materials for MEMS devices. Glass substrates, with their high geometric tolerances and chemical stability, can support the precision manufacturing of micron-scale MEMS structures, thus achieving technological breakthroughs in several cutting-edge fields.

[0003] However, the driving voltage of MEMS devices fabricated on glass substrates is typically higher than the power supply voltage of the MEMS device application device. Therefore, additional power supply and control modules are required for MEMS devices, which greatly limits the application of glass substrate MEMS devices. In view of this, a solution that enables MEMS devices to operate without additional power supply is urgently needed. Summary of the Invention

[0004] This application provides a charge pump, a method for driving a circuit, a display device, and an electronic device that can multiply the input voltage of a MEMS device application device to achieve self-supply of the MEMS device voltage, thereby eliminating the need for an additional power supply module.

[0005] In a first aspect, a charge pump is provided, comprising: a first driving circuit; the first driving circuit includes a first control circuit, a second control circuit, a first input circuit, a second input circuit, and a first output terminal; the first input circuit includes a first transistor, the control electrode of the first transistor being coupled to the first control circuit, the first electrode of the first transistor being coupled to a first power supply terminal, the second electrode of the first transistor being coupled to a first capacitor, and the first capacitor being coupled to the first output terminal; the second input circuit includes a second transistor, the control electrode of the second transistor being coupled to the second control circuit, the first electrode of the second transistor being coupled to a second power supply terminal, and the second electrode of the second transistor being coupled to the first capacitor; wherein, the first control circuit is used to control the first transistor to be turned on or off, and the second control circuit is used to control the second transistor to be turned on or off.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the charge pump further includes N first driving circuits, an external transistor, an external control circuit, and an external power supply terminal. The N first driving circuits are cascaded, with the output circuit of the Nth stage first driving circuit capacitively coupled to the (N-1)th stage first driving circuit. The first terminal of the external transistor is coupled to the capacitor of the Nth stage first driving circuit, and the control terminal of the external transistor is coupled to the external control circuit. The external transistor is used to control the on / off state of the external control circuit.

[0007] Based on the above technical solution, by cascading multiple drive circuits that can amplify the output voltage, the charge pump can output a higher multiple of the input voltage, thus meeting the requirement of starting MEMS devices with low input voltage. Furthermore, in the case of cascaded charge pumps, multiple control circuits in each drive stage can be connected to the same clock signal, thereby simplifying the operation process and improving circuit efficiency.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the N first driving circuits are coupled to an integrated gate driving circuit (GOA), the GOA comprising (N+1) second driving circuits, and the (N+1) second driving circuits are cascaded; the second output circuit of the k-th stage second driving circuit among the (N+1) second driving circuits is coupled to a general control circuit of the k-th stage first driving circuit among the N first driving circuits, the general control circuit comprising a first control circuit and a second control circuit, and the second output circuit is also coupled to a trigger circuit of the (k+1)-th stage second driving circuit, the voltage of the trigger circuit being used to adjust the output voltage of the (k+1)-th stage second driving circuit, where k is an integer greater than 0 and less than or equal to N; the (N+1)-th stage second output circuit is coupled to the external transistor.

[0009] Based on the above technical solution, by coupling the cascaded charge pump with the cascaded GOA circuit, the output voltage of the cascaded charge pump can be multiplied by adjusting only the trigger signal STV. Compared with the case where a cascaded charge pump that operates alone needs to adjust multiple spatiotemporal signals at the same time, the operating efficiency of the cascaded charge pump can be significantly improved.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, at least one of the trigger circuits in the integrated gate drive circuit GOA is coupled to a reset transistor, the reset transistor is coupled to a reset control circuit, and the reset control circuit is used to control the conduction of the reset transistor.

[0011] Based on the above technical solution, by adding a reset control circuit to the combined circuit of the cascaded charge pump and the cascaded GOA, the working efficiency of the combined circuit can be further improved, and the cumbersome voltage output process of the clock signal can be saved.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the N second output circuits are the output circuits of the N odd-numbered-level second driving circuits of the GOA, and the output circuit of the i-th level second driving circuit is coupled to the trigger circuit of the (i+1)-th level second driving circuit, and the output circuit of the i-th level second driving circuit is coupled to the total control circuit of the ((i+1) / 2)-th level first driving circuit, where i is an odd number and i is greater than 0.

[0013] In a second aspect, a method for driving a charge pump as described in the first aspect is provided. The method includes: at time q, inputting a low-level signal to a first control circuit and a second control circuit to charge a first capacitor; wherein the voltages at the first power supply terminal and the second power supply terminal are voltages in opposite directions, and q is an integer greater than or equal to 1; at time (q+1), inputting a high-level signal to the second control circuit to discharge the first capacitor, and wherein the voltage at the first output terminal is the sum of the potential difference of the first capacitor and the voltage at the first power supply terminal.

[0014] In conjunction with the second aspect, in some implementations of the second aspect, the first power supply terminal is coupled to a voltage controller, which is used to switch the voltage direction of the first power supply terminal to the opposite direction at the (q+1)th time.

[0015] Based on the above technical solution, by making the first transistor and the second transistor in the on and off states at different times, the first capacitor can be charged. When the first capacitor is discharged, the voltage of the first power supply terminal can be changed, which can increase the input voltage of the charge pump (i.e., the first power supply terminal or the second power supply terminal) by several times and output to other circuits of the MEMS device, thereby satisfying the situation of starting the MEMS device with a low input voltage.

[0016] In conjunction with the second aspect, in some implementations of the second aspect, the transistors of each stage of the first driving circuit in the N first driving circuits are turned on sequentially in the order from the first stage to the Nth stage.

[0017] In conjunction with the second aspect, in some implementations of the second aspect, the potential difference of the capacitors in each stage of the driving circuit is the same.

[0018] Thirdly, a microelectromechanical system device is provided, comprising: a charge pump as described in the first and second aspects.

[0019] Fourthly, a display device is provided, including the microelectromechanical system as described in the third aspect.

[0020] Fifthly, an electronic device is provided, including a display device as described in the fourth aspect. Attached Figure Description

[0021] Figure 1 This is a simplified circuit diagram for a loudspeaker suitable for microelectromechanical systems (MEMS) devices;

[0022] Figure 2 This is a schematic diagram of a GOA circuit;

[0023] Figure 3 This is a waveform diagram illustrating the operation of a GOA circuit;

[0024] Figure 4 This is a schematic diagram of a charge pump drive circuit proposed in an embodiment of this application;

[0025] Figure 5 This is a flowchart of a driving method for a charge pump circuit proposed in an embodiment of this application;

[0026] Figure 6 This is a waveform diagram of a charge pump circuit proposed in an embodiment of this application;

[0027] Figure 7 This is a schematic circuit diagram of a cascaded charge pump proposed in an embodiment of this application;

[0028] Figure 8 This is a flowchart of a driving method for a cascaded charge pump circuit proposed in an embodiment of this application;

[0029] Figure 9 This is a waveform diagram of a cascaded charge pump circuit proposed in an embodiment of this application;

[0030] Figure 10 This is a schematic diagram of a simulation result proposed in an embodiment of this application;

[0031] Figure 11 This is a schematic diagram of a combined circuit of a cascaded GOA circuit and a cascaded charge pump proposed in an embodiment of this application;

[0032] Figure 12 This is a waveform diagram of a combinational circuit proposed in an embodiment of this application;

[0033] Figure 13 This is a schematic diagram of another combined circuit proposed in an embodiment of this application;

[0034] Figure 14This is a waveform diagram of another combined circuit proposed in an embodiment of this application;

[0035] Figure 15 This is a schematic diagram of a combined circuit of an odd-even cascaded GOA circuit and a cascaded charge pump proposed in an embodiment of this application;

[0036] Figure 16 This is a waveform diagram of a combinational circuit proposed in an embodiment of this application;

[0037] Figure 17 This is a waveform diagram of another combined circuit proposed in an embodiment of this application. Detailed Implementation

[0038] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0039] This application will present various aspects, embodiments, or features relating to a system comprising multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0040] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the embodiments of this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0041] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0042] In the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more, and "at least one" and "one or more" refer to one, two, or more than two. The singular expressions "a," "an," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context explicitly indicates otherwise.

[0043] In the description of the embodiments of this application, the terms "upper," "lower," "left," "right," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship relative to the orientation or position of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and not to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. They can change accordingly depending on the orientation of the components in the accompanying drawings, and therefore should not be construed as limiting this application.

[0044] In the embodiments of this application, the same reference numerals are used to denote the same component or part. For the same part in the embodiments of this application, only one part or component may be labeled with reference numerals in the figures. It should be understood that the reference numerals also apply to other identical parts or components. In addition, the various parts in the figures are not drawn to scale, and the dimensions and sizes of the parts shown in the figures are only exemplary and should not be construed as limiting this application.

[0045] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0046] It should be noted that in the embodiments of this disclosure, the control electrode of a transistor specifically refers to the gate of the transistor; to distinguish between the source and drain of a transistor, one electrode is called the first electrode, the other is called the second electrode, and the gate is called the control electrode. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments are described using P-type transistors. When using a P-type transistor, the first electrode is the source, and the second electrode is the drain; the opposite is true for N-type transistors. It is conceivable that using an N-type transistor to implement the technical solutions of the following embodiments is something that those skilled in the art can easily conceive of without creative effort, and therefore falls within the protection scope of the embodiments of this disclosure.

[0047] Figure 1 This is a simplified circuit diagram for a loudspeaker suitable for microelectromechanical systems (MEMS) devices.

[0048] like Figure 1 As shown, the circuit diagram of the loudspeaker includes loudspeaker components BL1 and BL2, and capacitor C0. The right side of capacitor C0 is coupled to the positive terminal of BL2, and the left side of capacitor C0 is coupled to the positive terminal of BL1. Loudspeaker component BL1 is a woofer, loudspeaker BL2 is a tweeter, and capacitor C0 is a crossover capacitor.

[0049] One possible implementation is that high-frequency signals pass through tweeter BL2, while low-frequency and mid-frequency signals pass through speaker BL1. Specifically, by adjusting the value of capacitor C0, the current is blocked, thus preventing low-frequency and mid-frequency signals from passing through tweeter BL2.

[0050] The MEMS loudspeaker fabricated based on this circuit can be applied to the solutions described in the embodiments of this application. It should be noted that... Figure 1 The speaker circuit diagram and its MEMS speaker shown are merely examples. The methods described below in this application embodiment are also applicable to other devices manufactured based on MEMS devices.

[0051] To facilitate understanding, some terms or concepts that may be involved in the embodiments of this application will be briefly described first.

[0052] 1. Charge pump

[0053] A charge pump is a DC-DC circuit that uses capacitor charging and discharging to achieve voltage conversion. Its core components include capacitors, switching transistors, and clock signal controllers. It does not require inductors. It uses switching control to periodically switch the capacitor connection mode to achieve capacitor energy storage and charge transfer, thereby achieving boost, buck, or reverse voltage output.

[0054] 2. GOA circuit

[0055] GOA (gate-on-array) is a technology that integrates the gate driving circuit directly onto the display panel array substrate. By replacing the traditional external gate driving chip, it achieves internal integration of the panel driving function, reducing the number of peripheral circuit components and thus simplifying the circuit. In the embodiments of this application, the output signal of the GOA circuit is mainly used to control the conduction of the transistor in the charge pump.

[0056] For example, Figure 2 This is a schematic diagram of a GOA circuit. Figure 3 This is a waveform diagram of a GOA circuit in operation.

[0057] The following is combined with Figure 2 and Figure 3 Explain how to output a low-level voltage using a GOA circuit.

[0058] like Figure 2 As shown, the circuit includes clock signal switches CK and CKB, trigger signal switch STV, capacitors C1X and C2X, and seven transistors (i.e., transistors MX1, MX2...MX7 shown in the figure), a first power supply terminal VGH, and a second power supply terminal VGL. When the trigger signal switch STV outputs a low-level signal, capacitor C2X is charged, so that when the clock signal switch CKB outputs a low-level signal at the next moment, the output circuit of the GOA circuit outputs a low-level voltage.

[0059] Specifically, the first power supply terminal VGH outputs a high voltage, the second power supply terminal VGL outputs a low voltage, and the clock signal switches CK and CKB output waveform voltages in opposite directions. (See also...) Figure 4 , Figure 4 This is a schematic diagram of a charge pump drive circuit proposed in an embodiment of this application.

[0060] like Figure 3 The various moments shown.

[0061] At the first moment, the trigger signal switch STV outputs a high-level signal.

[0062] At this time, the clock signal switch CK outputs a low-level voltage (or signal), and the clock signal switch CKB outputs a high-level voltage. Therefore, the control electrodes of transistors MX1, MX3, and MX6 are input with low-level voltages and are in the on state, thereby causing the high-level signal output from the first power supply terminal VGH to be input to the output circuit of the GOA circuit, that is, the output voltage is the high-level voltage output from the first power supply terminal VGH.

[0063] Similar to the first moment, the trigger signal switch STV continues to output a high-level signal at the second moment, and the output voltage of the GOA circuit is a high-level voltage.

[0064] At the third moment, the trigger signal switch STV outputs a low-level signal.

[0065] At this time, the clock signal switch CK outputs a low-level voltage (or signal), the clock signal switch CKB outputs a high-level voltage, and the control electrodes of transistors MX1, MX3, and MX6 are input with a low-level voltage and are in the on state. Furthermore, because the control STV outputs a low-level voltage, transistors MX2 and MX7 are also in the on state, thus capacitor C2X is charging. Simultaneously, because the first power supply terminal VGH and the clock signal switch CKB output a high-level voltage, the output voltage of the GOA output circuit G1 is also a high-level voltage.

[0066] At the fourth moment, the trigger signal switch STV outputs a high-level signal.

[0067] At this time, the clock signal switch CK outputs a high-level voltage, and the clock signal switch CKB outputs a low-level voltage. Therefore, the control electrodes of transistors MX1, MX2, MX3, MX4, and MX6 all receive a high-level signal and are in the off state. Meanwhile, the capacitor is discharging through C2X, inputting a low-level signal to the control electrode of transistor MX7, turning it on. Subsequently, the low-level voltage output by the clock signal CKB is input to the output circuit of the GOA circuit, meaning the output voltage of the GOA circuit is a low-level voltage.

[0068] MEMS devices have been widely used in electronic devices across various fields, including antennas, phase shifters, sensors, radio frequency devices, optical communication components, and displays. Furthermore, with the development of technologies such as displays and artificial intelligence, devices in various fields are placing higher demands on MEMS devices. For example, in the field of display technology, to improve display quality, in addition to optimizing the internal circuitry of MEMS, high-quality materials are needed to enhance the performance of the MEMS structure.

[0069] With the development of materials synthesis technology, the industry has proposed a type of glass substrate as a material for manufacturing electronic devices. Due to its high geometric tolerance and chemical stability, it can support the precision manufacturing of micron-level MEMS structures. Therefore, MEMS devices made of glass substrates are becoming mainstream components in devices such as displays and sensors. However, the driving voltage of this MEMS device is often higher than the power supply voltage of the MEMS device application device (such as a display screen or sensor). Therefore, the power supply voltage connected to the MEMS device application device cannot meet the normal operation of the MEMS device, and additional power supply and control modules are required for the MEMS device. This greatly limits the application of glass substrate MEMS devices.

[0070] In view of this, embodiments of this application provide a charge pump, a microelectromechanical system (MEMS) device, a display device, and an electronic device. By adding a charge pump to a MEMS device made of a glass substrate, the input voltage of the MEMS device application device (such as a display screen or sensor) can be multiplied to achieve self-supply of the MEMS device voltage, thereby eliminating the need for an additional power supply module or device.

[0071] Figure 4 This is a schematic diagram of a charge pump driving circuit proposed in an embodiment of this application. It can amplify the input voltage of the charge pump and output it to a glass substrate MEMS device.

[0072] like Figure 4 As shown, the drive circuit of this charge pump includes: a first control circuit, a second control circuit, a first input circuit, a second input circuit, and a first output terminal. The above circuits are described in detail below.

[0073] First control circuit: Coupled to the control electrode of the first transistor T1, used to control the conduction of the first transistor T1. For example, the first control circuit can control the conduction of the first transistor T1 by outputting a second clock signal CK2 to the first transistor T1.

[0074] The second control circuit is coupled to the control electrode of the second transistor T2 and is used to control the conduction of the second transistor T2. The second control circuit can control the conduction of the second transistor T2 by outputting a first clock signal CK1 to the second transistor T2.

[0075] First input circuit: includes a first transistor T1, the control electrode of the first transistor T1 is coupled to a first control circuit, the first electrode of the first transistor T1 is coupled to a second variable power supply terminal SIG2, the second variable power supply terminal is coupled to a voltage controller, the second electrode of the first transistor T1 is coupled to a first capacitor C1, and the first capacitor C1 is coupled to a first output terminal OUTPUT.

[0076] The second input circuit includes a second transistor T2, the control electrode of the second transistor T2 is coupled to the second control circuit, the first electrode of the second transistor T2 is coupled to the first variable power supply terminal SIG1, the second electrode of the second transistor T2 is coupled to the first capacitor C1, and the second electrode of the second transistor T2 is also coupled to the first output terminal.

[0077] In some possible embodiments, the voltage of the second variable power supply terminal SIG2 is (+U)V, the voltage of the first variable power supply terminal SIG1 is (-U)V, and the first transistor T1 and the second transistor T2 can be P-type thin film transistors (TFTs). In this case, a low-level signal can turn on the TFT.

[0078] For example, see Figure 5 and Figure 6 , Figure 5 This is a flowchart of a driving method for a charge pump circuit proposed in an embodiment of this application, which can be regarded as... Figure 4 One possible driving method for the circuit shown is... Figure 6 This is a waveform diagram of a charge pump circuit proposed in an embodiment of this application, which can be regarded as... Figure 5 The waveform diagram of the driving method is shown. Figure 5 As shown, the driving method includes the following steps.

[0079] S510, the first control circuit and the second control circuit output a low-level signal to charge the first capacitor.

[0080] Specifically, the first control circuit can output a second clock signal to the first transistor T1, and the second control circuit can output a first clock signal to the second transistor T2. At the first moment (or the q-th moment, where q is an integer greater than or equal to 1), the first clock signal CK1 and the second clock signal CK2 are controlled to output low-level signals. At this moment, the first capacitor C1 is fully charged, and its potential difference is 2U. In other words, the potential difference of the first capacitor C1 is the sum of the absolute values ​​of the voltages at the second variable power supply terminal SIG2 and the first variable power supply terminal SIG1.

[0081] S520, the second control circuit outputs a high-level signal and switches the voltage of the second variable power supply terminal SIG2 to (-U)V.

[0082] Specifically, at the second time point (or the (q+1)th time point), the first clock signal is changed to a high-level signal, that is, the second transistor T2 is turned off, and the voltage at the second variable power supply terminal can be changed from (+U)V to (-U)V using a voltage controller. Therefore, at this time, the first capacitor C1 discharges, and its potential difference (or output voltage) remains (-2U)V, while the voltage at the second variable power supply terminal is (-U)V. Therefore, the voltage at the first output terminal is (-3U)V. It can be understood that, under these circumstances, the voltage at the first output terminal is the sum of the potential difference of the first capacitor and the voltage at the second variable power supply terminal.

[0083] It should be noted that this application embodiment does not limit the voltage magnitude of the second variable power terminal SIG2 and the first variable power terminal SIG1. The voltage of the second variable power terminal SIG2 and the first variable power terminal SIG1 can be the same in magnitude but opposite in direction as described above, or they can be different in magnitude but the same or opposite in direction. This application embodiment does not limit this, nor does it limit the types of the first transistor T1 and the second transistor T2.

[0084] Based on the above technical solution, by making the first transistor T1 and the second transistor T2 in the on and off states at different times, the first capacitor can be charged. When the first transistor T1 is on and the second transistor T2 is off, the voltage of the second variable power supply terminal SIG2 can be changed, so that the output voltage of the charge pump can be expanded to the sum of the potential difference of the first capacitor and the second variable power supply terminal SIG2. The output voltage can be output to other circuits of the MEMS device, thereby satisfying the situation of starting the MEMS device with a low input voltage.

[0085] The above embodiments are charge pumps with a single driving circuit. In practical applications, cascaded charge pumps composed of multiple driving circuits have a wider range of applications in MEMS devices. The working method of cascaded charge pumps will be described in detail below.

[0086] Figure 7 This is a schematic circuit diagram of a cascaded charge pump proposed in an embodiment of this application.

[0087] like Figure 7 As shown, the circuit of this charge pump includes two such... Figure 4 The driving circuit shown may further include: an external transistor TX, an external control circuit, and an external power supply terminal VGX. The first output terminal of the second driving circuit (i.e., the driving circuit on the right in the figure) is coupled to the first capacitor of the first driving circuit (i.e., the driving circuit on the left in the figure). The first terminal of the external transistor TX is coupled to the second capacitor C2 of the second driving circuit. The control terminal of the external transistor TX is coupled to the external control circuit. The external power supply terminal VGX is coupled to the second terminal of the external transistor TX. The external power supply terminal VGX can output a low-level signal. It should be understood that in this cascaded charge pump, the second driving circuit can be referred to as the second-stage driving circuit, and the first driving circuit can be referred to as the first-stage driving circuit.

[0088] It should be noted that the topology and components (capacitors, transistors, etc.) of each stage of the drive circuit in the cascaded charge pump can be the same. For ease of understanding, the components of each stage of the drive circuit are described separately in this embodiment. For example, the capacitor of the first drive circuit (i.e., the first-stage drive circuit) is the first capacitor C1, the capacitor of the second drive circuit (i.e., the second-stage drive circuit) is the second capacitor C2, the transistors of the first drive circuit are the first transistor T1 and the second transistor T2, and the transistors of the second drive circuit are the third transistor T3 and the fourth transistor T4. As another example, the first transistor T1 and the second transistor T2 of the first drive circuit are controlled to conduct by the first control circuit and the second control circuit, respectively; the third transistor T3 and the fourth transistor T4 of the second drive circuit are controlled to conduct by the third control circuit and the fourth control circuit, respectively, and so on.

[0089] In some possible embodiments, the first power supply terminal VGH and the second power supply terminal VGL are constant voltage power supplies of (+U)V and (-U)V, respectively, and are coupled to the transistors of each stage of the driving circuit. All transistors are P-type TFTs. Furthermore, the control circuits of each stage of the driving circuit receive different clock signals, while the control circuits within the same driving circuit receive the same clock signal. That is, the first and second control circuits of the first-stage driving circuit receive the first clock signal, and the third and fourth control circuits of the second-stage driving circuit receive the second clock signal. The following is in conjunction with… Figure 8 and Figure 9 This section introduces the cascaded charge pump. Figure 8 This is a flowchart of a driving method for a cascaded charge pump circuit proposed in an embodiment of this application, which can be regarded as a driving method. Figure 7 A flowchart of one method of the cascaded charge pump. Figure 9 This is a waveform diagram of a cascaded charge pump circuit proposed in an embodiment of this application, which can be regarded as... Figure 8 The waveform diagram of the driving method is shown.

[0090] like Figure 8 , Figure 9 The driving method steps and the various moments shown in the waveform diagram are illustrated.

[0091] S810 controls the first clock signal CK1 to be a low-level signal at the first moment.

[0092] At this time, the first clock signal inputs a low-level signal to the first transistor and the second transistor through the first control circuit and the second control circuit, so that the first transistor and the second transistor are in the conducting state. Meanwhile, the second clock signal sends a high-level signal to the control circuit of the second-stage drive circuit, so that the third transistor and the fourth transistor are in the off state. At this time, the first capacitor C1 is charged.

[0093] S820, at the second moment, controls the first clock signal CK1 to output a high-level signal.

[0094] At this time, the first transistor and the second transistor are in the off state, the first capacitor C1 is discharging, and its potential difference is (2U)V. The left side of the first capacitor is coupled to the first output terminal (that is, the output circuit of the cascaded charge pump), and the circuit on the right side of the first capacitor is in the open circuit state. Therefore, the voltage of the first output terminal is (-U)V.

[0095] S830, at the third moment, controls the second clock signal CK2 to output a low-level signal.

[0096] At this time, the second clock signal inputs a low-level signal to the third and fourth transistors through the third and fourth control circuits, causing the third and fourth transistors to be in the conducting state. At this time, the second capacitor C2 is charged and the first capacitor is discharged, with a potential difference of (2U)V. In the figure, the right side of the first capacitor is at a high potential and the left side is at a low potential. The voltage of the second power supply terminal VGL of the second stage drive circuit is (-U)V. Therefore, the voltage of the first output terminal (i.e., the output circuit of the cascaded charge pump) is (-3U)V. In other words, the voltage of the first output terminal at this time is the sum of the voltage of the first capacitor and the voltage of the second power supply terminal.

[0097] S840, at the fourth moment, controls the second clock signal to output a high-level signal.

[0098] At this time, the second clock signal outputs a high-level signal, the third transistor and the fourth transistor are in the off state, the second capacitor C2 discharges, and its potential difference is (2U)V. The voltage at the first output terminal is (-4U)V, which is the sum of the potential differences between the first capacitor and the second capacitor.

[0099] At the fifth moment, S850 controls the external clock signal CK3 to output a low-level signal.

[0100] At this time, the external clock signal inputs a low-level signal to the external transistor TX through the external control circuit, causing the external transistor TX to conduct. At this time, the voltage of the first output terminal is (-5U)V, which is the sum of the voltages of the first capacitor, the second capacitor, and the external power supply terminal VGX.

[0101] It should be understood that the cascaded charge pump with two drive circuits described above is merely an example, and the embodiments of this application do not limit the number of stages in the cascaded charge pump. Specifically, the cascaded charge pump may include N stages. Figure 4 The driving circuit shown has an output circuit of the Nth stage driving circuit coupled to the capacitor of the (N-1)th stage driving circuit, and the first terminal of the external transistor TX coupled to the capacitor of the Nth stage driving circuit. It can be understood that the working principle of the cascaded charge pump consisting of N driving circuits is the same as that of the cascaded charge pump with two driving circuits mentioned above, where N is greater than or equal to 2 and is a positive integer. When the cascaded charge pump composed of these N driving circuits performs... Figure 6 and Figure 7 When the method is used for driving, the output voltage of the N driving circuits is the sum of the potential difference of the capacitors in each driving circuit and the voltage of the external power supply terminal VGX. Furthermore, when the potential difference of the capacitors in each driving circuit is the same, the output voltage of the N driving circuits is (N+1 / 2) times the potential difference of the first capacitor C1.

[0102] It should be noted that, for ease of description, the driving circuits in the cascaded charge pumps of the above embodiments are driving circuits with the same topology and components. The method described in the embodiments of this application can also be applied to charge pumps composed of driving circuits with different topologies or components. For example, when the capacitors in each driving circuit are different, the potential difference of each capacitor during discharge will be different, which will cause the output voltage of the first output terminal (i.e., the output circuit of the cascaded charge pump) to be less than (-3U)V and / or (-5U)V as mentioned above. However, the voltage of the first output terminal is still the sum of the potential difference of the capacitors in each driving circuit and the voltage of the external power supply terminal VGX.

[0103] Based on the above technical solution, by cascading multiple drive circuits that can amplify the output voltage, the charge pump can output a higher multiple of the input voltage, thus meeting the requirements of high-voltage start-up MEMS devices. Furthermore, in the case of cascaded charge pumps, multiple control circuits in each drive stage can be connected to the same clock signal, thereby simplifying the operation process and improving circuit efficiency.

[0104] Furthermore, embodiments of this application also propose Figure 7 A schematic diagram of the simulation results of the method can be found in [reference]. Figure 10 , Figure 10 This is a schematic diagram of a simulation result proposed in an embodiment of this application, which illustrates... Figure 7 The simulation results illustrate the voltage changes of the first output circuit, the voltage at the right end of the first capacitor C1, and the voltage at the right end of the second capacitor C2, as well as the low-level signals output by the first clock signal, the second clock signal, and the external clock signal at different time periods. The specific simulation details are described below.

[0105] At the first moment, the voltage of the first output circuit is (-6.85)V.

[0106] At this moment (i.e., 10μs in the diagram), the voltage at the right end of the first capacitor C1 is (+7)V. The first clock signal begins to change from a high-level output signal to a low-level output signal. The low-level signal turns on the first transistor T1 and the second transistor T2, and the first capacitor C1 begins to charge. Then, at the second moment (i.e., 16μs in the diagram), the first clock signal begins to change from a low-level output signal to a high-level output signal, that is, the connection between the first output circuit and the low level is broken. Then, before the third moment (i.e., 20μs in the diagram), because the first output circuit of the cascaded charge pump is coupled to the left side of the first capacitor C1, the output voltage of the cascaded charge pump is (-6.85)V.

[0107] At the third moment, the voltage of the first output circuit changes from (-6.85)V to (-17.25)V.

[0108] At this point (20µs in the diagram), the second clock signal changes from a high-level output to a low-level output. This low-level signal turns on the third transistor T3 and the fourth transistor T4, completing the circuit between the right end of the first capacitor C1 and the third transistor T3. The first capacitor C1 discharges, and the voltage at its right end changes from +7V to -6.85V, causing the output voltage of the cascaded circuit to change from -6.85V to -17.25V. Simultaneously, the second capacitor C2 charges, and the voltage at its right end is +7V.

[0109] At the fifth moment, the voltage of the first output circuit changes from (-17.25)V to (-26.92)V.

[0110] At this time (i.e., 30us in the diagram), the external clock signal starts to change from a high-level signal output to a low-level signal output. The low-level signal turns on the external transistor TX, and the second capacitor C2 discharges. The voltage at the right end of the second capacitor C2 changes to (-6.85)V. Therefore, the voltage at the right end of the first capacitor C1 changes from (-6.85)V to (-17)V, thereby changing the voltage of the first output circuit of the cascaded charge pump from (-17.25)V to (-26.92)V.

[0111] Therefore, it can be concluded that the embodiments of this application Figure 7 The cascaded charge pump has the effect of multiplying the input voltage by the output voltage and then outputting it. However, it can also be seen that it cannot achieve the desired effect. Figure 7 and Figure 8 The effect of the aforementioned 3 or 5 times the input voltage (i.e., (-3U)V and (-5U)V mentioned above) can be attributed to the following scenario: During actual circuit transmission, from the end of the first capacitor's charging process to the turn-on of the transistor in the second-stage drive circuit (e.g., between the second and fifth moments), the first capacitor remains in a discharging state, resulting in some voltage loss. However, by appropriately allocating the sizes of the first and second capacitors, the output voltage of the cascaded charge pump can be made close to or equal to the input voltage. Figure 7 and Figure 8 (-5U)V in the method.

[0112] The above embodiments illustrate the working principle of the cascaded charge pump. To simplify the signal supply process and improve the working efficiency of the cascaded charge pump, this application also proposes a scheme to couple the cascaded charge pump with the integrated gate drive circuit (GOA).

[0113] See Figure 11 , Figure 11 This is a schematic diagram of a combined circuit of a cascaded GOA circuit and a cascaded charge pump proposed in an embodiment of this application. Figure 11The cascaded GOA circuit shown is a 4-stage GOA structure, while the cascaded charge pump circuit is a 3-stage structure, comprising 3 driving circuits. The power supplies of all 3 driving circuits are coupled to the first power supply terminal VGH and the second power supply terminal VGL, and the second terminal of the external transistor TX is coupled to the second power supply terminal VGL. It should be noted that the external transistor can also be coupled to the external power supply terminal VGX; this application does not limit the simple modifications to the circuit coupling in the embodiments.

[0114] Specifically, the cascaded GOA circuit includes four second drive circuits. The second output circuits of three of the second drive circuits are coupled to the control circuits of each stage of the three drive circuits, respectively. The remaining second output circuit (i.e., the second output circuit of the fourth-stage second drive circuit) is coupled to an external control circuit. These second drive circuits can also be referred to as GOA circuits; for ease of description, the term GOA circuit will be used in the following explanation.

[0115] For example, the second output circuit G1 of the first-stage GOA circuit is coupled to the first and second control circuits of the first-stage driver circuit, and is also coupled to the trigger circuit of the second-stage GOA circuit. The second output circuit G2 of the second-stage GOA circuit is coupled to the third and fourth control circuits of the second-stage driver circuit, and is also coupled to the trigger circuit of the third-stage GOA circuit. The second output circuit G3 of the third-stage GOA circuit is coupled to the fifth and sixth control circuits of the third-stage driver circuit, and is also coupled to the trigger circuit of the fourth-stage GOA circuit. The second output circuit G4 of the fourth-stage GOA circuit is coupled to an external control circuit, which is coupled to an external transistor TX. When each second output circuit outputs a low-level or high-level signal, the control circuit of each stage of the driver circuit can control the conduction of its corresponding transistor.

[0116] Figure 12 This is a waveform diagram of a combinational circuit proposed in an embodiment of this application, which can be regarded as... Figure 11 Waveform diagram of one driving method for the circuit shown.

[0117] As an example, in a 4-stage GOA circuit, each stage receives square wave voltages from the third clock signal CL1 and the fourth clock signal CL2, respectively. The square wave voltages of the third and fourth clock signals are equal in magnitude but opposite in direction. For instance, at the first moment, the third clock signal outputs a low-level voltage (also called a low-level signal), and the fourth clock signal outputs a high-level voltage (also called a high-level signal); at the second moment, the third clock signal outputs a high-level voltage, and the fourth clock signal outputs a low-level voltage, and so on. The driving method of the above circuit at multiple moments is described below.

[0118] At the first and second moments, the control trigger signal STV outputs a high-level signal.

[0119] At this time, the GOA circuits at each stage are not activated, and the second output circuit outputs a high-level voltage. Meanwhile, the control circuits of the drive circuits at each stage, coupled to the second output circuits, also output low-level signals to the transistors of each drive circuit. Therefore, the transistors of each drive circuit are in the off state, and the output voltage of the cascaded charge pump is (-U)V.

[0120] At the third moment, the control trigger signal STV outputs a low-level signal.

[0121] At this point, the first-stage GOA circuit starts up, using... Figure 2 The method shown is to output a low-level signal through its second output circuit at the next time step (the fourth time step).

[0122] At the fourth moment, the control trigger signal STV outputs a high-level signal, and the second output circuit G1 of the first-stage GOA circuit outputs a low-level signal.

[0123] At this time, the first and second control circuits of the first-stage drive circuit receive low-level signals, turning on the first transistor T1 and the second transistor T2, and charging the first capacitor. Simultaneously, the voltage of the trigger circuit of the second-stage GOA circuit changes from high to low, activating the second-stage GOA circuit. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the fifth time step).

[0124] At the fifth moment, the second output circuit G2 of the second-stage GOA circuit outputs a low-level signal.

[0125] At this time, the third and fourth control circuits of the second-stage drive circuit receive low-level signals, turning on the third transistor T3 and the fourth transistor T4, charging the second capacitor. Meanwhile, the output voltage of the cascaded charge pump is (-3µV). Simultaneously, the voltage of the trigger circuit of the third-stage GOA circuit changes from high to low, activating the third-stage GOA circuit. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the sixth time step).

[0126] At the sixth moment, the second output circuit G3 of the third-stage GOA circuit outputs a low-level signal.

[0127] At this time, the fifth and sixth control circuits of the third-stage drive circuit receive low-level signals, turning on the fifth transistor T5 and the sixth transistor T6, charging the third capacitor. Meanwhile, the output voltage of the cascaded charge pump is (-5µV). Simultaneously, the voltage of the trigger circuit of the fourth-stage GOA circuit changes from high to low, activating the fourth-stage GOA circuit. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the seventh time step).

[0128] At the seventh moment, the second output circuit G4 of the fourth-stage GOA circuit outputs a low-level signal.

[0129] At this moment, the external control circuit inputs a low-level signal, and the external transistor TX is turned on. The output voltage of the cascaded charge pump at this moment is (-7U)V.

[0130] From the eighth to the tenth moment, the second output circuits of the first-stage GOA circuit to the fourth-stage GOA circuit all output high-level signals.

[0131] At this time, the capacitors of the first drive circuits of each stage of the cascaded charge pump continue to discharge, and the output voltage of the cascaded charge pump is (-7U)V.

[0132] At the eleventh and twelfth moments, the combinational circuit executes the method described in the third and fourth moments above. At the twelfth moment, due to the low-level voltage output of the first-stage second drive circuit of the cascaded GOA circuit, the capacitor in the first-stage first drive circuit of the cascaded charge pump begins to charge, thereby causing the output voltage of the cascaded charge pump to become (-U)V.

[0133] At the thirteenth moment, the square wave voltages controlling the third and fourth clock signals both output high-level signals.

[0134] At this point, the third and fourth clock signals reset the combined circuit, preventing the second output circuit of each stage of the GOA circuit from outputting a low-level signal. For details, please refer to [link to relevant documentation]. Figure 2 The circuit and method shown prevent the cascaded charge pump from increasing its output voltage using the method described from the third to the seventh time point, so that its output voltage remains consistent with the previous time point.

[0135] It should be understood that the above-described combined circuit of cascaded GOA and cascaded charge pump is merely an example. This application does not limit the number of the first and second drive circuits in the combined circuit, that is, it does not limit the number of stages of the GOA circuit and the charge pump.

[0136] Specifically, the method described in this application embodiment is also applicable to the following combined circuits, including: a cascaded GOA circuit composed of (N+1) second driving circuits, and a cascaded charge pump circuit composed of N first driving circuits, wherein the cascaded GOA circuit is coupled to the cascaded charge pump circuit, and the coupling method is the same as described above. Figure 11 The combined circuit shown is the same. In other words, the k-th stage second drive circuit in the (N+1) second drive circuits is coupled to the total control circuit of the k-th stage first drive circuit in the N first drive circuits. The total control circuit includes the first control circuit and the second control circuit. The k-th stage second output circuit is also coupled to the trigger circuit of the (k+1)-th stage second drive circuit. k is greater than 0 and less than or equal to N, and k is a positive integer. In addition, the (N+1)-th stage second output circuit is coupled to the external transistor TX. The external transistor TX can be coupled to the second power supply terminal VGL or the external power supply terminal VGX.

[0137] and Figure 11 and Figure 12 The driving method of the circuit is the same. When the voltage of the trigger circuit of each stage of the second driving circuit changes sequentially (it can be from a high level voltage to a low level voltage), the output voltage of the N first driving circuits is the sum of the potential difference of the capacitors of each stage of the driving circuit and the voltage of the second power supply terminal VGL or the external power supply terminal VGX.

[0138] Based on the above technical solution, by coupling the cascaded charge pump with the cascaded GOA circuit, the output voltage of the cascaded charge pump can be multiplied by adjusting only the trigger signal STV. Compared with the case where a cascaded charge pump that operates alone needs to adjust multiple spatiotemporal signals at the same time, the operating efficiency of the cascaded charge pump can be significantly improved.

[0139] This application also proposes a reset control circuit for directly controlling the trigger circuit level of each stage of the GOA circuit. For example, see [link to relevant documentation]. Figure 13 , Figure 13 This is a schematic diagram of another combined circuit proposed in an embodiment of this application. When the reset control circuit is combined with... Figure 11 After the circuit shown is coupled, the combined circuit does not need to be reset by adjusting the voltage of the third and fourth clock signals. The reset control circuit can be used directly to control the trigger circuit of each stage of the GOA circuit to output a high level, thereby preventing the second output circuit of each stage of the GOA circuit from outputting a low level.

[0140] Specific coupling methods may include: at least one trigger circuit in the cascaded GOA circuit is coupled to the reset transistor TR, the reset transistor TR is coupled to the reset control circuit, and the reset control circuit is used to control the conduction of the reset transistor TR. For example, see... Figure 14 , Figure 14This is a waveform diagram of another combinational circuit proposed in the embodiments of this application, which can be regarded as... Figure 13 The waveform diagram of the combinational circuit shows that at the thirteenth moment, the reset control circuit RESET outputs a high-level voltage to the reset transistor TR, turning it off, thereby realizing the reset function of the combinational circuit of the cascaded GOA and the cascaded charge pump.

[0141] Based on the above technical solution, by adding a reset control circuit to the combined circuit of the cascaded charge pump and the cascaded GOA, the working efficiency of the combined circuit can be further improved, and the cumbersome voltage output process of the clock signal can be saved.

[0142] based on Figure 11 In addition to the combined circuit of the cascaded charge pump and the cascaded GOA, this application also proposes a method to effectively control the triggering (i.e., amplifying the output voltage) of the first driving circuits in each stage of the cascaded charge pump. This method can trigger a portion of the first driving circuits in the cascaded charge pump to output a multiplied voltage, while ensuring that the other portion of the first driving circuits is not triggered. In other words, the number of triggers (i.e., the amplification of the output voltage) and the number of stages of the first driving circuits in the cascaded charge pump can be effectively controlled, thereby controlling the amplification factor of the output voltage.

[0143] Specifically, see Figure 15 , Figure 15 This is a schematic diagram of a combined circuit of an odd-even cascaded GOA circuit and a cascaded charge pump proposed in an embodiment of this application, which will... Figure 11 The four second driving circuits serve as the odd-numbered driving circuits for the cascaded GOA of this combined circuit, and three even-numbered driving circuits are added. Specifically, the control circuits of the first driving circuits at each stage of the cascaded charge pump are coupled to the second output circuits of the odd-numbered driving circuits, and the second output circuits of the odd-numbered driving circuits are also coupled to the trigger circuits of the even-numbered driving circuits.

[0144] For example, the output circuit G1 (which can also be considered the second output circuit) of the first-stage GOA circuit (i.e., the second driving circuit) is coupled to the control circuit of the first-stage first driving circuit (i.e., the first-stage charge pump). The output circuit G1 of the first-stage GOA circuit is also coupled to the trigger circuit of the second-stage GOA circuit. The output circuit of the second-stage GOA circuit is coupled to the trigger circuit of the third-stage GOA circuit. The output circuit G2 of the third-stage GOA circuit is coupled to the control circuit of the first-stage second driving circuit (i.e., the second-stage charge pump). The output circuit G2 of the third-stage GOA circuit is also coupled to the trigger circuit of the fourth-stage GOA circuit, and so on. The trigger circuit of the seventh-stage GOA circuit is coupled to the output circuit of the sixth-stage GOA circuit, and the output circuit G4 of the seventh-stage GOA circuit is directly coupled to the external transistor TX.

[0145] The following is an introduction Figure 15The driving method for the combined circuit shown can be found in [reference needed]. Figure 16 , Figure 16 This is a waveform diagram of a combinational circuit proposed in an embodiment of this application, which can be regarded as... Figure 15 Waveform diagram of the combined circuit driving method.

[0146] The third and fourth clock signals output square wave cyclic voltages.

[0147] At the first moment, the third clock signal is controlled to output a low-level signal, and the fourth clock signal is controlled to output a high-level signal.

[0148] At the second moment, the third clock signal is controlled to output a high-level signal, and the fourth clock signal is controlled to output a low-level signal.

[0149] At both of the aforementioned moments, each stage of the cascaded GOA circuit in the combinational circuit outputs a high-level signal. For a detailed explanation of the GOA circuit's operating principle, please refer to [link / reference needed]. Figure 2 Therefore, the output signal of the cascaded charge pump of the combined circuit is (-U)V.

[0150] At the third moment, the third clock signal is controlled to output a low-level signal, the fourth clock signal is controlled to output a high-level signal, and the trigger signal STV changes from a high-level signal output to a low-level signal output.

[0151] At this point, the first-stage GOA circuit starts up, using... Figure 2 The method shown is to output a low-level signal through its second output circuit at the next time step (the fourth time step).

[0152] At the fourth moment, the trigger signal STV outputs a high-level signal, and the second output circuit G1 of the first-stage GOA circuit outputs a low-level signal.

[0153] At this time, the first and second control circuits of the first-stage first drive circuit receive low-level signals, turning on the first transistor T1 and the second transistor T2, and charging the first capacitor. Simultaneously, the signal of the trigger circuit of the second-stage GOA circuit changes from high to low, activating the second-stage GOA circuit. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the fifth time step).

[0154] At the fifth moment, the second output circuit of the second-stage GOA circuit outputs a low-level signal.

[0155] At this point, the trigger circuit of the third-stage GOA circuit changes from a high-level signal to a low-level signal, and the third-stage GOA circuit starts. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the sixth time step).

[0156] At the sixth moment, the second output circuit G2 of the third-stage GOA circuit outputs a low-level signal.

[0157] At this time, the third and fourth control circuits of the second-stage first drive circuit receive low-level signals, turning on the third transistor T3 and the fourth transistor T4, charging the second capacitor. Meanwhile, the output signal of the cascaded charge pump is (-3U)V. Simultaneously, the signal of the trigger circuit of the fourth-stage GOA circuit changes from high to low, activating the fourth-stage GOA circuit. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the seventh time step).

[0158] At the seventh moment, the second output circuit of the fourth-stage GOA circuit outputs a low-level signal.

[0159] At this point, the trigger circuit of the 5th stage GOA circuit changes from a high-level signal to a low-level signal, and the 5th stage GOA circuit starts. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the eighth time step).

[0160] At the eighth moment, the second output circuit G3 of the fifth-stage GOA circuit outputs a low-level signal.

[0161] At this time, the third and fourth control circuits of the third-stage first drive circuit receive low-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the third capacitor is charged. Meanwhile, the output signal of the cascaded charge pump is (-5µV). Simultaneously, the signal of the trigger circuit of the sixth-stage GOA circuit changes from high to low, and the sixth-stage GOA circuit starts. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the ninth time step).

[0162] At the ninth moment, the second output circuit of the sixth-stage GOA circuit outputs a low-level signal.

[0163] At this point, the trigger circuit of the 7th stage GOA circuit changes from a high-level signal to a low-level signal, and the 7th stage GOA circuit starts. Figure 2 The method shown outputs a low-level signal through its second output circuit at the next time step (the tenth time step).

[0164] At the tenth moment, the second output circuit G4 of the 7th stage GOA circuit outputs a low-level signal.

[0165] At this moment, the external control circuit inputs a low-level signal, and the external transistor TX is turned on. The output signal of the cascaded charge pump at this moment is (-7U)V.

[0166] The above example is Figure 15 The working principle of the cascaded charge pump outputting the maximum signal in the combined circuit shown is explained below. The method to make the output signal of the combined circuit less than the above maximum signal is also described below.

[0167] See also Figure 17 , Figure 17 This is a waveform diagram of another combinational circuit proposed in the embodiments of this application, which can be regarded as... Figure 15 Another waveform diagram of the combined circuit driving method.

[0168] and Figure 16 The waveforms are different, Figure 17 In the waveform, the 7th stage GOA circuit will not be activated, that is, the 7th stage GOA circuit will not output a low-level signal, thus preventing the output signal of the cascaded charge pump from being amplified.

[0169] Specifically, the situation from the first moment to the eighth moment can be referred to Figure 16 In the method described.

[0170] At the ninth moment, the second output circuit of the sixth-stage GOA circuit outputs a low-level signal.

[0171] At this time, a low-level signal is input to the trigger circuit of the 7th stage GOA circuit, and the 7th stage GOA circuit is started.

[0172] At the tenth moment, both the third and fourth clock signals output high-level signals (or signals), and the second output circuit G4 of the 7th stage GOA circuit outputs a high-level signal.

[0173] At this time, according to Figure 2 In the method described above, when the third clock signal and the fourth clock signal simultaneously output a high-level signal or a low-level signal, the output circuit of the GOA circuit will output a high-level signal instead of a low-level signal. Therefore, at the tenth moment, the second output circuit G4 of the 7th stage GOA circuit outputs a high-level signal, which prevents the external transistor TX from being turned on. At this moment, the output signal of the cascaded charge pump is still (-5U)V.

[0174] Based on the above technical solution, by changing the clock signal of the combined circuit of GOA circuit and cascaded charge pump, the input signal of MEMS device coupled to the combined circuit can be effectively controlled, thereby improving the availability and operating efficiency of the combined circuit.

[0175] It is important to note that Figure 15The circuit coupled to the first driving circuit of each stage of the cascaded charge pump is the odd-numbered stage second driving circuit of the cascaded GOA circuit. That is, the N second output circuits of the cascaded charge pump are the output circuits of the N odd-numbered stage second driving circuits of the cascaded GOA. The method described in the embodiments of this application can also be applied to the scenario where the even-numbered stage second driving circuit of the cascaded GOA circuit is coupled to the first driving circuit of each stage of the cascaded charge pump.

[0176] In one possible implementation, the output circuit of the i-th stage second drive circuit of the cascaded GOA circuit can be coupled to the control circuit of the ((i+1) / 2)-th stage first drive circuit of the cascaded charge pump, and the output circuit of the i-th stage second drive circuit is coupled to the trigger circuit of the (i+1)-th stage second drive circuit, where i is an odd number and i is greater than 0.

[0177] In another possible implementation, the output circuit of the i-th stage second drive circuit of the cascaded GOA circuit can be coupled to the control circuit of the (i / 2)-th stage first drive circuit of the cascaded charge pump, and the output circuit of the i-th stage second drive circuit is coupled to the trigger circuit of the (i+1)-th stage second drive circuit, where i is an even number and i is greater than 0.

[0178] In addition, this application also proposes a microelectromechanical system (MEMS) device, which includes the above-mentioned charge pump, cascaded charge pump, cascaded GOA circuit and combined circuit of cascaded charge pump.

[0179] This application also proposes a display device that includes the aforementioned driving circuit.

[0180] In some possible embodiments, the above-mentioned display device includes virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0181] In some possible embodiments, the above-described display device may also be referred to as a display substrate or a display panel.

[0182] This application also proposes a display that includes the above-described display device.

[0183] This application also proposes an electronic device that includes the aforementioned display.

[0184] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0185] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0186] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0187] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charge pump, characterized in that, include: First driving circuit; The first driving circuit includes a first control circuit, a second control circuit, a first input circuit, a second input circuit, and a first output terminal; The first input circuit includes a first transistor (T1), the control electrode of the first transistor (T1) is coupled to the first control circuit, the first electrode of the first transistor (T1) is coupled to the first power supply terminal (VGH), the second electrode of the first transistor (T1) is coupled to the first capacitor (C1), and the first capacitor (C1) is coupled to the first output terminal. The second input circuit includes a second transistor (T2), the control electrode of the second transistor (T2) is coupled to the second control circuit, the first electrode of the second transistor (T2) is coupled to the second power supply terminal (VGL), and the second electrode of the second transistor (T2) is coupled to the first capacitor (C1). The first control circuit is used to control the first transistor (T1) to be turned on or off, and the second control circuit is used to control the second transistor (T2) to be turned on or off.

2. The charge pump according to claim 1, characterized in that, The charge pump further includes N first driving circuits, an external transistor (TX), an external control circuit, and an external power supply terminal (VGX). The N first driving circuits are cascaded. The output circuit of the Nth stage first driving circuit is capacitively coupled to the (N-1)th stage first driving circuit. The first terminal of the external transistor (TX) is capacitively coupled to the Nth stage first driving circuit. The control terminal of the external transistor (TX) is coupled to the external control circuit. The external transistor (TX) is used to control the external control circuit to turn on or off.

3. The charge pump according to claim 1 or 2, characterized in that, The N first driving circuits are coupled to the integrated gate driving circuit GOA, and the GOA includes (N+1) second driving circuits, and the (N+1) second driving circuits are cascaded. The second output circuit of the k-th stage second driving circuit in the (N+1) second driving circuits is coupled to the overall control circuit of the k-th stage first driving circuit in the N first driving circuits. The overall control circuit includes a first control circuit and a second control circuit. The second output circuit is also coupled to the trigger circuit of the (k+1)-th stage second driving circuit. The voltage of the trigger circuit is used to adjust the output voltage of the (k+1)-th stage second driving circuit, where k is an integer greater than 0 and less than or equal to N. The (N+1)-th stage second output circuit is coupled to the external transistor (TX).

4. The charge pump according to claim 3, characterized in that, At least one of the trigger circuits in the integrated gate drive circuit GOA is coupled to a reset transistor (TR), which is coupled to a reset control circuit for controlling the conduction of the reset transistor (TR).

5. The charge pump according to claim 3 or 4, characterized in that, The N second output circuits are the output circuits of the N odd-numbered-level second driving circuits of the GOA, and the output circuit of the i-th level second driving circuit is coupled to the trigger circuit of the (i+1)-th level second driving circuit, and the output circuit of the i-th level second driving circuit is coupled to the total control circuit of the ((i+1) / 2)-th level first driving circuit, where i is an odd number and i is greater than 0.

6. A method for driving a circuit, characterized in that, A method for driving a charge pump as described in any one of claims 1 to 5, the driving circuit comprising: At time q, a low-level signal is input to the first control circuit and the second control circuit to charge the first capacitor; wherein the voltages at the first power supply terminal and the second power supply terminal are voltages in opposite directions, and q is an integer greater than or equal to 1; At time (q+1), a high-level signal is input to the second control circuit to discharge the first capacitor, and the voltage at the first output terminal is the sum of the potential difference of the first capacitor and the voltage at the first power supply terminal.

7. The method for driving the circuit according to claim 6, characterized in that, The first power supply terminal is coupled to a voltage controller, which is used to switch the voltage direction of the first power supply terminal to the opposite direction at the (q+1)th time.

8. The method for driving the circuit according to claim 6, characterized in that, In the N first driving circuits, each level of the first driving circuit is turned on sequentially in the order from the first level to the Nth level, and all transistors in each level of the first driving circuit are turned on in turn.

9. The method for driving the circuit according to claim 8, characterized in that, The capacitors in each stage of the driving circuit have the same potential difference.

10. A microelectromechanical system (MEMS) device, characterized in that, include: The charge pump as described in any one of claims 1 to 5.

11. A display device, characterized in that, Including the microelectromechanical system devices as described in claim 10.

12. An electronic device, characterized in that, Includes the display device as described in claim 11.

Images