A low current mismatched source switched charge pump
Patent Information
- Application Number
- CN202610916120.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-24
- Publication Date
- 2026-10-23
AI Technical Summary
但实际电路设计中，由于PMOS，NMOS管之间电流电压特性之间的不匹配，导致，使得电荷泵在UP/DN开关管同时开启时，仍然会有净电荷输出，从而导致环路滤波器上
的周期性电压抖动，从而恶化参考杂散(Reference Spur)，因此电流匹配性能对于电荷泵电路是一项十分重要的性能指标
[0042]本发明通过偏置电路中运算放大器AMP1的负反馈调节功能，使得电荷泵的充电电流能够持续跟踪放电电流，从而减小电荷泵的充放电电流失配，改善由于电荷泵充放电电流失配导致的PLL参考杂散以及输出相位噪声性能；本发明通过在核心电路中的UP/DN开关管旁分别添加一个栅宽尺寸为开关管1/2的dummy管来抑制UP/DN信号导致的电荷注入问题，以及通过在UP/DN电流源管的栅极添加电容C1，C2来抑制由于电流源管的寄生电容带来的电流源管栅极电压波动，使得电荷泵具有更好的开关特性。
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Figure CN122969370A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology, and specifically relates to a low-current mismatch charge pump. Background Technology
[0002] A charge pump circuit is essentially a switching current source that can be controlled by the UP / DN clock signal to charge and discharge the output node capacitor, thereby controlling the voltage across the capacitor at the output node. As a core module, it is widely used in phase-locked loops (PLLs) to form charge pump PLLs (CPPLLs).
[0003] Charge pump circuits generally require precise current and ideal switching characteristics. However, in actual circuit implementation, it is usually difficult to achieve these two requirements. The specific reasons are as follows:
[0004] (1) Charge and discharge current mismatch. Ideally, the charge and discharge current of the charge pump should be... Therefore, when both UP and NMOS switches are turned on simultaneously, the net input charge of the charge pump to the loop filter is 0, and the voltage across the loop filter remains constant. However, in actual circuit design, due to the mismatch between the current and voltage characteristics of the PMOS and NMOS transistors, ... This means that even when the UP / DN switches are both on, the charge pump will still have a net charge output, which will cause the loop filter to... Periodic voltage jitter can degrade reference spurs, making current matching performance a crucial performance indicator for charge pump circuits.
[0005] (2) Non-ideal switching characteristics. In an ideal state, the UP / DN switch behaves as an ideal switch. However, in actual design, due to non-ideal characteristics caused by parasitic components such as parasitic capacitance in the circuit, such as clock feedthrough, charge sharing, charge injection, etc., the charge pump cannot exhibit ideal switching characteristics. Summary of the Invention
[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention designs a source switch charge pump circuit with low current mismatch, including a core charge and a bias circuit; the bias circuit is connected to the core circuit; the bias circuit is used to provide the bias voltage required by the core circuit and control the charging and discharging current of the core circuit; the core circuit is used to charge and discharge the output node of the charge pump.
[0007] To solve the above technical problems, the present invention provides the following technical solution: a low-current mismatch charge pump, characterized in that it includes a bias circuit and a core circuit connected thereto. The core circuit is used to charge and discharge the loop filter connected to the output node of the charge pump. The bias circuit is used to provide the required bias voltage to the core circuit. The bias circuit includes an operational amplifier AMP1. The operational amplifier AMP1 adjusts the gate voltage of the current source tube in the core circuit through negative feedback to control the charging and discharging current of the core circuit, thereby completing the matching between the charging current and the discharging current of the charge pump.
[0008] Furthermore, the aforementioned core circuit includes:
[0009] PMOS transistor M7, PMOS transistor M8, PMOS transistor M13, NMOS transistor M9, PMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M14;
[0010] The source of PMOS transistor M7 and the drain of PMOS transistor M13 are connected to the power supply VDD.
[0011] The drain of NMOS transistor M9 and the source of NMOS transistor M14 are connected to ground GND.
[0012] The drain of PMOS transistor M7, the source of PMOS transistor M10, and the source and drain of PMOS transistor M8 are interconnected.
[0013] The gates of PMOS transistor M7 and NMOS transistor M9 are both connected to the UPN signal;
[0014] The gates of NMOS transistor M14 and PMOS transistor M13 are both connected to the DN signal;
[0015] The source of NMOS transistor M11, the drain of NMOS transistor M14, and the drain and source of NMOS transistor M12 are interconnected.
[0016] The gate of PMOS transistor M8 is connected to the UP signal;
[0017] The gate of NMOS transistor M12 is connected to the DNN signal;
[0018] The negative input terminal of the operational amplifier AMP1, the drain of the PMOS transistor M10, and the drain of the NMOS transistor M11 are interconnected.
[0019] Furthermore, the aforementioned PMOS transistor M7 and NMOS transistor M14 are switching transistors, which control the opening and closing of the charging and discharging current according to the UPN and DN signals, respectively.
[0020] PMOS transistor M10 and NMOS transistor M11 are current source transistors used to output charging and discharging current;
[0021] NMOS transistor M9 and PMOS transistor M13 are auxiliary switching transistors used to pull down the source potential of the corresponding current source transistor to ground or pull up to the power supply when the switching transistor is turned off, so as to achieve fast turn-off.
[0022] PMOS transistor M8 and NMOS transistor M12 are virtual transistors used to suppress the charge injection effect of UPN and DN signals.
[0023] Furthermore, the aforementioned bias circuit also includes:
[0024] The first current mirror unit is used to convert the input current I1 into a reference voltage to provide gate voltage bias for the current source transistor.
[0025] The second current mirror unit is used to assist the operational amplifier AMP1 in regulating the gate voltage of the PMOS transistor M10 to achieve charging and discharging current matching.
[0026] The first capacitor C1 and the second capacitor C2 are connected between the gate of the current source transistor in the core circuit and the power supply or ground, respectively, to suppress gate voltage fluctuations caused by parasitic capacitance.
[0027] Furthermore, the aforementioned first current mirror unit includes NMOS transistor M1 and NMOS transistor M2;
[0028] The second current mirror unit includes NMOS transistor M5 and NMOS transistor M6;
[0029] The source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, and the gate of NMOS transistor M2 is connected to the power supply and the source is grounded.
[0030] The drain and gate of NMOS transistor M1, the gate of NMOS transistor M5, and the gate of NMOS transistor M11 in the core circuit are interconnected and connected to the input current I1.
[0031] The source of PMOS transistor M3 is connected to the power supply, the gate is grounded, and the drain is connected to the source of PMOS transistor M4.
[0032] The gate of PMOS transistor M4 is also connected to the gate of PMOS transistor M10 in the core circuit, the output terminal of operational amplifier AMP1, and one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the power supply.
[0033] The drains of PMOS transistor M4 and NMOS transistor M5 are connected together to the positive input terminal of operational amplifier AMP1;
[0034] One end of the second capacitor C2 is connected to the gate of the NMOS transistor M5, and the other end is grounded;
[0035] The source of NMOS transistor M5 is connected to the drain of NMOS transistor M6, and the gate of NMOS transistor M6 is connected to the power supply and the source is grounded.
[0036] The gate of NMOS transistor M5 is also connected to the gate of NMOS transistor M11 in the core circuit.
[0037] Furthermore, the aforementioned NMOS transistors M1, M2, M5, and M6 form a 1:5 current mirror;
[0038] The gate width of PMOS transistor M8 is half that of PMOS transistor M7;
[0039] The gate width of NMOS transistor M12 is half that of NMOS transistor M14.
[0040] Furthermore, in the aforementioned source-switched charge pump, the operational amplifier AMP1 is a first-order rail-to-rail operational amplifier.
[0041] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:
[0042] This invention utilizes the negative feedback regulation function of operational amplifier AMP1 in the bias circuit to enable the charge pump's charging current to continuously track the discharge current, thereby reducing the charge pump's charge-discharge current mismatch and improving the PLL reference spurious and output phase noise performance caused by the charge pump's charge-discharge current mismatch. This invention also suppresses charge injection problems caused by the UP / DN signal by adding a dummy transistor with a gate width of half that of the switch transistor next to the UP / DN switch transistors in the core circuit, and suppresses parasitic capacitance of the current source transistors by adding capacitors C1 and C2 to the gate of the UP / DN current source transistors. The resulting gate voltage fluctuations in the current source transistor give the charge pump better switching characteristics. Attached Figure Description
[0043] Figure 1 This is a schematic diagram of the low-current mismatch source switch charge pump circuit designed in this invention;
[0044] Figure 2 This is a simulation diagram of the static current matching characteristics of the low current mismatch source switch charge pump in the design of this invention;
[0045] Figure 3 This is a simulation diagram of the dynamic switching characteristics of the low-current mismatch source switch charge pump in the design of this invention;
[0046] Figure 4 This is a simulation diagram of the dynamic switching characteristics of the low-current mismatch source switch charge pump in the design of this invention. Detailed Implementation
[0047] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.
[0048] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.
[0049] This invention provides a source-switched charge pump circuit with low current mismatch, such as... Figure 1 As shown, including
[0050] The circuit includes a core circuit and a bias circuit; the bias circuit is connected to the core circuit; the bias circuit is used to provide the bias voltage required by the core circuit and control the charging and discharging current of the core circuit; the core circuit is used to charge and discharge the output node of the charge pump.
[0051] For specific organizations, please see [link / details]. Figure 1 The source of PMOS transistor M7 and the drain of PMOS transistor M13 are connected to power supply VDD; the drain of NMOS transistor M9 and the source of NMOS transistor M14 are connected to ground GND; the drain of PMOS transistor M7, the source of PMOS transistor M10, and the source and drain of PMOS transistor M8 are interconnected; the gates of PMOS transistor M7 and NMOS transistor M9 are connected to the UPN signal; the gates of NMOS transistor M14 and PMOS transistor M13 are connected to the DN signal; the source of NMOS transistor M11, the drain of NMOS transistor M14, and the drain and source of NMOS transistor M12 are interconnected; the gate of PMOS transistor M8 is connected to the UP signal; the gate of NMOS transistor M12 is connected to the DNN signal; the negative terminal of operational amplifier AMP1, the drain of PMOS transistor M10, and the drain of NMOS transistor M11 are interconnected.
[0052] Design the specific structure of the bias circuit, such as Figure 1 As shown, the bias circuit also includes:
[0053] The first current mirror unit is used to generate a reference current; the reference current input current I1 is converted into a reference voltage by the current mirror transistor M1 and provided to NMOS transistors M5 and M11;
[0054] The second current mirror unit is used to provide bias for the core circuit. The actual function of the circuit composed of PMOS transistors M3, M4, M5, and M6 is to work with operational amplifier AMP1 to regulate the gate voltage of transistor M10, thereby achieving matching of charging and discharging currents. In the circuit, transistors M3, M4, M5, and M6 are connected in series, and the currents on them are equal. Since the operational amplifier has a virtual short, the voltages at its positive and negative input terminals are the same. At this time, the gate and source voltages of transistors M4 and M10 are also basically the same, thus... = .
[0055] The first capacitor C1 and the second capacitor C2 are connected between the gate of the current source transistor in the core circuit and the power supply or ground, respectively, to suppress gate voltage fluctuations caused by parasitic capacitance.
[0056] The source of NMOS transistor M1 is connected to the drain of NMOS transistor M2; the gate of NMOS transistor M2 is connected to the power supply VDD; the source of NMOS transistor M2 is connected to ground GND; the drain and gate of NMOS transistor M1, the gate of NMOS transistor M5, and the gate of NMOS transistor M11 are interconnected; the drain of NMOS transistor M1 is connected to the input current. The PMOS transistor M3 source and NMOS transistor M6 gate are connected to the power supply VDD; the PMOS transistor M3 gate and NMOS transistor M6 source are connected to ground GND; the PMOS transistor M3 drain is connected to the PMOS transistor M4 gate; the PMOS transistor M4 gate is connected to the core circuit PMOS transistor M10 gate, operational amplifier AMP1, and one end of capacitor C1; the other end of capacitor C1 is connected to the power supply VDD; the PMOS transistor M4 drain, NMOS transistor M5 drain, and the positive terminal of operational amplifier AMP1 are connected to the power supply VDD. Interconnected; one end of capacitor C2 is connected to the gate of NMOS transistor M5, and the other end is connected to ground GND; the source of NMOS transistor M5 is connected to the drain of NMOS transistor M6; the gate of NMOS transistor M5 is connected to the gate of NMOS transistor M11 in the core circuit; NMOS transistors M1, M2, M5, and M6 form a 1:5 current mirror; the gate width of PMOS transistor M8 is half the gate width of PMOS transistor M7; the gate width of NMOS transistor M12 is half the gate width of NMOS transistor M14.
[0057] In the implementation of the design, the core circuit is used to output the charging and discharging current of the charge pump. Specifically, PMOS transistor M10 and NMOS transistor M11 are current source transistors responsible for providing the charging and discharging current; PMOS transistor M8 and NMOS transistor M12 are dummy transistors, with gate widths half that of the UP switch M7 and DN switch M14, respectively. Due to the parasitic capacitances of the UP / DN switches… Because of the presence of parasitic capacitance, when the UPN / DN signal reverses, some charge will pass through the parasitic capacitance. Injected into the sources of PMOS transistor M10 and NMOS transistor M11, thus affecting the accuracy of the current source transistor's output current. By adding dummy transistors M8 / M12 with a gate width half that of the switching transistors, the opposite signal UP / DNN can be controlled through the parasitic capacitance of the dummy transistors. , Injecting charge reduces the parasitic capacitance of the switching transistor. This results in a charge injection effect; the PMOS transistor M9 and NMOS transistor M13 are auxiliary switching transistors. This is due to the parasitic capacitance of the current source transistor. , The presence of this issue means that when the UP / DN switch is turned off, the source potential of the current source transistor does not immediately drop to GND / push up to VDD, but instead slowly decreases / rises under the charging / discharging current, resulting in poor switching characteristics of the charge pump. By adding auxiliary switches M9 and M13, when the UP / DN switch is turned off, the auxiliary switches M9 and M13 will turn on, thereby quickly pulling the source potentials of the PMOS transistor M10 and NMOS transistor M11 down to GND / push up to VDD, respectively, achieving good switching characteristics.
[0058] In the implementation of the design, the bias circuit is used to provide the control voltage required for the gates of the core circuit PMOS transistors M10 and M11. The operational amplifier AMP1 is a first-order rail-to-rail operational amplifier. Through the "virtual short" function of the operational amplifier, the drain voltages of PMOS transistors M4 and M5 can continuously track the charge pump output node CP_OUT voltage. Operational amplifier AMP1 adjusts the gate voltage of PMOS transistor M10 through negative feedback, ensuring that the charge pump charging current matches the discharge current. These two functions of AMP1 enable the charge pump to maintain good charge and discharge current matching characteristics over a wide range of CP_OUT variations.
[0059] Capacitors C1 and C2 are connected to the gates of PMOS transistor M10 and NMOS transistor M11, respectively. Due to the parasitic capacitances present in PMOS transistor M10 and NMOS transistor M11... When the UP / DN switch is turned on, the source potential of the corresponding current source transistor is pulled up from GND to VDD / pulled down from VDD to GND. At this time, the source voltage changes. It will be through parasitic capacitance The parasitic capacitance affects the gate voltage of the current source transistor, leading to inaccurate charge pump charging and discharging current. Adding gate capacitors C1 and C2 can effectively reduce this parasitic capacitance. This results in the aforementioned non-ideal characteristics.
[0060] according to Figure 2The simulation diagram of the static current matching characteristics of the low-current mismatch source switch charge pump according to the embodiment of the present invention shows that within the operating range (0.2-1.2V), the charge pump has good charging and discharging current matching characteristics, with a maximum mismatch current of 4.56nA, which is within the set range. electric current . Figure 3 , Figure 4 This is a simulation diagram of the dynamic switching characteristics of the low-current mismatch source switching charge pump according to an embodiment of the present invention, where UP1 / DN1 are respectively Figure 1 The UP / DN switch signal in the system. Figure 3 and Figure 4 It can be seen that the charge pump has good switching characteristics.
[0061] The present invention designs a low-current mismatch source switching charge pump. The first-order rail-to-rail operational amplifier in the bias circuit regulates the gate voltage of the current source transistor through negative feedback adjustment, so that the charging current of the charge pump can continuously track the discharging current, achieving good current matching characteristics of the charge pump. In the core circuit, by adding a dummy transistor, an auxiliary switching transistor, and gate capacitors C1 and C2 in the bias circuit, the non-ideal characteristics caused by parasitic capacitance in the circuit are suppressed, achieving good switching characteristics of the charge pump.
[0062] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A low-current mismatch charge pump, characterized in that, It includes a bias circuit and a core circuit connected to it, the core circuit being used to charge and discharge the loop filter connected to the charge pump output node. The bias circuit is used to provide the required bias voltage to the core circuit. The bias circuit includes an operational amplifier AMP1. The operational amplifier AMP1 adjusts the gate voltage of the current source transistor in the core circuit through negative feedback, controls the charging and discharging current of the core circuit, and completes the matching between the charging current and the discharging current of the charge pump.
2. The low-current mismatch charge pump according to claim 1, characterized in that, The core circuit includes: PMOS transistor M7, PMOS transistor M8, PMOS transistor M13, NMOS transistor M9, PMOS transistor M10, NMOS transistor M11, NMOS transistor M12, NMOS transistor M14; The source of PMOS transistor M7 and the drain of PMOS transistor M13 are connected to the power supply VDD. The drain of NMOS transistor M9 and the source of NMOS transistor M14 are connected to ground GND. The drain of PMOS transistor M7, the source of PMOS transistor M10, and the source and drain of PMOS transistor M8 are interconnected. The gates of PMOS transistor M7 and NMOS transistor M9 are both connected to the UPN signal; The gates of NMOS transistor M14 and PMOS transistor M13 are both connected to the DN signal; The source of NMOS transistor M11, the drain of NMOS transistor M14, and the drain and source of NMOS transistor M12 are interconnected. The gate of PMOS transistor M8 is connected to the UP signal; The gate of NMOS transistor M12 is connected to the DNN signal; The negative input terminal of the operational amplifier AMP1, the drain of the PMOS transistor M10, and the drain of the NMOS transistor M11 are interconnected.
3. The low-current mismatch charge pump according to claim 2, characterized in that, PMOS transistor M7 and NMOS transistor M14 are switching transistors, which control the charging and discharging current to turn on and off according to the UPN and DN signals, respectively. PMOS transistor M10 and NMOS transistor M11 are current source transistors used to output charging and discharging current; NMOS transistor M9 and PMOS transistor M13 are auxiliary switching transistors used to pull down the source potential of the corresponding current source transistor to ground or pull up to the power supply when the switching transistor is turned off, so as to achieve fast turn-off. PMOS transistor M8 and NMOS transistor M12 are virtual transistors used to suppress the charge injection effect of UPN and DN signals.
4. The low-current mismatch charge pump according to claim 3, characterized in that, The bias circuit further includes: The first current mirror unit is used to convert the input current I1 into a reference voltage to provide gate voltage bias for the current source transistor. The second current mirror unit is used to assist the operational amplifier AMP1 in regulating the gate voltage of the PMOS transistor M10 to achieve charging and discharging current matching. The first capacitor C1 and the second capacitor C2 are connected between the gate of the current source transistor in the core circuit and the power supply or ground, respectively, to suppress gate voltage fluctuations caused by parasitic capacitance.
5. The low-current mismatch charge pump according to claim 4, characterized in that, The first current mirror unit includes NMOS transistor M1 and NMOS transistor M2; The second current mirror unit includes NMOS transistor M5 and NMOS transistor M6; The source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, and the gate of NMOS transistor M2 is connected to the power supply and the source is grounded. The drain and gate of NMOS transistor M1, the gate of NMOS transistor M5, and the gate of NMOS transistor M11 in the core circuit are interconnected and connected to the input current I1. The source of PMOS transistor M3 is connected to the power supply, the gate is grounded, and the drain is connected to the source of PMOS transistor M4. The gate of PMOS transistor M4 is also connected to the gate of PMOS transistor M10 in the core circuit, the output terminal of operational amplifier AMP1, and one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the power supply. The drains of PMOS transistor M4 and NMOS transistor M5 are connected together to the positive input terminal of operational amplifier AMP1; One end of the second capacitor C2 is connected to the gate of the NMOS transistor M5, and the other end is grounded; The source of NMOS transistor M5 is connected to the drain of NMOS transistor M6, and the gate of NMOS transistor M6 is connected to the power supply and the source is grounded. The gate of NMOS transistor M5 is also connected to the gate of NMOS transistor M11 in the core circuit.
6. The low current mismatch source switch charge pump according to claim 5, characterized in that: NMOS transistors M1, M2, M5, and M6 form a 1:5 current mirror; The gate width of PMOS transistor M8 is half that of PMOS transistor M7; The gate width of NMOS transistor M12 is half that of NMOS transistor M14.
7. The low current mismatch source switch charge pump according to any one of claims 1 to 6, characterized in that, The operational amplifier AMP1 is a first-order rail-to-rail operational amplifier.