A step-down DC-DC converter applied to a communication slice system

Abstract

The application discloses a buck type DC-DC converter applied to a communication system on chip, which comprises a load current detection circuit electrically connected with control signals Gate_P and Gate_N of a switching tube; the load current detection circuit is electrically connected with a dead time and logic circuit and a comparator circuit; the comparator circuit is a full MOS dynamic multiplexing comparator circuit, and comprises a three-stage amplifier and a pulse generation circuit; the three-stage amplifier comprises a first-stage amplifier for pre-amplification and providing a small gain and a large bandwidth, a second-stage amplifier for improving a voltage swing rate and a conversion speed, and a third-stage amplifier for shaping an output waveform; the comparator circuit comprises a large current high performance mode and a small current low power consumption mode; the load current detection circuit is used for detecting the size of the load current in each period, and changes the working mode of the comparator according to the size of the load current. According to the application, the performance of the buck type DC-DC converter is improved significantly, the output ripple is reduced, and the system efficiency is improved significantly.

Description

Technical Field

[0001] This invention relates to the technical field of buck DC-DC converters, and particularly to a buck DC-DC converter used in communication chip systems. Background Technology

[0002] Buck converters are important power management chips, offering advantages such as high efficiency, wide output voltage range, and good dynamic response. In communication system-on-a-chip applications powered by thin-film or coin cells, pulsed operation is often used to reduce average current. In system sleep mode, the load current is as low as μA. During operation, the load current reaches hundreds of mA. Using a buck converter under high current conditions can improve system efficiency, and in extremely light-load sleep mode, designing a low-power DC-DC converter is essential to prevent the static power consumption of the buck converter from degrading system efficiency.

[0003] A traditional buck DC-DC converter consists of a bandgap reference, a comparator, a zero-crossing detection circuit, an error amplifier, an on-time circuit, and a switching transistor, such as... Figure 1 As shown, a bandgap reference source generates a zero-temperature coefficient voltage, which, along with the output voltage, is connected to the input of an error amplifier. The output of the error amplifier is compared with the voltage sampled by resistor R1 and capacitor C1, and the resulting control signal controls the on and off states of the switching transistor. An adaptive on-time circuit controls the on-time of the upper transistor. A zero-crossing detection circuit ensures that in discontinuous conduction mode, the inductor current does not draw charge from the output, thus degrading system efficiency. The comparator is the module with the highest static power consumption in sleep mode. To reduce system power consumption, the comparator is often biased in a low-current mode. However, the low-current mode introduces subharmonic oscillations, so a high-efficiency and robust buck DC-DC converter is a key research focus.

[0004] In traditional buck DC-DC converters, the comparator's quiescent power consumption significantly degrades system efficiency under extremely light load conditions. To improve system efficiency, the traditional comparator circuit needs to be biased at a low current, but this results in an excessively slow comparator switching time, causing subharmonic oscillations in the circuit, reducing the system's operating frequency, and worsening the output ripple. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a buck DC-DC converter for use in communication on-chip systems, achieving higher efficiency over a wider load current range. Since the comparator is a major contributor to system efficiency degradation, it operates in either a high-current, high-performance mode or a low-current, low-power mode depending on the load current. In the low-current, low-power mode, the subharmonic oscillation problem of small bias current is solved by briefly operating the comparator in the high-current mode, with only a slight increase in power consumption. In the high-current, high-performance mode, the fast switching speed significantly improves the performance of the buck DC-DC converter and reduces output ripple. Furthermore, a load current detection circuit is designed to detect the load current magnitude per cycle and change the comparator's operating mode accordingly. To achieve the above-mentioned objectives and other advantages of the present invention, a buck DC-DC converter for use in communication on-chip systems is provided, comprising:

[0006] It includes a bandgap reference source, a zero-crossing detection circuit, a load current detection circuit, a comparator, an error amplifier, an on-time circuit, and a switching transistor, specifically including:

[0007] The control signals Gate_P and Gate_N of the switching transistors NMOS and PMOS are connected to the load current detection circuit.

[0008] The load current detection circuit outputs a DSM_EN electrical signal which is connected to a dead time, logic circuit, and comparator circuit.

[0009] The comparator circuit is a dynamic multiplexed comparator circuit with all MOS transistors. The comparator circuit includes a three-stage amplifier and a pulse generation circuit. The three-stage amplifier includes a first-stage amplifier for pre-amplification and providing small gain and large bandwidth, a second-stage amplifier for improving slew rate and switching speed, and a third-stage amplifier for shaping the output waveform.

[0010] The comparator circuit includes a high-current, high-performance mode and a low-current, low-power mode.

[0011] The load current detection circuit is used to detect the load current magnitude in each cycle and change the comparator's operating mode according to the load current magnitude.

[0012] Preferably, the load current detection circuit is used to detect the magnitude of the load current. When the load current is lower than a set threshold, it outputs a high signal. The high signal is connected to a comparator for a reusable pulse injection current, which controls the comparator to enter a low-current, low-power mode, significantly improving system efficiency.

[0013] Preferably, the comparator circuit can operate in both a high-current, high-performance mode and a low-current, low-power mode. In the low-current, low-power mode, the subharmonic oscillation problem of small bias current is solved by briefly operating the comparator in the high-current mode, with only a slight increase in power consumption. In the high-current, high-performance mode, the fast switching speed can significantly improve the performance of the buck DC-DC converter and reduce output ripple. A load current detection circuit is also designed to detect the load current magnitude each cycle and change the comparator's operating mode accordingly. When the output signal DSM_EN of the load current detection circuit is low, the comparator operates in the high-current, high-performance mode, with a 1μA bias current enabled. When the output signal DSM_EN of the load current detection circuit is high, the comparator operates in the low-current, low-power mode. Furthermore, when the comparator output signal CMP_OUT is low, the CMP_Contr signal is pulled low; when CMP_OUT is pulled high, CMP_Contr is simultaneously pulled high, and the comparator operates in the high-current mode to prevent subharmonic oscillation. This operating mode significantly reduces the comparator's switching time and has a lower average current. Attached Figure Description

[0014] Figure 1 This is a conventional structural diagram of a step-down DC-DC converter according to the present invention applied to a communication on-chip system;

[0015] Figure 2 The circuit diagram of the step-down DC-DC converter according to the present invention applied to a communication on-chip system;

[0016] Figure 3 This is a comparator circuit diagram of a buck DC-DC converter applied to a communication on-chip system according to the present invention;

[0017] Figure 4 This is a circuit diagram of a buck DC-DC converter applied to a communication chip system according to the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Reference Figure 2A step-down DC-DC converter for use in a communication on-chip system includes: a bandgap reference source, a load current detection circuit, a comparator, a zero-crossing detection circuit, an error amplifier, an on-time circuit, and a switching transistor. Specifically, the control signals Gate_P and Gate_N of the switching transistor are connected to the load current detection circuit. The load current detection circuit is connected to a dead-time and logic circuit and the comparator circuit. Power is first connected to the upper PMOS transistor of the switching transistor, which is then connected to the lower NMOS transistor and to an external inductor. The output of the inductor and the bandgap reference are connected to the input of the error amplifier. The output of the error amplifier and the voltage sampled by R1 and C1 are connected to the input of the comparator. The result of the comparator comparison is connected to the dead-time and logic circuits. The outputs of the dead-time and logic circuits control the switching transistor's on and off states via a driver circuit. The control signals Gate_P and Gate_N of the switching transistor are connected to the load current detection circuit. The output of the load current detection circuit is connected to the dead-time and logic circuits, and also to the comparator circuit to change the comparator's operating mode. The adaptive on-time circuit is controlled by dead time and logic circuit. When the comparator is pulled high, the adaptive on-time circuit starts to work. After one on-time, the end signal is connected to the logic circuit.

[0020] Furthermore, a bandgap reference source generates a zero-temperature coefficient voltage, which, along with the output voltage, is fed back to the input of the error amplifier. The output of the error amplifier is compared with the voltage sampled by resistor R1 and capacitor C1, and the resulting control signal controls the switching transistor's on and off states. An adaptive on-time circuit controls the on-time of the upper transistor. A zero-crossing detection circuit ensures that in discontinuous conduction mode, the inductor current does not draw charge from the output, thus improving system efficiency. A load current detection circuit detects the load current; when the load current falls below a set threshold, it outputs a high signal. This high signal connects to a comparator for multiplexed pulse injection current, controlling the comparator to enter a low-current, low-power mode, significantly improving system efficiency.

[0021] Furthermore, such as Figure 3As shown, the comparator circuit is a dynamically multiplexed comparator circuit using all MOS transistors. The comparator circuit includes a three-stage amplifier and a pulse generation circuit. The three-stage amplifier includes a first-stage amplifier for pre-amplification and providing low gain and high bandwidth, a second-stage amplifier for improving slew rate and switching speed, and a third-stage amplifier for shaping the output waveform. The input terminals of the comparator are connected to transistors M100 and M101. The bias current of M100 and M101 is provided by M108. The drain outputs of M100 and M101 are connected to M102, M103, M104, M105, M106, and M107 as cross-coupled transistor loads. The drain of M104 is connected to the gates of M114, M113, M112, and M109; the drain of M107 is connected to the gates of M109, M110, M111, and M112; and the drain of M114 is connected to M116 and M115. The drains of M115 and M111 are connected to the inverting input, and then through two stages of inverters to the output. The output signal CMP_OUT is connected to the input of a NAND gate via an inverter, and the other input of the NAND gate is connected to the output DSM_EN of the load current sensing circuit. Its output signal CMP_Contr is used to control the on or off of the 1μA bias current switch. The 1μA and 5nA current sources are connected to M20 and mirrored to M19. M19 is then connected to M18 and M17 to bias M21.

[0022] The comparator circuit includes a high-current, high-performance mode and a low-current, low-power mode.

[0023] The load current detection circuit is used to detect the load current magnitude in each cycle and change the comparator's operating mode according to the load current magnitude.

[0024] like Figure 4 As shown, the load current detection circuit includes a power supply voltage signal obtained by voltage division through a first resistor Ru and a second resistor Rd; the power supply voltage signal is connected to an operational amplifier; a first transistor M1 is connected to the operational amplifier; and a resistor RL is connected to the first transistor M1. The first transistor M1 is connected to a second transistor M2; the second transistor M2 is connected to a third transistor M3; and the drain of the third transistor M3 is connected to a fourth transistor M4 and a fifth transistor M5.

[0025] The control signal Gate_N for the NMOS transistor is connected to the seventh power supply M7 via an inverter. The control signal Gate_P for the PMOS transistor is connected to the eighth transistor M8. Gate_P is connected to the ninth transistor M9 and the tenth transistor M10 via an inverter. Gate_P is also connected to the gate of the sixth transistor M6 and the eleventh transistor M11 via two inverters. The drains of the sixth transistor M6 and the seventh transistor M7 are both connected to capacitor CH. The drains of the sixth transistor M6 and the seventh transistor M7 are connected to the sources of the ninth transistor M9 and the eighth transistor M8. The sources of the eighth transistor M8 and the drains of the ninth transistor M9 are connected to the tenth transistor M10 and the eleventh transistor M11, respectively. The drains of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are connected to capacitor CL and the negative terminal of the comparator input. The positive terminal of the comparator is connected to the output of the bandgap reference. The output of the comparator, DSM_EN, serves as the output signal of the load current sensing module.

[0026] Furthermore, to reduce module area and address subharmonic oscillation issues, this paper proposes a dynamic multiplexing comparator circuit using all MOS transistors. This circuit employs cross-coupled transistor pairs as loads, reducing area while maintaining overall gain regardless of changes in bias current. A pulse generation circuit is designed using resistors, capacitors, and logic gates. Figure 3 This is the circuit schematic of the dynamic multiplexing comparator proposed in this paper. The circuit consists of a three-stage amplifier and a pulse generation circuit. The all-MOS three-stage amplifier structure reduces the use of large resistors at low bias currents. The first-stage amplifier is used for pre-amplification, providing low gain and a large bandwidth; the second-stage amplifier is the main gain amplification stage, with a relatively large overall current, used to improve the slew rate and switching speed; the third-stage amplifier is used to shape the output waveform. The overall gain of the comparator is:

[0027]

[0028] Here, gm represents the transistor transconductance. This circuit uses a cross-coupled pair of transistors as the load for both the first and second stage amplifiers, offering the advantage of minimal gain variation under different bias currents. In both pulse width modulation (PWM) and pulse frequency modulation (PWM) modes, the comparator operates with a 1μA bias current enabled when the enable signal DSM_EN is low. When DSM_EN is high and CMP_OUT is low, the CMP_Contr signal is low, and the comparator operates in low-current mode. When CMP_OUT is pulled high, CMP_Contr is simultaneously pulled high, and the comparator operates in high-current mode to prevent subharmonic oscillations. This operating mode significantly reduces the comparator's toggle time and has a lower average current.

[0029] Furthermore, the main basis for switching between different modes is the magnitude of the load current. High current operates in pulse width modulation mode, while low current operates in pulse frequency modulation mode. Figure 4 This paper presents a load current detection circuit. The proposed circuit mainly consists of a sample-and-hold switch, a comparator, and an operational amplifier.

[0030] During the sample-and-hold switch phase, when the upper transistor is off and the lower transistor is on, the switch is off because both Gate_P and Gate_N are high. Transistor M7 is on, charging the voltage on capacitor CH to the supply voltage. When both NMOS and PMOS transistors are off, M7 and the sample-and-hold switch circuit are off, and the charge on capacitor CH discharges through M5 and M6. During the on-phase phase, transistor M7 remains off, and M6 is also off by the Gate_P signal. The sample-and-hold switch then opens, and VL samples the voltage on VH. To ensure the accuracy of the sampled voltage, CH >> CL is required. However, due to the non-ideal effects of clock feedthrough and charge injection, the VL voltage is affected to some extent. Therefore, devices M10 and M11 are added to reduce this impact.

[0031] Resistors Ru and Rd are implemented using inverting transistors and divide the supply voltage, significantly reducing the area required. However, to obtain accurate current, RL is implemented using high-density gate resistors with a resistance of 24MΩ. Due to the low response speed requirement of the operational amplifier, the quiescent current of the operational amplifier is only 30nA. The ratio of M4 to M5 is 1:10. The voltage at the positive terminal of the comparator is the reference voltage.

[0032] In summary, this application presents a buck DC-DC converter that maintains high efficiency even under extremely light load current. This is achieved by designing a reusable pulse-injected current comparator that can operate in both high-current, high-performance and low-current, low-power modes. In the low-current, low-power mode, the subharmonic oscillation problem with small bias current is solved by briefly operating the comparator in high-current mode, with only a slight increase in power consumption. In the high-current, high-performance mode, the fast switching speed significantly improves the performance of the buck DC-DC converter and reduces output ripple. Furthermore, a load current detection circuit is designed to detect the load current magnitude each cycle and adjust the comparator's operating mode accordingly.

[0033] The buck DC-DC converter proposed in this invention achieves a system efficiency of 83% at a load current of 100μA and 89% at 100mA. The comparator designed in this invention does not experience subharmonic oscillations in low-current, low-power mode, and has a static power consumption of only 100nA. The load current detection circuit can complete load current detection and switch the comparator's operating mode within two switching cycles.

[0034] The number of devices and processing scale described herein are for simplification of the invention. Applications, modifications, and variations of this invention will be readily apparent to those skilled in the art. Although embodiments of the invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. It can be applied to various fields suitable for this invention, and further modifications can be readily implemented by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, this invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A step-down DC-DC converter for use in communication on-chip systems, comprising a bandgap reference source, a zero-crossing detection circuit, a load current detection circuit, a comparator, an error amplifier, an on-time circuit, and a switching transistor, characterized in that, include: The control signals Gate_P and Gate_N of the switching transistor are connected to a load current detection circuit. The load current detection circuit is electrically connected to dead time, logic circuit, and comparator circuit. The comparator circuit is a dynamic multiplexed comparator circuit with all MOS transistors. The comparator circuit includes a three-stage amplifier and a pulse generation circuit. The three-stage amplifier includes a first-stage amplifier for pre-amplification and providing small gain and large bandwidth, a second-stage amplifier for improving slew rate and switching speed, and a third-stage amplifier for shaping the output waveform. The comparator circuit includes a high-current, high-performance mode and a low-current, low-power mode. The load current detection circuit is used to detect the load current magnitude in each cycle and change the comparator's operating mode according to the load current magnitude.

2. The step-down DC-DC converter for use in a communication chip system as described in claim 1, characterized in that, The load current detection circuit includes a power supply voltage signal divided by a first resistor Ru and a second resistor Rd, an operational amplifier connected to the power supply voltage signal, a first transistor M1 connected to the operational amplifier, and a resistor RL connected to the first transistor M1.

3. The step-down DC-DC converter for use in a communication chip system as described in claim 2, characterized in that, The first transistor M1 is electrically connected to the second transistor M2, the second transistor M2 is electrically connected to the third transistor M3, and the drain of the third transistor M3 is connected to the fourth transistor M4 and the fifth transistor M5. The control signal Gate_N of the NMOS switching transistor is connected to the seventh transistor M7 through an inverter. The control signal Gate_P of the PMOS switching transistor is connected to the eighth transistor M8, and is connected to the ninth transistor M9 and the tenth transistor M10 through an inverter. The gate of the sixth transistor M6 and the eleventh transistor M11 are connected through two inverters. The drain of the sixth transistor M6 and the drain of the seventh transistor M7 are both connected to the capacitor CH. The drain of the sixth transistor M6 and the drain of the seventh transistor M7 are connected to the source of the ninth transistor M9 and the eighth transistor M8. The drain of the eighth transistor M8 and the drain of the ninth transistor M9 are connected to the drain and source of the tenth transistor M10 and the eleventh transistor M11, respectively. The drain of the eighth transistor M8, the drain of the ninth transistor M9, the drain and source of the tenth transistor M10 and the eleventh transistor M11 are connected together to the capacitor CL and the comparator input.

4. The step-down DC-DC converter for use in a communication chip system as described in claim 1, characterized in that, The comparator circuit includes a high-current, high-performance mode and a low-current, low-power mode. When in pulse width modulation (PWM) and pulse frequency modulation (PWM) modes, the comparator operates in high-current, high-performance mode, with a 1μA bias current enabled. When the load current is extremely low, the load current detection mode control DSM_EN is high, and the comparator operates in low-current mode. When the comparator is in low-current, low-power mode, CMP_Contr is pulled high synchronously after CMP_OUT signal is pulled high. The comparator operates in high-current mode to prevent subharmonic oscillation.

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