Method and device for neutral point balancing and current direct component suppression in an inverter

Abstract

The application relates to the technical field of inverter control, and discloses a method and device for inverter midpoint balance and current DC component suppression, which comprises the following steps: based on the positive terminal voltage and the negative terminal voltage of a DC bus, a bus voltage deviation amount is calculated and obtained; based on the deviation between the bus voltage deviation amount and a midpoint balance reference value, a compensation amount is output after proportional integral adjustment; the compensation amount is superimposed to two-phase modulation waves to generate a driving control signal, so that the DC bus midpoint potential is corrected in a closed loop; and after the compensation amount is adjusted by pure integral adjustment according to the power flow direction of the inverter, the midpoint balance reference value is corrected in real time, so that the output current DC component is suppressed. Through two-stage loop cooperative control with bandwidth separation, the application realizes the cooperative control of 120 DEG two-phase inverter midpoint potential balance and output current DC component suppression, has a simple structure, fast dynamic response, high steady-state accuracy, and does not destroy the 120 DEG phase relationship of two phases.

Description

Technical Field

[0001] This invention relates to the field of inverter control technology, specifically to a method and apparatus for inverter midpoint balancing and DC current component suppression. Background Technology

[0002] Existing midpoint balancing control strategies for two-phase inverters are primarily designed for 180° anti-phase output architectures. Their technical approaches can be categorized into two types: one employs zero-sequence common-mode injection, utilizing the natural cancellation of midpoint currents between the two phases under 180° anti-phase conditions to superimpose a single compensation amount onto the two-phase modulation waves to achieve midpoint regulation; the other uses independent DC bias compensation, applying independent biases to the two-phase modulation waves to address asymmetrical loads. However, when the phase difference between the two phases is 120°, the midpoint currents cannot naturally cancel each other out, causing the aforementioned methods to fail and the midpoint potential to continuously drift. Simultaneously, the suppression of the DC component of the output current typically relies on direct closed-loop detection or simple superposition compensation, which is independent of the midpoint balancing control. Under 120° phase coupling, this can easily lead to mutual interference of control quantities, causing low-frequency oscillations or disrupting the preset phase relationship between the two phases.

[0003] In addition, traditional solutions all fix the midpoint balance reference value to zero, which cannot compensate for the static midpoint offset caused by inherent hardware deviations such as inconsistent power device parameters and zero drift of sampling circuits, thus limiting steady-state accuracy. Moreover, most solutions are only applicable to unidirectional inverter operation and lack adaptability to bidirectional power flow scenarios. When the load changes suddenly, the dynamic response is slow and it is easy to have compensation overshoot or convergence oscillation. Summary of the Invention

[0004] In view of this, the present invention provides a method and apparatus for inverter midpoint balancing and DC component suppression of current, so as to solve the problem that the midpoint potential drift and the DC component of the output current of a two-phase 120° inverter cannot be suppressed in a coordinated manner in the prior art.

[0005] In a first aspect, the present invention provides a method for inverter midpoint balancing and DC component suppression of current. The two-phase output terminals of the inverter and the midpoint of the DC bus respectively constitute two AC outputs, with a 120° phase difference between the two output voltages. The method utilizes two-stage control loops with different response speeds for coordinated regulation. One stage is a midpoint balancing control loop that adjusts the DC bus midpoint potential, and the other stage is a DC component suppression loop that suppresses the DC component of the output current. The response speed of the DC component suppression loop is slower than that of the midpoint balancing control loop. The method includes: calculating the bus voltage deviation based on the positive and negative terminal voltages of the DC bus; outputting a compensation amount after proportional-integral adjustment based on the deviation between the bus voltage deviation and the midpoint balancing reference value; superimposing the compensation amount onto the two-phase modulation wave to generate a drive control signal for closed-loop correction of the DC bus midpoint potential; and performing pure integral adjustment on the compensation amount according to the inverter power flow direction to real-time correct the midpoint balancing reference value to suppress the DC component of the output current.

[0006] The inverter midpoint balancing and DC component suppression method provided by this invention utilizes two-stage control loops with different response speeds for coordinated regulation. The midpoint balancing control loop outputs a compensation amount based on the deviation between the bus voltage deviation and the variable midpoint balancing reference value via proportional-integral regulation, which is then superimposed on the two-phase modulation wave to correct the DC bus midpoint potential in a closed loop. The DC component suppression loop performs pure integral regulation on the compensation amount according to the inverter power flow direction, correcting the midpoint balancing reference value in real time to bring the compensation amount close to zero, thereby suppressing the DC component of the output current. This method eliminates the need for additional hardware voltage equalization circuits, balances dynamic response performance with steady-state control accuracy, and significantly improves the inverter's operational reliability under conditions of load asymmetry, inconsistent device parameters, and bidirectional power flow.

[0007] In one optional implementation, the bus voltage deviation is the difference between the positive and negative voltages of the DC bus, used to characterize the potential drift direction and magnitude at the midpoint of the DC bus.

[0008] In one optional implementation, the process of outputting a compensation amount after proportional-integral adjustment based on the deviation between the bus voltage deviation and the midpoint balance reference value includes: calculating the difference between the midpoint balance reference value and the bus voltage deviation to obtain an error signal; performing proportional and integral operations on the error signal respectively, and summing the proportional operation result and the integral operation result to output the compensation amount.

[0009] In one optional implementation, the process of superimposing the compensation amount onto the two-phase modulation wave to generate the drive control signal includes: superimposing the compensation amount onto the two-phase original modulation wave respectively to change the duration of the zero-level clamping state of the two-phase bridge arm to obtain the two-phase corrected modulation wave; comparing the two-phase corrected modulation wave with the carrier wave respectively to generate drive control signals for each power device of the inverter to adjust the amount of charge flowing into or out of the midpoint of the DC bus.

[0010] In one optional implementation, the process of performing pure integral adjustment on the compensation amount according to the inverter power flow direction includes: correcting the polarity of the compensation amount according to the real-time power direction of the inverter; inputting the corrected compensation amount into the pure integral controller for integral calculation, and outputting the corrected midpoint balance reference value.

[0011] In one optional implementation, the polarity of the compensation amount is corrected according to the real-time power direction of the inverter, including: when the inverter outputs power to the grid, the compensation amount is inverted and input into the pure integral controller; when the inverter absorbs power from the grid, the compensation amount is input into the pure integral controller while maintaining its original polarity.

[0012] In one alternative implementation, the closed-loop bandwidth of the DC component suppression loop is less than the closed-loop bandwidth of the midpoint balance control loop.

[0013] Secondly, the present invention provides an inverter midpoint balancing and DC component suppression device, comprising: a data acquisition module for calculating the bus voltage deviation based on the positive and negative terminal voltages of the DC bus; a compensation module for outputting a compensation amount after proportional-integral adjustment based on the deviation between the bus voltage deviation and the midpoint balancing reference value; a drive module for generating a drive control signal by superimposing the compensation amount onto a two-phase modulation wave to correct the DC bus midpoint potential in a closed loop; and a correction module for real-time correction of the midpoint balancing reference value after performing pure integral adjustment on the compensation amount according to the inverter power flow direction to suppress the DC component of the output current.

[0014] Thirdly, the present invention provides an electronic device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0015] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the method described in the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1This is a flowchart illustrating the inverter midpoint balancing and DC current component suppression method according to an embodiment of the present invention. Figure 2 This is a control block diagram for balancing the DC bus midpoint and suppressing the DC component of the output current in a two-phase inverter with a 120° phase difference according to an embodiment of the present invention. Figure 3 This is a structural block diagram of an inverter midpoint balancing and DC current component suppression device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0020] For a T-type three-level inverter with a 120° phase difference between two phases and output terminals L1-N and L2-N each having an effective voltage of 120V, its DC bus consists of an upper bus capacitor and a lower bus capacitor connected in series. The connection point of the two capacitors forms the BUS midpoint (i.e., point N), which serves as the common terminal for the two-phase outputs. The two-phase output terminals and the BUS midpoint respectively constitute two AC outputs, with a 120° phase difference between the two-phase output voltages. Under ideal conditions, the voltage of the upper bus capacitor is equal to that of the lower bus capacitor, and the BUS midpoint potential is located at the midpoint of the DC bus voltage. However, in actual operation, due to factors such as asymmetrical two-phase loads, inconsistent power device parameters, switching dead-zone effect, and the DC component of the output current, the average current flowing through the BUS midpoint cannot be zero. This leads to an imbalance in the charging and discharging of the upper and lower bus capacitors, which in turn causes the midpoint potential to drift, resulting in uneven voltage distribution between the upper and lower capacitors. Midpoint potential drift not only causes two-phase output voltage distortion and excessive harmonic content, but also exacerbates the uneven stress of power switching transistors, shortens the service life of DC bus capacitors, and in severe cases, even triggers inverter failure and shutdown; at the same time, the DC component contained in the output current will further aggravate midpoint potential drift.

[0021] To address this, this embodiment provides a method for inverter midpoint balancing and DC component suppression of current. The two-phase output terminals of the inverter and the midpoint of the DC bus respectively constitute two AC outputs, with a 120° phase difference between the two output voltages. The method employs two-stage control loops with different response speeds for coordinated regulation. One stage is a midpoint balancing control loop that adjusts the DC bus midpoint potential; the other stage is a DC component suppression loop that suppresses the DC component of the output current, with the DC component suppression loop having a slower response speed than the midpoint balancing control loop. The midpoint balancing control loop dynamically suppresses the potential drift at the BUS midpoint, while the DC component suppression loop indirectly eliminates the DC bias component in the compensation amount by adjusting the midpoint balancing reference value, thereby suppressing the DC component in the inverter output current. The two loops are time-scale separated and uncoupled, avoiding coupled oscillations.

[0022] like Figure 1 As shown, the method includes: Step S1: Calculate the bus voltage deviation based on the positive and negative terminal voltages of the DC bus.

[0023] Among them, the bus voltage deviation is the difference between the positive and negative voltages of the DC bus, which is used to characterize the direction and magnitude of the potential drift at the midpoint of the DC bus.

[0024] Specifically, Figure 2 In the process, the positive terminal voltage BUSP and the negative terminal voltage BUSN of the DC bus are synchronously acquired in real time. BUSP and BUSN represent the real-time energy storage status of the upper and lower bus capacitors, respectively. Under ideal balanced operating conditions, the values ​​of BUSP and BUSN are equal, the midpoint potential has no offset, and the unbalance ΔU = 0. The acquired BUSP and BUSN are then sent to... Figure 2 The first summation node performs a difference calculation, and the resulting difference is the bus voltage deviation ΔU = BUSP - BUSN. This bus voltage deviation can intuitively characterize the direction and magnitude of the DC bus midpoint potential drift: a positive deviation indicates a higher upper bus capacitor voltage and a downward shift in the midpoint potential; a negative deviation indicates a higher lower bus capacitor voltage and an upward shift in the midpoint potential; the larger the absolute value of the deviation, the more severe the midpoint potential drift. This step only requires sampling from two bus voltages to quantify the midpoint imbalance, eliminating the need for an additional midpoint current sampling circuit, thus providing a basic feedback signal for subsequent closed-loop control.

[0025] Step S2: Based on the deviation between the bus voltage deviation and the midpoint balance reference value, output the compensation amount after proportional-integral adjustment.

[0026] The process of outputting a compensation amount based on the deviation between the bus voltage deviation and the midpoint balance reference value, after proportional-integral adjustment, includes: calculating the difference between the midpoint balance reference value and the bus voltage deviation to obtain an error signal; performing proportional and integral operations on the error signal respectively, and summing the proportional and integral operation results to output the compensation amount; wherein, the proportional operation is used to respond to the dynamic changes of the bus voltage deviation, and the integral operation is used to accumulate and reduce the steady-state error so that the bus voltage deviation approaches the midpoint balance reference value; the compensation amount includes an AC component and a DC component that respond to the periodic changes of the bus voltage deviation, and the DC component is the average value of the compensation amount over one or more output fundamental frequency cycles.

[0027] Specifically, Figure 2 In this process, the bus voltage deviation ΔU calculated in step S1 and the adaptively updated midpoint balance reference value BusErrRef are fed into the second summing node for subtraction to obtain the error signal error = BusErrRef - (BUSP - BUSN). Unlike the traditional fixed zero-reference control method, the midpoint balance reference value in this embodiment can be dynamically and adaptively adjusted to compensate for static offsets caused by inconsistent device parameters and zero-point drift during sampling. This error signal is simultaneously input into the proportional branch and the integral branch for parallel operation and then summed to output the compensation amount dV = Kp for modulation wave correction. error+Ki1∫errordt, where Kp is the proportional coefficient and Ki1 is the integral coefficient of the PI controller at this stage.

[0028] The proportional amplifier stage provides rapid output regulation to address instantaneous midpoint potential fluctuations, offering excellent dynamic response performance and quickly suppressing instantaneous midpoint voltage difference disturbances. The integral stage continuously accumulates steady-state residual errors, eliminating system steady-state deviations and ensuring that the bus voltage deviation converges to the midpoint equilibrium reference value under steady-state conditions. Considering the characteristics of the midpoint current composition, which contains both power frequency AC pulsation and DC bias components, the compensation output of the PI controller is an AC quantity with the same frequency as the inverter output current, superimposed with a small DC component. The amplitude of the compensation is proportional to the real-time bus voltage imbalance. The AC component is used to offset periodic midpoint charging and discharging pulsations, while the DC component corresponds to the system's static midpoint offset, providing a complete regulation signal for modulation wave correction.

[0029] Step S3: The compensation amount is superimposed on the two-phase modulation wave to generate a drive control signal, so as to correct the DC bus midpoint potential in a closed loop.

[0030] The process of superimposing the compensation amount onto the two-phase modulation wave to generate the drive control signal includes: superimposing the compensation amount onto the two-phase original modulation wave respectively to change the duration of the zero-level clamping state of the two-phase bridge arm and obtain the two-phase corrected modulation wave; comparing the two-phase corrected modulation wave with the carrier wave respectively to generate drive control signals for each power device of the inverter to adjust the amount of charge flowing into or out of the midpoint of the DC bus.

[0031] Specifically, Figure 2 In step S2, the same compensation amount dV is superimposed onto the two original modulation waves Mod, respectively. Figure 2 The third summing node completes the calculation to obtain the corrected modulation wave Mod_NP = Mod + dV. The compensation superposition operation can change the duration of the zero-level clamping of the two-phase bridge arms, thereby precisely adjusting the amount of charge flowing into and out of the DC bus midpoint and offsetting the asymmetrical charging and discharging trend of the upper and lower capacitors. After completing the modulation wave correction, the amplitudes of the two corrected modulation waves are compared with the carrier wave. Based on the instantaneous magnitude relationship between the modulation wave and the carrier wave, multiple drive control signals are generated. These drive signals directly control the turn-on and turn-off timing of each power device in the inverter, adjusting the midpoint charge balance in real time, constructing a negative feedback closed-loop control of the bus potential, and continuously suppressing midpoint potential drift. This scheme uses a unified compensation amount to synchronously correct the two-phase modulation waves, eliminating the need for separate phase adjustment units, resulting in a simple and unified control structure.

[0032] Step S4: After performing pure integral adjustment on the compensation amount according to the inverter power flow direction, the midpoint balance reference value is corrected in real time to suppress the DC component of the output current.

[0033] The process of performing pure integral adjustment of the compensation amount according to the inverter power flow direction includes: correcting the polarity of the compensation amount according to the real-time power direction of the inverter; inputting the corrected compensation amount into the pure integral controller for integral calculation, and outputting the corrected midpoint balance reference value.

[0034] Specifically, the polarity correction of the DC component based on the real-time power direction of the inverter includes: when the inverter outputs power to the grid, the compensation amount is inverted and input into the pure integral controller; when the inverter absorbs power from the grid, the compensation amount is input into the pure integral controller while maintaining its original polarity.

[0035] Specifically, Figure 2In this process, the tiny DC component contained in the compensation amount dV directly corresponds to the midpoint DC bias current iN_dc. This DC bias induces a DC component in the inverter's output current. This step constructs a low-speed pure integral adaptive loop to eliminate this problem at its source by dynamically correcting the midpoint balance reference value. The polarity of the compensation amount is corrected based on the real-time power flow of the inverter, and then the midpoint balance reference value is updated through integral calculation. The polarity correction logic is as follows: when the inverter outputs power to the grid (P>0), the compensation amount is inverted; when the inverter absorbs power from the grid (P<0), the original polarity of the DC component remains unchanged. This logic can be uniformly expressed as Err=-sgn(P). dV. The core mechanism of polarity correction is that the same compensated DC component has opposite effects on the adjustment of the midpoint potential under inverter and rectifier conditions. Polarity reversal can ensure that the loop always maintains negative feedback under bidirectional power conditions, avoiding control divergence and oscillation during operation switching.

[0036] Specifically, Figure 2 In this process, the polarity-corrected error Err is subtracted from the zero reference value to obtain the pure integral controller input 0-Err. This input is then fed into a pure integral controller containing only an integral element Ki / s. This controller has no proportional branch and is configured with only an independent integral coefficient Ki. The pure integral controller has steady-state zero-error tracking characteristics and only regulates the low-frequency DC component, significantly attenuating the power frequency AC component in the compensation quantity. At the same time, two-stage control loop bandwidth constraints are set. The bandwidth ωc2 of the second-stage pure integral DC suppression loop is much smaller than the bandwidth ωc1 of the first-stage PI midpoint balance loop. The time scales of the fast and slow loops are completely separated, uncoupled, and have no oscillation risk. The bandwidth of the second-stage loop is significantly smaller than that of the first-stage loop, reducing the dynamic mutual influence between the two loops and improving the independence of parameter tuning.

[0037] Specifically, Figure 2 In the process, the output of the pure integral controller updates the midpoint balance reference value BusErrRef in real time and feeds it back to the second summing node in step S2 to participate in error calculation. By slowly and adaptively adjusting the midpoint balance target value, the DC component in the compensation amount is gradually eliminated, and the dual control objectives of DC bus midpoint potential balance and inverter output current DC component suppression are achieved simultaneously.

[0038] Specifically, Figure 2In the process, the DC bus positive terminal voltage BUSP and the DC bus negative terminal voltage BUSN are input to the first summing node and subtracted to output the bus voltage imbalance BUSP-BUSN. The imbalance is subtracted from the feedback-obtained midpoint balance reference value BusErrRef and input to the second summing node to generate an error signal error. The error signal is input to the PI controller for calculation and outputs a compensation amount dV. The compensation amount is divided into two branches: the main regulation branch sends dV to the third summing node, which is superimposed with the two-phase original modulation wave Mod to generate a corrected modulation wave Mod_NP. The corrected modulation wave is input to the PWM modulator, and after comparison with the carrier wave, a drive signal is generated and output to the inverter. The DC suppression feedback branch sends the compensation amount dV to the power direction sign conversion unit, which performs polarity correction according to the positive or negative sign of the power P to obtain the error Err. The error Err is summed with the zero reference value to obtain 0-Err, which is input to the pure integral controller. The pure integral controller outputs a signal as the adaptively updated midpoint balance reference value BusErrRef, which is fed back to the second summing node to form a closed loop, fully demonstrating the signal flow and cooperative control logic of the two-level nested loop.

[0039] It should be noted that the response speed of the midpoint balancing control loop is greater than that of the DC component suppression loop. The ratio of the closed-loop bandwidth of the DC component suppression loop to that of the midpoint balancing control loop is between 1:5 and 1:10. This allows the DC component suppression loop to continuously integrate only the compensation amount, while strongly attenuating its power frequency AC component. Thus, DC component suppression is achieved without interfering with the dynamic response of the midpoint balancing control loop.

[0040] This embodiment achieves midpoint equalization through software modulation compensation, eliminating the need for additional voltage equalization hardware and modifying the main power topology, resulting in lower mass production costs. It adaptively generates a midpoint reference value via a pure integral loop, compensating for static offsets caused by devices and sampling, leading to higher steady-state equalization accuracy. The polarity of the compensation amount is corrected based on the power flow direction, ensuring stable operation without oscillations in both inverter and rectifier modes. The bandwidth of the fast and slow loops is separated and decoupled, balancing dynamic response and static accuracy. Both phases share a single compensation amount, resulting in a simple algorithm and minimal parameter tuning workload. The entire algorithm is implemented purely in software, reusing existing sampling signals and supporting online parameter tuning, making it easy to port. Simultaneously, it can equalize switching transistor voltage stress, delay bus capacitor aging, avoid midpoint imbalance overvoltage shutdown faults, reduce output harmonic distortion, and improve equipment operational reliability and grid-connected power quality.

[0041] This embodiment provides an inverter midpoint balancing and DC current component suppression device, such as... Figure 3 As shown, it includes: The acquisition module 301 is used to calculate the bus voltage deviation based on the positive and negative terminal voltages of the DC bus.

[0042] The compensation module 302 is used to output the compensation amount based on the deviation between the bus voltage deviation and the midpoint balance reference value after proportional-integral adjustment.

[0043] The drive module 303 is used to superimpose the compensation amount onto the two-phase modulated wave to generate a drive control signal, so as to correct the DC bus midpoint potential in a closed loop.

[0044] The correction module 304 is used to perform pure integral adjustment on the compensation amount according to the inverter power flow direction and then correct the midpoint balance reference value in real time to suppress the DC component of the output current.

[0045] The inverter midpoint balancing and DC component suppression device provided in this embodiment of the invention can execute the method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the various modules and units are the same as in the corresponding embodiments described above, and will not be repeated here.

[0046] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0047] The following is a detailed reference. Figure 4 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 002 or a program loaded from memory 008 into random access memory (RAM) 003. The RAM 003 also stores various programs and data required for the operation of the electronic device. The processor 001, ROM 002, and RAM 003 are interconnected via bus 004. An input / output (I / O) interface 005 is also connected to bus 004.

[0048] Typically, the following devices can be connected to I / O interface 005: input devices 006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 009. Communication device 009 allows electronic devices to exchange data via wireless or wired communication with other devices. Although Figure 4 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0049] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 009, or installed from memory 008, or installed from ROM 002. When the computer program is executed by processor 001, it performs the functions defined in the methods of the embodiments of the present invention.

[0050] Figure 4 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0051] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0052] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0053] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for inverter midpoint balancing and DC current component suppression, characterized in that, The inverter's two-phase output terminals and the DC bus midpoint respectively constitute two AC outputs, with a 120° phase difference between the two-phase output voltages. The method employs two-stage control loops with different response speeds for coordinated regulation. One stage is a midpoint balancing control loop that adjusts the DC bus midpoint potential, and the other stage is a DC component suppression loop that suppresses the DC component of the output current. The response speed of the DC component suppression loop is slower than that of the midpoint balancing control loop. The method includes: The bus voltage deviation is calculated based on the positive and negative terminal voltages of the DC bus. Based on the deviation between the bus voltage deviation and the midpoint balance reference value, the compensation amount is output after proportional-integral adjustment. The compensation amount is superimposed on the two-phase modulation wave to generate a drive control signal, so as to correct the DC bus midpoint potential in a closed loop. After performing pure integral adjustment on the compensation amount according to the inverter power flow direction, the midpoint balance reference value is corrected in real time to suppress the DC component of the output current.

2. The method according to claim 1, characterized in that, The bus voltage deviation is the difference between the positive and negative voltages of the DC bus, and is used to characterize the potential drift direction and magnitude at the midpoint of the DC bus.

3. The method according to claim 1, characterized in that, The process of outputting a compensation amount after proportional-integral adjustment based on the deviation between the bus voltage deviation and the midpoint balance reference value includes: The difference between the midpoint balance reference value and the bus voltage deviation is calculated to obtain the error signal; Perform proportional and integral operations on the error signal respectively, sum the proportional operation result and the integral operation result, and output the compensation amount.

4. The method according to claim 1, characterized in that, The process of superimposing the compensation amount onto the two-phase modulated wave to generate the drive control signal includes: The compensation amount is superimposed on the two original modulation waves to change the action time of the zero-level clamping state of the two bridge arms, thereby obtaining the two-phase corrected modulation waves. The two-phase modified modulation waves are compared with the carrier wave to generate drive control signals for each power device of the inverter, so as to regulate the amount of charge flowing into or out of the midpoint of the DC bus.

5. The method according to claim 1, characterized in that, The process of performing pure integral adjustment on the compensation amount according to the inverter power flow direction includes: The polarity of the compensation amount is corrected based on the real-time power direction of the inverter; The corrected compensation amount is input into the pure integral controller for integration calculation, and the corrected midpoint balance reference value is output.

6. The method according to claim 5, characterized in that, The polarity correction of the compensation amount based on the real-time power direction of the inverter includes: When the inverter outputs power to the grid, the compensation amount is inverted and then input to the pure integral controller. When the inverter absorbs power from the grid, the compensation amount is input to the pure integral controller while maintaining its original polarity.

7. The method according to claim 1, characterized in that, The closed-loop bandwidth of the DC component suppression loop is less than the closed-loop bandwidth of the midpoint balance control loop.

8. A device for inverter midpoint balancing and DC current component suppression, characterized in that, include: The acquisition module is used to calculate the bus voltage deviation based on the positive and negative terminal voltages of the DC bus. The compensation module is used to output the compensation amount based on the deviation between the bus voltage deviation and the midpoint balance reference value after proportional-integral adjustment. The drive module is used to superimpose the compensation amount onto the two-phase modulated wave to generate a drive control signal, so as to correct the DC bus midpoint potential in a closed loop. The correction module is used to perform pure integral adjustment on the compensation amount according to the inverter power flow direction, and then correct the midpoint balance reference value in real time to suppress the DC component of the output current.

9. An electronic device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the method of any one of claims 1 to 7.

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