Inductor-capacitor complementary voltage controlled oscillator with shared common mode filter

Abstract

The present disclosure relates to inductor-capacitor complementary voltage controlled oscillators with shared common mode filters. The present disclosure relates to an inductor-capacitor voltage controlled oscillator (VCO) with increased bandwidth and / or reduced common mode noise compared to other VCOs. The VCO can include a common mode filter disposed away from a decoupling network (e.g., not directly coupled to the decoupling network) to reduce an undesirable resonant frequency shift of the common mode filter. The separate common mode filter and decoupling network can reduce parasitic capacitance and / or parasitic inductance and / or variations in capacitance and inductance at different nodes of the VCO over an extended oscillation frequency bandwidth. As a result, the common mode filter can have a reduced undesirable resonant frequency shift over the extended oscillation frequency bandwidth, and thus, the VCO can have an extended oscillation frequency bandwidth.

Description

Background Technology

[0001] This disclosure relates in general to wireless communication, and more specifically to voltage-controlled oscillators for transmitter and / or receiver circuits.

[0002] In some applications, a voltage-controlled oscillator (VCO) may include a current source circuit, a resonator circuit, and a common-mode filter. The current source circuit generates a direct current (DC) signal based on a received bias voltage. The resonator circuit receives the DC signal from the current source circuit and generates the VCO output signal based on the DC signal. For example, the resonator circuit may generate an output signal with an oscillation frequency and voltage amplitude based on the inductance and capacitance values ​​of its components and the current value of the DC signal. In some cases, the common-mode filter suppresses at least a portion of one or more unwanted noise signals in the output signal. However, unwanted variations in current or voltage at different nodes of the VCO may undesirably reduce the common-mode filter's suppression of unwanted noise signals. Summary of the Invention

[0003] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects that may not be set forth below.

[0004] In one embodiment, an electronic device may include a voltage-controlled oscillator comprising: a first decoupling inductor, a first terminal of which is coupled to a power supply terminal; a first inductor-capacitor tank circuit coupled to a second terminal of the first decoupling inductor; a first current source circuit coupled to the first inductor-capacitor tank circuit; a differential capacitor, a first terminal of which is coupled to the first current source circuit; a differential inductor, a first terminal of which is coupled to the first current source circuit; a second current source circuit coupled to the second terminals of the differential capacitor and the differential inductor; a second inductor-capacitor tank circuit coupled to the second current source circuit; and a second decoupling inductor coupled to the second inductor-capacitor tank circuit and a ground terminal.

[0005] In another embodiment, the transceiver may include a voltage-controlled oscillator and a mixer. The voltage-controlled oscillator may include: a first current source circuit; a differential capacitor, a first terminal of which is coupled to the first current source circuit; a differential inductor, a first terminal of which is coupled to the first current source circuit; and a second current source circuit coupled to a second terminal of the differential capacitor and the second terminal of the differential inductor, wherein the voltage-controlled oscillator can generate an output signal. The mixer may be coupled to the voltage-controlled oscillator and can generate a combined signal based on the output signal.

[0006] In another embodiment, a voltage-controlled oscillator may include: a first current source circuit; a differential capacitor, the first terminal of which is directly coupled to the first current source circuit; a differential inductor, the first terminal of which is directly coupled to the first current source circuit; and a second current source circuit, the second current source circuit being directly coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor.

[0007] Various modifications to the features described above may be possible with respect to the various aspects of this disclosure. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, the various features discussed below with respect to one or more embodiments of the illustrated embodiments may be incorporated individually or in any combination into any of the foregoing aspects of this disclosure. The brief summary presented above is intended only to familiarize the reader with certain aspects and context of embodiments of this disclosure and does not limit the claimed subject matter. Attached Figure Description

[0008] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, in which the same reference numerals refer to the same parts.

[0009] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure; Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic devices; Figure 3 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of the transmitter of an electronic device; Figure 4 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of the receiver of an electronic device; Figure 5 It is based on the implementation scheme of this disclosure. Figure 3 transmitter and / or Figure 4A block diagram of the components of the voltage-controlled oscillator (VCO) of the receiver; Figure 6 It is based on the implementation scheme of this disclosure. Figure 5 A schematic diagram of a VCO, which includes differential capacitors and differential inductors, as well as a common-mode filter for the VCO; Figure 7 It is based on the implementation scheme of this disclosure. Figure 6 A schematic diagram of a VCO, which includes a single-ended capacitor and a common-mode filter; Figure 8 It is based on the implementation scheme of this disclosure. Figure 7 A schematic diagram of a VCO, which includes impedance components and a common-mode filter; and Figure 9 It is based on the implementation scheme of this disclosure. Figures 5 to 8 The layout of the VCO. Detailed Implementation

[0010] When describing elements of various embodiments of this disclosure, the articles “a,” “an,” and “the” are intended to refer to one or more elements present in the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and indicate that additional elements may be present in addition to those listed. Additionally, it should be understood that references to “an embodiment” or “an embodiment” of this disclosure are not intended to be construed as excluding the existence of additional embodiments that also incorporate the described features. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The use of the terms “approximately,” “close to,” “about,” “close to,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, and quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1%, 1%, 5%, 10%, 25%, etc. of the target). Furthermore, it should be understood that any exact values, figures, measurements, etc., provided herein are conceivable to include approximate values ​​of such exact values, figures, measurements, etc. (e.g., within limits of a suitable or conceivable error). Additionally, the term "set" can include one or more. That is, a set can include a single collection of one member, but a set can also include a collection of multiple members.

[0011] This disclosure relates to an inductor-capacitor complementary voltage-controlled oscillator, hereinafter referred to as a VCO, which has reduced common-mode noise compared to other VCOs, excluding the disclosed embodiment. Specifically, compared to other VCOs, the VCO can generate an output signal (e.g., a differential output signal) with an oscillation frequency and reduced common-mode noise. The VCO may include a common-mode filter and a decoupling network. The common-mode filter may include one or more capacitors and inductors having a resonant frequency corresponding to the frequency of the common-mode noise. Therefore, the common-mode filter can reduce (e.g., suppress) unwanted common-mode noise in the output signal.

[0012] An increase in the oscillation frequency of the output signal can correspond to a decrease in the values ​​of the capacitors and / or inductors of the common-mode filter. In some cases, an increase in the oscillation frequency of the output signal can reduce the capacitance and inductance values ​​of the common-mode filter compared to the capacitance and inductance values ​​of the decoupling network. If left unaddressed, the reduced capacitance and inductance values ​​of the common-mode filter may introduce unpredictable, increased, and / or varying undesirable parasitic capacitances and / or inductances at different nodes of the VCO. These undesirable parasitic capacitances and / or inductances may undesirably shift the resonant frequency of the common-mode filter and increase common-mode noise (e.g., reduce common-mode noise suppression).

[0013] In the embodiments disclosed herein, the VCO can reduce the undesirable resonant frequency shift of the common-mode filter by distancing the common-mode filter from the decoupling network setup. Specifically, the VCO may have a common-mode filter directly coupled to a first portion (e.g., a first unit) and a second portion (e.g., a second unit) of the VCO (e.g., coupled between the first and second portions). The decoupling network may be directly coupled to the first portion and a power supply terminal (e.g., coupled between the first portion and the power supply terminal), and directly coupled to the second portion of the VCO and a ground terminal (e.g., coupled between the second portion of the VCO and the ground terminal). Therefore, the dependence of the parasitic capacitance and / or parasitic inductance of the common-mode filter on the parasitic capacitance and / or parasitic inductance of the decoupling network can be reduced.

[0014] A VCO may include a common-mode filter separate from the decoupling network to reduce at least a portion of the adverse effects of differences in capacitance and inductance values ​​and / or widening of the gap between the common-mode filter and the decoupling network. For example, the parasitic capacitance and / or parasitic inductance of the common-mode filter and / or decoupling network may be reduced. In some cases, the parasitic capacitance and / or parasitic inductance at different nodes of the VCO, and / or variations in capacitance and inductance, may be reduced over an extended oscillation frequency bandwidth. Therefore, the common-mode filter may have a reduced resonant frequency offset over an extended oscillation frequency bandwidth, and thus, the VCO may have an extended oscillation frequency bandwidth.

[0015] Figure 1This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Among other things, the electronic device 10 may also include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuits), software elements (including machine-executable instructions), or a combination of both hardware and software elements (which may be referred to as logic units). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., through or via another component, communication bus, network) to send and / or receive signals between them. It should be noted that... Figure 1 This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0016] By way of example, electronic device 10 may include any suitable computing device, including desktop or laptop computers, portable or handheld electronic devices (such as wireless electronic devices or smartphones), tablet computers, wearable electronic devices, and other similar devices. In additional or alternative embodiments, electronic device 10 may include access points such as base stations, routers (e.g., wireless routers or Wi-Fi routers), hubs, switches, etc. It should be noted that Figure 1 The processor 12 and other related items may be embodied, in whole or in part, as software, hardware, or both. Furthermore, Figure 1 The processor 12 and other related items may be a single, contained processing module, or may be incorporated, wholly or partially, into any other element within the electronic device 10. The processor 12 may be implemented using any combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware component, dedicated hardware finite state machine, or any other suitable entity capable of performing computation or other manipulation of information. The processor 12 may include one or more application processors, one or more baseband processors, or both, and performs the various functions described herein.

[0017] exist Figure 1In the electronic device 10, processor 12 may be operatively coupled to memory 14 and non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may individually or collectively include memory 14 and / or non-volatile storage device 16 to store instructions or routines. Memory 14 and non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by processor 12 to enable electronic device 10 to provide various functions.

[0018] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0019] The input structure 22 of the electronic device 10 enables the user to interact with the electronic device 10 (e.g., pressing a button to increase or decrease the volume level). Like the network interface 26, the I / O interface 24 enables the electronic device 10 to interact with a variety of other electronic devices. In some embodiments, the I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as Lightning connectors, Universal Serial Bus (USB), or other similar connectors and protocols. Network interface 26 may include, for example, one or more interfaces for: a personal area network (PAN), such as an ultra-wideband (UWB) or Bluetooth network; a local area network (LAN) or wireless local area network (WLAN), such as a network employing one of the protocols in the IEEE 802.11x series (e.g., Wi-Fi); and / or a wide area network (WAN), such as any standard related to the 3rd Generation Partnership Project (3GPP), including, for example, 3rd generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), 4th generation (4G) cellular networks, Long Term Evolution (LTE) cellular networks, Long Term Evolution Licensed Assisted Access (LTE-LAA) cellular networks, 5th generation (5G) cellular networks and / or New Radio (NR) cellular networks, 6th generation (6G) or beyond 6G cellular networks, satellite networks, non-terrestrial networks, etc. Specifically, network interface 26 may include one or more interfaces for using cellular communication standards, such as those for defining and / or implementing frequency ranges for wireless communication, including millimeter wave (mmWave) frequency ranges (e.g., 24.25 GHz to 300 GHz). Network interface 26 of electronic device 10 may allow communication over the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0020] Network interface 26 may also include one or more interfaces for, for example, the following: broadband fixed wireless access networks (e.g., WiMAX), mobile broadband wireless networks (mobile WiMAX), asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video terrestrial broadcast (DVB-T) networks and their extended DVB handheld (DVB-H) networks, ultra-wideband (UWB) networks, AC power lines, etc.

[0021] As illustrated, network interface 26 may include a transceiver or modem 30. In some embodiments, all or part of the transceiver 30 may be located within processor 12. Transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas, and therefore may include both a transmitter and a receiver. The power supply 29 of electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0022] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic device 10. As illustrated, processor 12, memory 14, transceiver 30, transmitter or wireless transmission circuit 52, receiver 54 and / or antenna 55 (exemplified as 55A to 55N, collectively referred to as antenna 55) may be communicatively coupled to each other directly or indirectly (e.g., via or through another component, communication bus, network) to transmit and / or receive signals between each other.

[0023] Electronic device 10 may include a transmitter 52 and / or a receiver 54, both enabling the transmission and reception of signals between electronic device 10 and external devices via, for example, a network (e.g., including a base station or access point) or direct connection. As illustrated, transmitter 52 and receiver 54 may be combined into transceiver 30. Electronic device 10 may also have one or more antennas 55A to 55N electrically coupled to transceiver 30. Antennas 55A to 55N may be configured in omnidirectional or directional configurations, such as single-beam, dual-beam, or multi-beam arrangements. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in antennas 55A to 55N of an antenna group or module may be communicatively coupled to a corresponding transceiver 30 and each emits radio frequency signals that may combine constructively and / or destructively to form a beam. Electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas suitable for various communication standards. In some implementations, transmitter 52 and receiver 54 may transmit and receive information via other wired or line systems or devices.

[0024] As illustrated, various components of electronic device 10 can be coupled together via bus system 56. Bus system 56 may include, for example, a data bus, as well as power buses, control signal buses, and status signal buses in addition to the data bus. Components of electronic device 10 may be coupled together or use some other mechanism to accept or provide input to each other.

[0025] Figure 3 This is a schematic diagram of a transmitter 52 (e.g., a transmitting circuit, a wireless transmitting circuit) according to an embodiment of the present disclosure. As illustrated, the transmitter 52 can receive outgoing data 60 to be transmitted via one or more antennas 55 in the form of a digital signal. The digital-to-analog converter 62 of the transmitter 52 can convert the digital signal into an analog signal.

[0026] Modulator 63 combines the converted analog signal with a carrier signal to generate radio waves. Mixer 64 combines the carrier signal with a local oscillator signal 65 to generate a radio frequency signal (e.g., a combined signal). VCO 66-1 (e.g., a local oscillator) generates a local oscillator signal 65 having an oscillation frequency (e.g., a carrier frequency). In additional or alternative embodiments, VCO 66-1 generates a carrier signal having a carrier frequency (e.g., an oscillation frequency).

[0027] Power amplifier 67 receives a modulated signal from mixer 64. Power amplifier 67 amplifies the modulated signal to a suitable level to drive transmission of the signal via one or more antennas 55. Filter 68 of transmitter 52 (e.g., filter circuitry and / or software) can then remove unwanted noise from the amplified signal to generate a transmit signal 70 to be transmitted via one or more antennas 55. Filter 68 may include any suitable one or more filters for removing unwanted noise from the amplified signal, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters.

[0028] Although transmitter 52 is shown as including a single VCO 66-1, it should be understood that electronics 10 and / or transmitter 52 may include an additional VCO 66-1. In various embodiments, the additional VCO 66-1 may perform different operations of electronics 10 and / or transmitter 52, such as frequency synthesis applications and clock generation applications. Furthermore, power amplifier 67 and / or filter 68 may be referred to as part of the radio frequency front end (RFFE) (and more specifically, the transmitting front end of electronics 10). Additionally, transmitter 52 may include any suitable additional components not shown, or may exclude some of the illustrated components, such that transmitter 52 can transmit outgoing data 60 via one or more antennas 55. For example, transmitter 52 may include an additional mixer and / or VCO 66-1. As another example, if power amplifier 67 outputs an amplified signal within or substantially within the desired frequency range (so that filtering of the amplified signal is unnecessary), then transmitter 52 may not include filter 68.

[0029] Figure 4This is a schematic diagram of a receiver 54 (e.g., a receiving circuit) according to an embodiment of this disclosure. As illustrated, receiver 54 can receive a received signal 80 from one or more antennas 55 in the form of an analog signal. A low-noise amplifier 81 can amplify the received analog signal to a suitable level for processing by receiver 54. A mixer 82 can combine (e.g., mix) the amplified signal with a local oscillator signal 83 to generate an intermediate frequency (IF) signal or a baseband frequency signal (e.g., a combined signal). A VCO 66-2 (e.g., a second VCO, a local oscillator) can generate a local oscillator signal 83 with an oscillation frequency (such as an IF or baseband frequency) for down-converting the frequency of the incoming RF signal for processing.

[0030] Filter 85 (e.g., filter circuitry and / or software) removes unwanted noise, such as interchannel interference, from the received signal 80. Filter 85 also removes additional signals received by one or more antennas 55 at frequencies other than the desired signal. Filter 85 may include any one or more suitable filters for removing unwanted noise or signals from the received signal 80, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters. Low-noise amplifier 81 and / or filter 85 may be referred to as part of the RFFE, and more specifically, as the receiver front end of electronics 10.

[0031] Demodulator 86 may remove the radio frequency carrier signal from the filtered signal and / or extract the demodulated signal (e.g., envelope signal) for processing. In some embodiments, demodulator 86 may receive a signal indicating the frequency and phase of the received signal 80 and / or an intermediate frequency or baseband frequency generated from VCO 66-2 to remove the radio frequency carrier signal from the filtered signal and / or extract the demodulated signal (e.g., envelope signal) for processing. Analog-to-digital converter 88 may receive the demodulated analog signal and convert it into a digital signal of incoming data 90 for further processing by electronic device 10. Additionally, receiver 54 may include any suitable additional components not shown, or may exclude some of the illustrated components, such that receiver 54 can receive the received signal 80 via one or more antennas 55. For example, receiver 54 may include an additional mixer and / or VCO 66-2.

[0032] Figure 5This is a block diagram of the components of a VCO 66 for transmitter 52 and / or receiver 54 according to embodiments of the present disclosure, which generates an output signal 102. For example, VCOs 66-1 and 66-2 discussed above may be collectively referred to as VCO 66. As discussed above, transmitter 52 and / or receiver 54 may include VCO 66. Output signal 102 may include a differential output signal. In some embodiments, output signal 102 may correspond to local oscillator signals 65 and / or 83 discussed above. VCO 66 may include an inductor-capacitor (LC) tank circuit system 104 (e.g., a differential resonator circuit), a current source circuit 106 (e.g., a voltage-controlled current source circuit), a common-mode filter 108 (e.g., a common-mode resonator, a tail filter), and a decoupling network 110. LC tank circuit system 104 may include a first LC tank 112 and a second LC tank 114. The current source circuit 106 may include a first current source 116 (e.g., a first voltage-controlled current source) and a second current source 118 (e.g., a second voltage-controlled current source).

[0033] VCO 66 may include a first unit 120 and a second unit 122, each unit including a portion (e.g., half or nearly half) of an LC tank circuit 104 and a current source circuit 106. Specifically, the first unit 120 may include a first LC tank 112 and a first current source 116. Furthermore, the second unit 122 may include a second LC tank 114 and a second current source 118. A common-mode filter 108 may be disposed between the first unit 120 and the second unit 122 and / or coupled to the first unit and the second unit (e.g., coupled between the first unit and the second unit).

[0034] The first LC slot 112 may be coupled to power supply terminal 124 via (e.g., through) decoupling network 110. The first LC slot 112 may receive a bias voltage 126 (e.g., VDD, a DC signal) via power supply terminal 124. In some embodiments, the power supply 29 discussed above may be coupled to power supply terminal 124. In some cases, power supply 29 may generate and / or output the bias voltage 126. Alternatively or additionally, VCO 66 may receive the bias voltage 126 from any other feasible circuitry. Furthermore, the first LC slot 112 may receive any alternative to the bias voltage 126 or any other feasible input signal besides the bias voltage.

[0035] Decoupling network 110 may include one or more capacitors and inductors. Decoupling network 110 may reduce voltage fluctuations of bias voltage 126 and / or one or more noises and / or harmonics of VCO 66 relative to power supply terminal 124 and / or ground terminal 128. For example, decoupling network 110 may reduce one or more noises and / or harmonics of VCO 66 relative to other circuitry and / or components of electronic device 10 including VCO 66.

[0036] The first current source 116 may be differentially coupled to the first LC tank 112 via a first node 132 and a second node 134. In the depicted embodiment, the first node 132 may correspond to the positive output terminal 136 of the VCO 66, and the second node 134 may correspond to the negative output terminal 138 of the VCO 66. The first current source 116 may be coupled to the second current source 118 via a common-mode filter 108. Therefore, the first unit 120 may be coupled to the second unit 122 via (e.g., through) the common-mode filter 108. Furthermore, the second current source 118 may be differentially coupled to the second LC tank 114 via (e.g., through) a decoupling network 110 via a third node 142 and a fourth node 144. In some embodiments, the third node 142 and the fourth node 144 may correspond to or have the second positive output terminal and the second negative output terminal of the VCO 66 (e.g., in place of the positive output terminal 136 and the negative output terminal 138, or other than the positive output terminal and the negative output terminal). The second LC slot 114 can be coupled to the ground terminal 128 via the decoupling network 110. For example, the ground terminal 128 may have a ground voltage, such as a virtual ground voltage, 0 volts, or near 0 volts. In some embodiments, the power supply 29 discussed above may be coupled to the ground terminal 128.

[0037] The first current source 116 may receive a bias voltage 126 from the first LC tank 112. A common-mode filter 108 may provide low impedance (e.g., near-short-circuit connection, near-short-circuit impedance or resistance, near-zero or zero impedance or resistance, etc.) to the bias voltage 126. Therefore, the second current source 118 may receive the bias voltage 126 from the first cell 120 via the common-mode filter 108. Furthermore, the first current source 116 and the second current source 118 may generate and / or provide a DC signal based on the received bias voltage 126. For example, the first current source 116 and the second current source 118 may each include a voltage-controlled current source to generate and / or output a DC signal (e.g., a desired current). The DC signal may have an oscillation frequency of zero, near-zero, approximately zero, relatively zero, and / or below a threshold frequency.

[0038] The LC channel system 104, including the first LC channel 112 and the second LC channel 114, can generate an output signal 102 based on a received DC signal and / or a bias voltage 126. For example, the first LC channel 112 and the second LC channel 114 can have an oscillation frequency (e.g., a desired oscillation frequency) within a resonant frequency range. Therefore, the LC channel system 104 can generate an output signal 102 having an oscillation frequency within a resonant frequency range. In some embodiments, the LC channel system 104 can generate an output signal 102 with an oscillation frequency corresponding to a carrier signal having a carrier frequency used to transmit the outgoing data 60 discussed above. In alternative or additional embodiments, the LC channel system 104 can generate an output signal 102 with an oscillation frequency corresponding to an intermediate or baseband oscillation signal used for down-conversion and processing of the received signal 80 discussed above.

[0039] In some cases, VCO 66 may have undesirable common-mode noise 139 on the first unit 120 and undesirable common-mode noise 140 on the second unit 122. Without compensation, the common-mode noise 139 and 140 may cause undesirable voltage and / or frequency shifts around the output signal 102, resulting in undesirable flicker and / or phase noise in the output signal 102. For example, the common-mode noise 139 and 140 may include undesirable flicker noise and / or phase noise, and / or may correspond to one or more undesirable harmonics of the output signal, among other possibilities.

[0040] As described above, the common-mode filter 108 can provide low impedance (e.g., a relatively short-circuit connection) to the bias voltage 126. Furthermore, the common-mode filter 108 can have a resonant frequency range associated with undesirable common-mode noise 139 and 140. Therefore, the common-mode filter 108 can reduce (e.g., suppress) undesirable common-mode noise 139 and 140 of the output signal 102 while providing relatively short circuit paths to the bias voltage 126, the DC signal, and the output signal 102. For example, the resonant frequency range can correspond to the frequency range associated with one or more harmonics (e.g., integer multiples) of the output signal 102 and / or the resonant frequency range of the LC tank circuit system 104.

[0041] Common-mode filter 108 may include one or more capacitors and inductors. Furthermore, as described above, decoupling network 110 may include one or more capacitors and inductors. An increase in the oscillation frequency of the output signal 102 may disproportionately decrease the values ​​of one or more capacitors and inductors in common-mode filter 108 compared to the values ​​of one or more capacitors and inductors in decoupling network 110. If disregarded, the reduced values ​​of capacitors and inductors in common-mode filter 108 compared to the values ​​of capacitors and inductors in decoupling network 110 may increase parasitic capacitance and / or parasitic inductance between common-mode filter 108 and decoupling network 110, thereby undesirably shifting the resonant frequency range of common-mode filter 108. In some cases, this undesirable shift in the resonant frequency range of common-mode filter 108 may increase common-mode noise 139 and 140.

[0042] In the depicted embodiment, the common-mode filter 108 is positioned away from the decoupling network 110 (e.g., not directly coupled to the decoupling network), and instead, is directly coupled to the first unit 120 and the second unit 122 (e.g., coupled between the first unit and the second unit). Therefore, the dependence of the parasitic capacitance and / or parasitic inductance of the common-mode filter 108 on the decoupling network 110 is reduced. Furthermore, the dependence of the parasitic capacitance and / or parasitic inductance of the decoupling network 110 on the common-mode filter 108 is reduced. Therefore, one or more values ​​of the parasitic capacitance and / or parasitic inductance between the common-mode filter 108, the decoupling network 110, and / or the common-mode filter 108 and the decoupling network 110 can be reduced. Moreover, for example, compared to other VCOs with a common-mode filter 108 directly coupled to the decoupling network 110, the resonant frequency of the common-mode filter 108 may not be undesirably shifted or may have a reduced undesirable shift. Therefore, VCO 66 can have increased and / or extended oscillation frequency bandwidth based on reduced common-mode noise 139 and 140.

[0043] Figure 6 This is a schematic diagram of a VCO 66 according to an embodiment of the present disclosure, the VCO including differential capacitors and differential inductors, and a common-mode filter 108. In the depicted embodiment, a first LC tank 112 may include a first inductor 150, a first capacitor bank 152, and a first variable capacitor 154 (e.g., a varactor diode). Furthermore, a second LC tank 114 may include a second inductor 158, a second capacitor bank 160, and a second variable capacitor 162 (e.g., a varactor diode). Additionally or alternatively, the first LC tank 112 and / or the second LC tank 114 may include switched capacitor circuitry, among other possibilities. The first capacitor bank 152 and the second capacitor bank 160 may each include multiple capacitors.

[0044] The first inductor 150 may be coupled to the power supply terminal 124 via a first decoupling inductor 156 (e.g., a first degraded inductor) of the decoupling network 110. The first decoupling inductor 156 may reduce noise at the voltage terminal 124 at VCO 66 and / or reduce noise at the voltage terminal 124 at VCO 66. The first decoupling inductor 156 may be tapped onto the first inductor 150 (e.g., coupled to the winding of the first inductor). For example, the first decoupling inductor 156 may be tapped onto the center tap of the first inductor 150, which divides the first inductor 150 into two split (e.g., half-split) inductors. Alternatively or additionally, the first decoupling inductor 156 may be tapped onto any other part or location of the first inductor 150, and other possibilities.

[0045] The second inductor 158 may be coupled to ground terminal 128 via a second decoupling inductor 164 (e.g., a second degraded inductor) of decoupling network 110. The second decoupling inductor 164 may reduce noise at ground terminal 128 at VCO 66, and / or reduce noise at VCO 66 at ground terminal 128. The second decoupling inductor 164 may be tapped onto the winding of the second inductor 158. For example, the second decoupling inductor 164 may be tapped onto the center tap of the second inductor 158, among other possibilities. In some embodiments, decoupling network 110 may include a decoupling capacitor 182 coupled to the first decoupling inductor 156 and the second decoupling inductor 164. For example, the decoupling capacitor 182 may be tapped onto the winding of the first decoupling inductor 156 (e.g., to the center tap of the winding of the first decoupling inductor) and tapped onto the winding of the second decoupling inductor 164.

[0046] The first inductor 150 and the second inductor 158 can be inductively coupled to a signal having an oscillation frequency within the resonant frequency range of the LC tank circuit system 104 with a coupling factor (K) equal to or greater than a first threshold. The first threshold can be 0.3 or less, 0.4 or more, 0.44 or more, 0.5 or more, 0.72 or more, 0.76 or more, 0.9 or more, or 1, among other possibilities. In different embodiments, the first inductor 150 and the second inductor 158 can have different dimensions corresponding to the resonant frequency range of the LC tank circuit system 104. For example, the first inductor 150 can be inductively coupled to the second inductor 158 to form a transformer to generate or provide an output signal 102 having an oscillation frequency within the resonant frequency range of the LC tank circuit system 104.

[0047] Furthermore, the first inductor 150 and the second inductor 158 can perform inductive decoupling for signals having oscillation frequencies outside the resonant frequency range of the LC tank circuit system 104 based on a coupling factor equal to or less than a second threshold. The second threshold can be 1 or less, 0.9 or less, 0.85 or less, 0.72 or less, 0.64 or less, 0.5 or less, 0.4 or less, 0.2 or less, 0.1 or less, or 0.05 or less, and other possibilities. Therefore, the first inductor 150 and the second inductor 158 can perform inductive decoupling for common-mode noise 139 and 140 having undesired oscillation frequencies outside the resonant frequency range of the LC tank circuit system 104. Thus, the first inductor 150 and the second inductor 158 can at least partially decouple and / or isolate the first unit 120 from the second unit 122 for common-mode noise 139 and 140.

[0048] In some cases, the capacitance and inductance values ​​of the first LC tank 112 and the second LC tank 114 may be equal, nearly equal, or substantially equal. It should be understood that in different embodiments, the first LC tank 112 and the second LC tank 114 may include different circuit components. For example, the first LC tank 112 and the second LC tank 114 may include different numbers of capacitors and / or inductors for generating the output signal 102. The capacitance and inductance values ​​of the first LC tank 112 and the second LC tank 114 may correspond to the oscillation frequency of the output signal 102. In some cases, the oscillation frequency may be higher than a threshold (e.g., higher than 0.1 GHz, higher than 1 GHz, higher than 10 GHz, higher than 19 GHz, etc.) and / or within the resonant frequency range of the LC tank circuit system 104 (e.g., 24.25 GHz to 300 GHz or millimeter wave frequencies, and other possibilities).

[0049] In the depicted embodiments, the first current source 116 may include a first N-channel switch 166 (e.g., a first n-channel metal-oxide-semiconductor (NMOS) switch) and a second N-channel switch 168 (e.g., a second NMOS switch) forming a first voltage-controlled current source. Furthermore, the second current source 118 may include a first P-channel switch 172 (e.g., a first p-channel metal-oxide-semiconductor (PMOS) switch) and a second P-channel switch 174 (e.g., a second PMOS switch) forming a second voltage-controlled current source. It should be understood that in alternative or additional embodiments, the first current source 116 and / or the second current source 118 may each include different switches (such as any feasible transistors) and / or different numbers of switches to provide a voltage-controlled current source.

[0050] The gate terminal of the second N-channel switch 168 may be coupled (e.g., cross-coupled) to the drain terminal of the first N-channel switch 166 via a first node 132. The gate terminal of the first N-channel switch 166 may be coupled (e.g., cross-coupled) to the drain terminal of the second N-channel switch 168 via a second node 134. As described above, in some embodiments, the first node 132 may correspond to the positive output terminal 136 of the VCO 66, and the second node 134 may correspond to the negative output terminal 138 of the VCO 66. The first inductor 150, the first capacitor bank 152, and the first variable capacitor 154 may be coupled to the drain terminal of the first N-channel switch 166 via the first node 132, and may be coupled to the drain terminal of the second N-channel switch 168 via the second node 134.

[0051] The drain terminals of the first N-channel switch 166 and the second N-channel switch 168 can be coupled to the voltage terminal 124 via the first LC slot 112 and the decoupling network 110. Specifically, the drain terminals of the first N-channel switch 166 and the second N-channel switch 168 can be coupled to the voltage terminal 124 via the first inductor 150 and the first decoupling inductor 156 of the decoupling network 110.

[0052] The gate terminal of the second P-channel switch 174 may be coupled (e.g., cross-coupled) to the drain terminal of the first P-channel switch 172 via a third node 142. The gate terminal of the first P-channel switch 172 may be coupled (e.g., cross-coupled) to the drain terminal of the second P-channel switch 174 via a fourth node 144. As described above, in some embodiments, the third node 142 and the fourth node 144 may correspond to or have a second positive output terminal and a second negative output terminal of the VCO 66 (e.g., replacing the positive output terminal 136 and the negative output terminal 138 or other than the positive output terminal and the negative output terminal). The second inductor 158, the second capacitor bank 160, and the second variable capacitor 162 may be coupled to the drain terminal of the first P-channel switch 172 via the third node 142 and may be coupled to the drain terminal of the second P-channel switch 174 via the fourth node 144.

[0053] The drain terminals of the first P-channel switch 172 and the second P-channel switch 174 can be coupled to the ground terminal 128 via the second LC slot 114 and the decoupling network 110. Specifically, the drain terminals of the first P-channel switch 172 and the second P-channel switch 174 can be coupled to the ground terminal 128 via the second inductor 158 and the second decoupling inductor 164.

[0054] The source terminals of the first N-channel switch 166, the second N-channel switch 168, the first P-channel switch 172, and the second P-channel switch 174 can be coupled to the common-mode filter 108. For example, the common-mode filter 108 can couple the source terminals of the first N-channel switch 166 and the second N-channel switch 168 to the source terminals of the first P-channel switch 172 and the second P-channel switch 174. As described above, the common-mode filter 108 can conduct a bias voltage 126, a DC signal (e.g., current), and / or an output signal 102 (e.g., a differential output signal) between the first unit 120 and the second unit 122. Therefore, the first current source 116 and the second current source 118 can generate a DC signal based on the bias voltage 126. Furthermore, the first inductor 150 and the second inductor 158 can differentially receive the DC signal in response to the VCO 66 receiving the bias voltage 126 (or any other feasible input signal). In addition, the first LC slot 112 and the second LC slot 114 can generate the output signal 102.

[0055] In the depicted embodiments, the common-mode filter 108 may include a differential inductor 180 and a differential capacitor 182. First terminals of the differential inductor 180 and differential capacitor 182 may be coupled to the source terminals of a first N-channel switch 166 and a second N-channel switch 168. Second terminals of the differential inductor 180 and differential capacitor 182 may be coupled to the source terminals of a first P-channel switch 172 and a second P-channel switch 174. In some embodiments, the differential inductor 180 may include a single inductor (e.g., a single winding). In alternative or additional embodiments, the differential inductor 180 may include a series-coupled first inductor 180-1 (e.g., a first winding) and a second inductor 180-2 (e.g., a second winding). For example, the first winding and the second winding may each correspond to half or any other feasible portion of the winding of the differential inductor 180. Furthermore, the first inductor 180-1 and the second inductor 180-2 may each have half or any other portion of the inductance of the differential inductor 180.

[0056] The capacitance value of differential capacitor 182 and the inductance value of differential inductor 180 can each correspond to the resonant frequency range of common-mode filter 108. Therefore, differential inductor 180 and differential capacitor 182 can reduce (e.g., suppress) undesirable common-mode noise 139 and 140 of output signal 102. Differential capacitor 182 and differential inductor 180 can be located away from decoupling network 110 (e.g., not directly coupled to the decoupling network), and alternatively, can be directly coupled to first unit 120 and second unit 122 (e.g., coupled between the first unit and the second unit). Therefore, the dependence of parasitic capacitance and / or parasitic inductance of differential capacitor 182 and differential inductor 180 on decoupling network 110 can be reduced. Furthermore, one or more values ​​and / or undesirable variations of parasitic capacitance and / or parasitic inductance of differential capacitor 182 and differential inductor 180 can be reduced. Therefore, the source terminals of the first N-channel switch 166, the second N-channel switch 168, the first P-channel switch 172, and the second P-channel switch 174 can receive signals with reduced current fluctuations (e.g., noise current fluctuations). For example, the source terminals of the first N-channel switch 166, the second N-channel switch 168, the first P-channel switch 172, and the second P-channel switch 174 can receive signals with improved stability.

[0057] VCO 66 may have an increased and / or extended oscillation frequency bandwidth due to reduced current fluctuations at the source terminals of switches 166, 168, 172, and 174. Furthermore, VCO 66 may have reduced unwanted voltage and / or frequency offset on the output signal 102. In some cases, VCO 66 may have an improved signal-to-noise ratio to generate the output signal 102 without increasing power consumption. Alternatively or additionally, compared to other VCOs, VCO 66 may generate an output signal 102 with phase noise (e.g., constant phase noise, reduced phase noise) by consuming a reduced amount of electrical power. That is, VCO 66 may have improved efficiency in generating an output signal 102 with phase noise. Therefore, VCO 66 may improve the operation of transmitter 52, receiver 54, and / or electronic device 10 by generating a signal with improved signal integrity based on reduced noise and / or improved efficiency based on reduced power consumption. For example, the improved signal may reduce timing error rates and / or improve the integrity of transmitted and / or received data, etc.

[0058] Figure 7This is a schematic diagram of a VCO 66 according to an embodiment of the present disclosure, including single-ended capacitors 184 and 186, a differential capacitor 182, a differential inductor 180, and a common-mode filter 108. As described above, the first terminals of the differential inductor 180 and the differential capacitor 182 are coupled to the source terminals of the first N-channel switch 166 and the second N-channel switch 168. The second terminals of the differential inductor 180 and the differential capacitor 182 are coupled to the source terminals of the first P-channel switch 172 and the second P-channel switch 174. Furthermore, the differential inductor 180 may include a single winding. Alternatively, the differential inductor 180 may include a first differential inductor 180-1 and a second differential inductor 180-2.

[0059] In the depicted embodiment, the first terminal of the first single-ended capacitor 184 is coupled to the source terminals of the first N-channel switch 166 and the second N-channel switch 168. The first terminal of the second single-ended capacitor 186 is coupled to the second terminal of the first single-ended capacitor 184. Furthermore, a ground terminal (e.g., ground terminal 128) is coupled to the second terminal of the first single-ended capacitor 184 and the first terminal of the second single-ended capacitor 186. The second terminal of the second single-ended capacitor 186 is coupled to the source terminals of the first P-channel switch 172 and the second P-channel switch 174.

[0060] Single-ended capacitors 184 and 186 may have capacitance values ​​to reduce (e.g., suppress) unwanted common-mode noise 139 and 140 and / or one or more harmonics of the output signal 102 at the source terminals of the first N-channel switch 166, the second N-channel switch 168, the first P-channel switch 172, and the second P-channel switch 174. Therefore, VCO 66 may have increased and / or extended noise reduction frequency bandwidth based on reduced parasitic capacitance and / or parasitic inductance values ​​at the source terminals of switches 166, 168, 172, and 174.

[0061] Figure 8 This is a schematic diagram of a VCO 66 according to an embodiment of the present disclosure, the VCO including an impedance component 188, single-ended capacitors 184 and 186, a differential capacitor 182 and a differential inductor 180, and a common-mode filter 108. As described above, the first terminals of the differential inductor 180 and the differential capacitor 182 are coupled to the source terminals of a first N-channel switch 166 and a second N-channel switch 168. The second terminals of the differential inductor 180 and the differential capacitor 182 are coupled to the source terminals of a first P-channel switch 172 and a second P-channel switch 174. Furthermore, the differential inductor 180 may include a single winding. Alternatively, the differential inductor 180 may include a first differential inductor 180-1 and a second differential inductor 180-2.

[0062] In the depicted embodiment, impedance component 188 is tapped onto the winding of differential inductor 180. For example, impedance component 188 may be coupled to any portion of the winding of differential inductor 180, such as the center tap of the winding of differential inductor 180. In some embodiments, impedance component 188 may be coupled between the first differential inductor 180-1 and the second differential inductor 180-2. Furthermore, impedance component 188 is coupled to the second terminal of the first single-ended capacitor 184 and the first terminal of the second single-ended capacitor 186.

[0063] Impedance component 188 may include resistors, capacitors, inductors, or any combination thereof, as well as other possibilities. Impedance component 188 may have an impedance value to reduce (e.g., suppress) unwanted common-mode noise 139 and 140 and / or one or more harmonics of the output signal 102 at the source terminals of the first N-channel switch 166, the second N-channel switch 168, the first P-channel switch 172, and the second P-channel switch 174. Therefore, VCO 66 may have an increased and / or extended noise reduction frequency bandwidth based on the reduced parasitic capacitance, parasitic inductance, and / or current fluctuations at the source terminals of switches 166, 168, 172, and 174.

[0064] Figure 9 This is a layout of VCO 66 according to an embodiment of this disclosure. In the depicted embodiment, an LC tank circuit system 104, a current source circuit 106, a common-mode filter 108, a decoupling network 110, and a ground terminal 128 are shown. The LC tank circuit system 104 may include inductors 150 and 158, capacitor banks 152 and 160, and variable capacitors 154 and 162. The current source circuit 106 may include switches 166, 168, 172, and 174. The common-mode filter 108 may include differential inductors 180 (e.g., differential inductors 180-1 and 180-2), differential capacitors 182, and single-ended capacitors 184 and 186. In alternative or additional embodiments, the common-mode filter 108 may include the impedance component 188 discussed above.

[0065] The common-mode filter 108 is not directly coupled to the decoupling network 110. For example, the common-mode filter 108 is positioned away from the decoupling network 110 in the layout. As illustrated, the common-mode filter 108 is located on the opposite side or end of the VCO 66 compared to the decoupling network 110, and is instead directly coupled to the first inductor 150 of the first unit 120 and the second inductor 158 of the second unit 122 (e.g., coupled between the first inductor and the second inductor). The VCO 66 can occupy a similar area compared to other VCOs with a decoupling network 110 coupled to the common-mode filter 108.

[0066] For example, VCO 66 may not include additional circuitry (e.g., filters) to reduce (e.g., suppress) unwanted common-mode noise 139 and 140 and / or one or more harmonics of the output signal 102 at the source terminals of switches 166, 168, 172, and 174. Therefore, VCO 66 can be improved compared to other VCOs by occupying the same (e.g., similar) area while having reduced current ripple. Thus, VCO 66 may not occupy additional area compared to other VCOs having a decoupling network coupled to a common-mode filter and / or disposed on the same side of the common-mode filter, based on distributing the common-mode filter 108 on the opposite side of the decoupling network 110. For example, the common-mode filter 108 may be disposed on a second side (e.g., a second end) of VCO 66 above inductors 150 and 158, while the decoupling network 110 is disposed on a first side (e.g., a first end) of VCO 66 below inductors 150 and 158.

[0067] Furthermore, the first inductor 150 may be disposed within the threshold proximity of the second inductor 158. The threshold proximity may be 1 picometer or less, 100 nanometers (nm) or less, 57 nm or less, 8 nm or less, 674 millimeters (mm) or less, 94 mm or less, 10 mm or less, 0.1 mm or less, and other possibilities. In some embodiments, the second inductor 158 may cover or under the first inductor 150, for example, on or in a printed circuit board (PCB), and other possibilities. Therefore, the first inductor 150 and the second inductor 158 may occupy less surface area compared to the area occupied by the first inductor 150 and the second inductor 158 arranged in different configurations (e.g., side-by-side). In some cases, the first inductor 150 and the second inductor 158 may occupy an area corresponding to the area of ​​either the first inductor 150 or the second inductor 158, which is smaller than the area occupied by the first inductor 150 and the second inductor 158 arranged in different configurations. For example, the first inductor 150 and the second inductor 158 may occupy an area corresponding to a portion of the area occupied by the first inductor 150 and the second inductor 158 arranged side by side. In view of the foregoing, it should be understood that... Figure 9 The layout is provided as an example, and VCO 66 can have any other feasible layout and / or variations thereof.

[0068] The specific embodiments described above have been shown by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0069] The techniques presented and claimed herein are referenced and applied to specific examples of physical and practical nature that significantly improve the art and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements designated as “component for [performing] [function]…” or “step for [performing] [function]…”, such elements are intended to be interpreted in accordance with 35 USC 112(f). However, for any claim containing elements designated in any other manner, such elements are intended not to be interpreted in accordance with 35 USC 112(f).

Claims

1. A voltage-controlled oscillator, the voltage-controlled oscillator comprising: First inductor - capacitor tank circuit; The first current source circuit is coupled to the first inductor-capacitor tank circuit. A differential capacitor having a first terminal coupled to the first current source circuit; A differential inductor having a first terminal coupled to the first current source circuit; A second current source circuit is coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor. as well as The second inductor-capacitor tank circuit is coupled to the second current source circuit.

2. The voltage-controlled oscillator according to claim 1, wherein the first current source circuit includes a first N-channel switch and a second N-channel switch.

3. The voltage-controlled oscillator according to claim 2, wherein the first terminal of the differential capacitor is coupled to the source terminal of the first N-channel switch and the source terminal of the second N-channel switch, and the first terminal of the differential inductor is coupled to the source terminal of the first N-channel switch and the source terminal of the second N-channel switch.

4. The voltage-controlled oscillator according to claim 1, wherein the second current source circuit includes a first P-channel switch and a second P-channel switch.

5. The voltage-controlled oscillator of claim 4, wherein the source terminal of the first P-channel switch is coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor, and the source terminal of the second P-channel switch is coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor.

6. The voltage-controlled oscillator according to claim 1, wherein the voltage-controlled oscillator comprises... A first single-ended capacitor, the first single-ended capacitor having a first terminal coupled to the first current source circuit, and A second single-ended capacitor, the second single-ended capacitor having The first terminal, coupled to the second terminal of the first current source circuit, and The second terminal is coupled to the second current source circuit.

7. The voltage-controlled oscillator of claim 6, wherein the voltage-controlled oscillator includes an impedance component coupled to the center tap of the differential inductor, the second terminal of the first single-ended capacitor, and the first terminal of the second single-ended capacitor.

8. The voltage-controlled oscillator according to claim 1, wherein the voltage-controlled oscillator comprises... A first decoupling inductor, the first decoupling inductor having The first terminal, the first terminal being coupled to the power supply, and The second terminal is coupled to the first inductor-capacitor tank circuit, and The second decoupling inductor has The first terminal, coupled to the second inductor-capacitor tank circuit, and The second terminal is coupled to the ground terminal.

9. The voltage-controlled oscillator according to claim 1, wherein the voltage-controlled oscillator includes a differential output terminal, the differential output terminal being coupled to the first inductor-capacitor tank circuit and the first current source circuit, or coupled to the second inductor-capacitor tank circuit and the second current source circuit.

10. A transceiver, the transceiver comprising: A voltage-controlled oscillator, the voltage-controlled oscillator comprising: First current source circuit; A differential capacitor having a first terminal coupled to the first current source circuit; A differential inductor having a first terminal coupled to the first current source circuit; and A second current source circuit, coupled to a second terminal of the differential capacitor and a second terminal of the differential inductor, wherein the voltage-controlled oscillator is configured to generate an output signal; and A mixer coupled to the voltage-controlled oscillator, the mixer being configured to generate a signal based on the output signal.

11. The transceiver of claim 10, wherein the voltage-controlled oscillator comprises... A first decoupling inductor, the first decoupling inductor having a first terminal coupled to a power supply terminal. The first inductor-capacitor tank circuit is coupled to the second terminal of the first decoupling inductor, and the first current source circuit is coupled to the first inductor-capacitor tank circuit. The second inductor-capacitor tank circuit is coupled to the second current source circuit, and The second decoupling inductor is coupled to the second inductor-capacitor tank circuit and the ground terminal.

12. The transceiver of claim 10, wherein the differential capacitor and the differential inductor are configured to reduce the voltage amplitude of the common-mode noise signal or the second harmonic signal of the output signal of the voltage-controlled oscillator.

13. The transceiver of claim 10, wherein the first current source circuit includes a first N-channel switch and a second N-channel switch, the first terminal of the differential capacitor is coupled to the source terminals of the first N-channel switch and the second N-channel switch, and the first terminal of the differential inductor is coupled to the source terminals of the first N-channel switch and the second N-channel switch.

14. The transceiver of claim 10, wherein the second current source circuit includes a first P-channel switch and a second P-channel switch, the source terminals of the first P-channel switch and the second P-channel switch being coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor.

15. A voltage-controlled oscillator, the voltage-controlled oscillator comprising: First current source circuit; A differential capacitor having a first terminal directly coupled to the first current source circuit; A differential inductor having a first terminal directly coupled to the first current source circuit; as well as The second current source circuit is directly coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor.

16. The voltage-controlled oscillator of claim 15, wherein the first current source circuit comprises a first N-channel switch and a second N-channel switch.

17. The voltage-controlled oscillator of claim 16, wherein the first terminal of the differential capacitor is coupled to the source terminal of the first N-channel switch and the source terminal of the second N-channel switch, and the first terminal of the differential inductor is coupled to the source terminal of the first N-channel switch and the source terminal of the second N-channel switch.

18. The voltage-controlled oscillator of claim 15, wherein the second current source circuit comprises a first P-channel switch and a second P-channel switch.

19. The voltage-controlled oscillator of claim 18, wherein the source terminal of the first P-channel switch is coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor, and the source terminal of the second P-channel switch is coupled to the second terminal of the differential capacitor and the second terminal of the differential inductor.

20. The voltage-controlled oscillator of claim 15, the voltage-controlled oscillator comprising a decoupling network disposed at a first end of the layout, wherein the differential capacitor and the differential inductor are disposed at a second end of the layout different from the first end.

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