A high-stability adjustable dead-zone driving circuit for GaN gate driving chip

Abstract

This invention relates to a highly stable adjustable dead-time driving circuit for GaN gate driver chips, belonging to the technical field of gallium nitride half-bridge gate driver chips. The dead-time driving circuit includes a negative voltage detection circuit for detecting V in the GaN driving circuit. SW The node generates a negative voltage, outputting a detection signal VNL; three pulses, VGL, VGH, and VDH, act as inputs for the control signals; two current sources simulate the current detected in the GaN drive path; and the power rail VIN simulates the voltage detected in the GaN drive path. SW Used to simulate the negative voltage in the GaN driving path; the negative voltage control circuit converts the detected negative voltage output signal VNL into a control signal VZC; the dead-time main control circuit, based on the power supply voltage VIN and the load current I... d In addition to the VZC signal, the dead time is dynamically output. This invention ensures the efficient and stable operation of gallium nitride power devices.

Description

Technical Field

[0001] This invention belongs to the technical field of gallium nitride half-bridge gate driver chip, and relates to a highly stable adjustable dead-time driving circuit for GaN gate driver chips. Background Technology

[0002] The significant advantages of gallium nitride (GaN) power devices have driven the rapid development of corresponding GaN gate driver integrated circuits, leading to the widespread application of GaN-based power electronic systems in the power electronics field. In high-frequency half-bridge applications, reverse conduction losses during the dead time have become a key bottleneck limiting system efficiency and reliability. Unlike traditional silicon-based devices, GaN devices lack parasitic body diodes, resulting in a reverse conduction voltage drop during the dead time that can be up to three times that of silicon devices. Therefore, under high-frequency switching conditions, reverse conduction losses increase exponentially. For example, in an 800V platform for electric vehicles, an increase of only 1 ns in the dead time can reduce system efficiency by approximately 0.8%, while the thermal stress induced by reverse conduction further accelerates device aging.

[0003] At high switching frequencies, the rate of voltage change (dV / dt) at the switching node can reach 200V / ns. A fixed dead time cannot compensate for the delay caused by load fluctuations during voltage transition. Specifically, the optimal dead time shortens when the input voltage decreases or the load current increases, and lengthens when the input voltage increases or the load current decreases. Therefore, adjustable control of the high-side and low-side power switching timing is crucial for improving overall system efficiency. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a highly stable adjustable dead-time driving circuit for GaN gate driver chips, which realizes level shifting with sub-nanosecond transmission delay. This circuit structure can speed up signal transmission, effectively block high dv / dt noise, and ensure the correctness of output logic.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A highly stable adjustable dead-time drive circuit for GaN gate drive chips includes first PMOS transistors MP1 to MP5, first NMOS transistors MN1 to MN6, eleventh NMOS transistors MN11 to thirteenth NMOS transistors MN13, first resistors R1 to R3, first RS flip-flop RS1, first capacitors C1 to C3, first inverters INV1 to INV3, first AND gates AND1 to AND gates AND2, first D flip-flop D1, and a delay unit DELAY. The source of the first NMOS transistor MN1 is grounded, and its gate and drain are shorted and then connected to the input detection current I.d The sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are grounded, and their gates are connected to the gates of the first NMOS transistor MN1 and the eleventh NMOS transistor MN11, respectively. Their drains are connected to the drain of the first PMOS transistor MP1 and one end of the first resistor R1, respectively. The source of the fourth NMOS transistor MN4 is connected to the drain of the eleventh NMOS transistor MN11, its gate is connected to the output of the first inverter INV1, and its drain is connected to the drain of the second PMOS transistor MP2. The source of the fifth NMOS transistor MN5 is connected to one end of the second resistor R2, and its gate is connected to the source of the fourth NMOS transistor MN4. The source of the thirteenth NMOS transistor MN13, i.e., node VA, is connected to the drain of the third PMOS transistor MP3; the sources of the sixth NMOS transistor MN6 and the eleventh NMOS transistor MN11 are both grounded, their gates are connected to the output of the first AND gate AND1, and their drains are connected to the drain of the fifth PMOS transistor MP5; the source of the twelfth NMOS transistor MN12 is connected to one end of the third capacitor C3, its gate is connected to the current comparison detection signal VC1, and its drain is connected to one end of the second capacitor and one input of the second AND gate AND2; the drain of the thirteenth NMOS transistor MN13 is connected to the power supply VDD; The source of the first PMOS transistor MP1 is connected to the power supply VDD, and its gate and drain are shorted and then connected to the drain of the second NMOS transistor MN2; the source of the second PMOS transistor MP2 is connected to the power supply VDD, its gate is connected to the gate of the first PMOS transistor MP1, and its drain is connected to the drain of the fourth NMOS transistor MN4; the source of the third PMOS transistor MP3 is connected to the power supply VDD, and its gate and drain are shorted and then connected to the drain of the fifth NMOS transistor MN5; the source of the fourth PMOS transistor MP4 is connected to the power supply VDD, its gate is connected to the gate of the third PMOS transistor MP3, and its drain is connected to the source of the fifth PMOS transistor MP5; the gate of the fifth PMOS transistor MP5 is connected to the output of the first AND gate AND1, and its drain is connected to the drain of the sixth NMOS transistor MN6; One end of the first resistor R1 is connected to the power supply VIN, and the other end is connected to the drain of the third NMOS transistor MN3; one end of the second resistor R2 is connected to the source of the fifth NMOS transistor MN5, and the other end is grounded; one end of the third resistor R3 is connected to the power supply VDD, and the other end is connected to the other input terminal of the second AND gate AND2. The input of the first inverter INV1 is connected to the output of the delay timer DELAY, i.e., the VDM node, and the output is connected to the gate of the fourth NMOS transistor MN4; the input of the second inverter INV2 is connected to the output of the first RS flip-flop RS1, and the output is connected to one input of the first AND gate AND1; the input of the third inverter INV3 is connected to the input pulse VDH, and the output is connected to the other input of the first AND gate AND1. The D input of the first D flip-flop D1 is connected to the power supply VDD, the CLK input is connected to the pulse signal VGL, the CLR input is connected to the pulse signal VGH, and the output is connected to the input of the delay unit DELAY. One end of the first capacitor C1 is connected to the gate of the fifth NMOS transistor MN5, and the other end is grounded; one end of the second capacitor C2 is connected to one input of the second AND gate AND2, and the other end is grounded; the other end of the fourth capacitor C3 is grounded. The output of the second AND gate AND2 outputs a signal.

[0006] The circuit also includes a negative pressure detection circuit and a negative pressure control circuit; the R input terminal of the first RS flip-flop RS1 is connected to the output terminal of the fifth inverter INV5 of the negative pressure detection circuit and the R input terminal of the second RS flip-flop of the negative pressure control circuit, and the S input terminal is connected to the input pulse signal VDH.

[0007] The negative pressure detection circuit is used to detect the negative pressure detection node V in the GaN driving circuit. SW The generated negative voltage outputs a detection signal VNL; three pulse signals VGL, VGH, and VDH are used as inputs for analog control signals; current I... d Used to simulate the current detected in a GaN driving circuit; power supply VIN is used to simulate the voltage detected in a GaN driving circuit, with negative voltage detection node V. SW Used to simulate negative voltage in GaN driving circuits; the negative voltage control circuit is used to convert the detection signal VNL output by the negative voltage detection circuit into a control signal VZC.

[0008] Preferably, the negative voltage detection circuit includes a sixth PMOS transistor MP6 to a seventh PMOS transistor MP7, a seventh NMOS transistor MN7 to an eighth NMOS transistor MN8, a first NLDMOS transistor NLD1, a fifth inverter INV4, and a comparator CMOP; The gate and source of the first NLDMOS transistor NLD1 are connected to the drain of the eighth NMOS transistor MN8, and its drain is connected to the negative voltage detection node V. SW ; The source of the seventh NMOS transistor MN7 is grounded, and the source of the eighth NMOS transistor MN8 is grounded. Both its gate and drain are connected to the gate of the eighth NMOS transistor MN8 and the fixed current source I. B Connection; Current I B Used to simulate the current detected in the GaN drive path; the drain of the eighth NMOS transistor MN8 is connected to the drain of the sixth PMOS transistor MP6 and the drain of the seventh PMOS transistor MP7. The sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the power supply VDD, and their gates are connected to the drain of the eighth NMOS transistor MN8 and the power supply VDD, respectively. Their drains are connected to the drain of the eighth NMOS transistor MN8 and the positive input terminal of the comparator CMOP. The input of the fifth inverter INV5 is connected to the output of the comparator CMOP, and the output is connected to the upper input R of the second RS flip-flop RS2 and the R input of the first RS flip-flop RS1 in the negative voltage control circuit. The negative input terminal of the comparator CMOP is grounded.

[0009] Preferably, the negative voltage control circuit includes an eighth PMOS transistor MP8 to a tenth PMOS transistor MP10; an eighth NMOS transistor MN8 to a tenth NMOS transistor MN10; a fourth resistor R4 to a fifth resistor R5; a second RS flip-flop RS2; a fourth capacitor C4; a fourth inverter INV4; a sixth inverter INV6 to a seventh inverter INV7; and a NAND gate. The source of the tenth NMOS transistor MN10 is grounded; the source of the ninth NMOS transistor MN9 is grounded, its gate is connected to the output of the seventh inverter INV7, and its drain is connected to the drain of the eighth PMOS transistor MP8; the gate and drain of the tenth NMOS transistor MN10 are both connected to the drain of the tenth PMOS transistor MP10. The source of the eighth PMOS transistor MP8 is connected to the power supply VDD, its gate is connected to the output of the seventh inverter INV7 and one input of the NAND gate, and its drain is connected to the drain of the ninth NMOS transistor MN9; the source of the ninth PMOS transistor MP9 is connected to the power supply VDD, its gate is connected to the gate of the tenth PMOS transistor MP10, and its drain is connected to one end of the fifth resistor R5; the source of the tenth PMOS transistor MP10 is connected to the power supply VDD. One end of the fourth resistor R4 is connected to one end of the fourth capacitor C4 and the other input terminal of the NAND gate, and the other end is connected to the drain of the ninth NMOS transistor MN9; the other end of the fifth resistor R5 is connected to the output terminal of the fourth inverter INV4; the other end of the fourth capacitor C4 is grounded. The input of the fourth inverter INV4 is connected to the output of the NAND gate; the input of the sixth inverter INV6 is connected to the output of the first AND gate AND1, i.e., the VDM node, and the output is connected to the S input of the second RS flip-flop RS2; the input of the seventh inverter INV7 is connected to the output of the second RS flip-flop RS2, and the output is connected to the gate of the ninth NMOS transistor MN9. The R input terminal of the second RS flip-flop is connected to the output terminal of the fifth inverter INV5 of the negative voltage detection circuit and the R input terminal of the first RS flip-flop RS1.

[0010] Preferably, the circuit further includes a dead-time main control circuit, which controls the power supply voltage VIN and current I.d And the control signal VZC dynamically outputs the dead time.

[0011] Preferably, when the detection voltage VIN is valid, the fourth NMOS transistor MN4 is controlled to pull down the voltage at node VA, thereby increasing the dead time of the output; when the detection current I... d When effective, the second PMOS transistor MP2 is controlled to pull up the voltage of the VA node, thereby reducing the dead time of the output; When V SW When the node is under negative voltage, the first NLDMOS transistor NLD1 pulls down the voltage of node VC, controlling the negative voltage detection signal VNL output by the comparator CMOP to flip. When the negative voltage detection signal VNL is valid, the output of the second RS flip-flop RS2 outputs a rising edge, causing the output signal VNC of the seventh inverter INV7 to flip, charging the fourth resistor R4 and the fourth capacitor C4, causing the NAND gate to output a short pulse, and causing the VZC node to output a short pulse control signal.

[0012] Preferably, when the detection voltage VIN is valid, the fourth NMOS transistor MN4 and the eleventh NMOS transistor MN11 are turned on, pulling down the voltage at the upper end of the first capacitor C1, reducing the current in the path of the fifth NMOS transistor MN5, and thus reducing the current of the fourth PMOS transistor MP4. This slows down the charging speed at the upper end of the second capacitor C2, increasing the output dead time. When the detection current I... d When effective, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, which in turn turns on the first PMOS transistor MP1 and the second PMOS transistor MP2. The voltage at the upper end of the first capacitor C1 is pulled up by the fourth NMOS transistor MN4, which increases the current in the path of the fifth NMOS transistor MN5, and thus increases the current of the fourth PMOS transistor MP4. This speeds up the charging of the upper end of the second capacitor C2 and reduces the output dead time. When V SW When the node negative voltage is effective, the gate and source of the first LDMOS transistor NLD1 are shorted, causing its parasitic reverse diode to reach the voltage across the conduction clamp, forcing the upper end of the eighth NMOS transistor MN8 to follow V. SW The voltage changes to a negative voltage, causing the voltage at the upper input terminal of comparator CMOP to be less than the voltage at the lower input terminal, resulting in a low-level output of the negative voltage detection signal VNL. When the negative voltage detection signal VNL is valid, a short pulse is simultaneously input to VDM, causing the second RS flip-flop RS2 to output a rising edge, which in turn enables the eighth PMOS transistor MP8 to charge the upper end of the fourth capacitor C4, controlling the NAND gate to output a short pulse signal, which in turn turns off the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10, causing the VZC node to output a short pulse and pull down the voltage at the upper end of the first capacitor C1, thus reducing the dead time of the output.

[0013] Option 2: A GaN half-bridge driving system, comprising a GaN half-bridge circuit and the highly stable adjustable dead-time driving circuit for GaN gate driving chips described in Option 1.

[0014] The beneficial effects of this invention are as follows: This invention enhances the adjustability of the dead time by adding a negative pressure detection circuit and a negative pressure control module circuit to the adjustable dead time circuit, and by detecting V... SW The node negative pressure incorporates a negative pressure control module, effectively preventing V from being negatively impacted in the next cycle. SW The generation of negative voltage enhances the ability to adjust the dead time, effectively reducing reverse conduction losses in GaN devices. It is effectively compatible with high-speed gallium nitride gate driver chips.

[0015] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a diagram of the dead-zone driving circuit for high-frequency GaN gate drive chips according to the present invention. Figure 2 This indicates the location of the dead-zone drive circuit in the half-bridge drive chip architecture of this invention; Figure 3 The adjustable working waveform diagram with negative pressure detection; Figure 4 The adjustable working waveform diagram without negative pressure detection; Figure 5 The waveform diagrams are shown for the dead-zone drive circuit of the present invention under different load conditions. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0019] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0020] Example 1: Please see Figure 1 This embodiment provides a highly stable adjustable dead-time driving circuit for GaN gate driver chips. The circuit includes a negative voltage detection circuit for detecting V in the GaN driving circuit. SW The negative voltage generated by the node outputs a detection signal VNL; three pulses, VGL, VGH, and VDH, act as inputs for the control signals; two current sources simulate the current detected in the GaN drive path; and the power rail V... IN Used to simulate the voltage detected in the GaN driving path, the negative voltage detection node is the power rail V. SW Used to simulate the negative voltage in the GaN driving path; the negative voltage control circuit converts the detected negative voltage output signal VNL into a control signal VZC; the dead-time main control circuit, based on the power supply voltage V... IN The system dynamically outputs the dead time based on the load current Id and the VZC signal, ensuring efficient and stable operation of gallium nitride power devices.

[0021] Specifically, the circuit includes first PMOS transistors MP1 to tenth PMOS transistors MP10, first NMOS transistors MN1 to thirteenth NMOS transistors MN13, first resistors R1 to fifth resistors R5, first RS flip-flops RS1 to second RS flip-flops RS2, first NLDMOS transistor NLD1, first capacitors C1 to fourth capacitors C4, first inverters INV1 to seventh inverters INV7, first AND gates AND1 to second AND gates AND2, NAND gates NAND, comparator CMOP, first D flip-flop D1, and delay unit DELAY.

[0022] The gate and source of the first NLDMOS transistor NLD1 are connected to the drain of the eighth NMOS transistor MN8, and its drain is connected to the negative voltage detection node V. SW The source of the first NMOS transistor MN1 is grounded, and its gate and drain are shorted and then connected to the input detection current I. d The sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are grounded, and their gates are connected to the gates of the first NMOS transistor MN1 and the eleventh NMOS transistor MN11, respectively. Their drains are connected to the drain of the first PMOS transistor MP1 and the lower end of the first resistor R1, respectively. The source of the fourth NMOS transistor MN4 is connected to the drain of the eleventh NMOS transistor MN11, its gate is connected to the output of the first inverter INV1, and its drain is connected to the drain of the second PMOS transistor MP2. The source of the fifth NMOS transistor MN5 is connected to the upper end of the second resistor R2, its gate is connected to the source of the fourth NMOS transistor MN4 and the source of the thirteenth NMOS transistor MN13 (i.e., node VA), and its drain is connected to the drain of the third PMOS transistor MP3. The sixth NMOS transistor MN6 and the seventh NMOS transistor M... The sources of N7, MN8, MN9, MN10, and MN11 are grounded, and their gates are connected to the output of AND1, the fixed current source IB, the gate of MN7, the output of INV7, the drain of MP10, and the gate of MN3, respectively. The drains of MN3 are connected to the drain of MP5, the fixed current source IB, the drain of MP6, the drain of MP8, the drain of MP10, and the source of MN4, respectively. The source of MN12 is connected to the upper end of the third capacitor C3, the gate is connected to the current comparison detection signal VC1, and the drain is connected to the upper end of the second capacitor.

[0023] The source of the first PMOS transistor MP1 is connected to the power supply VDD, and its gate and drain are shorted and then connected to the drain of the second NMOS transistor MN2. The source of the second PMOS transistor MP2 is connected to the power supply VDD, its gate is connected to the gate of the first PMOS transistor MP1, and its drain is connected to the drain of the fourth NMOS transistor MN4. The source of the third PMOS transistor MP3 is connected to the power supply VDD, and its gate and drain are shorted and then connected to the drain of the fifth NMOS transistor MN5. The source of the fourth PMOS transistor MP4 is connected to the power supply VDD, its gate is connected to the gate of the third PMOS transistor MP3, and its drain is connected to the drain of the fourth NMOS transistor MN4. The source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4, its gate is connected to the output of the first AND gate AND1, and its drain is connected to the sixth NMOS transistor MN2. The drain of transistor MN6 is connected to the power supply VDD; the sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the power supply VDD, and their gates are connected to the drain of the eighth NMOS transistor MN8 and the power supply VDD, respectively. The drain of MP8 is connected to the drain of the eighth NMOS transistor MN8; the source of the eighth PMOS transistor MP8 is connected to the power supply VDD, its gate is connected to the output of the seventh inverter INV7, and its drain is connected to the drain of the ninth NMOS transistor MN9; the source of the ninth PMOS transistor MP9 is connected to the power supply VDD, its gate is connected to the gate of the tenth PMOS transistor MP10, and its drain is connected to the upper end of the fifth resistor R5; the source of the tenth PMOS transistor MP9 is connected to the power supply VDD, its gate is connected to the gate of the ninth PMOS transistor MP9, and its drain is connected to the drain of the tenth NMOS transistor MN10.

[0024] The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are connected at their upper ends to the power supply VIN, the source of the fifth NMOS transistor MN5, the power supply VDD, the capacitor C3, and the drain of the ninth PMOS transistor MP9. Their lower ends are connected to the third NMOS transistor MN3, ground, the upper input of the second AND gate AND2, the drain of the ninth NMOS transistor MN9, and the output of the fourth inverter INV4.

[0025] The input of the first inverter INV1 is connected to the output of the delay DELAYA, and the output is connected to the gate of the fourth NMOS transistor MN4; the input of the second inverter INV2 is connected to the output of the first RS flip-flop RS1, and the output is connected to the upper input of the first AND gate AND1; the input of the third inverter INV3 is connected to the input pulse VDH, and the output is connected to the lower input of the first AND gate AND1; the input of the fourth inverter INV4 is connected to the output of the NAND gate NAND, and the output is connected to the lower end of the first resistor R5; the input of the fifth inverter INV5 is connected to the output of the comparator CMOP, and the output is connected to the upper input of the second RS flip-flop RS2; the input of the sixth inverter INV6 is connected to the output of the first AND gate AND1, and the output is connected to the lower input of the second RS flip-flop RS2; the input of the seventh inverter INV7 is connected to the output of the second RS flip-flop RS2, and the output is connected to the gate of the ninth NMOS transistor MN9.

[0026] The upper input of the first RS flip-flop is connected to the output of comparator CMOP, and the lower input is connected to the input pulse VDH; the upper input of the second RS flip-flop is connected to the output of the fifth inverter INV5; the upper input of the second RS flip-flop is connected to the output of the fifth inverter INV5, and the lower input is connected to the output of the sixth inverter.

[0027] The upper input of the comparator CMOP is connected to the drain of the sixth PMOS transistor, the lower input is grounded, and the output is connected to the input of the fifth inverter.

[0028] The first D flip-flop has its upper input connected to power supply VDD, its middle input connected to pulse signal VGL, its lower input connected to pulse signal VGH, and its output connected to the input of the delay unit DELAY.

[0029] The input of the delay unit DELAY is connected to the output of the first D flip-flop D1, and the output is connected to the gate of the fourth NMOS transistor MN4.

[0030] The upper end of the first capacitor C1 is connected to the gate of the fifth NMOS transistor MN5, and the lower end is grounded; the upper end of the second capacitor C2 is connected to the lower input terminal of the second AND gate AND2, and the lower end is grounded; the upper end of the third capacitor C3 is connected to the lower input terminal of the NAND gate NAND; the upper end of the fourth capacitor C4 is connected to the twelfth NMOS transistor MN12, and the lower end is grounded.

[0031] The upper input of the NAND gate is connected to the output of the seventh inverter INV7, the lower input is connected to the upper end of the fourth resistor R4, and the output is connected to the input of the fourth inverter INV4.

[0032] The upper input of the first AND gate AND1 is connected to the output of the second inverter INV2, the lower input is connected to the output of the third inverter, and the output is connected to the gate of the sixth NMOS transistor MN6; the upper input of the second AND gate AND2 is connected to the gate of the sixth NMOS transistor MN6, the lower input is the upper end of the second capacitor C2, and the output outputs a signal.

[0033] Example 2: The circuit of Example 1 is applied to a GaN half-bridge drive system, such as... Figure 2 As shown, it consists of three main parts: a dead-time module, a level-shifting module, and an output buffer (B). H and B L The input signal, along with the GaN power transistor module, passes through a dead-time module to insert a dead-time, then is divided into two voltage domains by a level shifting circuit, and finally passes through a buffer (B) H and B L These drive the upper and lower GaN transistors respectively. When the upper GaN transistor switches from on to off, due to the freewheeling effect of the load inductor, V... SW The node voltage continues to drop. At this point, if the dead time is too short, less than the actual value required for soft-switching operation, switching losses will reduce system efficiency. If the dead time is too long, the switching node voltage V... SW If the current is lower than expected, it will cause reverse conduction losses in the power device. Because gallium nitride power devices do not have parasitic diodes, their reverse conduction losses during freewheeling are much greater than those of silicon-based power devices.

[0034] In this embodiment, a negative pressure detection circuit and a negative pressure control circuit are added. When V SW When the voltage becomes negative, the body diode of NLD1 conducts, the freewheeling current forms a path, and clamps the bias voltage VC to V. SW +VD (VD represents the forward voltage drop of the body diode); when V SW When operating at high or positive voltage levels, this circuit effectively isolates the high-voltage and low-voltage domains, thus protecting the bias circuit and comparator circuit. At this time, signal VDH controls the conduction state of switch RS, and VDM synchronously follows VDH. Subsequently, the output VNC of the RS flip-flop generates a rising edge, discharging capacitor Cp and causing the NAND gate output to go high, thereby driving VZC to a fixed bias voltage. VDM then becomes a short-time pulse signal, its pulse width determined by the falling edges of VNL and VDH. The RS flip-flop then flips, generating a falling edge at VNC, beginning the charging of capacitor Cp, and VZC generates a corresponding pulse. The pulse width of VZC is determined by the duration of the VDM pulse and the capacitance of Cp, and can dynamically follow the changes in the pulse width of VDM. Without a negative voltage detection circuit and a negative voltage control circuit, the circuit waveform would be as follows: Figure 3As shown. Negative voltage does not affect the output waveform, but the excessively long dead time may lead to severe negative conduction losses. With the addition of a negative voltage detection circuit and a negative voltage control circuit, the waveform becomes as follows. Figure 4 As shown, when negative pressure occurs, the output dead time is truncated, the dead time is reduced, and the loss is reduced. Figure 5 The circuit waveforms are shown under different load conditions.

[0035] In summary, the circuit of this invention incorporates a negative voltage detection circuit and a negative voltage control circuit, which can effectively adjust the dead time when a negative voltage occurs in the circuit, reducing the impact of the negative voltage and minimizing circuit operating losses. It is effectively compatible with high-speed gallium nitride gate driver chips.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A highly stable adjustable dead-time drive circuit for GaN gate drive chips, comprising first PMOS transistors MP1 to MP5, first NMOS transistors MN1 to MN6, eleventh NMOS transistors MN11 to thirteenth NMOS transistors MN13, first resistors R1 to R3, first RS flip-flop RS1, first capacitors C1 to C3, first inverters INV1 to INV3, first AND gates AND1 to AND gates AND2, first D flip-flop D1, and a delay unit DELAY; The source of the first NMOS transistor MN1 is grounded, and its gate and drain are shorted and then connected to the input detection current I. d The sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are grounded, and their gates are connected to the gates of the first NMOS transistor MN1 and the eleventh NMOS transistor MN11, respectively. Their drains are connected to the drain of the first PMOS transistor MP1 and one end of the first resistor R1, respectively. The source of the fourth NMOS transistor MN4 is connected to the drain of the eleventh NMOS transistor MN11, its gate is connected to the output of the first inverter INV1, and its drain is connected to the drain of the second PMOS transistor MP2. The source of the fifth NMOS transistor MN5 is connected to one end of the second resistor R2, and its gate is connected to the source of the fourth NMOS transistor MN4. The source of the thirteenth NMOS transistor MN13, i.e., node VA, is connected to the drain of the third PMOS transistor MP3; the sources of the sixth NMOS transistor MN6 and the eleventh NMOS transistor MN11 are both grounded, their gates are connected to the output of the first AND gate AND1, and their drains are connected to the drain of the fifth PMOS transistor MP5; the source of the twelfth NMOS transistor MN12 is connected to one end of the third capacitor C3, its gate is connected to the current comparison detection signal VC1, and its drain is connected to one end of the second capacitor and one input of the second AND gate AND2; the drain of the thirteenth NMOS transistor MN13 is connected to the power supply VDD; The source of the first PMOS transistor MP1 is connected to the power supply VDD, and its gate and drain are shorted and then connected to the drain of the second NMOS transistor MN2; the source of the second PMOS transistor MP2 is connected to the power supply VDD, its gate is connected to the gate of the first PMOS transistor MP1, and its drain is connected to the drain of the fourth NMOS transistor MN4; the source of the third PMOS transistor MP3 is connected to the power supply VDD, and its gate and drain are shorted and then connected to the drain of the fifth NMOS transistor MN5; the source of the fourth PMOS transistor MP4 is connected to the power supply VDD, its gate is connected to the gate of the third PMOS transistor MP3, and its drain is connected to the source of the fifth PMOS transistor MP5; the gate of the fifth PMOS transistor MP5 is connected to the output of the first AND gate AND1, and its drain is connected to the drain of the sixth NMOS transistor MN6; One end of the first resistor R1 is connected to the power supply VIN, and the other end is connected to the drain of the third NMOS transistor MN3; one end of the second resistor R2 is connected to the source of the fifth NMOS transistor MN5, and the other end is grounded; one end of the third resistor R3 is connected to the power supply VDD, and the other end is connected to the other input terminal of the second AND gate AND2. The input of the first inverter INV1 is connected to the output of the delay timer DELAY, i.e., the VDM node, and the output is connected to the gate of the fourth NMOS transistor MN4; the input of the second inverter INV2 is connected to the output of the first RS flip-flop RS1, and the output is connected to one input of the first AND gate AND1; the input of the third inverter INV3 is connected to the input pulse VDH, and the output is connected to the other input of the first AND gate AND1. The D input of the first D flip-flop D1 is connected to the power supply VDD, the CLK input is connected to the pulse signal VGL, the CLR input is connected to the pulse signal VGH, and the output is connected to the input of the delay unit DELAY. One end of the first capacitor C1 is connected to the gate of the fifth NMOS transistor MN5, and the other end is grounded; one end of the second capacitor C2 is connected to one input of the second AND gate AND2, and the other end is grounded; the other end of the fourth capacitor C3 is grounded. The output of the second AND gate AND2 outputs a signal. Its features are, The circuit also includes a negative pressure detection circuit and a negative pressure control circuit; the R input terminal of the first RS flip-flop RS1 is connected to the negative pressure detection circuit and the negative pressure control circuit, and the S input terminal is connected to the input pulse signal VDH; The negative pressure detection circuit is used to detect the negative pressure detection node V in the GaN driving circuit. SW The generated negative voltage outputs a detection signal VNL; three pulse signals VGL, VGH, and VDH are used as inputs for analog control signals; current I... d Used to simulate the current detected in a GaN driving circuit; power supply VIN is used to simulate the voltage detected in a GaN driving circuit, with negative voltage detection node V. SW Used to simulate negative voltage in GaN driving circuits; the negative voltage control circuit is used to convert the detection signal VNL output by the negative voltage detection circuit into a control signal VZC.

2. The highly stable adjustable dead-time driving circuit for GaN gate driver chips according to claim 1, characterized in that, The negative voltage detection circuit includes the sixth PMOS transistor MP6 to the seventh PMOS transistor MP7, the seventh NMOS transistor MN7 to the eighth NMOS transistor MN8, the first NLDMOS transistor NLD1, the fifth inverter INV4, and the comparator CMOP; The gate and source of the first NLDMOS transistor NLD1 are connected to the drain of the eighth NMOS transistor MN8, and its drain is connected to the negative voltage detection node V. SW ; The source of the seventh NMOS transistor MN7 is grounded, and the source of the eighth NMOS transistor MN8 is grounded. Both its gate and drain are connected to the gate of the eighth NMOS transistor MN8 and the fixed current source I. B Connection; Current I B Used to simulate the current detected in the GaN drive path; the drain of the eighth NMOS transistor MN8 is connected to the drain of the sixth PMOS transistor MP6 and the drain of the seventh PMOS transistor MP7. The sources of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the power supply VDD, and their gates are connected to the drain of the eighth NMOS transistor MN8 and the power supply VDD, respectively. Their drains are connected to the drain of the eighth NMOS transistor MN8 and the positive input terminal of the comparator CMOP. The input of the fifth inverter INV5 is connected to the output of the comparator CMOP, and the output is connected to the upper input R of the second RS flip-flop RS2 and the R input of the first RS flip-flop RS1 in the negative voltage control circuit. The negative input terminal of the comparator CMOP is grounded.

3. The highly stable adjustable dead-time driving circuit for GaN gate driver chips according to claim 2, characterized in that, The negative voltage control circuit includes the eighth PMOS transistor MP8 to the tenth PMOS transistor MP10; the eighth NMOS transistor MN8 to the tenth NMOS transistor MN10; the fourth resistor R4 to the fifth resistor R5; the second RS flip-flop RS2; the fourth capacitor C4; the fourth inverter INV4; the sixth inverter INV6 to the seventh inverter INV7; and the NAND gate. The source of the tenth NMOS transistor MN10 is grounded; the source of the ninth NMOS transistor MN9 is grounded, its gate is connected to the output of the seventh inverter INV7, and its drain is connected to the drain of the eighth PMOS transistor MP8; the gate and drain of the tenth NMOS transistor MN10 are both connected to the drain of the tenth PMOS transistor MP10. The source of the eighth PMOS transistor MP8 is connected to the power supply VDD, its gate is connected to the output of the seventh inverter INV7 and one input of the NAND gate, and its drain is connected to the drain of the ninth NMOS transistor MN9; the source of the ninth PMOS transistor MP9 is connected to the power supply VDD, its gate is connected to the gate of the tenth PMOS transistor MP10, and its drain is connected to one end of the fifth resistor R5; the source of the tenth PMOS transistor MP10 is connected to the power supply VDD. One end of the fourth resistor R4 is connected to one end of the fourth capacitor C4 and the other input terminal of the NAND gate, and the other end is connected to the drain of the ninth NMOS transistor MN9; the other end of the fifth resistor R5 is connected to the output terminal of the fourth inverter INV4; the other end of the fourth capacitor C4 is grounded. The input of the fourth inverter INV4 is connected to the output of the NAND gate; the input of the sixth inverter INV6 is connected to the output of the first AND gate AND1, i.e., the VDM node, and the output is connected to the S input of the second RS flip-flop RS2; the input of the seventh inverter INV7 is connected to the output of the second RS flip-flop RS2, and the output is connected to the gate of the ninth NMOS transistor MN9. The R input terminal of the second RS flip-flop is connected to the output terminal of the fifth inverter INV5 of the negative voltage detection circuit and the R input terminal of the first RS flip-flop RS1.

4. The highly stable adjustable dead-time driving circuit for GaN gate driver chips according to any one of claims 1 to 3, characterized in that, The circuit also includes a dead-time main control circuit, which adjusts the power supply voltage VIN and current I based on the dead-time main control circuit. d And the control signal VZC dynamically outputs the dead time.

5. The highly stable adjustable dead-time driving circuit for GaN gate driver chips according to claim 3, characterized in that, When the detected voltage VIN is valid, the fourth NMOS transistor MN4 is controlled to pull down the voltage at node VA, increasing the dead time of the output; when the detected current I... d When effective, the second PMOS transistor MP2 is controlled to pull up the voltage of the VA node, thereby reducing the dead time of the output; When V SW When the node is under negative voltage, the first NLDMOS transistor NLD1 pulls down the voltage of node VC, controlling the negative voltage detection signal VNL output by the comparator CMOP to flip. When the negative voltage detection signal VNL is valid, the output of the second RS flip-flop RS2 outputs a rising edge, causing the output signal VNC of the seventh inverter INV7 to flip, charging the fourth resistor R4 and the fourth capacitor C4, causing the NAND gate to output a short pulse, and causing the VZC node to output a short pulse control signal.

6. The highly stable adjustable dead-time driving circuit for GaN gate driver chips according to claim 3, characterized in that, When the detection voltage VIN is valid, the fourth NMOS transistor MN4 and the eleventh NMOS transistor MN11 are turned on, pulling down the voltage at the upper end of the first capacitor C1, reducing the current in the path of the fifth NMOS transistor MN5, and thus reducing the current of the fourth PMOS transistor MP4. This slows down the charging speed at the upper end of the second capacitor C2, increasing the output dead time. When the detection current I... d When effective, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, which in turn turns on the first PMOS transistor MP1 and the second PMOS transistor MP2. The voltage at the upper end of the first capacitor C1 is pulled up by the fourth NMOS transistor MN4, which increases the current in the path of the fifth NMOS transistor MN5, and thus increases the current of the fourth PMOS transistor MP4. This speeds up the charging of the upper end of the second capacitor C2 and reduces the output dead time. When V SW When the node negative voltage is effective, the gate and source of the first LDMOS transistor NLD1 are shorted, causing its parasitic reverse diode to be clamped to the voltage across the conduction terminals, forcing the upper end of the eighth NMOS transistor MN8 to follow V. SW The voltage changes to a negative voltage, causing the voltage at the upper input terminal of comparator CMOP to be less than the voltage at the lower input terminal, resulting in a low-level output of the negative voltage detection signal VNL. When the negative voltage detection signal VNL is valid, a short pulse is simultaneously input to VDM, causing the second RS flip-flop RS2 to output a rising edge, which in turn enables the eighth PMOS transistor MP8 to charge the upper end of the fourth capacitor C4, controlling the NAND gate to output a short pulse signal, which in turn turns off the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10, causing the VZC node to output a short pulse and pull down the voltage at the upper end of the first capacitor C1, thus reducing the dead time of the output.

7. A GaN half-bridge driving system, comprising a GaN half-bridge circuit, characterized in that, It also includes any one of claims 1 to 3 for a highly stable adjustable dead-time drive circuit for GaN gate drive chips.

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