Frequency predictor and method of predicting an output frequency

Abstract

The present application provides a frequency predictor and a method for predicting an output frequency for adjusting an output frequency of a phase-locked loop (PLL) of an electronic system. The frequency predictor includes an intelligent unit for performing the following operations: referring to a correspondence between PLL frequencies and parameters, setting a parameter value of the PLL required by the phase-locked loop according to a target output frequency; referring to a correspondence between frequency deviation amounts and temperatures, adjusting the parameter value of the PLL according to a local temperature of the electronic system; referring to a correspondence between temperatures and load amounts, predicting a future temperature according to a load amount of at least one load source of the electronic system, and adjusting the parameter value of the PLL according to the future temperature, so that the phase-locked loop outputs a predicted frequency to reflect a load amount variation of the electronic system.

Description

Technical Field

[0001] This invention relates to an electronic system with a phase-locked loop, and more particularly to a frequency predictor and a method for predicting the output frequency for adjusting the output frequency of the phase-locked loop of the electronic system. Background Technology

[0002] A System-on-a-Chip (SoC) is a technology that integrates all the functional modules of an entire system onto a single chip. By embedding multiple functional components into a single chip, SoCs make electronic devices (such as smartphones, embedded systems, and wearable devices) lighter, more energy-efficient, and more powerful. The advantages of SoCs include reduced cost, smaller space requirements, and improved energy efficiency.

[0003] SoCs typically have an internally adjustable phase-locked loop (PLL). Although the target output frequency of the PLL can be pre-adjusted at the factory using a test bench, during actual operation after leaving the factory, the temperature of the electronic system may change due to different system loads, causing the target output frequency of the PLL to deviate. Some types of SoCs require stable and accurate clock frequencies to ensure correct functioning, such as the Baud rate of UART (Universal Asynchronous Receiver / Transmitter) and the eye pattern of USB (Universal Serial Bus).

[0004] SoCs often have fixed clock input sources, such as SPI (Serial Peripheral Interface) clock, eSPI (Enhanced Serial Peripheral Interface) clock, LPC (Low Pin Count) clock, Ethernet clock, etc. If the frequencies corresponding to the aforementioned clock input sources are known in advance, they can be provided to processing devices such as processors and controllers to verify the output frequency of the phase-locked loop (PLL) and continuously correct or learn, making the PLL's output frequency more stable and accurate. Summary of the Invention

[0005] In view of this, the present invention provides a frequency predictor and a method for predicting the output frequency, which predicts the future temperature of the electronic system by referring to the changes in the load source of the electronic system, and adjusts the parameters used to control the output frequency of the phase-locked loop in advance based on the future temperature, thereby making the output frequency of the phase-locked loop more stable and accurate.

[0006] A frequency predictor according to an embodiment of the present invention is used to adjust the output frequency of a phase-locked loop (PLL) of an electronic system. This frequency predictor includes an intelligent unit that performs the following operations: referring to a correspondence between PLL frequency and parameters, setting the required PLL parameter values ​​for the aforementioned PLL based on a target output frequency; referring to a correspondence between frequency deviation and temperature, adjusting the aforementioned PLL parameter values ​​based on the local temperature of the aforementioned electronic system; referring to a correspondence between temperature and load, predicting a future temperature based on the load of at least one load source of the aforementioned electronic system, and adjusting the aforementioned PLL parameter values ​​based on the future temperature, so that the aforementioned PLL outputs a predicted frequency to reflect changes in the load of the aforementioned electronic system.

[0007] In some embodiments, the aforementioned intelligent unit further performs the following: obtaining the frequency of at least one clock input source in the aforementioned electronic system as a first reference frequency; and verifying, based on the aforementioned first reference frequency, whether the aforementioned predicted frequency output by the aforementioned phase-locked loop based on the aforementioned PLL parameters conforms to the aforementioned target output frequency.

[0008] In some embodiments, the aforementioned intelligent unit further performs the following: generating the correspondence between the aforementioned temperature and load based on the load of the aforementioned electronic system from the past to the present and the local temperature.

[0009] In some embodiments, the aforementioned frequency predictor further includes: a database storing the correspondence between the aforementioned PLL frequency and parameters, the correspondence between the aforementioned frequency deviation and temperature, the aforementioned target output frequency, and the frequency of the aforementioned clock input source.

[0010] In some embodiments, the aforementioned intelligent unit further performs the following: reading the correspondence between the PLL frequency and parameters, and the correspondence between the frequency deviation and temperature from the aforementioned database; correcting the correspondence between the PLL frequency and parameters based on the aforementioned PLL parameters and the aforementioned predicted frequency; and correcting the correspondence between the frequency deviation and temperature based on the deviation between the aforementioned predicted frequency and the aforementioned target output frequency, and the aforementioned future temperature.

[0011] In some embodiments, the aforementioned smart unit receives the aforementioned local temperature from a temperature sensor of the aforementioned electronic system.

[0012] In some embodiments, a microcontroller unit of the aforementioned electronic system monitors the load of the aforementioned load source and transmits the data to the aforementioned intelligent unit.

[0013] In some embodiments, when the clock input source providing the aforementioned reference frequency stops outputting, the aforementioned intelligent unit uses the frequency of another clock input source of the aforementioned electronic system as a second reference frequency to verify the aforementioned predicted frequency.

[0014] In some embodiments, the aforementioned intelligent unit is a programmable device capable of loading programs to perform tasks of calculation, processing, and control.

[0015] A method for predicting output frequency according to another embodiment of the present invention is used to adjust the output frequency of a phase-locked loop (PLL) of an electronic system. This method includes the following steps: referencing a PLL frequency-parameter correspondence, setting the required PLL parameter values ​​for the aforementioned PLL based on a target output frequency; referencing a frequency deviation-temperature correspondence, adjusting the aforementioned PLL parameter values ​​based on the local temperature of the aforementioned electronic system; and referencing a temperature-load correspondence, predicting a future temperature based on the load of at least one load source of the aforementioned electronic system, and adjusting the aforementioned PLL parameter values ​​based on the future temperature, so that the aforementioned PLL outputs a predicted frequency to reflect changes in the load of the aforementioned electronic system.

[0016] In some embodiments, the aforementioned method for predicting the output frequency further includes: obtaining the frequency of at least one clock input source in the aforementioned electronic system as a first reference frequency; and verifying, based on the aforementioned first reference frequency, whether the aforementioned predicted frequency output by the aforementioned phase-locked loop based on the aforementioned PLL parameters conforms to the aforementioned target output frequency.

[0017] In some embodiments, the aforementioned method for predicting the output frequency further includes: generating the correspondence between the temperature and the load based on the load of the aforementioned electronic system from the past to the present and the local temperature.

[0018] In some embodiments, the aforementioned method for predicting the output frequency further includes: correcting the correspondence between the PLL frequency and the parameters based on the aforementioned PLL parameters and the aforementioned predicted frequency; and correcting the correspondence between the frequency deviation and the temperature based on the deviation between the aforementioned predicted frequency and the aforementioned target output frequency, and the aforementioned future temperature. Attached Figure Description

[0019] Figure 1 An example architecture diagram of an electronic system 10 with a phase-locked loop 101 is shown.

[0020] Figure 2 This diagram shows an example configuration of the frequency predictor 102 according to an embodiment of the present invention.

[0021] Symbol Explanation

[0022] 10: Electronic Systems

[0023] 101: Phase-locked loop (PLL)

[0024] 102: Frequency Predictor

[0025] 102a: Database

[0026] 102b: Intelligent Unit

[0027] 103: Microcontroller Unit (MCU)

[0028] 104: Internal Bus

[0029] 105a~105c: Pulse 1 counter to Pulse 3 counter

[0030] SP: Output clock of the phase-locked loop

[0031] S1: eSPI or LPC clock signal source

[0032] S2: SPI clock signal source

[0033] S3: EMAC clock signal source

[0034] LT: Local temperature

[0035] RT: PLL Reference Data Sheet

[0036] TF: Target output frequency

[0037] f1~f3: The set frequencies of S1~S3

[0038] PC: Program Count

[0039] HR: Cache hit rate

[0040] HG: Allowed host instruction set

[0041] DI: Interruption demand of the device

[0042] FP: Curve showing the relationship between frequency and PLL parameters

[0043] ΔF-T: Curve showing the relationship between deviation and temperature

[0044] T-L1: Relationship between temperature and program counter (PC)

[0045] T-L2: Relationship between temperature and hit rate (HR)

[0046] T-L3: Relationship curve between temperature and allowed host instruction quantity (HG)

[0047] T-L4: Relationship between temperature and device interruption demand (DI) curve Detailed Implementation

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings.

[0049] The frequency predictor of the present invention performs a method for predicting the output frequency, which is used to adjust the output frequency of a phase-locked loop (hereinafter referred to as PLL) in an electronic system.

[0050] Figure 1 An example architecture diagram of an electronic system 10 with a phase-locked loop 101 is shown. In this electronic system 10, a method for predicting the output frequency is performed by a frequency predictor 102, thereby adjusting the output frequency of the phase-locked loop 101 in the electronic system 10.

[0051] Figure 1 In the electronic system 10, for example but not limited to, phase-locked loop 101, frequency predictor 102, and micro-controller unit (MCU) 103.

[0052] The microcontroller unit 103 is connected to multiple clock signal sources. Here, for example, but not limited to, the multiple clock signal sources include the eSPI / LPC clock, the SPI clock, and the EMAC (Ethernet Media Access Control) clock. In addition, the microcontroller unit 103 also receives the output clock (frequency) SP of the phase-locked loop 101.

[0053] The microcontroller unit 103 executes its pre-assigned operations according to the aforementioned eSPI / LPC clock, SPI clock, and EMAC clock. During operation, the microcontroller unit 103 simultaneously monitors the load levels (load status) corresponding to multiple load sources of the electronic system 10. These load sources include, for example, the program count (PC), cache hit rate (HR), host grant (HG), and device interrupt request (DI), but are not limited to these. These load sources (PC, HR, HG, DI) are related to the operational busyness of the electronic system 10, and each, in combination, may affect the local temperature (LT) of the electronic system 10. The microcontroller unit 103 transmits the load levels (L1~L4) of the aforementioned load sources (program count PC, cache hit rate HR, host grant (HG), and device interrupt request (DI)) to the frequency predictor 102.

[0054] The frequency predictor 102 receives the local temperature LT, PLL reference data table RT, target output frequency TF of the phase-locked loop 101, and set frequencies f1 to fN of one or more (first to Nth) clock signal sources (S1 to SN) from the electronic system 10. Figure 1 For simplicity, N=3 is assumed, but it is not limited to this. Furthermore, the first clock signal source S1 to the third clock signal source S3 are, for example, the aforementioned eSPI / LPC clock, SPI clock, and EMAC clock, respectively. In this embodiment, the electronic system 10, for example, has a temperature sensor (not shown) that obtains the local temperature LT of the electronic system 10 and transmits it to the frequency predictor 102. Moreover, the PLL reference data table RT, the target output frequency TF, and the set frequencies f1~f3 of the first clock signal source S1 to the third clock signal source S3 can, for example, be transmitted by the microcontroller unit 103 to the frequency predictor 102 via the internal bus 104 of the electronic system 10.

[0055] Furthermore, the electronic system 10 has three (N) pulse counters to count the number of periodic pulses of the aforementioned first to Nth clock signal sources S1 to SN, respectively. In this embodiment, N equals 3, and the electronic system 10 has a first pulse counter 105a to a third pulse counter 105c. The first pulse counter 105a to the third pulse counter 105c receive the first clock signal source S1 (eSPI / LPC clock), the second clock signal source S2 (SPI clock), and the third clock signal source S1 (EMAC clock), respectively, to obtain the number of pulses in each cycle. In addition, the first pulse counter 105a to the third pulse counter 105c receive the output clock SP of the phase-locked loop 101 and obtain the number of pulses in each cycle of the output clock SP of the phase-locked loop 101. In addition, the frequency predictor 102 also receives the output clock SP of the phase-locked loop 101.

[0056] Figure 2 This diagram shows an example configuration of the frequency predictor 102 according to an embodiment of the present invention. Hereinafter, reference will be made to... Figure 2 Explain how the frequency predictor 102 works.

[0057] like Figure 2As shown, the frequency predictor 102 is equipped with a database 102a and an intelligence unit 102b. Database 102a stores the PLL reference data table RT received by the frequency predictor 102, the target output frequency TF of the phase-locked loop 101, and the set frequencies f1~f3 of the first clock signal source S1 to the third clock signal source S3. Based on the PLL reference data table RT, the intelligence unit 102b can further organize the correspondence between PLL frequencies and parameters (FP), which can be recorded using lookup tables, relationship curves, or formulas. Here, as... Figure 2 The diagram shows the relationship between frequency and PLL parameters (FP), but it is not limited to this. The intelligent unit 102b can use this correspondence between PLL frequency and parameters (FP) to set the parameters required for the phase-locked loop 101 according to the target output frequency RT.

[0058] Database 102a also stores the correspondence between frequency deviation and temperature (DT), which can be recorded using reference tables, relationship curves, or formulas. Here, for example... Figure 2 The diagram shows the relationship between frequency deviation and temperature (ΔF-T). Based on this frequency deviation-temperature relationship (DT) and the local temperature (LT) of the electronic system 10, the intelligent unit 102b can determine the frequency deviation (ΔF) between the output frequency of the phase-locked loop 101 affected by temperature and the target output frequency (TF). It should be noted that the data for this frequency deviation-temperature relationship (DT) can be obtained through actual measurement by the manufacturer, for example, by recording the deviation between the actual output frequency and the target output frequency and their corresponding relationship when the phase-locked loop operates at different temperatures. In the operation described below, the intelligent unit 102b can continuously correct this frequency deviation-temperature relationship (DT) based on changes in the local temperature (LT) and the actual frequency output of the phase-locked loop 101.

[0059] In some embodiments of the present invention, the intelligent unit 102b, for example but not limited to, is a programmable device that includes computing power and control logic and can be loaded with a program to perform tasks of calculation, processing, and control. In this embodiment, the intelligent unit 102b may be implemented, for example, by a microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), and embedded device, but is not limited thereto.

[0060] In some embodiments, the intelligent unit 102b loads a program to execute a method for predicting the output frequency, thereby adjusting the output clock SP of the phase-locked loop 101 of the electronic system 10. Specifically, the intelligent unit 102b performs the following operations.

[0061] The intelligent unit 102b refers to the correspondence between PLL frequency and parameters FP and sets the required PLL parameter value PV for the phase-locked loop 101 according to the target output frequency TF. For example, if the target output frequency TF received by the intelligent unit 102b is 20MHz, it refers to the correspondence between PLL frequency and parameters FP, finds the PLL parameter value PV (e.g., a value represented by multiple bits) corresponding to this target output frequency, and outputs it to the phase-locked loop 101.

[0062] The intelligent unit 102b further adjusts the PLL parameter value PV based on the correspondence between frequency deviation and temperature DT, and the local temperature LT of the received electronic system 10. Since the local temperature LT affects the output clock SP of the phase-locked loop 101, the intelligent unit 102b further adjusts the required PLL parameter value PV of the phase-locked loop 101 based on the local temperature LT. More specifically, the intelligent unit 102b obtains the frequency deviation (ΔF) caused by the local temperature LT based on the correspondence between frequency deviation and temperature DT, and uses the frequency deviation (ΔF) in conjunction with the PLL reference data table RT to further adjust the required PLL parameter value PV of the phase-locked loop 101.

[0063] Frequency predictor 102 receives load data (L1-L4) from different load sources (program counter PC, cache hit rate HR, allowed master instruction count HG, and device interrupt demand DI) from microcontroller unit 103. Frequency predictor 102 can generate corresponding formulas or curves based on temperature and load values ​​L1-L4. Figure 2 In this context, the frequency predictor 102 generates, for example, curves of temperature relative to the program counter PC, cache hit rate HR, allowed host instruction quantity HG, and device interrupt demand DI, namely, curves T-L1, T-L2, T-L3, and T-L4. Furthermore, formulas or curves (temperature-load correspondence) based on previously experimented and recorded past local temperatures and past loads of load sources (load data) can be provided to the intelligent unit 102b as initial values.

[0064] Thus, when the load of the load sources of electronic system 10 (program counter PC, cache hit rate HR, allowed host instruction quantity HG, or device interrupt demand quantity DI) increases or decreases, the intelligent unit 102b can use a formula or curve corresponding to a single load source and temperature (e.g., the T-L1 curve), or a combination of formulas or curves corresponding to multiple load sources and temperature (e.g., T-L1 to T-L4 curves), to predict the temperature change caused by the load change, thereby predicting a future temperature. The intelligent unit 102b, using this future temperature and the aforementioned frequency deviation-temperature correspondence DT, adjusts the PLL parameter value PV to be set for the phase-locked loop 101 in advance, causing the phase-locked loop 101 to output a predicted frequency to reflect the load change of electronic system 10. Therefore, even if the local temperature LT changes in the future due to the load change of electronic system 10, the frequency generated by the phase-locked loop 101 will tend to be stable and accurate because the intelligent unit 102b has already adjusted the PLL parameter value PV for the phase-locked loop 101 in advance. Here, the combined use of formulas or curves corresponding to multiple load sources and temperatures represents various calculation combinations of the correlation terms of multiple temperature-corresponding load quantities, such as linear combinations of T-L1, T-L2, T-L3, and T-L4 curves, but is not limited to this.

[0065] Reference Figure 1 and Figure 2 The first pulse counter 105a, the second pulse counter 105b, and the third pulse counter 105c count the number of pulses in each cycle of the eSPI / LPC clock signal source (S1), the SPI clock signal source (S2), and the EMAC clock signal source (S3), respectively. The first pulse counter 105a, the second pulse counter 105b, and the third pulse counter 105c also count the pulses of the clock SP output from the phase-locked loop 101 to obtain the number of pulses in each cycle. The first pulse counter 105a, the second pulse counter 105b, and the third pulse counter 105c output the aforementioned pulse counting results to the intelligent unit 102b.

[0066] Subsequently, the intelligent unit 102b reads the target output frequency TF from the database 102a, and the frequency of the eSPI / LPC clock signal source (S1), SPI clock signal source (S2), or EMAC clock signal source (S3). It then compares, for example, the ratio of the frequency of the SPI clock signal source to the target output frequency TF, and the ratio of the pulse count value of the SPI clock signal source (S1) to the pulse count value of the output clock (SP) of the phase-locked loop 101, to verify whether the output frequency of the phase-locked loop 101 is correct.

[0067] Since the pulse counting results of the first to third pulse counters (105a~105c) require time to process (e.g., one clock cycle), the pulse counting results can be provided to the intelligent unit 102b to verify the frequency results output by the phase-locked loop 101 in the past (also known as past frequency results). The intelligent unit 102b can use this past frequency result to verify whether the parameters previously given to the phase-locked loop 101 were correct, and thus correct the correspondence between PLL frequency and parameters FP in the database 102a. Similarly, the intelligent unit 102b can use this past frequency result to verify whether the frequency offset when the temperature changes is correct, and thus correct the correspondence between frequency deviation and temperature DT in the database 102a.

[0068] Typically, the results from multiple clock input sources (eSPI / LPC, SPI, EMAC) S1~S3, after being counted by a pulse counter, can be provided to the intelligent unit 102b for verification. However, if a non-constantly input clock source, such as eSPI_CLK (the clock input source of the eSPI bus), is used for verification, the intelligent unit 102b will dynamically adjust whether to include this input source for verification. Assuming it has been included for verification, when the clock input source (eSPI_CLK) stops inputting, the intelligent unit 102b will receive a significantly abnormal pulse counter result. The intelligent unit 102b will then refer to the pulse count results of other clock input sources, such as clock signal sources S1, S2, or S3, and exclude the count result of the eSPI_CLK clock input source. When the eSPI_CLK clock input source resumes inputting, the intelligent unit 102b will receive a more reasonable result and will then include the pulse count result of this clock input source in the verification process again.

[0069] As described above, the intelligent unit 102b can correct the correspondence between frequency deviation and temperature DT in the database 102a. Therefore, the intelligent unit 102b can modify or learn the formula or curve (e.g., T-L1, T-L2, T-L3, and T-L4) corresponding to the load of the load source based on the current local temperature LT, past local temperatures, and load changes, making the temperature prediction more accurate when the load of the load source changes. Since the intelligent unit 102b can continuously improve the accuracy of temperature prediction when the load changes, when adjusting the PLL parameter value PV of the phase-locked loop 101 in response to load and temperature changes, it can adjust the parameters to better match the future temperature of the electronic system 10, making the frequency generated by the phase-locked loop 101 more stable and accurate.

[0070] Based on the content disclosed in this invention, it has the following features.

[0071] (1) The intelligent unit in the frequency predictor of the present invention can refer to the changes of various load sources of the electronic system to predict the future temperature of the electronic system and pre-adjust the PLL parameter values ​​to be provided to the phase-locked loop so that the frequency generated by the phase-locked loop tends to be stable and accurate.

[0072] (2) The frequency predictor of the present invention uses a pulse counter to count the output clock of the phase-locked loop and various clock input sources, and then feeds it back to the intelligent unit to verify and correct the data in the database.

[0073] (3) The frequency predictor of the present invention can also use the intelligent unit to determine whether the input source should be included in the verification for non-fixed continuous input clock input sources.

[0074] (4) The intelligent unit in the frequency predictor of the present invention will improve and learn the formula or curve of temperature corresponding to load source load based on the current local temperature, past local temperature, and load changes, so that the temperature prediction can be more accurate, thereby improving the parameter adjustment and making the frequency generated by PLL more stable and accurate.

[0075] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A frequency predictor, characterized in that, For adjusting the output frequency of a phase-locked loop (PLL) of an electronic system, including: One intelligent unit performs the following operations: Referring to the correspondence between PLL frequency and parameters, the PLL parameter values ​​required for the aforementioned phase-locked loop are set according to a target output frequency; Referring to the correlation between frequency deviation and temperature, the PLL parameter values ​​are adjusted according to the local temperature of the aforementioned electronic system. Referring to the relationship between temperature and load, a future temperature is predicted based on the load of at least one load source of the aforementioned electronic system, and the PLL parameter value is adjusted based on the future temperature so that the aforementioned phase-locked loop outputs a predicted frequency to reflect the load changes of the aforementioned electronic system.

2. The frequency predictor as described in claim 1, characterized in that, The aforementioned intelligent unit further executes: The frequency of at least one clock input source in the aforementioned electronic system is obtained as a first reference frequency; and Based on the aforementioned first reference frequency, verify whether the aforementioned predicted frequency output by the aforementioned phase-locked loop based on the aforementioned PLL parameters conforms to the aforementioned target output frequency.

3. The frequency predictor as described in claim 2, characterized in that, The aforementioned intelligent unit further executes: Based on the load of the aforementioned electronic system from the past to the present and the local temperature, the aforementioned correspondence between temperature and load is generated.

4. The frequency predictor as described in claim 2, characterized in that, Including: A database stores the correspondence between the aforementioned PLL frequency and parameters, the correspondence between the aforementioned frequency deviation and temperature, the aforementioned target output frequency, and the frequency of the aforementioned clock input source.

5. The frequency predictor as described in claim 4, characterized in that, The aforementioned intelligent unit further executes: Read the correspondence between the PLL frequency and parameters, and the correspondence between the frequency deviation and temperature from the aforementioned database; Based on the aforementioned PLL parameters and the aforementioned prediction frequency, the correspondence between the aforementioned PLL frequency and parameters is corrected; as well as Based on the deviation between the predicted frequency and the target output frequency, and the future temperature, the correspondence between the frequency deviation and the temperature is corrected.

6. The frequency predictor as claimed in claim 1, characterized in that, The aforementioned intelligent unit receives the aforementioned local temperature from a temperature sensor of the aforementioned electronic system.

7. The frequency predictor as described in claim 6, characterized in that, A microcontroller unit of the aforementioned electronic system monitors the load of the aforementioned load source and transmits the data to the aforementioned intelligent unit.

8. The frequency predictor as described in claim 2, characterized in that, When the clock input source providing the aforementioned reference frequency stops outputting, the aforementioned intelligent unit uses the frequency of another clock input source of the aforementioned electronic system as a second reference frequency to verify the aforementioned predicted frequency.

9. The frequency predictor as claimed in claim 1, characterized in that, The aforementioned intelligent unit is a programmable device that can be loaded with programs to perform tasks of calculation, processing, and control.

10. A method for predicting output frequency, characterized in that, The method for adjusting the output frequency of a phase-locked loop (PLL) in an electronic system includes: Referring to the correspondence between PLL frequency and parameters, the PLL parameter values ​​required for the aforementioned phase-locked loop are set according to a target output frequency; Referring to the correlation between frequency deviation and temperature, the PLL parameter values ​​are adjusted according to the local temperature of the aforementioned electronic system. Referring to the relationship between temperature and load, a future temperature is predicted based on the load of at least one load source of the aforementioned electronic system, and the PLL parameter value is adjusted based on the future temperature so that the aforementioned phase-locked loop outputs a predicted frequency to reflect the load changes of the aforementioned electronic system.

11. The method for predicting output frequency as described in claim 10, characterized in that, Including: The frequency of at least one clock input source in the aforementioned electronic system is obtained as a first reference frequency; and Based on the aforementioned first reference frequency, verify whether the aforementioned predicted frequency output by the aforementioned phase-locked loop based on the aforementioned PLL parameters conforms to the aforementioned target output frequency.

12. The method for predicting output frequency as described in claim 11, characterized in that, Including: Based on the load of the aforementioned electronic system from the past to the present and the local temperature, the aforementioned correspondence between temperature and load is generated.

13. The method for predicting output frequency as described in claim 11, characterized in that, Including: Based on the aforementioned PLL parameters and prediction frequencies, the correspondence between the aforementioned PLL frequencies and parameters is corrected; and Based on the deviation between the predicted frequency and the target output frequency, and the future temperature, the correspondence between the frequency deviation and the temperature is corrected.

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