A sub-harmonic injection-locked phase-locked loop applied to a wireless communication transceiver system

Abstract

The application discloses a sub-harmonic injection locking phase-locked loop applied to a wireless communication transceiver system, which comprises an injection time calibration circuit, a digital control delay chain and a narrow pulse generation circuit, wherein the injection time calibration circuit comprises a time amplifier, a time-to-digital converter connected with the time amplifier, a digital calibration circuit connected with the time-to-digital converter and a lock detection circuit connected with the digital calibration circuit, the digital calibration circuit comprises an injection phase error detection circuit, an optimal injection time selection circuit connected with the injection phase error detection circuit and a finite state machine connected with the optimal injection time selection circuit. The application can automatically calibrate the injection time of the sub-harmonic injection locking phase-locked loop quickly, and does not sacrifice the phase noise performance of the sub-harmonic injection locking phase-locked loop.

Description

Technical Field

[0001] This invention relates to the technical field of subharmonic injection locked phase-locked loops, and particularly to a subharmonic injection locked phase-locked loop applied to wireless communication transceiver systems. Background Technology

[0002] Subharmonically Injection-Locked Phase-Locked Loop (SILPLL) is a high-performance frequency synthesis circuit that can achieve excellent output phase noise performance under low power consumption conditions. With the continuous development of modern wireless communication technology, advanced communication systems have increasingly stringent requirements for the power consumption and output phase noise of frequency synthesis circuits, thus research on SILPLL is becoming increasingly popular.

[0003] Traditional SILPLL circuit architecture, such as Figure 1 As shown, it mainly consists of two parts: a phase-locked loop (PLL) and an injection path. The PLL comprises five main components: a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a multi-modulus divider (MMD). The high-frequency signal output from the VCO is divided by the MMD to obtain the low-frequency signal f. DIV PFD identification f DIV and reference signal f REF The frequency difference or phase difference between the two signals is used to output corresponding voltage signals UP and DOWN. The CP further converts the UP and DOWN voltage signals into current signals and outputs them to the LPF. The LPF then integrates and filters these signals to convert them into DC voltage V. CTRL Through V CTRL The VCO output is continuously adjusted until the phase-locked loop locks. The injection path consists of two parts: a digitally controlled delay line (DCDL) and a narrow pulse generation circuit, with the reference signal f... REF After passing through the DCDL and narrow pulse generation circuit, the injection signal f is generated. INJ Injected signal f INJImproving VCO output phase noise performance through injection locking technology. Since the phase-locked loop (PLL) and injection path of a SILPLL simultaneously regulate the VCO output phase, a phase mismatch between the two phase adjustment paths can cause the SILPLL to fail to lock. To avoid this problem, traditional SILPLLs typically use manual adjustment of the DCDL delay to align the phases of the PLL and injection paths. This calibration method has poor robustness and is difficult to apply in practical integrated circuit systems. Therefore, researching self-calibrating injection time SILPLLs is of great significance. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a subharmonic injection-locked phase-locked loop (SILPLL) for use in wireless communication transceiver systems, which can quickly and automatically calibrate the injection time of the SILPLL circuit without sacrificing the phase noise performance of the SILPLL. To achieve the above-mentioned objective and other advantages of the present invention, a subharmonic injection-locked phase-locked loop for use in wireless communication transceiver systems is provided, comprising:

[0005] An injection time calibration circuit is provided, comprising a time amplifier, a time-to-digital converter connected to the time amplifier, a digital calibration circuit connected to the time-to-digital converter, a lock detection circuit, a DCDL circuit, and a narrow pulse generation circuit connected to the digital calibration circuit.

[0006] The digital calibration circuit includes an injection phase error detection circuit, an optimal injection time selection circuit connected to the injection phase error detection circuit, and a finite machine state connected to the optimal injection time selection circuit.

[0007] The locking detection circuit is used to detect the locking status of the phase-locked loop.

[0008] Preferably, the injected phase error detection circuit includes an adder ADD1 and a trigger DFF1, and the injected phase error detection circuit is used to detect the magnitude and polarity of the difference between the current output and the target output of the time-to-digital converter in the calibration loop.

[0009] Preferably, when the phase-locked loop is locked, the lock flag bit DLD_OUT of the lock detection circuit will change from low to high, and the phase error detection circuit will read the output value N of the time-to-digital converter at this time through the trigger DFF1. TDC And use it as the calibration target value N TARGETOnce calibration begins, adder ADD1 will continuously output the current N. TDC With the target value N TARGET The size of the difference N error And the polarity SIGN, so that the optimal injection time selection circuit can make a determination.

[0010] Preferably, the finite state machine is used to generate control signals for the digital calibration circuit; when the main loop is locked, DLD_OUT is pulled high, and the finite state machine will sample DLD_OUT twice to ensure that the sampling result is correct.

[0011] After injection enable ENP_INJ is turned off, the phase difference detection flag P must be set immediately. flag The signal is pulled high, and then the optimal injection time selection circuit performs a state transition and completes the selection and output of the optimal control word through the successive comparison logic circuit.

[0012] Preferably, the optimal injection time selection circuit is used to select and output the optimal DCDL control codeword, and the optimal injection time selection circuit includes a successive comparison logic search circuit, a minimum error control word search circuit, and an optimal control word selection circuit. The successive comparison logic search circuit compares the DCDL control word from high to low according to the sign bit SIGN output by the accumulator, and then finds the optimal injection time control word according to the binary search algorithm.

[0013] Compared with the prior art, the beneficial effects of this invention are: the SILPLL circuit proposed in this invention can achieve automatic calibration of injection time without sacrificing noise performance, thereby significantly improving the robustness of SILPLL.

[0014] The SILPLL proposed in this invention has a total calibration time of 36.9μs at a clock frequency of 249.6MHz, and the phase difference between the injection path and the phase-locked loop path of the SILPLL after calibration is less than 0.8ps. Attached Figure Description

[0015] Figure 1 A schematic diagram of the conventional structure of the subharmonic injection locked phase-locked loop applied to a wireless communication transceiver system according to the present invention;

[0016] Figure 2 This is a schematic diagram of the subharmonic injection locked phase-locked loop (PLL) applied to a wireless communication transceiver system according to the present invention.

[0017] Figure 3 A schematic diagram of the locking detection circuit structure of the subharmonic injection locked phase-locked loop applied to a wireless communication transceiver system according to the present invention;

[0018] Figure 4A schematic diagram of the digital calibration circuit structure of the subharmonic injection phase-locked loop applied to a wireless communication transceiver system according to the present invention;

[0019] Figure 5 The present invention provides a phase difference detection circuit for a subharmonic injection-locked phase-locked loop applied to a wireless communication transceiver system;

[0020] Figure 6 The timing diagram of the finite state machine for a subharmonic injection phase-locked loop applied to a wireless communication transceiver system according to the present invention;

[0021] Figure 7 A schematic diagram of the binary search algorithm for subharmonic injection-locked phase-locked loop applied to a wireless communication transceiver system according to the present invention;

[0022] Figure 8 The present invention provides a flowchart of the digital calibration circuit for a subharmonic injection locked phase-locked loop applied to a wireless communication transceiver system. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Reference Figure 2 A subharmonic injection-locked phase-locked loop (PLL) for use in wireless communication transceiver systems, comprising:

[0025] An injection time calibration circuit is included, comprising a time amplifier, a time-to-digital converter connected to the time amplifier, a digital calibration circuit connected to the time-to-digital converter, a lock detection circuit, a DCDL circuit, and a narrow pulse generation circuit connected to the digital calibration circuit; a reference signal f REF With MMD output f DIV Connect the PFD to its input terminal. The UP and DOWN signals output by the PFD are connected to the input terminal of the CP. The output of the CP is connected to the input terminal of the LPF. The output of the LPF is V. CTRL Connected to the VCO input, the VCO output f VCO Connecting to the input of the MMD, the above circuit collectively constitutes a SILPLL phase-locked loop. Additionally, the UP and DOWN signals output by the PFD, and the V signal output by the LPF... CTRL Together with the output ENP_DLD of the digital calibration circuit, they form the input of the lock detection circuit, with the reference signal f REFWith MMD output f DIV Connect to the input of the time amplifier; the output of the time amplifier is directly connected to the input of the time-to-digital converter; the reference signal f. REF The 6-bit digital signal TDC_CODE<5:0> output by the time-to-digital converter and the output DLD_OUT of the lock detection circuit together constitute the input of the digital calibration circuit. The 8-bit digital output DCDL_CODE<7:0> of the digital calibration circuit and the reference signal f REF The input terminal of DCDL is connected, the output of DCDL and the output of the digital calibration circuit ENP_INJ are connected to the input terminal of the narrow pulse generation circuit, and the output of the narrow pulse generation circuit f is connected to the input terminal of the narrow pulse generation circuit. INJ Connected to the VCO input, the above circuitry constitutes the injection time calibration circuit for SILPLL.

[0026] Furthermore, during initial operation, SILPLL only opens the phase-locked loop (PLL), while its injection time calibration circuit remains closed. At this time, SILPLL will not perform injection locking. After the PLL completes locking, the output DLD_OUT of the lock detection circuit goes high. Once DLD_OUT is high, the SILPLL calibration loop opens and begins operation. The injection time calibration circuit first reads the current time-to-digital converter's output codeword and places it in a register. Then, it uses this value as the calibration target for injection time calibration. During calibration, SILPLL's digital calibration circuit sets its output ENP_DLD low, disabling the lock detection circuit to prevent interference with calibration. Subsequently, the digital calibration circuit enables the narrow pulse generator's enable signal ENP_INJ for one reference period to inject into the VCO. Due to a phase mismatch between the injection path and the PLL, the output f after VCO injection will... VCO A phase shift will occur, and this phase shift will appear at f after MMD frequency division. DIV This leads to the reference signal f REF With MMD output f DIVWhen a phase deviation occurs, the time amplifier in the injection time calibration circuit amplifies this phase deviation and outputs it to the time-to-digital converter (TD-SCDMA). The TD-SCDMA quantizes the amplified phase difference and outputs it to the digital calibration circuit. The digital calibration circuit compares the current input of the TD-SCDMA with the calibration target stored in the previous register and adjusts the control word DCDL_CODE<7:0> based on the comparison result. Since DCDL has an 8-bit control word, to ensure calibration accuracy, the digital calibration circuit uses a binary search algorithm to traverse all the codewords used in DCDL and records the corresponding error values. After the traversal is complete, the codeword corresponding to the minimum error value is selected for output. For an 8-bit DCDL control array, a total of 9 rounds of loop traversal are required to complete the calibration. After calibration, the outputs ENP_DLD and ENP_INJ of the digital calibration circuit will remain high, and the phase-locked loop and the injection lock of the injection path will operate simultaneously.

[0027] Furthermore, such as Figure 3 As shown, the connection relationship of the lock detection circuit is as follows:

[0028] Reference voltage upper limit V MAX and LPF output V CTRL Connected to the input of comparator A1, the reference voltage lower limit V MIN and LPF output V CTRL The inputs of comparators A1 and A2 are connected to the AND gate input, and the AND gate output LRD is connected to the counter input. The UP and DOWN signals output from the PFD are connected to the input of the phase difference detection circuit, and the PEC output of the phase difference detection circuit is connected to the counter input. The UP signal output from the PFD, the output signal ENP_DLD of the digital calibration circuit, and the counter's count setting value LD_Counter<10:0> are connected to the counter input, and the counter output DLD_OUT is connected to the digital calibration circuit input.

[0029] Furthermore, since the injection time calibration loop only operates after the phase-locked loop (PLL) is individually locked, a lock-in detection circuit must be used to detect the PLL's lock-in state. Determining the PLL's lock-in state mainly involves two parts: analog and digital. The analog part primarily detects the input signal V of the lock-in detection circuit. CTRL The digital part mainly implements the counting function and outputs the lock flag DLD_OUT to check whether UP, DOWN, and DOWN meet the locking requirements.

[0030] First, the LPF output V CTRL Level detection, due to V CTRLVoltage-controlled VCO tuning has a limited linear range due to the finite linearity of the VCO tuning curve. Therefore, to ensure proper locking of the phase-locked loop, it is essential to ensure that VCO remains stable during locking. CTRL The voltage is within the target range. Reference voltage upper limit V. MAX and the lower limit of the reference voltage V MIN Used to determine V CTRL Target voltage range. Only when V CTRL Voltage greater than V MIN And less than V MAX When this happens, comparators A1 and A2 will simultaneously output a high level, and then the output LRD of the AND gate will be pulled high, indicating that V CTRL The voltage has met the locking requirements.

[0031] Secondly, the phase difference between the PFD output signals UP and DOWN is detected. During phase-locked loop (PLL) locking, the phase difference between UP and DOWN must be very small. The phase difference detection circuit can determine whether UP and DOWN meet the locking requirements. The phase difference detection circuit is as follows: Figure 5 As shown, this circuit mainly consists of two flip-flops D1 and D2, a variable delay chain, two NOT gates, and one XNOR gate. D1 is responsible for outputting a variable delay chain with a width of T. delay The narrow pulse signal, D2 is responsible for comparing the phase difference between the PFD output signals UP and DOWN with the variable delay chain delay T. delay The magnitudes of the two. When the difference between UP and DOWN is greater than T. delay When the rising edge of signal A arrives later than that of signal B, DFF2 will acquire a low level on the rising edge of signal B, and the phase difference lock flag PEC will always be low; when the phase difference between UP and DOWN is less than T... delay When signal A rises before signal B, DFF2 will acquire a high level, and PEC will remain high. Only when PEC is high does it indicate that the phase difference between UP and DOWN meets the locking requirements. Finally, to ensure that DLD_OUT accurately indicates the locked state, a counter will start counting when LRD and PEC are both high and the enable signal ENP_DLD is high. Only when the counter reaches the set value LD_Counter<10:0> will the lock flag DLD_OUT be pulled high, indicating that locking has occurred.

[0032] Furthermore, such as Figure 4 The digital calibration circuit includes an injection phase error detection circuit, an optimal injection time selection circuit connected to the injection phase error detection circuit, and a finite element state connected to the optimal injection time selection circuit. The specific circuit connection is as follows:

[0033] The outputs of the time-to-digital converter, TDC_CODE<5:0> and the latch detection circuit, DLD_OUT, are connected to flip-flop DFF1. DFF1 outputs N. TARGET The output TDC_CODE<5:0> of the time-to-digital converter is connected to the input of adder ADD1. Adder ADD1 outputs the sign bit SIGN and the error value N. error These circuits, connected to the inputs of the successive approximation logic search circuit and the minimum error control word search circuit respectively, constitute the injection phase difference detection circuit of the digital calibration circuit. Furthermore, the outputs of the successive approximation logic search circuit and the minimum error control word search circuit are connected to the inputs of the optimal control word selection circuit. The 8-bit digital output DCDL_CODE<7:0> of the optimal control word selection circuit is connected to the DCDL input of the SILPLL. These circuits constitute the optimal injection time selection circuit of the digital calibration circuit. Finally, the output DLD_OUT of the lock detection circuit and the reference signal f... REF and calibration setting value N CAL Connected to the input terminal of the timing control circuit, the timing control circuit outputs P. flag The Current_State<3:0> circuit is connected to the injection phase difference detection circuit and the optimal injection time selection circuit, respectively. The outputs ENP_INJ and ENP_DLD of the timing control circuit are connected to the narrow pulse generation circuit and the input of the lock detection circuit of SILPLL, respectively. The above circuits constitute the finite state machine of the digital calibration circuit.

[0034] Furthermore, the digital calibration circuit is the core of the SILPLL calibration function. This circuit mainly consists of an injection phase error detection circuit, a finite state machine, and an optimal injection time selection circuit. The working principle of each part will be explained below, and finally, the overall workflow diagram of the digital calibration circuit will be given.

[0035] The phase error injection detection circuit is mainly used to detect the magnitude and polarity of the difference between the current output and the target output of the time-to-digital converter in the calibration loop. It primarily consists of an adder (ADD1) and a flip-flop (DFF1). When the SILPLL's phase-locked loop is locked, the lock flag (DLD_OUT) of the lock detection circuit changes from low to high. At this time, the phase error injection detection circuit reads the output value of the time-to-digital converter through flip-flop (DFF1) and uses it as the calibration target value N. TARGET After calibration begins, adder ADD1 will continuously output the current N. TDC With the target value N TARGET The size of the difference N error And the polarity SIGN, so that the optimal injection time selection circuit can make a judgment.

[0036] Finite state machines are mainly used to generate control signals for digital calibration circuits, and their timing diagrams are as follows: Figure 6 As shown. First, when the SILPLL's phase-locked loop is not locked, its locking flag DLD_OUT is always low. At this time, the DLD enable signal ENP_DLD outputs high to ensure the DLD circuit works, while the other signals remain in the initialization state. Then, when the main loop is locked, DLD_OUT is pulled high to avoid the reference signal f REF Metastability issues arise during DLD_OUT sampling. A finite-state opportunity requires sampling DLD_OUT twice consecutively to ensure correct sampling results. When DLD_OUT is sampled as high, ENP_DLD is set low to disable the DLD circuit. DLD_OUT then returns to low to prevent interference with calibration. After ENP_DLD is set low, the digital calibration circuit begins calibration. Since calibration only requires detecting the phase difference change at the SILPLL PLL input after injection, continuous injection locking is unnecessary. Therefore, the injection enable signal ENP_INJ is only enabled for one reference cycle per calibration round. Furthermore, to ensure the SILPLL main loop state remains consistent at the start of each injection calibration round, the digital calibration circuit... CAL Calibration is performed only once per reference cycle to ensure the main loop returns to its initial state after injection calibration is disabled. Since SILPLL immediately performs injection locking and changes the phase at the main loop input after injection enable ENP_INJ is turned on, the phase difference detection flag P must be immediately set after injection enable ENP_INJ is turned off to ensure accurate calibration results. flag The signal is pulled high, and then the optimal injection time selection circuit performs a state transition and completes the selection and output of the optimal control word through the successive comparison logic circuit. After calibration, the injection enable signal ENP_INJ and the DLD enable signal ENP_DLD will be set to high level, and SILPLL will lock the calibration circuit with the found optimal control word.

[0037] Furthermore, the optimal injection timing selection circuit primarily functions to select and output the optimal DCDL control codeword. It mainly consists of a successive comparison logic search circuit, a minimum error control word search circuit, and an optimal control word selection circuit. The successive comparison logic search circuit compares the DCDL control word from high to low based on the sign bit SIGN output by the accumulator, and then uses a binary search algorithm to find the optimal injection timing control word. Taking a 3-bit DCDL as an example, the corresponding binary search algorithm is illustrated below. Figure 7As shown. First, during initialization, the control word DCDL_CODE<2:0> is set to the intermediate codeword 100. After the calibration circuit starts working, the binary search algorithm will start from the highest bit of the control word DCDL_CODE based on the sign bit SIGN injected into the phase error circuit. <2> Initiate injection timing calibration until DCDL_CODE is complete. <0> The calibration continues until the desired result is achieved. Furthermore, in each calibration cycle, the error value N injected into the phase error detection circuit output is adjusted. error The minimum counting error N stored in the minimum error control word search circuit. error,min The two values ​​are compared, and the smaller value is updated in the minimum error control word search circuit. Finally, when the calibration is completed, the control word corresponding to the minimum error control word search circuit is output as the optimal control word, and the calibration can be considered to be completed.

[0038] The flowchart of the digital calibration circuit is as follows: Figure 8 As shown. The calibration time required for a single calibration by the digital calibration circuit can be derived from the workflow. The SILPLL digital calibration circuit operates with a reference clock period of T. REF At that time, a k-bit DCDL circuit requires k+1 rounds of loop counting, and each round of loop counting lasts N. CAL After k+1 rounds of counting, two more rounds are needed to complete the injection time calibration. Therefore, the total calibration time of this invention can be expressed as:

[0039] T CAL =(k·N) CAL +N CAL +2)·T REF (1)

[0040] The number of devices and processing scale described herein are for simplification of the invention. Applications, modifications, and variations of this invention will be readily apparent to those skilled in the art. Although embodiments of the invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. It can be applied to various fields suitable for this invention, and further modifications can be readily implemented by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, this invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A subharmonic injection-locked phase-locked loop (PLL) for use in wireless communication transceiver systems, characterized in that, include: An injection time calibration circuit is provided, comprising a time amplifier, a time-to-digital converter connected to the time amplifier, a digital calibration circuit connected to the time-to-digital converter, a lock detection circuit, a numerically controlled delay chain, and a narrow pulse generation circuit connected to the digital calibration circuit. The digital calibration circuit includes an injection phase error detection circuit, an optimal injection time selection circuit connected to the injection phase error detection circuit, and a finite machine state connected to the optimal injection time selection circuit. The locking detection circuit is used to detect the locking status of the phase-locked loop.

2. The subharmonic injection-locked phase-locked loop (PLL) for use in a wireless communication transceiver system as described in claim 1, characterized in that, The injected phase error detection circuit includes an adder ADD1 and a flip-flop DFF1, and is used to detect the magnitude and polarity of the difference between the current output and the target output of the time-to-digital converter in the calibration circuit.

3. The subharmonic injection-locked phase-locked loop (PLL) for use in a wireless communication transceiver system as described in claim 2, characterized in that, When the phase-locked loop is locked, the lock flag bit DLD_OUT of the lock detection circuit will change from low to high. The phase error detection circuit will then read the output value of the time-to-digital converter at this time through trigger DFF1 and use it as the calibration target value N. TARGET Once calibration begins, adder ADD1 will continuously output the current N. TDC With the target value N TARGET The size of the difference N error And the polarity SIGN, so that the optimal injection time selection circuit can make a judgment.

4. The subharmonic injection-locked phase-locked loop (PLL) for use in a wireless communication transceiver system as described in claim 3, characterized in that, The finite state machine is used to generate control signals for the digital calibration circuit; when the main loop is locked, DLD_OUT is pulled high, and the finite state machine will sample DLD_OUT twice to ensure that the sampling result is correct. After injection enable ENP_INJ is turned off, the phase difference detection flag P must be set immediately. flag The signal is pulled high, and then the optimal injection time selection circuit performs a state transition and completes the selection and output of the optimal control word through the successive comparison logic circuit.

5. A subharmonic injection-locked phase-locked loop (PLL) for use in a wireless communication transceiver system as described in claim 4, characterized in that, The optimal injection time selection circuit is used to select and output the control codeword of the optimal numerical control delay chain. The optimal injection time selection circuit includes a successive comparison logic search circuit, a minimum error control word search circuit, and an optimal control word selection circuit. The successive comparison logic search circuit compares the control word of the numerical control delay chain from high to low according to the sign bit SIGN output by the accumulator, and then finds the optimal injection time control word according to the binary search algorithm.

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