Apparatus for automatically activating a phase-locked loop of an analog front end device and method thereof

Abstract

An analog front end device is provided, including a phase-locked loop, a first register, an analog-to-digital converter, and a controller. The phase-locked loop is activated based on a clock enable signal to generate a clock signal. The first register stores first data related to an analog signal based on the clock signal. The analog-to-digital converter converts the analog signal into the first data based on the clock signal. The controller determines whether the phase-locked loop is activated to generate the clock enable signal according to a flag, and operates in a sampling mode based on a first instruction. When the controller operates in the sampling mode, the controller activates the phase-locked loop and the functional circuit using the clock enable signal. When the controller exits the sampling mode, the controller deactivates the phase-locked loop and the functional circuit.

Description

[Technical Field]

[0001] This disclosure generally relates to apparatus and methods for automatically activating phase-locked loops of analog front-end devices operating in low-power modes. [Background Technology]

[0002] Typically, analog front-end devices remain in a low-power mode and are only activated when sampling signals to minimize power consumption and extend battery life. Furthermore, a precise clock is essential for accurate sampling, thus requiring a phase-locked loop (PLL). However, PLLs consume a great deal of power, significantly reducing battery life. Therefore, activating and deactivating the PLL at the correct time is crucial.

[0003] The phase-locked loop (PLL) of an analog front-end device is typically activated or deactivated by a remote MCU (or host) via a communication interface. When the MCU is executing multiple threads, the command to activate or deactivate the PLL may conflict with other commands. If the PLL is not activated in a timely manner, the data read from the registers of the analog front-end device may be incorrect. If the PLL is not deactivated in a timely manner, it will consume more power, leading to a shorter battery life. [Summary of the Invention]

[0004] This paper provides an analog front-end device and its method. The analog front-end device provided herein can wake up from a low-power mode to a sampling mode or an access mode using the method provided herein. Furthermore, the analog front-end device can also return to a low-power mode when the sampling mode or access mode is completed. Additionally, a flag indicating whether a phase-locked loop (PLL) is activated is provided. By monitoring this flag, the analog front-end device can easily determine whether the PLL is activated.

[0005] In one embodiment, an analog front-end device includes a phase-locked loop (PLL), a first register, an analog-to-digital converter (ADC), and a controller. The PLL is activated based on a clock enable signal to generate a clock signal. The first register stores first data associated with the analog signal based on the clock signal. The ADC retrieves setting parameters from the first register based on the clock signal and converts the analog signal into the first data based on the clock signal. The controller determines whether to activate the PLL to generate the clock enable signal based on a flag and operates in sampling mode based on a first instruction. When the controller operates in sampling mode, it activates the PLL using the clock enable signal. When the controller exits sampling mode, it deactivates the PLL.

[0006] According to one embodiment of the present invention, the electronic circuit further includes a second register. The second register stores a flag indicating whether the phase-locked loop (PLL) is activated. When the flag is set to the first level, the PLL is activated. When the flag is set to the second level, the PLL is deactivated.

[0007] According to one embodiment of the present invention, before the controller activates the phase-locked loop, the controller determines whether the phase-locked loop has been activated by determining whether a flag is set to the first criterion.

[0008] According to one embodiment of the present invention, the analog front-end device further includes a timer. The timer counts a delay time based on an idle signal and generates a clock disable signal when the delay time reaches a predetermined period. When the first register is idle, the controller activates the idle signal to trigger the timer to count the delay time. When the delay time reaches the predetermined period, the timer triggers the clock disable signal to disable the phase-locked loop and sets a flag to a second level.

[0009] According to one embodiment of the present invention, the setting parameters include pulse repetition period, sampling period of sampling mode, offset error, full-scale error, differential nonlinearity (DNL), and integral nonlinearity (INL). The pulse repetition period includes low-power mode and sampling mode.

[0010] According to one embodiment of the present invention, the analog front-end device further includes an interface. The interface receives a first instruction from a host. When the interface receives the first instruction, the interface provides the first instruction to the controller.

[0011] According to one embodiment of the present invention, when the host transmits a second instruction to access first data in a first register, the controller operates in access mode. When the controller operates in access mode, it activates a phase-locked loop (PLL). Before activating the PLL, the controller checks a flag to determine whether the PLL has already been activated. When the flag indicates that the PLL has been deactivated, the controller activates the PLL. The first data and clock signal are provided to the host via an interface.

[0012] According to one embodiment of the invention, the controller operates periodically in sampling mode and occasionally in access mode according to a received second instruction.

[0013] According to one embodiment of the present invention, the first instruction defines the pulse repetition period and the duty cycle of the sampling mode during the pulse repetition period. When the controller does not operate in the sampling mode during the pulse repetition period, the analog front-end device operates in a low-power mode to minimize power consumption.

[0014] According to one embodiment of the invention, the access mode occurs when the controller is not operating in sampling mode.

[0015] In another embodiment, a method for accessing a first register of an analog front-end device operating in a low-power mode is provided. The analog front-end device further includes a phase-locked loop (PLL) for generating a clock signal. The method includes the following steps: determining whether a flag is set to the first threshold; when the flag is not set to the first threshold, activating the PLL to generate a clock signal; and accessing the first register based on the clock signal.

[0016] According to one embodiment of the present invention, the method further includes the following steps: When the flag is set to the first criterion, it is determined that the phase-locked loop (PLL) is activated. When the flag is not set to the first criterion, it is determined that the PLL is deactivated and then the PLL is activated.

[0017] According to one embodiment of the present invention, the method further includes the following steps: determining whether a first register is idle; calculating a delay time when the first register is idle; determining whether the delay time has reached a predetermined period; deactivating the phase-locked loop and canceling the flag when the delay time has reached the predetermined period; and keeping the phase-locked loop active and continuing to calculate the delay time when the delay time has not reached the predetermined period.

[0018] According to one embodiment of the present invention, the analog front-end device further includes an interface. The method further includes the following steps: receiving a first instruction from a host via the interface; the analog front-end device operating in a sampling mode; activating a phase-locked loop (PLL) in the sampling mode to generate a clock signal; and deactivating the PLL and functional circuitry after the sampling mode. The step of accessing a first register based on the clock signal further includes the following steps: writing first data associated with an analog signal into the first register based on the clock signal.

[0019] According to one embodiment of the present invention, an analog signal is converted into first data by an analog-to-digital converter. The first data is digital data. The setting parameters of the analog-to-digital converter are stored in a first register. The setting parameters include pulse repetition period, sampling period of the sampling mode, offset error, full-scale error, differential nonlinearity (DNL), and integral nonlinearity (INL). The pulse repetition period includes a low-power mode and a sampling mode.

[0020] According to one embodiment of the present invention, the period of the sampling mode is defined in the first instruction.

[0021] According to one embodiment of the present invention, the method further includes the following steps: Receiving a second instruction from a host via an interface. Based on the second instruction, simulating front-end device operation in access mode. In access mode, a phase-locked loop (PLL) is activated to generate a clock signal. First data is provided to the host from a first register via the interface. After access mode, the PLL and functional circuitry are deactivated. The step of accessing the first register based on the clock signal further includes the following steps: Reading the first data in the first register based on the clock signal.

[0022] According to one embodiment of the present invention, the sampling mode operates periodically, while the access mode operates occasionally based on a received second instruction.

[0023] According to one embodiment of the present invention, a first instruction defines a pulse repetition period. During the pulse repetition period, the analog front-end device operates in either a sampling mode or a low-power mode. The duty cycle of the sampling mode is defined in the first instruction.

[0024] According to one embodiment of the present invention, when the analog front-end device is not operating in sampling mode, the analog front-end device operates in access mode.

[0025] The following embodiments will be described in detail with reference to the accompanying drawings. [Attached Image Description]

[0026] A more complete understanding of the invention can be obtained by reading the following detailed description and referring to the examples in the accompanying drawings:

[0027] Figure 1 This is a block diagram of a simulated front-end device according to an embodiment of the present invention;

[0028] Figure 2 This is a flowchart of a method for accessing a first register of an analog front-end device in low-power mode according to an embodiment of the present invention;

[0029] Figure 3 According to one embodiment of the present invention, the operation of an analog front-end circuit is illustrated.

Detailed Implementation Methods

[0030] The following description is for illustrative purposes only and should not be construed as limiting. The scope of this disclosure is defined by the appended claims.

[0031] In the following detailed description, numerous specific details and embodiments are set forth for purposes of explanation in order to provide a thorough understanding of this disclosure. The use of the same and / or corresponding numbers in the drawings of different embodiments does not imply any association between the different embodiments.

[0032] Furthermore, in some embodiments of this disclosure, terms involving attachments, couplings, etc., such as “connection” and “interconnection”, refer to a relationship in which structures are directly or indirectly (e.g., electrical connection) fixed or connected to each other through intervening structures, as well as movable or rigid attachments or relationships, unless otherwise explicitly stated.

[0033] Furthermore, relative spatial expressions are used in this specification. For example, "below," "bottom," "above," or "top" are used to describe the position of one element relative to another. It should be understood that if the device is inverted, an element "below" will become an element "above."

[0034] It should be understood that although the terms first, second, third, etc., are used herein to describe various elements, components, regions, layers, parts, and / or portions, these elements, components, regions, layers, parts, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, part, or portion from another. Therefore, the first element, component, region, layer, part, or portion in the specification may be referred to as the second element, component, region, layer, part, or portion in the claims without departing from the teachings of this disclosure.

[0035] It should be understood that the description of these exemplary embodiments is intended to be consistent with the appendix. Figure 1 When reading this document, the accompanying drawings should be considered an integral part of the overall written description. The drawings are not to scale. Furthermore, to simplify the drawings, structures and equipment are shown schematically.

[0036] The terms “approximately,” “about,” and “substantially” generally mean a value within + / - 20% of the declared value, more typically within + / - 10%, + / - 5%, + / - 3%, + / - 2%, + / - 1%, or + / - 0.5%. The declared values ​​in this disclosure are approximate. Even without specific description, the declared values ​​include the meaning of “approximately,” “about,” or “substantially.”

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. It should be understood that, in each case, terms as defined in commonly used dictionaries should be interpreted as meaning consistent with the relevant skill and background of this disclosure or the context of this disclosure, and should not be idealized or overly formalized unless so defined.

[0038] Furthermore, in some embodiments of this disclosure, terms involving attachments, couplings, etc., such as “connection” and “interconnection”, refer to a relationship in which structures are directly or indirectly (e.g., electrical connection) fixed or connected to each other through intervening structures, as well as movable or rigid attachments or relationships, unless otherwise explicitly stated.

[0039] In drawings, similar elements and / or features may have the same reference number. Individual components of the same type can be distinguished by adding letters or numbers after the component symbol, thus differentiating similar components and / or features.

[0040] Figure 1 This is a block diagram of a simulated front-end device according to an embodiment of the present invention. Figure 1As shown, the analog front-end device 100 receives analog signals ANA from the functional circuit 10, including an analog-to-digital converter 110, a first register 120, a phase-locked loop 130, a second register 140, a controller 150, a timer 160, and an interface 170.

[0041] like Figure 1 As shown, functional circuit 10 generates an analog signal ANA. According to some embodiments of the invention, functional circuit 10 may include multiple sensors to sense the environment to generate the analog signal ANA. According to some embodiments of the invention, functional circuit 10 can be any type of circuit for generating the analog signal ANA.

[0042] The analog-to-digital converter 110 is activated by the conversion enable signal ENV and converts the analog signal ANA of the functional circuit 10 into first data RDT according to the clock signal CLK. According to some embodiments of the present invention, the first data RDT is digital data.

[0043] The first register 120 stores the first data RDT generated by the analog-to-digital converter 110 and the setting parameters PRM of the analog-to-digital converter 110. According to some embodiments of the present invention, the setting parameters PRM include... Figure 3 The pulse repetition period TPRP (which will be described in the following paragraphs) Figure 3 The sampling period TSA (described below), offset error, full-scale error, differential nonlinearity (DNL), and integral nonlinearity (INL) are included. According to some embodiments of the invention, a clock signal CLK is required when reading or writing first data RDT from or to the first register 120. According to some embodiments of the invention, the analog-to-digital converter 110 retrieves the setting parameter PRM from the first register 120 based on the clock signal CLK.

[0044] Phase-locked loop 130 is activated based on clock enable signal ENC to generate clock signal CLK, and analog-to-digital converter 110 and first register 120 operate according to clock signal CLK. According to some embodiments of the invention, when phase-locked loop 130 is deactivated, analog-to-digital converter 110 is deactivated.

[0045] The second register 140 stores a flag F to indicate whether the phase-locked loop 130 is activated. According to one embodiment of the invention, when flag F is set to the first level, it indicates that the phase-locked loop 130 is activated. According to another embodiment of the invention, when flag F is set to the second level, it indicates that the phase-locked loop 130 is deactivated. According to some embodiments of the invention, when flag F is set to the first level, flag F is at a high logic level. When flag F is set to the second level, flag F is at a low logic level.

[0046] Controller 150 generates a clock enable signal ENC to activate / deactivate phase-locked loop 130 and a conversion enable signal ENV to activate analog-to-digital converter 110 to operate based on the clock signal CLK generated by phase-locked loop 130. Furthermore, controller 150 determines whether phase-locked loop 130 is activated based on flag F. In other words, before controller 150 activates / deactivates phase-locked loop 130 using the clock enable signal ENC, controller 150 determines whether phase-locked loop 130 is activated by determining whether flag F is set to the first bit.

[0047] like Figure 1 As shown, timer 160 counts the delay time based on the idle signal SID. According to some embodiments of the invention, when controller 150 determines that the first register 120 is in an idle state, controller 150 activates the idle signal SID to trigger timer 160 to count the delay time. When the delay time reaches a predetermined period, timer 160 activates the clock disable signal DEN to disable the phase-locked loop 130, thereby reducing the overall power consumption of the analog front-end device 100. According to some embodiments of the invention, flag F is set to the first level by the clock enable signal ENC and the second level by the clock disable signal DEN.

[0048] Figure 2 This is a flowchart of a method for accessing a first register of an analog front-end device in low-power mode according to an embodiment of the present invention. In the following paragraphs, method 200 will be combined with Figure 1 The analog front-end device 100 is described in detail below. According to certain embodiments of the present invention, when the analog front-end device 100 operates in a low-power mode, the phase-locked loop 130 is deactivated to reduce power consumption, and the functional circuit 10 continues to generate the analog signal ANA.

[0049] According to other embodiments of the present invention, when the analog front-end device 100 operates in access mode, the controller 150 of the analog front-end device 100 executes method 200 to activate and deactivate the phase-locked loop 130. According to yet another embodiment of the present invention, when the analog front-end device 100 operates in sampling mode, the controller 150 executes steps S210-S230 to activate the phase-locked loop 130 and executes steps S280-S290 to deactivate the phase-locked loop 130.

[0050] According to one embodiment of the present invention, when the analog front-end device 110 operates in sampling mode, the analog front-end device 100 converts the analog signal ANA into first data RDT based on the clock signal CLK. According to another embodiment of the present invention, when the analog front-end device 100 operates in access mode, the host 20 accesses the first data RDT stored in the first register 120. Sampling mode and access mode will be described in the following paragraphs.

[0051] In step S210, the controller 150 determines whether the flag F stored in the second register 140 is set to the first threshold. According to some embodiments of the invention, since the flag F is configured to indicate whether the phase-locked loop 130 is activated, the controller 150 determines whether the phase-locked loop 130 is activated by determining whether the flag F is set to the first threshold. When the flag F is set to the first threshold, it indicates that the phase-locked loop 130 is activated. When the flag F is set to the second threshold, it indicates that the phase-locked loop 130 is deactivated.

[0052] When controller 150 determines in step S210 that flag F is not set to the first criterion, controller 150 activates the clock enable signal ENC to activate phase-locked loop 130 to generate clock signal CLK (step S220), and sets flag F to the first criterion (step S230). After generating clock signal CLK, the first register 120 is accessed using clock signal CLK (step S240).

[0053] According to certain embodiments of the present invention, the first data RDT generated by the functional circuit 10 and associated with the analog signal ANA can be written to the first register 120 using the clock signal CLK. According to other embodiments of the present invention, the first data RDT stored in the first register 120 can be read using the clock signal CLK, as will be described in the following paragraphs.

[0054] Controller 150 further determines whether the first register 120 is idle (step S250). When controller 150 determines in step S250 that the first register 120 is idle, controller 150 activates the idle signal SID to trigger timer 160 to count the delay time (step S260). When controller 150 determines in step S250 that the first register 120 is not idle, controller 150 returns to step S240 to access the first register 120.

[0055] After step S260, it is determined whether the delay time counted by timer 160 has reached a predetermined period (step S270). According to one embodiment of the present invention, when it is determined in step S260 that the delay time has not reached the predetermined period, controller 150 returns to step S260, and timer 160 continues to count the delay time. According to another embodiment of the present invention, when it is determined in step S270 that the delay time has reached the predetermined period, timer 160 activates the clock disable signal DEN to disable phase-locked loop 130 (step S280).

[0056] According to certain embodiments of the invention, the timer 160 may be integrated into the controller 150. In other words, the controller 150 counts the delay time and activates the clock disable signal DEN to disable the phase-locked loop 130 when the delay time reaches a predetermined period.

[0057] refer to Figure 2 When the phase-locked loop 130 is deactivated in step S280, the controller 150 further sets the flag F to a second level (step S290). According to certain embodiments of the present invention, setting the flag F to the second level indicates that the phase-locked loop 130 has been deactivated.

[0058] refer to Figure 1 The analog front-end circuit 100 also includes an interface 170. According to some embodiments of the invention, the analog front-end circuit 100 communicates with the host 20 via interface 170. According to some embodiments of the invention, the controller 150 receives a first instruction INS1 from the host 20 via interface 180 to operate in sampling mode. When the controller 150 operates in sampling mode, the controller 150 activates a phase-locked loop 130 to generate a clock signal CLK and uses a conversion signal ENV to activate an analog-to-digital converter 110, converting the analog signal ANA into a first data RDT based on the clock signal CLK. According to some embodiments of the invention, the host 20 may be a microcontroller unit (MCU).

[0059] According to another embodiment of the invention, controller 150 receives a second instruction INS2 from host 20 via interface 180 to operate in access mode. When controller 150 operates in access mode, controller 150 activates phase-locked loop 130 to generate a clock signal CLK so as to provide the first data RDT stored in the first register 120 to host 20 via interface 170. Sampling mode and access mode will be further described in the following paragraphs.

[0060] Figure 3 The operation of an analog front-end circuit according to an embodiment of the present invention is illustrated. In the following paragraphs, it will be combined with... Figure 1 Description of analog front-end circuit 100 Figure 3 .

[0061] like Figure 3 As shown, the Pulse Repetition Period (TPRP) includes Sampling Mode (MS), Low Power Mode (MLP), and Access Mode (MA), and the TPRP repeats one after another. In other words, Figure 1 The analog front-end device 100 operates in sampling mode MS during each pulse repetition period TPRP. After sampling mode MS, the analog front-end device 100 operates in low-power mode MLP, thereby greatly reducing the overall power consumption.

[0062] That is, the analog front-end device 100 periodically operates in sampling mode MS to store the first data RDT generated by the analog-to-digital converter 110 in the first register 120, and occasionally operates in access mode MA to transfer the first data RDT in the first register 120 to the host 20. According to an embodiment of the present invention, the controller 150 of the analog front-end device 100 performs... Figure 2 Method 200, or a part thereof, is used to activate phase-locked loop 130 during sampling mode MS or access mode MA.

[0063] According to another embodiment of the invention, the controller 150 activates the phase-locked loop 130 before the sampling mode MS or the access mode MA, so that the clock signal CLK is stable during the sampling mode MS and the access mode MA. In other words, the clock signal CLK should be stable before the analog-to-digital converter 110 converts the analog signal ANA or accesses the first register 120.

[0064] like Figure 3 As shown, Access Mode MA occurs occasionally within the cycle of Low Power Mode MLP. More specifically, the timing of Access Mode MA depends on when host 20 transmits the second instruction INS2. That is, the timing of Access Mode MA is unpredictable. According to some embodiments of the invention, Access Mode MA may not overlap with Sampling Mode MS. According to other embodiments of the invention, Access Mode MA may overlap with Sampling Mode MS. Figure 3 In this embodiment, the access mode MA and the sampling mode MS do not overlap.

[0065] According to some embodiments of the present invention, the pulse repetition period TPRP and the sampling period TSA are defined in the first instruction INS1. According to some embodiments of the present invention, the first instruction INS1 may be a driver for the analog front-end device 100. Once the first instruction INS1 is provided to the analog front-end device 100, the behavior of the analog front-end device 100 is specified. According to some embodiments of the present invention, the analog front-end device 100 issues an interrupt to the host 20, and the host 20 sends a second instruction INS2 to read the first data RDT from the first register 120.

[0066] like Figure 3 As shown, when the pulse repetition period TPRP and the sampling period TSA are defined in the first instruction INS1, the period of the low-power mode MLP is also specified. The smaller the duty cycle of the sampling period TSA to the pulse repetition period TPRP, the lower the power consumption of the analog front-end device 100.

[0067] Furthermore, once the first instruction INS1 is provided to the analog front-end device 100, the host 20 no longer needs to control the analog front-end device 100. For example... Figure 2As shown, controller 150 executes method 200 to activate / deactivate phase-locked loop 130 without host 20 control. The resources and communication channels of host 20 can be reserved for other applications.

[0068] This document provides an analog front-end device and its method. The analog front-end device provided herein can wake up from a low-power mode to a sampling mode or an access mode using the method provided herein. Furthermore, the analog front-end device can return to a low-power mode after completing the sampling mode or access mode. Additionally, a flag indicating whether a phase-locked loop (PLL) is activated is provided. By monitoring the flag, the analog front-end device can more easily determine whether a PLL is activated.

[0069] While some embodiments of this disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure, as defined by the appended claims. For example, those skilled in the art will readily understand that many features, functions, processes, and materials described herein can be varied while remaining within the scope of this disclosure. Furthermore, the scope of this application is not intended to be limited to embodiments of the specific processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specifications. As will be readily understood from the disclosure of this disclosure by those of ordinary skill in the art, existing or later-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. An analog front-end device, comprising: A phase-locked loop (PLL) generates a clock signal based on the activation of a clock enable signal. The first register stores first data related to the analog signal based on the clock signal; An analog-to-digital converter retrieves setting parameters from the first register based on the clock signal and converts the analog signal into the first data based on the clock signal. The controller determines whether to activate the phase-locked loop to generate the clock enable signal based on a flag, and operates in sampling mode based on a first instruction; When the controller operates in this sampling mode, it uses the clock enable signal to activate the phase-locked loop; When the controller exits the sampling mode, it disables the phase-locked loop.

2. The electronic circuit of claim 1, further comprising: The second register stores the flag indicating whether the phase-locked loop is activated; When the flag is set to the first time, the phase-locked loop is activated; When the flag is set to the second criterion, the phase-locked loop is deactivated.

3. The analog front-end device as claimed in claim 2, wherein before the controller activates the phase-locked loop, the controller determines whether the phase-locked loop has been activated by determining whether the flag is set to the first criterion.

4. The analog front-end device as described in claim 2, further comprising: A timer that counts a delay time based on an idle signal and generates a clock disable signal when the delay time reaches a predetermined period; When the first register is idle, the controller activates the idle signal to trigger the timer to count the delay time; When the delay time reaches the predetermined period, the timer triggers the clock disable signal to disable the phase-locked loop and sets the flag to the second level.

5. The analog front-end device as claimed in claim 4, wherein the setting parameters include pulse repetition period, sampling period of the sampling mode, offset error, full-scale error, differential nonlinearity (DNL), and integral nonlinearity (INL). The pulse repetition period includes a low-power mode and the sampling mode.

6. The analog front-end device as claimed in claim 4, further comprising: The interface receives the first instruction from the host. When the interface receives the first instruction, it provides the first instruction to the controller.

7. The analog front-end device of claim 6, wherein when the host transmits a second instruction to access the first data in the first register, the controller operates in access mode; When the controller operates in this access mode, the controller activates the phase-locked loop; Before activating the phase-locked loop, the controller checks the flag to determine whether the phase-locked loop has been deactivated. When the flag indicates that the phase-locked loop (PLL) is deactivated, the controller activates the PLL. The first data and the clock signal are provided to the host through this interface.

8. The analog front-end device of claim 7, wherein the controller operates periodically in the sampling mode and occasionally in the access mode according to the received second instruction.

9. The analog front-end device as claimed in claim 7, wherein the first instruction defines a pulse repetition period and the duty cycle of the sampling mode in the pulse repetition period; When the controller does not operate in the sampling mode during the pulse repetition period, the analog front-end device operates in a low-power mode to minimize power consumption.

10. The analog front-end device of claim 9, wherein the access mode occurs when the controller is not operating in the sampling mode.

11. A method for accessing a first register of an analog front-end device operating in a low-power mode, wherein the analog front-end device further includes a phase-locked loop that generates a clock signal, the method comprising: Determine whether the flag is set as the first criterion; When the flag is not set to the first time, the phase-locked loop is activated to generate the clock signal; Access the first register based on the clock signal.

12. The method of claim 11, further comprising: When this flag is set to the first position, it indicates that the phase-locked loop is activated; and When the flag is not set to the first position, it is determined that the phase-locked loop is deactivated and then activated.

13. The method of claim 11, further comprising: Determine if the first register is free; Calculate the delay time when the first register is idle; Determine whether the delay time has reached the predetermined period; When the delay time reaches the predetermined period, the phase-locked loop is deactivated and the flag is removed; and If the delay time does not reach the predetermined period, the phase-locked loop remains active and the delay time continues to be calculated.

14. The method of claim 11, wherein the analog front-end device further includes an interface, and the method further includes: Receive the first instruction from the host through this interface; Operate in sampling mode; Activate the phase-locked loop to generate the clock signal in this sampling mode; and After this sampling mode, the phase-locked loop and this functional circuit are disabled; The step of accessing the first register based on the clock signal further includes: Based on the clock signal, the first data related to the analog signal is written into the first register.

15. The method of claim 14, wherein the analog signal is converted into the first data by an analog-to-digital converter; in, The first piece of data is numerical data; The parameters for setting the analog-to-digital converter are stored in the first register; The settings parameters include pulse repetition period, sampling period of the sampling mode, offset error, full-scale error, differential nonlinearity (DNL), and integral nonlinearity (INL). The pulse repetition period includes a low-power mode and a sampling mode.

16. The method of claim 15, wherein the period of the sampling mode is defined in the first instruction.

17. The method of claim 14, further comprising: Receive a second instruction from the host through this interface; Operate in access mode based on this second instruction; Activate the phase-locked loop to generate the clock signal in this access mode; The first data is provided to the host from the first register through this interface; and After this access mode, the phase-locked loop and the functional circuit are disabled; The step of accessing the first register based on the clock signal further includes: The first data in the first register is read based on the clock signal.

18. The method of claim 17, wherein the sampling mode operates periodically, while the access mode operates occasionally based on the receipt of the second instruction.

19. The method of claim 17, wherein the first instruction defines a pulse repetition period; in, The analog front-end device operates in the sampling mode or the low-power mode during the pulse repetition period; The working period of this sampling mode is defined in the first instruction.

20. The method of claim 19, wherein the simulated front-end device operates in the sampling mode when the simulated front-end device is not operating in the access mode.

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